Lateral Double-Diffused Semiconductor Field-Effect Transistor with Stress Medium Layer and Fabrication Method Thereof

Abstract

The present invention discloses a lateral double-diffused semiconductor field-effect transistor with a stress medium layer and a manufacturing method thereof. A partially folded structure is provided in the upper part of the substrate; a stress medium layer is deposited on the surface of the folded drift region, and an extended gate electrode covers the surface of the stress medium layer. The planar extended gate electrode located above the stress medium layer eliminates the electric field concentration at the corner of the fully folded structure, avoiding premature breakdown at the corner and improving the breakdown voltage of the device. The stress medium layer applies a positive stress in the X direction to the drift region through three surfaces and two dimensions, and the positive stress is superimposed in the drift region to induce an increase in the carrier mobility in the drift region; at the same time, when the device is in the off state, the optimal doping concentration of the drift region is increased; when the device is in the on state, a carrier accumulation layer is formed on the surface of the drift region, and the carrier accumulation layer can serve as a low-resistance current path to reduce the specific on-resistance of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to a lateral double-diffused semiconductor field-effect transistor with a stress dielectric layer and a manufacturing method thereof. Background Art

[0002] The lateral double-diffused metal oxide semiconductor field-effect transistor (Lateral Double–diffused MOSFET, abbreviated as LDMOS) benefits from the fact that three electrodes fabricated on the device surface can be monolithically integrated with digital and analog circuits through the BCD (Bipolar-CMOS-DMOS) process. It has the advantages of easy integration, good thermal stability, good frequency stability, low power consumption, majority-carrier conduction, small power drive, high switching speed, etc., and is widely used in power integrated circuits.

[0003] The area of the LDMOS device accounts for a large proportion in the entire chip, and its power consumption is much greater than that of other analog and digital devices in the chip, accounting for most of the losses in the entire power integrated circuit. However, for LDMOS devices, high breakdown voltage and low specific on-resistance are contradictory in design and process manufacturing. Therefore, it is very necessary to further reduce the specific on-resistance of the device without sacrificing the breakdown voltage of the device to reduce the chip power consumption. The design of low-resistance new LDMOS devices is one of the key technologies for energy conservation and emission reduction in the field of power semiconductors.

[0004] For this reason, designers have proposed a folded structure with an extended gate electrode to reduce the specific on-resistance of the device. The extended gate electrode attracts carriers on the surface of the drift region to achieve a low-resistance current path; the extended gate electrode assists in depleting the drift region to increase the optimal doping concentration of the drift region; the folded structure increases the channel density and the low-resistance current path density of the device. However, when the device withstands reverse voltage, electric field concentration occurs at the corners of the folded structure, and premature breakdown occurs at the corners of the device, restricting the further increase of the breakdown voltage of the device. In addition, the accumulation of carriers on the surface of the drift region and the increase in the optimal doping concentration of the drift region will lead to strong inter-carrier scattering and ionized impurity scattering, resulting in a decrease in the carrier mobility. Summary of the Invention

[0005] In order to solve the problems that the traditional folded-structure transistor has poor breakdown characteristics when the device withstands reverse voltage, and the accumulation of carriers on the surface of the drift region and the increase in the optimal doping concentration of the drift region will lead to strong inter-carrier scattering and ionized impurity scattering, resulting in a decrease in the carrier mobility, etc., the present invention provides a lateral double-diffused semiconductor field-effect transistor with a stress dielectric layer.

[0006] Meanwhile, the present invention also provides a manufacturing method of the lateral double-diffused semiconductor field-effect transistor with the stress dielectric layer.

[0007] The specific technical solution of the present invention is as follows:

[0008] A lateral double-diffused semiconductor field-effect transistor with a stress medium layer, comprising a substrate of semiconductor material; a partially folded structure is formed on the upper half of the substrate through a trench etching process;

[0009] A base region and a drift region are respectively formed on the left and right sides of the lower half of the substrate;

[0010] An active region is formed on the surface of the base region;

[0011] A drain region is formed in the non-folded structure region corresponding to the drift region;

[0012] A base-substrate contact is formed on the left side of the source region;

[0013] A buffer layer and a stress medium layer are formed at the folded structure and corresponding to the drift region, and both the buffer layer and the stress medium layer are in an inverted "U" shape. The buffer layer is located between the stress medium layer and the drift region. The length of the stress medium layer is equivalent to the length of the drift region. The right boundary of the stress medium layer is on the drain region side in the drift region, and the left boundary of the stress medium layer is close to the right side of the boundary line between the drift region and the base region;

[0014] A gate insulating layer is formed at the folded structure and corresponding to the base region;

[0015] An extended gate electrode is formed on the surface of the gate insulating layer and at the top of the stress medium layer; the length of the extended gate electrode is adjusted according to the breakdown voltage requirement;

[0016] A source electrode is formed at the folded structure and corresponding to the part of the source region and the base-substrate contact; the source electrode is in an inverted "U" shape;

[0017] A drain electrode with a flat plate structure is formed on the top surface of the drain region.

[0018] Further, the ratio range of the height to the width of the protrusion in the above-mentioned folded structure is 1 to 4.

[0019] Further, the ratio range of the width of the protrusion to the width of the substrate in the above-mentioned folded structure is 1 / 4 to 1 / 2.

[0020] Further, the ratio range of the thickness of the stress medium layer (8) located at the top of the protrusion to the length of the drift region is 1 / 20 to 1 / 5.

[0021] Further, the ratio of the thickness of the stress medium layer (8) to the thickness of the buffer layer (7) is 10 to 100.

[0022] Further, the typical value of the intrinsic stress of the stress medium layer (8) is 2 GPa to 4 GPa.

[0023] In addition, the present invention also provides a method for manufacturing the above-mentioned lateral double-diffused semiconductor field-effect transistor with a stress dielectric layer, including the following steps:

[0024] Step 1: Take a semiconductor material as the substrate;

[0025] Step 2: Form a base region and a drift region on the substrate through ion implantation or thermal diffusion process;

[0026] Step 3: Form a source region and a drain region on the base region and the drift region respectively through ion implantation;

[0027] Step 4: Form a base-substrate contact by ion implantation outside the source region in the base region;

[0028] Step 5: Form a partially folded structure on the region of the substrate surface outside the drain region through plasma etching;

[0029] Step 6: Grow a buffer layer on the substrate surface;

[0030] Step 7: Deposit a stress dielectric layer on the buffer layer. By adjusting the deposition process parameters, the dielectric layer has intrinsic stress;

[0031] Step 8: Remove the stress dielectric layer by plasma etching method, and only retain the stress dielectric layer above the drift region;

[0032] Step 9: Remove the buffer layer by plasma etching method, and only retain the buffer layer above the drift region;

[0033] Step 10: Grow a gate oxide layer on the substrate surface and deposit polysilicon, and then etch the polysilicon to form an extended gate electrode;

[0034] Step 11: Deposit a passivation layer on the device surface, and then etch contact holes;

[0035] Step 12: Form a source electrode by short-circuiting through contact holes above the source region and the base-substrate contact;

[0036] Step 13: Form a drain electrode by contact holes above the drain region.

[0037] The beneficial effects of the technical solution of the present invention are as follows:

[0038] 1. When the device of the present invention is under reverse breakdown voltage, the extended gate electrode at the top of the stress dielectric layer and the planar drain region make the equipotential lines from the flat drain electrode to the extended gate electrode evenly distributed in the stress dielectric layer above the protrusion, eliminating the electric field concentration at the corner of the fully folded structure, and improving the breakdown voltage of the device.

[0039] 2. The present invention uses a stress material as the gate dielectric layer, without the need to additionally set an isolation layer to apply stress, thus saving chip area.

[0040] 3. In the present invention, using a stress material as the gate dielectric layer can apply stress in two dimensions (Y and Z directions). The positive stress applied in two dimensions is superimposed in the drift region, thereby obtaining a greater improvement in the carrier mobility in the stress-induced drift region;

[0041] 4. In the present invention, applying stress in the Y direction eliminates stress attenuation in the device width direction.

[0042] 5. In the present invention, applying stress along the X direction (tensile stress S xx > 0 for N-channel LDMOS, compressive stress S xx < 0 for P-channel LDMOS) improves the mobility. According to the piezoresistive mobility model (Shu T C, Wang W C, Huang J, et al. Exploring the effect of width on performance enhancement in NMOSFETs with a silicon–carbon alloy stressor and a tensile stress silicon nitride liner [J]. Applied Surface Science, 2008, 254(19): 6177-6181), the electron mobility formula for the <100> crystal orientation is:

[0043] μ xx = μ0·[1 + 1.022S xx - 0.534(S yy + S zz )] (1)

[0044] The electron mobility formula for the <110> crystal orientation is:

[0045] μ xx = μ0·(1 + 0.312S xx - 0.534S yy + 0.176S zz ) (2)

[0046] According to the analysis of the above two formulas, for N-channel LDMOS devices, regardless of whether the positive stress points to the <100> crystal orientation or the <110> crystal orientation, since the coefficients of S xx shown in Equation (1) and Equation (2) are both greater than the coefficients of S zz , it can be known that the method of applying stress along the X direction (S xx > 0) in the present invention has a better effect on improving the electron mobility than the stress along the Z direction or the Y direction (S ZZ>0) is more obvious. Therefore, the present invention can more significantly improve the effect of electron mobility.

[0047] At the same time, according to the above formulas (1) and (2), it can be known that the tensile stress (S xx >0) in the X direction in the present invention can simultaneously improve the electron mobility in the <100> crystal orientation and the <110> crystal orientation.

[0048] 6. The introduction of the stress medium layer eliminates the problem of carrier mobility degradation in the folded drift region due to excessive impurity concentration and carrier accumulation effect. In addition, the use of the folded structure to introduce positive stress into the drift region from three sides and two dimensions can effectively prevent the relaxation of stress in the direction of the bottom of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 FIG. is a three-dimensional schematic diagram of a folded strained silicon laterally diffused metal oxide element semiconductor field effect transistor according to the present invention.

[0050] Figure 2 FIG. is a cross-sectional view of the device according to the present invention along Figure 1 the tangent line A-A' in FIG.

[0051] Figure 3 FIG. is a cross-sectional view of the device according to the present invention along Figure 1 the tangent line B-B' in FIG.

[0052] Figure 4 FIG. is a cross-sectional view of the device according to the present invention along Figure 1 the tangent line C-C' in FIG.

[0053] Figure 5 FIG. is a schematic diagram for comparing the output characteristics of an embodiment of the present invention with a conventional LDMOS device.

[0054] Figure 6 FIG. is a schematic diagram for comparing the breakdown voltage of an embodiment of the present invention with a conventional LDMOS device.

[0055] Figure 7 FIG. is a schematic diagram for comparing the potential distribution of an embodiment of the present invention with a conventional LDMOS device.

[0056] DESCRIPTION OF THE REFERENCE NUMERALS IN THE DRAWINGS:

[0057] 1 - Substrate; 2 - Base region; 3 - Drift region; 4 - Source region; 5 - Drain region; 6 - Base region substrate contact; 7 - Buffer layer; 8 - Stress medium layer; 9 - Gate insulating layer; 10 - Extended gate electrode; 11 - Source electrode; 12 - Drain electrode.

[0058] Figures 1 to 4In the X direction (current flow direction), it can be the <100> crystal orientation or the <110> crystal orientation. The Y direction is the height direction of the device, and the Z direction is the device width direction or can also be the channel width direction; the substrate is the (001) crystal plane. Detailed implementation mode

[0059] The basic design concept of the present invention is:

[0060] The transistor is provided with a stress dielectric layer. The stress dielectric layer applies a positive stress along the X direction to the drift region from three surfaces (the three surfaces are the top surface and two side surfaces) in two dimensions (the two dimensions are Figure 1 in the Y direction and Z direction in the present invention) to the drift region. The positive stress in the X direction applied by the three surfaces in two dimensions is superimposed in the drift region to achieve a greater stress. The superimposed positive stress induces an increase in the carrier mobility in the drift region. At the same time, the stress dielectric layer on the side surface can relieve the stress relaxation at the top; in the off state, the extended gate electrode assists in depleting the drift region to thereby increase the optimal doping concentration of the drift region. In the on state, the carrier accumulation layer formed on the surface of the drift region provides a low-resistance current path, and the partial folded structure improves the channel density and the low-resistance current path density, and the specific on-resistance of the device is greatly reduced. In addition, the planar extended gate electrode on the top of the stress dielectric layer and the planar drain region eliminate the electric field concentration at the corner of the fully folded structure, and the breakdown voltage of the device is increased.

[0061] The present invention is further described in detail below with reference to the accompanying drawings through embodiments.

[0062] This embodiment provides a specific structure of a lateral double-diffused semiconductor field-effect transistor with a stress dielectric layer, as shown in Figure 1 and Figure 2 and includes:

[0063] A substrate 1 of elemental semiconductor material (such as silicon or germanium);

[0064] The upper half of the substrate 1 has a partial folded structure (one protrusion and two grooves), and the ratio of the protrusion height to the protrusion width ranges from 1 to 4, and the ratio of the protrusion height to the device width ranges from 1 / 4 to 1 / 2;

[0065] Base regions 2 and drift regions 3 are respectively formed on the left and right sides of the lower half of the substrate 1. The depths of the base regions 2 and the drift regions 3 are greater than the protrusion height (or the groove depth);

[0066] A source region 4 formed on the surface of the base region 2, and the depth of the source region 4 is greater than the protrusion height (or the groove depth);

[0067] A drain region 5 is formed in the non-folded structure region corresponding to the drift region 3, and the depth of the drain region 5 is greater than the protrusion height (or the groove depth);

[0068] A base substrate contact 6 formed outside the source region 4 in the base region 2;

[0069] A buffer layer 7 (such as silicon dioxide) and a stress medium layer 8 (such as silicon nitride) are formed at the folded structure and at the portion corresponding to the drift region, and both the buffer layer 7 and the stress medium layer 8 are in an inverted "U" shape. The buffer layer 7 is located between the stress medium layer 8 and the drift region 3. Specifically: the length of the stress medium layer 8 is equivalent to the length of the drift region 3, the length of the stress medium layer 8 is equivalent to the length of the drift region 3, the right boundary of the stress medium layer 8 is located on the drain region 5 side in the drift region 3, the left boundary of the stress medium layer 8 is close to the right side of the boundary line between the drift region 3 and the base region 2, and the top of the stress medium layer 8 is a planar structure; the ratio range of the thickness of the stress medium layer 8 to the thickness of the buffer layer 7 is 10 to 100; the ratio range of the height by which the stress medium layer 8 protrudes above the protrusion to the height of the protrusion is 1 / 10 to 1 / 4; the typical value of the intrinsic stress of the stress medium layer 8 is 2 GPa to 4 GPa; the thickness of the stress medium layer 8 at the top of the protrusion is adjusted according to the breakdown voltage requirement. Preferably: the ratio range of the thickness of the stress medium layer 8 at the top of the protrusion to the length of the drift region is 1 / 20 to 1 / 5;

[0070] A gate insulating layer 9 is formed at the folded structure and at the portion corresponding to the base region 2;

[0071] An extended gate electrode 10 is formed on the surface of the gate insulating layer 9 and on the top of the stress medium layer 8; the length of the extended gate electrode 10 is adjusted according to the breakdown voltage requirement. Typically, the right boundary of the extended gate electrode 10 is located between the middle of the drift region 3 and the right boundary of the drift region;

[0072] A source electrode 11 is formed at the folded structure and at the portion corresponding to the contact 6 between the source region 4 and the base region substrate; the source electrode 11 is in an inverted "U" shape;

[0073] A drain electrode 12 with a flat plate structure is formed on the top surface of the drain region 5.

[0074] The stress medium layer 8 deposited on the surface of the folded drift region 3 can apply a positive stress in the X direction to the drift region 3 of the device from two dimensions on three sides. The positive stress in the X direction applied from the three sides is superimposed within the drift region 3, and the superimposed positive stress induces an increase in the carrier mobility within the drift region 3. In addition, when the device is in the off state, the stress medium layer 8 and the extended gate electrode 10 assist in depleting the drift region 3 from three sides in two dimensions, and the optimal doping concentration of the drift region 3 is increased. When in the on state, the MIS structure formed by the extended gate electrode 10, the stress medium layer 8, and the semiconductor substrate 1 forms a carrier accumulation layer on the surface of the drift region 3. The carrier accumulation layer serves as a low-resistance current path to reduce the specific on-resistance of the device. The folded structure increases the channel density and the low-resistance current path density, further reducing the specific on-resistance of the device. The introduction of the stress medium layer 8 eliminates the problem of carrier mobility degradation in the folded drift region 3 due to excessive impurity concentration and carrier accumulation effects. The stress introduced from the side by the stress medium layer 8 can effectively prevent stress relaxation in the direction towards the bottom of the device. In addition, the extended gate electrode 10 located on top of the stress medium layer 8 and the planar drain region 5 eliminate the electric field concentration at the corner of the fully folded structure, avoiding premature breakdown at the corner and increasing the breakdown voltage of the device.

[0075] The device can be fabricated according to the following steps:

[0076] Step 1: Take an elemental semiconductor material as the substrate 1;

[0077] Step 2: Form the base region 2 and the drift region 3 on the substrate 1 by ion implantation or thermal diffusion process;

[0078] Step 3: Form the source region 4 and the drain region 5 on the base region 2 and the drift region 3 by ion implantation respectively;

[0079] Step 4: Form the base substrate contact 6 by ion implantation outside the source region 4 in the base region 2;

[0080] Step 5: Form a partially folded structure on the surface of the substrate 1 outside the drain region 5 by plasma etching;

[0081] Step 6: Grow a buffer layer 7 on the surface of the substrate 1;

[0082] Step 7: Deposit the stress medium layer 8 on the buffer layer 7;

[0083] Step 8: Remove the stress medium layer 8 in the specified region by plasma etching method, and only retain the stress medium layer 8 above the drift region 3;

[0084] Step 9: Remove the buffer layer 7 in the specified region by plasma etching method, and only retain the buffer layer 7 above the drift region 3;

[0085] Step 10: Grow a gate oxide layer 9 on the surface of the substrate 1 and deposit polysilicon, and then etch the polysilicon to form an extended gate electrode 10;

[0086] Step 11: Deposit a passivation layer on the device surface, and then etch contact holes;

[0087] Step 12: Form a source electrode 11 by short-circuiting through the contact holes above the source region 4 and the substrate contact 6 of the base region;

[0088] Step 13: Form a drain electrode 12 through the contact holes above the drain region 5.

[0089] Through simulation tests, for an N-channel LDMOS device with a drift region length of 2 μm, as Figure 5 shown, the intrinsic compressive stress of 2 GPa in the stress medium layer reduces the specific on-resistance of this embodiment from 5.8 mΩ·mm 2 to 4.6 mΩ·mm 2 , and the specific on-resistance is reduced by 20%. Compared with a traditional LDMOS device with a specific on-resistance of 12 mΩ·mm 2 , the specific on-resistance of this embodiment is reduced by 52%. As Figure 6 shown, the breakdown voltage of this embodiment is about 51 V, which is the same as that of the traditional LDMOS device, and no premature breakdown occurs. Compared with the breakdown voltage of the fully folded LDMOS device, the breakdown voltage is increased, which is because the electric field concentration phenomenon in the fully folded structure is eliminated. As Figure 7 shown, the equipotential lines of the stress medium layer are parallel to each other and evenly distributed.

[0090] The above are only the preferred embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the technical principle of the present invention, several improvements and replacements can still be made, and these improvement and replacement solutions also fall within the protection scope of the present invention.

Claims

1. A lateral double-diffused semiconductor field-effect transistor with a stress medium layer, characterized in that: A substrate (1) including a semiconductor material; a partially folded structure is formed on the upper part of the substrate (1) through a trench etching process; Base regions (2) and drift regions (3) are respectively formed on the left and right sides of the lower half of the substrate (1); An active region (4) is formed on the surface of the base region (2); A drain region (5) is formed in the non-folded structure region corresponding to the drift region (3); A base-substrate contact (6) is formed on the left side of the source region (4); A buffer layer (7) and a stress medium layer (8) are formed at the folded structure and corresponding to the part of the drift region, and both the buffer layer (7) and the stress medium layer (8) are in an inverted "U" shape. The buffer layer (7) is located between the stress medium layer (8) and the drift region (3). The length of the stress medium layer (8) is equivalent to the length of the drift region (3). The right boundary of the stress medium layer (8) is located on the side of the drain region (5) in the drift region (3). The left boundary of the stress medium layer (8) is close to the right side of the demarcation line between the drift region (3) and the base region (2); A gate insulating layer (9) is formed at the folded structure and corresponding to the part of the base region (2); An extended gate electrode (10) is formed on the surface of the gate insulating layer (9) and on the top of the stress medium layer (8); the length of the extended gate electrode (10) is adjusted according to the breakdown voltage requirement; A source electrode (11) is formed at the folded structure and corresponding to the part of the source region (4) and the base-substrate contact (6); the source electrode (11) is in an inverted "U" shape; A drain electrode (12) with a flat structure is formed on the top surface of the drain region (5).

2. The lateral double-diffused semiconductor field-effect transistor with a stress medium layer according to claim 1, characterized in that: The ratio range of the height to the width of the protrusion in the folded structure is 1 - 4.

3. The lateral double-diffused semiconductor field effect transistor with a stress medium layer according to claim 1, wherein: The ratio range of the width of the protrusion in the folded structure to the width of the substrate is 1 / 4 - 1 / 2.

4. The lateral double-diffused semiconductor field-effect transistor having a stress medium layer according to claim 1, characterized in that: The ratio range of the thickness of the stress medium layer (8) located at the top of the protrusion to the length of the drift region is 1 / 20 - 1 / 5.

5. The lateral double-diffused semiconductor field effect transistor having a stress medium layer according to claim 1, wherein: The ratio of the thickness of the stress medium layer (8) to the thickness of the buffer layer (7) is 10 - 100.

6. The lateral double-diffused semiconductor field-effect transistor with a stress medium layer according to claim 1, characterized in that: The typical value of the intrinsic stress of the stress medium layer (8) is 2 GPa - 4 GPa.

7. A method for fabricating the lateral double-diffused semiconductor field effect transistor with a stress medium layer as described in claim 1, characterized in that, Including the following steps: Step 1: Take a semiconductor material as the substrate (1); Step 2: Form the base region (2) and the drift region (3) on the substrate (1) through ion implantation or thermal diffusion process; Step 3: Respectively form the source region (4) and the drain region (5) in the base region (2) and the drift region (3) through ion implantation; Step 4: Form the base-substrate contact (6) in the base region (2) outside the source region (4) through ion implantation; Step 5: Form a partially folded structure on the surface of the substrate (1) in the region outside the drain region (5) through plasma etching; Step 6: Grow the buffer layer (7) on the surface of the substrate (1); Step 7: Deposit the stress medium layer (8) on the buffer layer (7), and by adjusting the deposition process parameters, the medium layer (8) has intrinsic stress; Step 8: Etch the stress medium layer (8) through plasma etching, and only retain the stress medium layer (8) above the drift region (3); Step 9: Etch the buffer layer (7) through plasma etching, and only retain the buffer layer (7) above the drift region (3); Step 10: Grow a gate oxide layer (9) on the surface of the substrate (1) and deposit polysilicon, and then etch the polysilicon to form an extended gate electrode (10); Step 11: Deposit a passivation layer on the device surface, and then etch contact holes; Step 12: Form a source electrode (11) by short-circuiting through contact holes above the source region (4) and the base region substrate contact (6); Step 13: Form a drain electrode (12) through a contact hole above the drain region (5).

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