Clock Signal Dynamic Alignment Method and Phase Aligner

Abstract

The present invention discloses a clock dynamic alignment method and phase aligner. The method comprises: generating a plurality of discrete-phase derived clocks from an original clock; iteratively adjusting the output clock until the rising edge of the output clock is between the rising edge of the original clock and the rising edge of a first derived clock; the first derived clock being the derived clock with the smallest phase deviation from the original clock; and comparing the rising edge of the output clock with the original clock and the first derived clock during each iterative adjustment. A count value is updated based on the comparison result, and a derived clock is selected from each derived clock based on the updated count value as a selected derived clock. The selected derived clock is input into a programmable logic block array, and the adjusted output clock is then obtained from the end of the programmable logic block array. By implementing the present invention, dynamic compensation can be performed based on temperature or voltage changes in an FPGA, thereby improving the phase alignment of the output clock with the original clock.

Description

Technical Field

[0001] The present invention relates to the technical field of digital chip design, and in particular to a clock dynamic alignment method and a phase aligner. Background Art

[0002] An FPGA is a programmable device that contains an array of user-programmable logic blocks and customizable hard cores. Sometimes, the hard core generates a clock that needs to be fed into the programmable logic array. In this case, the raw clock signal from the hard core is typically routed to a global / local clock driver and then driven by the user program in the fabric (the programmable logic array) through the global / local clock network. However, the raw clock signal is delayed within the programmable logic array. Typically, due to delays in the global / local clock driver and the programmable logic array, the raw clock signal's phase deviates significantly from the phase provided by the hard core by the time it reaches the end of the programmable logic array. To address this issue, existing technologies use PLLs (phase-locked loops) to achieve phase alignment. In practice, this typically involves aligning the rising edge of the output signal at the end of the programmable logic array to a position close to the rising edge of the raw clock signal, achieving macroscopic phase alignment. However, PLLs employ a fixed phase shift approach, achieving fixed phase shift compensation through a pre-set phase shift amplitude. The delay of the raw clock signal within the programmable logic array varies with the temperature or voltage of the FPGA. Existing PLLs cannot dynamically compensate for these temperature or voltage changes, resulting in poor phase alignment. Summary of the Invention

[0003] The embodiment of the present invention provides a clock dynamic alignment method and a phase aligner, which can dynamically compensate according to the temperature or voltage changes of the FPGA, thereby improving the phase alignment effect of the output clock and the original clock.

[0004] An embodiment of the present invention provides a clock dynamic alignment method, comprising: obtaining an original clock generated by a hard core and an output clock at an end of a programmable logic block array;

[0005] Generating a plurality of derived clocks with discrete phases based on the original clock; wherein the phase of each derived clock has a different phase deviation value from the original clock;

[0006] Iteratively adjusting the output clock until the rising edge of the output clock is between the rising edge of the original clock and the rising edge of a first derived clock; wherein the first derived clock is a derived clock having the smallest phase deviation from the original clock;

[0007] During each iterative adjustment, the rising edge of the output clock is compared with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock, the rising edge of the original clock, and the rising edge of the first derived clock. A count value is updated based on the relative position, and a derived clock is selected from each derived clock based on the updated count value as a selected derived clock. The selected derived clock is input into the programmable logic block array, and then the adjusted output clock is obtained from the end of the programmable logic block array.

[0008] Furthermore, the step of generating a plurality of discrete phase derived clocks based on the original clock specifically includes:

[0009] The original clock is input into each delay unit connected in series in sequence, so that each delay unit outputs a corresponding derived clock, thereby obtaining derived clocks of several discrete phases.

[0010] Furthermore, comparing the rising edge of the output clock with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock with the rising edge of the original clock and the rising edge of the first derived clock specifically includes:

[0011] Sampling the original clock and the first derived clock respectively according to the output clock to obtain a first sampling vector;

[0012] Sampling the output clock according to the original clock and the first derived clock respectively to obtain a second sampling vector;

[0013] The relative positions of the rising edge of the output clock, the rising edge of the original clock, and the rising edge of the first derived clock are determined according to the first sampling vector and the second sampling vector.

[0014] Furthermore, updating the count value according to the relative position specifically includes:

[0015] If the rising edge of the output clock is before the rising edge of the original clock and the rising edge of the first derived clock, generating a first pulse signal, and increasing the count value by one according to the first pulse signal;

[0016] If the rising edge of the output clock is later than the rising edge of the original clock and the rising edge of the first derived clock, a second pulse signal is generated, and the count value is reduced by one according to the second pulse signal;

[0017] If the rising edge of the output clock is between the rising edge of the original clock and the rising edge of the first derived clock, no pulse signal is generated and the count value remains unchanged.

[0018] Based on the above method embodiment, an embodiment of the present invention provides a phase aligner; the phase aligner includes: a delayer, a multiplexer, a comparator, and a counter;

[0019] The delayer is used to generate a plurality of discrete phase derived clocks according to the original clock generated by the hard core; wherein the phase of each derived clock has a different deviation value from the phase of the original clock;

[0020] The multiplexer is configured to select a derived clock from the derived clocks as a selected derived clock according to a current count value, and output the selected derived clock to the programmable logic block array;

[0021] The comparator is configured to obtain an output clock from an end of the programmable logic block array, compare a rising edge of the output clock with the original clock and a first derived clock, and determine a relative position of the rising edge of the output clock to the rising edges of the original clock and the first derived clock; wherein the first derived clock is a derived clock having a minimum phase deviation from the original clock;

[0022] The counter is used to update the count value according to the relative position.

[0023] Furthermore, the comparator compares the rising edge of the output clock with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock with the rising edge of the original clock and the rising edge of the first derived clock, specifically including:

[0024] Sampling the original clock and the first derived clock respectively according to the output clock to obtain a first sampling vector;

[0025] Sampling the output clock according to the original clock and the first derived clock respectively to obtain a second sampling vector;

[0026] The relative positions of the rising edge of the output clock, the rising edge of the original clock, and the rising edge of the first derived clock are determined according to the first sampling vector and the second sampling vector.

[0027] Furthermore, it also includes: a direction analyzer;

[0028] If the rising edge of the output clock is before the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer outputs a first pulse signal to the counter;

[0029] If the rising edge of the output clock is after the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer outputs a second pulse signal to the counter;

[0030] If the rising edge of the output clock is between the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer does not output a pulse signal.

[0031] Furthermore, the counter is used to update the count value according to the relative position, specifically including:

[0032] When the first pulse signal is received, the count value is increased by one; when the second pulse signal is received, the count value is decreased by one; when no pulse signal is received, the count value remains unchanged.

[0033] The following beneficial effects are achieved by implementing the embodiments of the present invention:

[0034] An embodiment of the present invention provides a clock signal dynamic alignment method and a phase aligner. The method iteratively adjusts the output clock signal during phase alignment. During each iterative adjustment, the rising edge of the output clock is compared with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock, the rising edge of the original clock, and the rising edge of the first derived clock. The relative position during each iteration can be used to determine the direction of the delay change of the output signal during each adjustment, and thus the delay change caused by temperature and voltage changes. The count value is then updated according to the relative position, and a derived clock is selected from each derived clock as the selected derived clock according to the updated count value. This allows the derived clock with the closest phase to be dynamically selected according to the direction of the delay change, thereby achieving dynamic compensation and improving the accuracy of phase alignment. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The present invention provides a flow chart of a method for dynamic clock alignment according to an embodiment of the present invention.

[0036] Figure 2 This is a structural diagram of a phase aligner provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0037] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0038] First, let's explain the Chinese meanings of some of the English words that may be involved below: FPGA: Field Programmable Gate Array; Fabric: Structure, construction, refers to the programmable logic block array in FPGA; Delay Unit:

[0039] Delay unit; MUX (multiplexer): multiplexer; Comparer: comparator; DirectionAnalyzer: direction analyzer; Counter: counter; Delay Lines: delay (delay line formed by cascading multiple Delay Units); PLL: phase-locked loop; Hard Core: hard core; clock_original: original clock generated by the hard core; clock_compared: output clock given at the end of the programmable logic block array; clock_d[0]-clock_d[2^n-1]: each derived clock; clock_aligned: selected derived clock selected according to the count value; clock_d[0]: the derived clock with the smallest phase deviation from the original clock, that is, the first derived clock.

[0040] like Figure 1 As shown, an embodiment of the present invention provides a clock dynamic alignment method, including:

[0041] Step S101: Acquire the original clock generated by the hard core and the output clock at the end of the programmable logic block array.

[0042] Step S102: Generate a plurality of discrete phase derived clocks according to the original clock; wherein the phase of each derived clock is different from the phase deviation value of the original clock,

[0043] Step S103: iteratively adjust the output clock until the rising edge of the output clock is between the rising edge of the original clock and the rising edge of the first derived clock; wherein the first derived clock is the derived clock with the smallest phase deviation from the original clock; during each iterative adjustment, the rising edge of the output clock is compared with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock to the rising edge of the original clock and the rising edge of the first derived clock, update the count value according to the relative position, select a derived clock from each derived clock according to the updated count value as the selected derived clock, input the selected derived clock into the programmable logic block array, and then obtain the adjusted output clock from the end of the programmable logic block array.

[0044] In step S101, the original clock generated by the hard core and the output clock provided by the programmable logic block array (Fabric) are directly obtained. Due to the delay in the Fabric, the phase of the output clock has already deviated significantly from the phase of the original clock. Therefore, the output clock needs to be phase compensated so that the phase of the output clock is close to or even completely aligned with the phase of the original clock to achieve phase alignment.

[0045] With respect to step S102, in a preferred implementation, generating a plurality of discrete-phase derived clocks based on the original clock specifically includes: inputting the original clock into each delay unit connected in series, so that each delay unit outputs a corresponding derived clock, thereby obtaining a plurality of discrete-phase derived clocks.

[0046] Specifically, in the present invention, 2^n delay units are connected in series to form a delayer, and then the original clock is input into the delayer. Then, each delay unit outputs a derived clock with a different phase from the original clock, and the phases between the derived clocks are also different, thereby obtaining derived clocks with several discrete phases. In addition, the 2^n delay units need to cover one cycle of clock_original.

[0047] For step S103, in a preferred implementation, comparing the rising edge of the output clock with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock to the rising edge of the original clock and the rising edge of the first derived clock specifically includes: sampling the original clock and the first derived clock according to the output clock to obtain a first sampling vector; sampling the output clock according to the original clock and the first derived clock to obtain a second sampling vector; and determining the relative position of the rising edge of the output clock to the rising edge of the original clock and the rising edge of the first derived clock according to the first sampling vector and the second sampling vector.

[0048] In a preferred embodiment, updating the count value according to the relative position specifically includes: if the rising edge of the output clock is before the rising edge of the original clock and the rising edge of the first derived clock, generating a first pulse signal, and adding one to the count value according to the first pulse signal; if the rising edge of the output clock is after the rising edge of the original clock and the rising edge of the first derived clock, generating a second pulse signal, and subtracting one from the count value according to the second pulse signal; if the rising edge of the output clock is between the rising edge of the original clock and the rising edge of the first derived clock, no pulse signal is generated, and the count value remains unchanged.

[0049] The following is a detailed description of the entire process of iterative adjustment of the output clock:

[0050] Step 1: Get clock_d[0], clock_original, and clock_compared. clock_d[0], clock_original, and clock_compared are clocks with the same frequency; then use clock_compared to sample clock_original and clock_d[0] to get the first sampling vector: Vector_c_t[1:0]; use clock_original and clock_d[0] to sample clock_compared to get the second sampling vector Vector_t_c[1:0];

[0051] Step 2: Based on the values of Vector_c_t[1:0] and Vector_t_c[1:0], determine the relative positions of the rising edge of clock_compared, the rising edge of clock_original, and the rising edge of clock_d[0].

[0052] Schematically: If Vector_c_t[1:0]=2b00, Vector_t_c[1:0]=2b11, the rising edge of clock_compared is before the rising edge of clock_original and clock_d[0].

[0053] If Vector_c_t[1:0]=2b11, Vector_t_c[1:0]=2b00, the rising edge of clock_compared is after the rising edges of clock_original and clock_d[0].

[0054] If Vector_c_t[2:0]=2b10, Vector_t_c[1:0]=2b01, the rising edge of clock_compared is between clock_original and clock_d[0].

[0055] Step 3: Control the adjustment direction of the count value based on the relative position determined above. Specifically, if the rising edge of clock_compared is before the rising edge of clock_original and clock_d[0], generate a first pulse signal, preferably a low-level signal (0 signal), and then increase the count value by 1 according to the first pulse signal.

[0056] If the rising edge of clock_compared is after the rising edge of clock_original and clock_d[0], a second pulse signal is generated, preferably a high-level signal (1 signal), and then the count value is reduced by 1 according to the first pulse signal;

[0057] If the rising edge of clock_compared is between the rising edges of clock_original and clock_d[0], no pulse signal is generated and the count value remains unchanged.

[0058] Step 4: After updating the count, select the corresponding derived clock from the multiple derived clocks based on the count value as the selected derived clock. The selected derived clock is then output to the programmable logic block array, and the adjusted output clock is finally obtained at the end of the programmable logic block array. This step implements a phase adjustment of the output clock. It should be noted that when the initial count value is 0, the derived clock corresponding to the initial count value is clock_d[0]. When the count value is 1, the derived clock corresponding to the initial count value is clock_d[1]. When the count value is 2, the derived clock corresponding to the initial count value is clock_d[2], and so on.

[0059] Step 5: Repeat steps 1, 2, 3, and 4 until the rising edge of the output clock at the end of the programmable logic block array is between the rising edges of clock_original and clock_d[0], completing the phase alignment between the output clock and the original clock. The phase of the aligned output clock achieves macroscopic phase alignment between the original clock and the first derived clock.

[0060] The clock dynamic alignment method disclosed in the above-mentioned embodiment of the present invention can determine the direction of delay change caused by temperature and voltage changes based on the relative position of the rising edge of clock_compared and clock_original and clock_d[0]. Then, the count value is controlled to count up or down, thereby selecting the optimal selected derived clock from each derived clock, so that the phase of the output clock output by the selected derived clock after the delay within the programmable logic block array is closest to the original clock. When the delay amount within the programmable logic block array changes with temperature and voltage, the selected derived clock will also change, thereby achieving dynamic phase compensation and improving the accuracy of phase alignment.

[0061] like Figure 2 As shown, an embodiment of the present invention provides a phase aligner, comprising: a delayer, a multiplexer, a comparator, and a counter;

[0062] The delayer is used to generate a plurality of discrete phase derived clocks according to the original clock generated by the hard core; wherein the phase of each derived clock has a different deviation value from the phase of the original clock;

[0063] The multiplexer is configured to select a derived clock from the derived clocks as a selected derived clock according to a current count value, and output the selected derived clock to the programmable logic block array;

[0064] The comparator is configured to obtain an output clock from an end of the programmable logic block array, compare a rising edge of the output clock with the original clock and a first derived clock, and determine a relative position of the rising edge of the output clock to the rising edges of the original clock and the first derived clock; wherein the first derived clock is a derived clock having a minimum phase deviation from the original clock;

[0065] The counter is used to update the count value according to the relative position.

[0066] In a preferred embodiment, the comparator compares the rising edge of the output clock with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock with the rising edge of the original clock and the rising edge of the first derived clock, specifically including:

[0067] Sampling the original clock and the first derived clock respectively according to the output clock to obtain a first sampling vector;

[0068] Sampling the output clock according to the original clock and the first derived clock respectively to obtain a second sampling vector;

[0069] The relative positions of the rising edge of the output clock, the rising edge of the original clock, and the rising edge of the first derived clock are determined according to the first sampling vector and the second sampling vector.

[0070] In a preferred embodiment, it further comprises: a direction analyzer;

[0071] If the rising edge of the output clock is before the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer outputs a first pulse signal to the counter;

[0072] If the rising edge of the output clock is after the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer outputs a second pulse signal to the counter;

[0073] If the rising edge of the output clock is between the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer does not output a pulse signal.

[0074] In a preferred embodiment, the counter is used to update the count value according to the relative position, specifically including:

[0075] When the first pulse signal is received, the count value is increased by one; when the second pulse signal is received, the count value is decreased by one; when no pulse signal is received, the count value remains unchanged.

[0076] The following combination Figure 2 The working principle of the phase aligner provided by the present invention is described.

[0077] The delay lines are composed of 2^n delay units connected in series. They receive the input clock_original and generate various derived clocks clock_d[0]-clock_d[2^n-1], and then output each derived clock to the multiplexer (MUX).

[0078] The multiplexer (MUX) is used to select a derived clock Clock_aligned from clock_d[0]-clock_d[2^n-1] based on the count value transmitted by the counter (Counter); and input Clock_aligned into the programmable logic block array (Fabric). Then, after the delay of the programmable logic block array, Clock_aligned forms the output signal clock_compared at the end of the programmable logic block array.

[0079] The comparator is used to compare the phases of the clock signals. Specifically, the comparator obtains clock_d[0], clock_original, and clock_compared. Then, clock_compared is used to sample clock_original and clock_d[0] to obtain the first sampling vector: Vector_c_t[1:0]. Clock_original and clock_d[0] are used to sample clock_compared to obtain the second sampling vector Vector_t_c[1:0]. Then, Vector_c_t[1:0] and Vector_t_c[1:0] are input to the direction analyzer.

[0080] A direction analyzer determines, based on the first sampling vector and the second sampling vector, whether the rising edge of clock_compared is before, after, or between clock_original and clock_d[0].

[0081] If Vector_c_t[1:0]=2b00, Vector_t_c[1:0]=2b11, it is determined that the rising edge of clock_compared is before the rising edges of clock_original and clock_d[0]. At this time, the direction analyzer sends the first pulse signal, 0 signal, to the counter.

[0082] If Vector_c_t[1:0]=2b11, Vector_t_c[1:0]=2b00, it is determined that the rising edge of clock_compared is after the rising edge of clock_original and clock_d[0]. At this time, the direction analyzer sends the second pulse signal, 1 signal, to the counter.

[0083] If Vector_c_t[2:0]=2b10, Vector_t_c[1:0]=2b01, it is determined that the rising edge of clock_compared is between clock_original and clock_d[0]. At this time, the direction analyzer does not send a pulse signal to the counter.

[0084] The counter increases the count value by one when receiving the first pulse signal, decreases the count value by one when receiving the second pulse signal, and keeps the count value unchanged if no pulse signal is received.

[0085] During the initialization of the entire phase aligner, the Direction Analyzer controls the Counter to quickly increase the count value, so that the phase of clock_aligned selected by the control MUX from the Delay Lines also moves quickly until the rising edge of clock_compared is between clock_original and clock_d[0], achieving rapid phase alignment.

[0086] After initialization is complete, the voltage and temperature compensation phase begins, operating periodically. The DirectionAnalyzer submodule controls the output count value of the Counter submodule to increment, decrement, or remain unchanged, depending on whether the rising edge of clock_compared is before, after, or between clock_original and clock_d[0]. This ensures that the rising edge of clock_compared falls between clock_original and clock_dl[0], achieving phase compensation.

[0087] The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A clock dynamic alignment method, characterized in that: include: Get the original clock generated by the hard core and the output clock at the end of the programmable logic block array; Generating a plurality of derived clocks with discrete phases based on the original clock; wherein the phase of each derived clock has a different phase deviation value from the original clock; Iteratively adjusting the output clock until the rising edge of the output clock is between the rising edge of the original clock and the rising edge of a first derived clock; wherein the first derived clock is a derived clock having the smallest phase deviation from the original clock; During each iterative adjustment, the rising edge of the output clock is compared with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock to the rising edge of the original clock and the rising edge of the first derived clock, and a count value is updated according to the relative position. A derived clock is selected from each derived clock according to the updated count value as a selected derived clock, and the selected derived clock is input into the programmable logic block array. Then, an adjusted output clock is obtained from an end of the programmable logic block array and the adjusted output clock is used as the output clock. The comparing the rising edge of the output clock with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock to the rising edge of the original clock and the rising edge of the first derived clock specifically includes: sampling the original clock and the first derived clock according to the output clock to obtain a first sampling vector; sampling the output clock according to the original clock and the first derived clock to obtain a second sampling vector; and determining the relative position of the rising edge of the output clock to the rising edge of the original clock and the rising edge of the first derived clock according to the first sampling vector and the second sampling vector; The updating of the count value according to the relative position specifically includes: if the rising edge of the output clock is before the rising edge of the original clock and the rising edge of the first derived clock, a first pulse signal is generated, and the count value is increased by one according to the first pulse signal; if the rising edge of the output clock is after the rising edge of the original clock and the rising edge of the first derived clock, a second pulse signal is generated, and the count value is reduced by one according to the second pulse signal; if the rising edge of the output clock is between the rising edge of the original clock and the rising edge of the first derived clock, no pulse signal is generated, and the count value is kept unchanged.

2. The clock dynamic alignment method according to claim 1, wherein: The step of generating a plurality of derived clocks of discrete phases according to the original clock specifically includes: The original clock is input into each delay unit connected in series in sequence, so that each delay unit outputs a corresponding derived clock, thereby obtaining derived clocks of several discrete phases.

3. A phase aligner, characterized in that: include: Delays, multiplexers, comparators, counters, and direction analyzers; The delayer is used to generate a plurality of discrete phase derived clocks according to the original clock generated by the hard core; wherein the phase of each derived clock has a different deviation value from the phase of the original clock; The multiplexer is configured to select a derived clock from the derived clocks as a selected derived clock according to a current count value, and output the selected derived clock to the programmable logic block array; The comparator is configured to obtain an output clock from an end of the programmable logic block array, compare a rising edge of the output clock with the original clock and a first derived clock, and determine a relative position of the rising edge of the output clock to the rising edges of the original clock and the first derived clock; wherein the first derived clock is a derived clock having a minimum phase deviation from the original clock; The counter is used to update the count value according to the relative position; The comparing the rising edge of the output clock with the original clock and the first derived clock to determine the relative position of the rising edge of the output clock to the rising edge of the original clock and the rising edge of the first derived clock specifically includes: sampling the original clock and the first derived clock according to the output clock to obtain a first sampling vector; sampling the output clock according to the original clock and the first derived clock to obtain a second sampling vector; and determining the relative position of the rising edge of the output clock to the rising edge of the original clock and the rising edge of the first derived clock according to the first sampling vector and the second sampling vector; If the rising edge of the output clock is before the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer outputs a first pulse signal to the counter; if the rising edge of the output clock is after the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer outputs a second pulse signal to the counter; if the rising edge of the output clock is between the rising edge of the original clock and the rising edge of the first derived clock, the direction analyzer does not output a pulse signal.

4. The phase aligner according to claim 3, wherein: The counter is used to update the count value according to the relative position, specifically including: When the first pulse signal is received, the count value is increased by one; when the second pulse signal is received, the count value is decreased by one; when no pulse signal is received, the count value remains unchanged.

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