Manufacturing Method of Array Substrate, Array Substrate, Display Device, and Detection Unit

Abstract

A method of manufacturing an array substrate is provided. The method includes providing a substrate including a gate pad configured to bond a gate driver integrated circuit, a data pad configured to bond a data driver integrated circuit, and a plurality of peripheral layout gate (PLG) primitive lines connecting the gate pad and the data pad; forming a PLG test pad on the substrate; forming a shorting bar connecting the PLG test pad to a first terminal of the plurality of PLG primitive lines; forming a plurality of test pins respectively connected to second terminals of the plurality of PLG primitive lines, wherein the plurality of test pins are formed in a first dummy region of the substrate, and the first dummy region is adjacent to an array substrate region of the substrate; and connecting the plurality of test pins to a probing unit to test the connectivity of the plurality of PLG primitive lines.

Description

Technical Field

[0001] The present invention relates to display technology, and in particular, to a method for manufacturing an array substrate, an array substrate, a display device, and a detection unit. Background Art

[0002] Generally, a mother board is manufactured to include a plurality of array substrate regions, and then the mother board is cut into a plurality of array substrates. Before cutting the mother board, the connectivity of the gate lines and data lines is tested. To test the connectivity of the gate lines and data lines in the substrate, a detection unit can be used to load signals into the lead regions of the substrate pads. A plurality of detection blocks can respectively correspond to a plurality of lead regions of the substrate. The test electrodes in contact with the detection blocks can be connected to the gate lines and data lines on the array substrate through test lines, so that the test electrodes can send test signals from the gate lines and data lines or send test signals to the gate lines and data lines. Summary of the Invention

[0003] In one aspect, the present disclosure provides a method for manufacturing an array substrate, including: providing a substrate, the substrate including gate pads configured to engage a gate driver integrated circuit, data pads configured to engage a data driver integrated circuit, and a plurality of peripheral layout gate (PLG) primitive lines connecting the gate pads and the data pads; forming PLG test pads on the substrate; forming shorting bars that connect the PLG test pads to a first terminal of the plurality of PLG primitive lines; forming a plurality of test pins, the plurality of test pins being respectively connected to a second terminal of the plurality of PLG primitive lines, wherein the plurality of test pins are formed in a first dummy region of the substrate, the first dummy region being adjacent to the array substrate region of the substrate; and connecting the plurality of test pins to a detection unit to test the connectivity of the plurality of PLG primitive lines.

[0004] Optionally, before providing the substrate, further including forming a plurality of additional pads between the data pads and the gate pads; wherein each of the plurality of PLG primitive lines is formed to extend from a corresponding first terminal to a corresponding second terminal, the corresponding second terminal being connected to a corresponding one of the plurality of test pins; and each of the plurality of PLG primitive lines includes a first portion and a second portion respectively located in the array substrate region and respectively on two sides of a corresponding additional pad in the plurality of additional pads, and a connecting portion connecting the first portion and the second portion, the connecting portion being in the first dummy region.

[0005] Optionally, connecting the plurality of test pins to the probing unit includes connecting the plurality of test pins to a printed circuit board of the probing unit through a probing block of the probing unit, so as to electrically connect the plurality of test pins with a quantity of N to gates of a plurality of transistors with a quantity of N connected in series in the printed circuit board; wherein a first test pin among the plurality of test pins with a quantity of N is further electrically connected to a source of a first transistor among the plurality of transistors with a quantity of N; a drain of a last transistor among the plurality of transistors with a quantity of N is electrically connected to a light-emitting element of the printed circuit board; a source of an nth transistor between the first transistor and the last transistor is connected to a drain of an (n - 1)th transistor, 1 < n < N; and a drain of the nth transistor is connected to a source of an (n + 1)th transistor.

[0006] Optionally, the method further includes providing a test voltage signal to the PLG test pad; wherein, when the test voltage signal is provided to the PLG test pad, the light-emitting element in the off state indicates that the connectivity of at least one of the plurality of PLG original wires is damaged.

[0007] Optionally, the method further includes providing a test voltage signal to the PLG test pad; wherein, when the test voltage signal is provided to the PLG test pad, the light-emitting element in the on state indicates that the connectivity of each of the plurality of PLG original wires is intact.

[0008] Optionally, the method further includes cutting the substrate to form an array substrate based on the light-emitting element being in the on state; wherein the plurality of PLG original wires are cut to form a plurality of PLG wires, and the plurality of PLG wires are configured to transmit signals between a gate driver integrated circuit and a data driver integrated circuit in a display device having the array substrate, wherein the gate driver integrated circuit is bonded to the gate pad, and the data driver integrated circuit is bonded to the data pad.

[0009] Optionally, before setting the substrate, it further includes forming a plurality of additional pads between the data pads and the gate pads; wherein each of the plurality of PLG original wires is formed to extend from a corresponding first terminal to a corresponding second terminal, and the corresponding second terminal is connected to a corresponding one of the plurality of test pins; and each of the plurality of PLG original wires includes a first portion and a second portion respectively in the array substrate area and on both sides of a corresponding one of the plurality of additional pads, and a connecting portion connecting the first portion and the second portion, the connecting portion being in the first dummy area; and cutting each of the plurality of PLG original wires along a first cutting line, thereby removing the connecting portion.

[0010] Optionally, cut the plurality of PLG original wires along a first cutting line between the first dummy area and the array substrate area, thereby removing the plurality of test pins.

[0011] Optionally, cut the plurality of PLG original wires along a second cutting line between a second dummy area and the array substrate area, thereby removing the shorting bars.

[0012] Optionally, the plurality of additional pads are a plurality of additional gate pads; the gate pads and the plurality of additional gate pads are directly adjacent to the first cutting line between the array substrate area and the first dummy area respectively; the data pads are directly adjacent to the second cutting line between the array substrate area and the second dummy area; and the shorting bars and the first terminals are located in the second dummy area.

[0013] Optionally, before setting the substrate, it further includes forming a plurality of gate lines and a plurality of gate line leads respectively connected to the plurality of gate lines; the plurality of gate line leads, the first portion and the second portion respectively extend at least partially into a corresponding one of the plurality of additional pads; the first portion is located on a first side of the plurality of gate line leads; and the second portion is located on a second side of the plurality of gate line leads.

[0014] Optionally, the method further includes using a plurality of data line test pads and a plurality of data lead shorting bars to test the connectivity of a plurality of data lines in the substrate; wherein the plurality of PLG original wires and the plurality of data leads respectively extend at least partially into the data pads; and the plurality of data leads are respectively connected to the plurality of data lines.

[0015] In another aspect, the present disclosure provides an array substrate manufactured by the method described herein.

[0016] In another aspect, the present disclosure provides a display device including the array substrate described herein or an array substrate manufactured by the method described herein, a gate driver integrated circuit bonded to the gate pad, and a data driver integrated circuit bonded to the data pad.

[0017] In another aspect, the present disclosure provides a probing unit for testing the connectivity of a plurality of PLG primitive wires in a substrate, including: a printed circuit board; a probing block; and N connection lines respectively connecting the probing block and the printed circuit board; wherein, the printed circuit board includes: N transistors connected in series; and a light-emitting element; wherein, the gates of the N transistors are respectively electrically connected to the N connection lines; the source of the first transistor among the N transistors is electrically connected to the first connection line among the N connection lines; the drain of the last transistor among the N transistors is electrically connected to the light-emitting element; the source of the nth transistor between the first transistor and the last transistor is connected to the drain of the (n - 1)th transistor, 1 < n < N; and the drain of the nth transistor is connected to the source of the (n + 1)th transistor.

[0018] In another aspect, the present disclosure provides an array substrate, including: a gate pad configured to bond a gate driver integrated circuit; a data pad configured to bond a data driver integrated circuit; a plurality of peripheral layout gate (PLG) lines configured to transmit signals between a gate driver integrated circuit bonded to the gate pad and a data driver integrated circuit bonded to the data pad; a PLG test pad; and a plurality of first test pads.

[0019] Optionally, the array substrate further includes: a plurality of additional pads located between the data pad and the gate pad; and a plurality of additional PLG lines configured to transmit signals between adjacent additional pads. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] According to various disclosed embodiments, the following drawings are merely examples for illustrative purposes and are not intended to limit the scope of the present invention.

[0021] Figure 1 A substrate for manufacturing an array substrate according to some embodiments of the present disclosure is shown.

[0022] Figure 2 is Figure 1 a partial view of the structure of the substrate in the enlarged area.

[0023] Figure 3Shows a method for manufacturing an array substrate according to some embodiments of the present disclosure.

[0024] Figure 4 Is a partial view of the structure of a substrate according to some embodiments of the present disclosure.

[0025] Figure 5 Shows a method for manufacturing an array substrate according to some embodiments of the present disclosure.

[0026] Figure 6 Is a schematic diagram showing the structure of a detection unit according to some embodiments of the present disclosure.

[0027] Figure 7 Is a partial view of an array substrate manufactured by a method according to some embodiments of the present disclosure.

[0028] Figure 8 Is a partial view of the structure of a substrate according to some embodiments of the present disclosure.

[0029] Figure 9 Shows the structure of a plurality of PLG proto-lines around an additional pad according to some embodiments of the present disclosure.

[0030] Figure 10 Shows a method for manufacturing an array substrate according to some embodiments of the present disclosure.

[0031] Figure 11 Is a partial view of an array substrate manufactured by a method according to some embodiments of the present disclosure. Detailed Description

[0032] The present disclosure will now be described more specifically with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the exact forms disclosed.

[0033] The present disclosure particularly provides a method for manufacturing an array substrate, an array substrate, a display device, and a detection unit, which substantially overcome one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, the present disclosure provides a method for manufacturing an array substrate. In some embodiments, the method includes providing a substrate, the substrate including gate pads configured to bond with a gate driver integrated circuit, data pads configured to bond with a data driver integrated circuit, and a plurality of peripheral layout gate (PLG) primitive lines connecting the gate pads and the data pads; forming PLG test pads on the substrate; forming shorting bars that connect the PLG test pads to a first terminal of the plurality of PLG primitive lines; forming a plurality of test pins respectively connected to a second terminal of the plurality of PLG primitive lines, wherein the plurality of test pins are formed in a first dummy region of the substrate, the first dummy region being adjacent to an array substrate region of the substrate; and connecting the plurality of test pins to a detection unit to test the connectivity of the plurality of PLG primitive lines.

[0034] Figure 1 is a substrate for manufacturing an array substrate according to some embodiments of the present disclosure. Referring to Figure 1 , substrate S is provided to manufacture an array substrate. After testing the connectivity of signal lines in substrate S, substrate S is cut to form an array substrate. For example, substrate S can be cut along a first cutting line CL1 and along a second cutting line CL2. Thus, substrate S includes an array substrate region ASR, a first dummy region DR1, and a second dummy region DR2. The first cutting line CL1 is a first boundary line between the first dummy region DR1 and the array substrate region ASR. The second cutting line CL2 is a second boundary line between the second dummy region DR2 and the array substrate region ASR.

[0035] Figure 2 is Figure 1 a partial view of the structure of the substrate in the enlarged region in Figure 2 shown in Figure 1 the structure of substrate S in the enlarged region ZR in Figure 2 . Referring to

[0036] Referring toFigure 2 In some embodiments, the substrate further includes a plurality of first test pads TP1 and a plurality of second test pads TP2. Optionally, the substrate further includes a plurality of first shorting bars SB1, which are used to test the connectivity of the plurality of first signal lines and the plurality of second signal lines. In one example, the plurality of first signal lines are a plurality of data lines, and the plurality of second signal lines are a plurality of gate lines. In another example, the plurality of first signal lines are a plurality of gate lines, and the plurality of second signal lines are a plurality of data lines. The substrate further includes a plurality of first leads Lw1 respectively connected to the plurality of first signal lines and a plurality of second leads Lw2 respectively connected to the plurality of second signal lines. The plurality of first leads Lw1 at least partially extend into the first pad PAD1, and the plurality of second leads Lw2 at least partially extend into the second pad PAD2. In one example, the plurality of first leads Lw1 are a plurality of data leads respectively connected to the plurality of data lines, and the plurality of second leads Lw2 are a plurality of gate line leads respectively connected to the plurality of gate lines. In another example, the plurality of first lead lines Lw1 are a plurality of gate line leads respectively connected to a plurality of gate lines, and the plurality of second lead lines Lw2 are a plurality of data lead lines respectively connected to a plurality of data lines.

[0037] Reference again Figure 2 In some embodiments, the substrate further includes a plurality of peripheral layout gate (PLG) primary lines P connected to the first pad PAD1 and the second pad PAD2 (eg, connected to the gate pad and the data pad). PLG When the substrate is cut into array substrates and multiple PLG primary lines P are cut PLG When a plurality of PLG lines are formed, a display device is formed using the array substrate. In the display device, a gate driver integrated circuit is bonded to a gate pad and a data driver integrated circuit is bonded to a data pad, and a plurality of PLG lines are configured to transmit signals between the gate driver integrated circuit and the data driver integrated circuit. PLG The conductive pad at least partially extends into the first pad PAD1 and at least partially extends into the second pad PAD2.

[0038] The inventors of the present disclosure have found that it is difficult to test Figure 2 The substrate shown has multiple PLG primary lines P PLG Although the plurality of first test pads TP1 and the plurality of second test pads TP2 can be used to test the connectivity of the plurality of first signal lines and the plurality of second signal lines, the plurality of PLG primary lines P PLG Cannot be included in the test. When multiple PLG original lines P PLG When one or more of the PLG primary lines have connectivity issues and are not detected, the array substrate cut from the substrate will have defects, resulting in waste of materials and resources in the subsequent manufacturing process.PLG A surprisingly effective method of connectivity.

[0039] Figure 3 FIG. shows a method of manufacturing an array substrate according to some embodiments of the present disclosure. Referring to Figure 3 , this method includes setting a substrate S, and testing the connectivity of a plurality of PLG primitive wires in the substrate S using a probing unit PR. The probing unit PR includes a printed circuit board PCB and a probing block PB. The probing block PB is electrically connected to the printed circuit board PCB and is electrically connected to a plurality of PLG primitive wires in the substrate S. The probing block PB is a collection of electrical contacts. The probing block PB can be implemented in a blade type, or a needle type, or a thin film type.

[0040] Figure 4 is a partial view of the structure of a substrate according to some embodiments of the present disclosure. Referring to Figure 4 , in some embodiments, the substrate further includes a PLG test pad TP PLG and a shorting bar SB, the shorting bar SB connecting the PLG test pad TP PLG to a first terminal t1 of a plurality of PLG primitive wires P PLG . For example, the shorting bar SB shorts a first terminal t1 of a plurality of PLG primitive wires P PLG and connects it to the PLG test pad TP PLG . When a test voltage signal is applied to the PLG test pad TP PLG , the test voltage is simultaneously applied to a first terminal t1 of a plurality of PLG primitive wires P PLG . In addition, in some embodiments, the substrate further includes a plurality of test pins Pint, the plurality of test pins Pint being respectively connected to a second terminal t2 of a plurality of PLG primitive wires P PLG . The plurality of test pins Pint are located in a first dummy region DR1 of the substrate. The first dummy region DR1 is adjacent to the array substrate region ASR of the substrate. When a test voltage signal is applied to the PLG test pad TP PLG , the test voltage is simultaneously applied to the plurality of test pins Pint.

[0041] Therefore, in some embodiments, the method of manufacturing an array substrate further includes setting a substrate including a gate pad configured to engage a gate driver integrated circuit, a data pad configured to engage a data driver integrated circuit, and a plurality of PLG primitive wires P PLG connecting the gate pad and the data pad; forming a PLG test pad TP PLG on the substrate; forming a connection that connects the PLG test pad TP PLG to a plurality of PLG primitive wires P PLGA shorting bar SB for the first terminal t1; and a plurality of test pins Pint are formed, and the plurality of test pins Pint are respectively connected to a plurality of PLG raw wires P PLG The second terminal t2. The plurality of test pins Pint are formed in a first dummy region DR1 of the substrate, and the first dummy region DR1 is adjacent to the array substrate region ASR of the substrate.

[0042] In some embodiments, the method of manufacturing an array substrate further includes forming a plurality of first signal lines SL1, forming a plurality of second signal lines SL2, forming a plurality of first leads Lw1, and forming a plurality of second leads Lw2. The plurality of first leads Lw1 are formed to be respectively connected to the plurality of first signal lines SL1. The plurality of second leads Lw2 are formed to be respectively connected to the plurality of second signal lines SL2. Optionally, the plurality of first signal lines SL1 are a plurality of data lines, the plurality of first leads Lw1 are a plurality of data leads, the plurality of second signal lines SL2 are a plurality of gate lines, and the plurality of second leads Lw2 are a plurality of gate line leads. Optionally, the method further includes forming a plurality of first wire shorting bars SB1 to test the connectivity of the plurality of first signal lines SL1. Optionally, the plurality of first wire shorting bars SB1 are a plurality of data lead shorting bars.

[0043] Figure 5 shows a method of manufacturing an array substrate according to some embodiments of the present disclosure. Referring to Figure 3 With Figure 5 , in some embodiments, this method further includes connecting the plurality of test pins Pint to a probing unit PR to test the plurality of PLG raw wires P PLG Connectivity. Specifically, in some embodiments, the method includes connecting the plurality of test pins PINT to a printed circuit board PCB of the probing unit PR through a probing block PB of the probing unit PR.

[0044] Figure 6 is a schematic diagram showing the structure of a probing unit according to some embodiments of the present disclosure. Referring to Figure 6 , in some embodiments, the probing unit PR includes a printed circuit board PCB; a probing block PB; a plurality of connection lines Lc with a quantity of N, which respectively connect the probing block PB and the printed circuit board PCB. In some embodiments, the printed circuit board includes a plurality of transistors TFT connected in series with a quantity of N; and a light emitting element LE. As Figure 6 shown, in one example, the gates of the plurality of transistors TFT with a quantity of N are respectively electrically connected to the plurality of connection lines Lc with a quantity of N. The source of the first transistor TFT1 among the plurality of transistors TFT with a quantity of N is electrically connected to the first connection line Lc1 among the plurality of connection lines Lc with a quantity of N. The last transistor TFT among the plurality of transistors TFT with a quantity of N NThe drain is electrically connected to the light-emitting element LE. The source of the nth transistor between the first transistor TFT1 and the last transistor TFT is connected to the drain of the (n-1)th transistor, where 1 < n < N. The drain of the nth transistor is connected to the source of the (n+1)th transistor. N The source of the nth transistor between the first transistor TFT1 and the last transistor TFT is connected to the drain of the (n-1)th transistor, where 1 < n < N. The drain of the nth transistor is connected to the source of the (n+1)th transistor.

[0045] Referring Figure 5 and Figure 6 As shown in FIGS. 1-3, by connecting a plurality of test pins Pint to the printed circuit board PCB of the detection unit PR through the detection block PB of the detection unit PR, the plurality of test pins Pint with the number of N are respectively electrically connected to the gates of the plurality of transistors TFT with the number of N connected in series in the printed circuit board PCB. The first test pin Pint1 among the plurality of test pins with the number of N is also electrically connected to the source of the first transistor among the plurality of transistors TFT with the number of N through the detection block PB and the first connection line Lc1 among the plurality of connection lines Lc with the number of N, for example.

[0046] In some embodiments, the method further includes the step of testing the connectivity of a plurality of PLG original wires P PLG Specifically, the step of testing the connectivity includes providing a test voltage signal to the PLG test pad TP PLG When the test voltage signal is applied to the PLG test pad TP PLG The test voltage signal is simultaneously applied to the plurality of PLG original wires P PLG .

[0047] When the connectivity of at least one of the plurality of PLG original wires P PLG is damaged, for example, when at least one of the plurality of PLG original wires P PLG is damaged or otherwise open-circuited, the test voltage signal cannot be sent to the light-emitting element LE because at least one of the plurality of transistors TFT is in the off state. Therefore, when the test voltage signal is provided to the PLG test pad TP PLG The light-emitting element LE in the off state indicates that the connectivity of at least one of the plurality of PLG original wires P PLG is damaged.

[0048] In some embodiments, the method further includes repairing the damaged connectivity of at least one of the plurality of PLG original wires P PLG based on the light-emitting element being in the off state, or discarding the substrate to save costs.

[0049] When the connectivity in each of the plurality of PLG original wires P PLG is intact, for example, when the plurality of PLG original wires P PLGWhen each of them is not damaged or otherwise open-circuited, a test voltage signal is simultaneously applied to the gates of a plurality of N transistors TFT and the source of a first transistor TFT1 of a plurality of N transistors TFT. The plurality of N transistors TFT are all turned on by the test voltage signal. The test voltage signal is sent to a light-emitting element (e.g., a light-emitting diode) through the plurality of N transistors TFT. Thus, when the test voltage signal is provided to the PLG test pad TP PLG the light-emitting element LE in the on state indicates that the connectivity of each of the plurality of PLG raw wires P PLG is intact.

[0050] In some embodiments, the method further includes cutting the substrate to form an array substrate based on the light-emitting element being in the on state. Figure 7 is a partial view of an array substrate manufactured by a method according to some embodiments of the present disclosure. Referring to Figure 4 and Figure 7 in some embodiments, the plurality of PLG raw wires P PLG are cut to form a plurality of PLG lines PLGL. The plurality of PLG lines PLGL are configured to transmit signals between a gate driver integrated circuit and a data driver integrated circuit in a display device having an array substrate, where the gate driver integrated circuit is bonded to a gate pad (e.g., a second pad PAD2), and the data driver integrated circuit is bonded to a data pad (e.g., a first pad PAD1).

[0051] In some embodiments, the method includes cutting the substrate along a first cutting line CL1. The first cutting line CL1 is located between a first dummy region DR1 and an array substrate region ASR. Referring to Figure 4 and Figure 7 a plurality of test pins are removed due to cutting the substrate along the first cutting line CL1.

[0052] In some embodiments, the method includes cutting the substrate along a second cutting line CL2. The second cutting line CL2 is located between a second dummy region DR2 and an array substrate region ASR. Referring to Figure 4 and Figure 7 a shorting bar SB is removed due to cutting the substrate along the second cutting line CL2. During cutting the substrate along the second cutting line CL2, a plurality of first wire shorting bars SB1 for testing the connectivity of a plurality of first signal lines are also removed.

[0053] Figure 8 is a partial view of the structure of a substrate according to some embodiments of the present disclosure. Referring to Figure 8, the substrate for manufacturing the array substrate further includes a plurality of additional pads PADa, which are located between the first pad PAD1 and the second pad PAD2, for example, between the data pad and the gate pad. Optionally, the first pad PAD1 is a data pad configured to be bonded to a data driving integrated circuit, the second pad PAD2 is a gate pad configured to be bonded to a gate driving integrated circuit, and the plurality of additional pads PADa are respectively configured to be bonded to a plurality of additional gate pads of a plurality of additional gate driving integrated circuits. Optionally, the first pad PAD1 is a gate pad configured to be bonded to a gate driving integrated circuit, the second pad PAD2 is a data pad configured to be bonded to a data driving integrated circuit, and the plurality of additional pads PADa are respectively configured to be bonded to a plurality of additional data pads of a plurality of additional data driving integrated circuits.

[0054] Reference Figure 8 , a plurality of PLG original wires P PLG Each of the PLG original wires P in PLG is formed to extend from a corresponding first terminal to a corresponding second terminal, and the corresponding second terminal is connected to a corresponding one of the plurality of test pins Pint. The plurality of PLG original wires P PLG surround three sides of each of the plurality of additional pads PADa. On one side of the substrate having the plurality of additional pads PADa and the second pad PAD2, the plurality of PLG original wires P PLG Each of the PLG original wires P in PLG has an undulating line that surrounds three sides of each of the plurality of additional pads PADa.

[0055] Figure 9 shows the structure of a plurality of PLG original wires around additional pads in some embodiments according to the present disclosure. Referring to Figure 8 And Figure 9 , in some embodiments, each of the plurality of PLG original wires P PLG Each of the PLG original wires P in PLG includes a first portion P1 and a second portion P2 that are respectively located in the array substrate region ASR and on both sides of a corresponding one of the plurality of additional pads PADa, and a connecting portion Pc that connects the first portion P1 and the second portion P2. The connecting portion Pc is located in the first dummy region DR1.

[0056] In one example, the connection portion Pc includes a first portion Pc1, a second portion Pc2, and a third portion Pc3. Optionally, the second portion Pc2 extends along a first extension direction of a plurality of first signal lines SL1. Optionally, the first portion P1 and the first portion Pc1 extend from the array substrate region ASR to the first dummy region DR1 along a second extension direction of a plurality of second signal lines SL2. Optionally, the third portion Pc3 and the second portion P2 extend from the first dummy region DR1 to the array substrate region ASR along the second extension direction of the plurality of second signal lines SL2.

[0057] Figure 10 illustrates a method of manufacturing an array substrate according to some embodiments of the present disclosure. Referring to Figure 8 and Figure 10 , in some embodiments, the method further includes connecting a plurality of test pins Pint to the detection unit PR to test the connectivity of a plurality of PLG raw wires P PLG . Specifically, in some embodiments, the method includes connecting a plurality of test pins Pint to a printed circuit board PCB of the detection unit PR through a detection block PB of the detection unit PR.

[0058] Referring to Figure 6 and Figure 10 , when the connectivity of at least one of the plurality of PLG raw wires P PLG is damaged, for example, when at least one of the plurality of PLG raw wires P PLG is damaged or otherwise open-circuited, the test voltage signal cannot be sent to the light-emitting element LE because at least one of the plurality of transistors TFT is in an off state. Therefore, when the test voltage signal is provided to the PLG test pad TP PLG , the light-emitting element LE in the off state indicates that the connectivity of at least one of the plurality of PLG raw wires P PLG is damaged.

[0059] In some embodiments, the method further includes, based on the light-emitting element being in the off state, repairing the damaged connectivity of at least one of the plurality of PLG raw wires P PLG , or discarding the substrate to save costs.

[0060] Referring to Figure 6 and Figure 10 , when the connectivity of each of the plurality of PLG raw wires P PLG is intact, for example, in the plurality of PLG raw wires P PLGWhen each of them is not damaged or otherwise open-circuited, a test voltage signal is simultaneously applied to the gates of a plurality of N transistors TFT and the source of the first transistor TFT1 among the plurality of N transistors TFT. The plurality of N transistors TFT are all turned on by the test voltage signal. The test voltage signal is sent to a light-emitting element (e.g., a light-emitting diode) through the plurality of N transistors TFT. Therefore, when the test voltage signal is provided to the PLG test pad TP PLG the light-emitting element LE in the on state indicates that the connectivity of each of the plurality of PLG original lines P PLG is intact.

[0061] In some embodiments, the method further includes cutting the substrate to form an array substrate based on the light-emitting element being in the on state. Figure 11 is a partial view of an array substrate manufactured by the method according to some embodiments of the present disclosure. Referring to Figure 8 and Figure 11 in some embodiments, the plurality of PLG original lines P PLG are cut to form a plurality of PLG lines PLGL. The plurality of PLG lines PLGL are configured to transmit signals between a gate driver integrated circuit and a data driver integrated circuit in a display device having an array substrate, wherein the gate driver integrated circuit is bonded to a gate pad (e.g., the second pad PAD2), and the data driver integrated circuit is bonded to a data pad (e.g., the first pad PAD1).

[0062] In some embodiments, the method includes cutting the substrate along a first cutting line CL1. The first cutting line CL1 is located between a first dummy region DR1 and an array substrate region ASR. Referring to Figure 8 and Figure 11 since the substrate is cut along the first cutting line CL1, a plurality of test pins are removed. Each of the plurality of PLG original lines P PLG along the first cutting line CL1 is cut, thereby removing the connection portion Pc. PLG

[0063] In some embodiments, the method includes cutting the substrate along a second cutting line CL2. The second cutting line CL2 is located between a second dummy region DR2 and an array substrate region ASR. Referring to Figure 8 and Figure 11 since the substrate is cut along the second cutting line CL2, a shorting bar SB is removed. During the cutting of the substrate along the second cutting line CL2, a plurality of first wire shorting bars SB1 for testing the connectivity of a plurality of first signal lines are also removed.

[0064] Referring to Figure 4 , Figure 7 , Figure 8 andFigure 11 , in some embodiments, the second pad PAD2 is a gate pad, and the plurality of additional pads PADa are a plurality of additional gate pads. The second pad PAD2 and the plurality of additional pads PADa are respectively directly adjacent to a first cut line CL1 between the array substrate region ASR and the first dummy region DR1. The first pad PAD1 (e.g., a data pad) is directly adjacent to a second cut line CL2 between the array substrate region ASR and the second dummy region DR2. The shorting bar SB and the first terminal t1 are located in the second dummy region DR2 and are removed during the cutting step. The second terminal t2 is located in the first dummy region DR1 and is removed during the cutting step.

[0065] Referring to Figure 4 , Figure 7 , Figure 8 and Figure 11 , in some embodiments, before setting the substrate, the method further includes forming a plurality of first signal lines SL1 (e.g., a plurality of data lines), forming a plurality of first leads Lw1 respectively connected to the plurality of first signal lines SL1, forming a plurality of second signal lines SL2 (e.g., a plurality of gate lines), and forming a plurality of second leads Lw2 respectively connected to the plurality of second signal lines SL2. Optionally, the plurality of second leads Lw2 (e.g., a plurality of gate line leads), the first portion P1, and the second portion P2 respectively at least partially extend into a corresponding one of the plurality of additional pads PADa. The first portion P1 is located on a first side of the plurality of second leads Lw2, and the second portion P2 is located on a second side of the plurality of second leads Lw2.

[0066] In some embodiments, the method further includes using a plurality of first test pads TP1 (e.g., a plurality of data line test pads) and a plurality of first wire shorting bars SB1 (e.g., a plurality of data lead shorting bars) to test the connectivity of a plurality of first signal lines (e.g., a plurality of data lines) in the substrate. The plurality of PLG original wires P PLG and the plurality of first leads Lw1 (e.g., a plurality of data leads) respectively at least partially extend into the first pad PAD1 (e.g., a data pad). The plurality of first leads Lw1 (e.g., a plurality of data leads) are respectively connected to the plurality of first signal lines SL1 (e.g., a plurality of data lines).

[0067] On the other hand, the present disclosure provides an array substrate manufactured by the method described herein. In some embodiments, the array substrate includes a plurality of gate lines, a plurality of data lines, a gate pad for bonding a gate driver integrated circuit, a data pad for bonding a data driver integrated circuit, a plurality of peripheral layout gate lines for connecting the gate pad and the data pad, a plurality of gate line leads respectively connected to the plurality of gate lines, and a plurality of data leads respectively connected to the plurality of data lines. The plurality of peripheral layout gate lines, the plurality of gate line leads, the plurality of data leads, the gate pad, and the data pad are located in the peripheral region of the array substrate. In the display region of the array substrate, the array substrate includes a plurality of sub-pixels.

[0068] On the other hand, the present disclosure provides a display device. In some embodiments, the display device includes the array substrate described herein, a gate driver integrated circuit bonded to the gate pad, and a data driver integrated circuit bonded to the data pad. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, GPS devices, etc. Optionally, the display device is an organic light emitting diode display device. Optionally, the display device is a liquid crystal display device.

[0069] On the other hand, the present disclosure provides a probing unit for testing the connectivity of a plurality of PLG primitive lines in a substrate. In some embodiments, the probing unit includes a printed circuit board; a probing block; and a plurality of connection lines numbered N respectively connecting the probing block and the printed circuit board. In some embodiments, the printed circuit board includes a plurality of transistors numbered N connected in series; and a light emitting element. Optionally, the gates of the plurality of transistors numbered N are respectively electrically connected to the plurality of connection lines numbered N. Optionally, the source of the first transistor among the plurality of transistors numbered N is electrically connected to the first connection line among the plurality of connection lines numbered N. Optionally, the drain of the last transistor among the plurality of transistors numbered N is electrically connected to the light emitting element. Optionally, the source of the nth transistor between the first transistor and the last transistor is connected to the drain of the (n - 1)th transistor, where 1 < n < N. Optionally, the drain of the nth transistor is connected to the source of the (n + 1)th transistor.

[0070] In another aspect, the present disclosure provides a substrate. In some embodiments, the substrate includes a gate pad configured to engage a gate driver integrated circuit; a data pad configured to engage a data driver integrated circuit; a plurality of peripheral layout gate (PLG) primitive lines connecting the gate pad and the data pad; a PLG test pad; a shorting bar connecting the PLG test pad to a first terminal of the plurality of PLG primitive lines; and a plurality of test pins respectively connected to second terminals of the plurality of PLG primitive lines, wherein the plurality of test pins are formed in a first dummy region of the substrate, and the first dummy region is adjacent to an array substrate region of the substrate.

[0071] In some embodiments, the substrate further includes a plurality of additional pads between the data pad and the gate pad. Optionally, each of the plurality of PLG primitive lines extends from a corresponding first terminal to a corresponding second terminal, and the corresponding second terminal is connected to a corresponding one of the plurality of test pins; and each of the plurality of PLG primitive lines includes a first portion and a second portion respectively in the array substrate region and on two sides of a corresponding one of the plurality of additional pads, and a connecting portion connecting the first portion and the second portion, and the connecting portion is in the first dummy region.

[0072] In some embodiments, the plurality of additional pads are a plurality of additional gate pads. Optionally, the gate pad and the plurality of additional gate pads are directly adjacent to a first boundary line between the array substrate region and the first dummy region respectively. Optionally, the data pad is directly adjacent to a second boundary line between the array substrate region and a second dummy region. Optionally, the shorting bar and the first terminal are in the second dummy region.

[0073] In some embodiments, the substrate further includes a plurality of gate line leads respectively connected to a plurality of gate lines. Optionally, the plurality of gate line leads, the first portion, and the second portion respectively at least partially extend into a corresponding one of the plurality of additional pads. Optionally, the first portion is on a first side of the plurality of gate line leads. Optionally, the second portion is on a second side of the plurality of gate line leads.

[0074] In some embodiments, the substrate further includes a plurality of data line test pads and a plurality of data lead shorting bars for testing the connectivity of a plurality of data lines in the substrate. Optionally, the plurality of PLG primitive lines and the plurality of data leads respectively at least partially extend into the data pads. Optionally, the plurality of data leads are respectively connected to the plurality of data lines.

[0075] The foregoing description of the embodiments of the present invention has been presented for purposes of illustration and description. It is not exhaustive and is not intended to limit the present invention to the precise forms or exemplary embodiments disclosed. Thus, the foregoing description should be considered illustrative rather than restrictive. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to explain the principles of the present invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the present invention and the various modifications suitable for the particular use or implementation being considered. The scope of the present invention is intended to be defined by the appended claims and their equivalents, where all terms are meant in their broadest reasonable sense unless otherwise stated. Thus, terms such as "the invention," "the present invention," etc. do not necessarily limit the scope of the claims to a particular embodiment, and references to exemplary embodiments of the present invention do not imply a limitation on the present invention and should not be inferred as such. The present invention is limited only by the spirit and scope of the appended claims. Additionally, these claims may refer to "first," "second," etc. followed by a noun or element. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by such nomenclature, unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the present invention. It should be understood that those skilled in the art may make changes to the described embodiments without departing from the scope of the present invention as defined by the appended claims. Further, no element or component in this disclosure is intended to be dedicated to the public, whether or not the element or component is expressly recited in the appended claims.

Claims

1. A method of manufacturing an array substrate, comprising: Providing a substrate, the substrate including a gate pad configured to engage a gate driver integrated circuit, a data pad configured to engage a data driver integrated circuit, and a plurality of peripheral layout gate (PLG) primitive lines connecting the gate pad and the data pad; Forming a PLG test pad on the substrate; Forming a shorting bar that connects the PLG test pad to a first terminal of the plurality of PLG primitive lines; Forming a plurality of test pins, the plurality of test pins being respectively connected to a second terminal of the plurality of PLG primitive lines, wherein the plurality of test pins are formed in a first dummy region of the substrate, the first dummy region being adjacent to an array substrate region of the substrate; And Connecting the plurality of test pins to a probing unit to test the connectivity of the plurality of PLG primitive lines.

2. The method according to claim 1, further comprising forming a plurality of additional pads between the data pad and the gate pad before providing the substrate; Among them, Each of the plurality of PLG primitive lines is formed to extend from a corresponding first terminal to a corresponding second terminal, the corresponding second terminal being connected to a corresponding one of the plurality of test pins; and Each of the plurality of PLG primitive lines includes a first portion and a second portion respectively located in the array substrate region and respectively on two sides of a corresponding one of the plurality of additional pads, and a connecting portion connecting the first portion and the second portion, the connecting portion being in the first dummy region.

3. The method according to claim 1 or 2, wherein connecting the plurality of test pins to the probing unit includes connecting the plurality of test pins to a printed circuit board of the probing unit through a probing block of the probing unit, so that the plurality of test pins with a quantity of N are respectively electrically connected to gates of a plurality of transistors with a quantity of N connected in series in the printed circuit board; wherein a first test pin of the plurality of test pins with a quantity of N is further electrically connected to a source of a first transistor of the plurality of transistors with a quantity of N; a drain of a last transistor of the plurality of transistors with a quantity of N is electrically connected to a light-emitting element of the printed circuit board; a source of an nth transistor between the first transistor and the last transistor is connected to a drain of an (n - 1)th transistor, 1 < n < N; a drain of the nth transistor is connected to a source of an (n + 1)th transistor.

4. The method according to claim 3, further comprising providing a test voltage signal to the PLG test pad; Among them, When the test voltage signal is provided to the PLG test pad, the light-emitting element in an off state indicates that the connectivity of at least one of the plurality of PLG primitive lines is impaired.

5. The method according to claim 3, further comprising providing a test voltage signal to the PLG test pad; Among them, When the test voltage signal is provided to the PLG test pad, the light-emitting element in the on state indicates that the connectivity of each of the plurality of PLG original wires is intact.

6. The method according to claim 5, further comprising cutting the substrate to form an array substrate based on the light-emitting element being in the on state; Among them, The plurality of PLG original wires are cut to form a plurality of PLG wires configured to transmit signals between the gate driver integrated circuit and the data driver integrated circuit in a display device having the array substrate, wherein the gate driver integrated circuit is bonded to the gate pad and the data driver integrated circuit is bonded to the data pad.

7. The method according to claim 6, further comprising forming a plurality of additional pads between the data pad and the gate pad before setting the substrate; Among them, Each of the plurality of PLG original wires is formed to extend from a corresponding first terminal to a corresponding second terminal, and the corresponding second terminal is connected to a corresponding one of the plurality of test pins; and Each of the plurality of PLG original wires includes a first portion and a second portion respectively in the array substrate region and on opposite sides of a corresponding one of the plurality of additional pads, and a connecting portion connecting the first portion and the second portion, the connecting portion being in the first dummy region; And Cutting each of the plurality of PLG original wires along a first cutting line to remove the connecting portion.

8. The method according to claim 6 or 7, wherein, Cutting the plurality of PLG original wires along a first cutting line between the first dummy region and the array substrate region to remove the plurality of test pins.

9. The method according to claim 6 or 7, wherein Cutting the plurality of PLG original wires along a second cutting line between the second dummy region and the array substrate region to remove the shorting bar.

10. The method according to claim 2, wherein the plurality of additional pads are a plurality of additional gate pads; The gate pad and the plurality of additional gate pads are directly adjacent to the first cutting line between the array substrate region and the first dummy region; The data pad is directly adjacent to the second cutting line between the array substrate region and the second dummy region; and The shorting bar and the first terminal are located in the second dummy region.

11. The method according to claim 10, wherein, Before setting the substrate, further comprising forming a plurality of gate lines and a plurality of gate line leads respectively connected to the plurality of gate lines; The plurality of gate line leads, the first portion, and the second portion respectively extend at least partially into a corresponding one of the plurality of additional pads; The first portion is located on a first side of the plurality of gate line leads; and The second portion is located on a second side of the plurality of gate line leads.

12. The method according to claim 1, further comprising testing the connectivity of a plurality of data lines in the substrate using a plurality of data line test pads and a plurality of data lead shorting bars; Among them, The plurality of PLG original wires and the plurality of data leads respectively extend at least partially into the data pads; The plurality of data leads are respectively connected to the plurality of data lines.

13. An array substrate manufactured by the method according to any one of claims 1 to 12.

14. A display device, comprising the array substrate according to claim 13, the gate driver integrated circuit bonded to the gate pad, and the data driver integrated circuit bonded to the data pad.

15. A probing unit for testing the connectivity of a plurality of PLG primitive wires in a substrate, comprising: A printed circuit board; A probing block; And A plurality of N connecting wires respectively connecting the probing block and the printed circuit board; Wherein, the printed circuit board comprises: A plurality of N transistors connected in series; and A light-emitting element; Wherein, the gates of the plurality of N transistors are respectively electrically connected to the plurality of N connecting wires; The source of the first transistor among the plurality of N transistors is electrically connected to the first connecting wire among the plurality of N connecting wires; The drain of the last transistor among the plurality of N transistors is electrically connected to the light-emitting element; The source of the nth transistor between the first transistor and the last transistor is connected to the drain of the (n - 1)th transistor, 1 < n < N; and The drain of the nth transistor is connected to the source of the (n + 1)th transistor.

16. An array substrate, comprising: A gate pad configured to bond a gate driver integrated circuit; A data pad configured to bond a data driver integrated circuit; A plurality of peripheral layout gate (PLG) wires configured to transmit signals between the gate driver integrated circuit bonded to the gate pad and the data driver integrated circuit bonded to the data pad; A PLG test pad; and A plurality of first test pads.

17. The array substrate according to claim 16, further comprising: A plurality of additional pads located between the data pad and the gate pad; And A plurality of additional PLG wires configured to transmit signals between adjacent additional pads.

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