Anti-interference bandgap reference circuit

Abstract

The present invention discloses an anti-interference bandgap reference circuit, which includes a power supply locking circuit, a bandgap reference circuit, and an output circuit that are connected in sequence. The power supply locking circuit is used to generate a fixed voltage and serve as the reference voltage of the bandgap reference circuit. The bandgap reference circuit is used to generate the bandgap reference voltage. The output circuit is used to output the bandgap reference voltage. One end of the power supply locking circuit is connected to the input power supply, and the other end is connected to the ground terminal. The power supply locking circuit includes six MOS transistors, one resistor, and one triode. In the present invention, a power supply locking circuit is added at the front end of the bandgap reference circuit. By utilizing the component characteristics, the reference voltage is locked at a specific voltage as the power supply of the bandgap reference circuit, thereby enabling the bandgap reference circuit to be free from input interference.

Description

Technical Field

[0001] The present invention relates to a reference circuit in the field of microelectronics, and more particularly to an anti-interference bandgap reference circuit. Background Art

[0002] In most microelectronic circuit applications, an accurate reference voltage is necessary. In standard processes, a standard bandgap reference circuit is used. Normally, the input voltage does not fluctuate, but in the application of a DC-to-DC buck converter, it will be interfered by the swing of the output terminal, and the reference voltage will also swing accordingly. In order to make the reference voltage stable and not interfered, a relatively large capacitance to ground must be added during design to stabilize the reference voltage.

[0003] In the standard CMOS process, the circuit design of the bandgap reference circuit is as Figure 1 shown. The circuit consists of two PMOS transistors, two NMOS transistors, two PNP transistors, one resistor, and one PMOS transistor, one PNP transistor, and one resistor in the output stage. Using Figure 1 the bandgap reference circuit for simulation experiments gives Figure 4 , from Figure 4 it can be seen that during the swing of the power supply (V3A) between 5V and 3.3V, the output voltage (VDC_BG) will fluctuate with the power supply swing; in the prior art, in order to reduce the fluctuation of the output voltage, a technical solution of adding one resistor and one capacitor is usually adopted, as Figure 2 and Figure 5 shown. With the continuous miniaturization of the current process, to solve the problem by increasing the capacitor area, the capacitor area needs to be enlarged by 100 times, accounting for about 1 / 4 of the chip area, which greatly increases the cost in actual application.

[0004] Therefore, it is urgent to solve the above problems. Summary of the Invention

[0005] Object of the Invention: The object of the present invention is to provide an anti-interference bandgap reference circuit with low cost and a stable reference voltage.

[0006] Technical Solution: To achieve the above object, the present invention discloses an anti-interference bandgap reference circuit, including a power supply locking circuit connected in sequence for generating a fixed voltage and serving as the reference voltage of the bandgap reference circuit, a bandgap reference circuit for generating a bandgap reference voltage, and an output circuit for outputting the bandgap reference voltage. One end of the power supply locking circuit is connected to the input power supply, and one end is connected to the ground terminal. The power supply locking circuit includes 6 MOS transistors, 1 resistor, and 1 triode.

[0007] Among them, the power supply locking circuit includes a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a fourth resistor, and a fourth triode. The drain of the sixth MOS transistor is connected to the reference voltage. The gate of the sixth MOS transistor is connected to the bandgap reference circuit and the output circuit. The source of the sixth MOS transistor is connected to the fourth resistor. The other end of the fourth resistor is connected to the first pole of the fourth triode. The gate and the second pole of the fourth triode are both connected to the ground terminal. The sources of the eighth MOS transistor and the ninth MOS transistor are connected to the input power supply. The drain of the eighth MOS transistor is connected to the reference voltage. The gates of the eighth MOS transistor, the ninth MOS transistor, and the drain are connected together. The drain of the eleventh MOS transistor is connected to the drain of the ninth MOS transistor. The gate of the eleventh MOS transistor is connected to the gate of the tenth MOS transistor. The source of the eleventh MOS transistor is connected to the ground terminal. The source of the seventh MOS transistor is connected to the reference voltage. The gate of the seventh MOS transistor is connected to the bandgap reference circuit and the output circuit. The drain of the seventh MOS transistor is connected to the drain of the tenth MOS transistor. The drain and the gate of the tenth MOS transistor are connected together. The source of the tenth MOS transistor is connected to the ground terminal.

[0008] Preferably, the sixth MOS transistor, the tenth MOS transistor, and the eleventh MOS transistor are NMOS transistors, and the seventh MOS transistor, the eighth MOS transistor, and the ninth MOS transistor are PMOS transistors.

[0009] Furthermore, the bandgap reference circuit includes a second MOS transistor, a third MOS transistor, a fourth MOS transistor, a fifth MOS transistor, a second triode, a third triode, and a first resistor. The sources of the second MOS transistor and the third MOS transistor are connected to the reference voltage. The gates of the second MOS transistor, the third MOS transistor, the sixth MOS transistor, and the seventh MOS transistor are connected together. The drain and the gate of the third MOS transistor are connected together. The drain of the second MOS transistor is connected to the drain of the fourth MOS transistor. The drain of the third MOS transistor is connected to the drain of the fifth MOS transistor. The gates of the fourth MOS transistor and the fifth MOS transistor are connected together. The drain and the gate of the fourth MOS transistor are connected together. The source of the fifth MOS transistor is connected to the first resistor and then to the first pole of the third triode. The source of the fourth MOS transistor is connected to the first pole of the second triode. The gates and the second poles of the second triode and the third triode are both connected to the ground terminal.

[0010] Furthermore, the second MOS transistor and the third MOS transistor are PMOS transistors, and the fourth MOS transistor and the fifth MOS transistor are NMOS transistors.

[0011] Preferably, the output circuit includes a first MOS transistor, a first triode, a second resistor, a third resistor, and a first capacitor. The source of the first MOS transistor is connected to the reference voltage. The gate of the first MOS transistor is connected to the gates of the second MOS transistor, the third MOS transistor, the sixth MOS transistor, and the seventh MOS transistor. The drain of the first MOS transistor is connected to one end of the second resistor. The other end of the second resistor is connected to the first pole of the first triode. The gate and the second pole of the first triode are both connected to the ground terminal. The third resistor is connected to the first capacitor. The other end of the third resistor is connected to the drain of the first MOS transistor. The other end of the first capacitor is connected to the ground terminal. The connection point of the third resistor and the first capacitor is the output terminal.

[0012] Furthermore, the first MOS transistor is a PMOS transistor.

[0013] Advantageous effects: Compared with the prior art, the present invention has the following remarkable advantages:

[0014] (1). In the layout of the present invention, the capacitor area is reduced by 99%. By utilizing the characteristics of MOS transistors and triodes, a stable input power supply for the bandgap reference circuit is provided, and the interference of the input voltage swing on the reference voltage is solved with almost no increase in cost; that is, a power supply locking circuit is added at the front end of the bandgap reference circuit, and the reference voltage is locked at a specific voltage as the power supply of the bandgap reference circuit by utilizing the component characteristics, so as to make the bandgap reference circuit get rid of the swing interference at the input end.

[0015] (2). The power supply locking circuit of the present invention is composed of six MOS transistors, one resistor, and one triode. The architecture is simple and can effectively reduce the layout area, providing an effective and reliable reference voltage in the chip design of DC to DC. Description of the Drawings

[0016] Figure 1 Schematic diagram of the existing bandgap reference circuit;

[0017] Figure 2 Schematic diagram of adding a resistor and a capacitor to the output of the existing bandgap reference circuit;

[0018] Figure 3 Schematic diagram of the circuit of the present invention;

[0019] Figure 4 For Figure 1 Circuit timing simulation diagram;

[0020] Figure 5 For Figure 2 Circuit timing simulation diagram;

[0021] Figure 6 For Figure 3 Circuit timing simulation diagram.

[0022] Figure 7Schematic diagram of adding a common voltage locking circuit to the input of an existing bandgap reference circuit;

[0023] Figure 8 For Figure 7 Circuit timing simulation diagram. Specific implementation manners

[0024] The technical solutions of the present invention will be further described below with reference to the accompanying drawings.

[0025] As Figure 3 shown, an anti-interference bandgap reference circuit of the present invention includes a power supply locking circuit, a bandgap reference circuit, and an output circuit connected in sequence. One end of the power supply locking circuit is connected to the input power supply, and the other end is connected to the ground terminal.

[0026] The power supply locking circuit is used to generate a fixed voltage and serve as the reference voltage of the bandgap reference circuit. The power supply locking circuit includes the sixth MOS transistor N6, the seventh MOS transistor P7, the eighth MOS transistor P8, the ninth MOS transistor P9, the tenth MOS transistor N10, the eleventh MOS transistor N11, the fourth resistor R4, and the fourth triode Q4. The bandgap reference circuit is used to generate the bandgap reference voltage. The bandgap reference circuit includes the second MOS transistor P2, the third MOS transistor P3, the fourth MOS transistor N4, the fifth MOS transistor N5, the second triode Q2, the third triode Q3, and the first resistor R1. The output circuit is used to output the bandgap reference voltage. The output circuit includes the first MOS transistor P1, the first triode Q1, the second resistor R2, the third resistor R3, and the first capacitor C1. The power supply locking circuit is connected to the bandgap reference circuit to provide a stable voltage and current to the bandgap reference circuit. The bandgap reference circuit is used to generate the bandgap reference voltage and output it through the output circuit. The principle of the key power supply locking circuit of the present invention is that the seventh MOS transistor P7, the eighth MOS transistor P8, the ninth MOS transistor P9, the tenth MOS transistor N10, and the eleventh MOS transistor N11 use the current mirror principle to provide a stable current source; and the fixed voltage between the first stage and the gate of the fourth triode Q4 plus the fixed current flowing through the fourth resistor R4 and the conduction voltage of the sixth MOS transistor N6 generate a fixed voltage to lock the reference voltage VREF. Under this architecture, the interference caused by the swing of the input power supply V3A can be eliminated.

[0027] In the present invention, the drain of the sixth MOS transistor N6 is connected to the reference voltage VREF. The gate of the sixth MOS transistor N6 is connected to the gates of the first MOS transistor P1, the second MOS transistor P2, and the third MOS transistor P3. The source of the sixth MOS transistor N6 is connected to the fourth resistor R4. The other end of the fourth resistor R4 is connected to the first pole of the fourth triode Q4. The gate and the second pole of the fourth triode Q4 are both connected to the ground terminal GNDA. The sources of the eighth MOS transistor P8 and the ninth MOS transistor P9 are connected to the input power supply V3A. The drain of the eighth MOS transistor P8 is connected to the reference voltage VREF. The gates and the drains of the eighth MOS transistor P8 and the ninth MOS transistor P9 are connected to each other. The drain of the eleventh MOS transistor N11 is connected to the drain of the ninth MOS transistor P9. The gate of the eleventh MOS transistor N11 is connected to the gate of the tenth MOS transistor N10. The source of the eleventh MOS transistor N11 is connected to the ground terminal GNDA. The source of the seventh MOS transistor P7 is connected to the reference voltage VREF. The gate of the seventh MOS transistor P7 is connected to the gates of the first MOS transistor P1, the second MOS transistor P2, and the third MOS transistor P3. The drain of the seventh MOS transistor P7 is connected to the drain of the tenth MOS transistor N10. The drain and the gate of the tenth MOS transistor N10 are connected to each other. The source of the tenth MOS transistor N10 is connected to the ground terminal GNDA.

[0028] The sources of the second MOS transistor P2 and the third MOS transistor P3 are connected to the reference voltage VREF. The gates of the second MOS transistor P2, the third MOS transistor P3, the sixth MOS transistor N6, and the seventh MOS transistor P7 are connected to each other. The drain and the gate of the third MOS transistor P3 are connected to each other. The drain of the second MOS transistor P2 is connected to the drain of the fourth MOS transistor N4. The drain of the third MOS transistor P3 is connected to the drain of the fifth MOS transistor N5. The gates of the fourth MOS transistor N4 and the fifth MOS transistor N5 are connected to each other. The drain and the gate of the fourth MOS transistor N4 are connected to each other. The source of the fifth MOS transistor N5 is connected to the first resistor (R1), and then connected to the first pole of the third triode Q3. The source of the fourth MOS transistor N4 is connected to the first pole of the second triode Q2. The gates and the second poles of the second triode Q2 and the third triode Q3 are both connected to the ground terminal GNDA.

[0029] The source of the first MOS transistor P1 is connected to the reference voltage VREF. The gate of the first MOS transistor P1 is connected to the gates of the second MOS transistor P2, the third MOS transistor P3, the sixth MOS transistor N6, and the seventh MOS transistor P7. The drain of the first MOS transistor P1 is connected to one end of the second resistor R2. The other end of the second resistor R2 is connected to the first pole of the first triode Q1. The gate and the second pole of the first triode Q1 are both connected to the ground terminal GNDA. The third resistor R3 and the first capacitor C1 are connected. The other end of the third resistor R3 is connected to the drain of the first MOS transistor P1. The other end of the first capacitor C1 is connected to the ground terminal GNDA. The connection point of the third resistor R3 and the first capacitor C1 is the output terminal VBG, and the output terminal VBG outputs the voltage VDC_BG.

[0030] In the present invention, the first MOS transistor P1, the second MOS transistor P2, the third MOS transistor P3, the seventh MOS transistor P7, the eighth MOS transistor P8, and the ninth MOS transistor P9 are PMOS transistors. The fourth MOS transistor N4, the fifth MOS transistor N5, the sixth MOS transistor N6, the tenth MOS transistor N10, and the eleventh MOS transistor N11 are NMOS transistors.

[0031] During simulation, the input power supply V3A swings between 3.3V and 5V. Figure 4 The output voltage VDC_BG in [reference] shows two-stage voltages. It is 1.214 when the input is 3.3V and 1.221 when the input is 5V, and there is also an obvious surge from 1.209V to 1.226V. Figure 5 The VDC_BG in [reference] still has two-stage voltages, but after the large capacitor C1 absorbs the surges, there are no surges in VDC_BG during the input swing. Figure 6 In [reference], the VDC_BG not only eliminates the two-stage voltages but also suppresses the surges to 0.001V. From Figure 4 、 Figure 5 and Figure 6 comparisons, it can be clearly seen that the present invention can keep VDC_BG at a fixed voltage under the condition of large swings at the input end. From this result, in addition to being applicable to DC to DC buck products, it can also be used in various products that require a stable reference voltage, such as precision comparators.

[0032] Figure 7 The left half of [reference] is a common voltage locking circuit, which is composed of the fourth resistor R4, the sixth MOS transistor N6, the seventh MOS transistor N7, the eighth MOS transistor N8, and the ninth MOS transistor N9. The seventh MOS transistor N7, the eighth MOS transistor N8, and the ninth MOS transistor N9 are connected in series. By using the superposition of the MOS transistor startup voltage and the resistor to adjust the flowing current, the gate voltage of the sixth MOS transistor N6 is locked, thereby providing a stable VREF.

[0033] Figure 8 Then it is to compareFigure 1 Among the existing bandgap reference circuits, Figure 3 Among the circuits of the present invention and Figure 7 Among the simulation results of adding a common voltage locking circuit to the input of the existing bandgap reference circuit, the waveform at the bottom is the result of adding a common voltage locking circuit to the input of the existing bandgap reference circuit. Compared with the existing bandgap reference circuit, it can also eliminate the two-stage voltage of VDC_BG, but there is still a spike of 0.008V; the spike of 0.008V will cause misjudgment when used in a precision comparator; while the present invention can eliminate the two-stage voltage and suppress the spike to 0.001V.

Claims

1. An anti-interference bandgap reference circuit, characterized in that: It includes a power supply locking circuit, a bandgap reference circuit, and an output circuit that are connected in sequence. The power supply locking circuit is used to generate a fixed voltage and serve as the reference voltage of the bandgap reference circuit. One end of the power supply locking circuit is connected to the input power supply, and the other end is connected to the ground terminal. The power supply locking circuit includes six MOS transistors, one resistor, and one triode; the power supply locking circuit includes the sixth MOS transistor (N6), the seventh MOS transistor (P7), the eighth MOS transistor (P8), the ninth MOS transistor (P9), the tenth MOS transistor (N10), the eleventh MOS transistor (N11), the fourth resistor (R4), and the fourth triode (Q4). The drain of the sixth MOS transistor (N6) is connected to the reference voltage (VREF). The gate of the sixth MOS transistor (N6) is connected to the bandgap reference circuit and the output circuit. The source of the sixth MOS transistor (N6) is connected to the fourth resistor (R4). The other end of the fourth resistor (R4) is connected to the first pole of the fourth triode (Q4). The base and the second pole of the fourth triode (Q4) are both connected to the ground terminal (GNDA). The sources of the eighth MOS transistor (P8) and the ninth MOS transistor (P9) are connected to the input power supply (V3A). The drain of the eighth MOS transistor (P8) is connected to the reference voltage (VREF). The gates of the eighth MOS transistor (P8) and the ninth MOS transistor (P9) are connected to each other, and the drains are also connected to each other. The drain of the eleventh MOS transistor (N11) is connected to the drain of the ninth MOS transistor (P9). The gate of the eleventh MOS transistor (N11) is connected to the gate of the tenth MOS transistor (N10). The source of the eleventh MOS transistor (N11) is connected to the ground terminal (GNDA). The source of the seventh MOS transistor (P7) is connected to the reference voltage (VREF). The gate of the seventh MOS transistor (P7) is connected to the bandgap reference circuit and the output circuit. The drain of the seventh MOS transistor (P7) is connected to the drain of the tenth MOS transistor (N10). The drain and the gate of the tenth MOS transistor (N10) are connected to each other. The source of the tenth MOS transistor (N10) is connected to the ground terminal (GNDA).

2. The anti-interference bandgap reference circuit according to claim 1, wherein: The sixth MOS transistor (N6), the tenth MOS transistor (N10), and the eleventh MOS transistor (N11) are NMOS transistors, and the seventh MOS transistor (P7), the eighth MOS transistor (P8), and the ninth MOS transistor (P9) are PMOS transistors.

3. The anti-interference bandgap reference circuit according to claim 1, characterized in that: The bandgap reference circuit includes a second MOS transistor (P2), a third MOS transistor (P3), a fourth MOS transistor (N4), a fifth MOS transistor (N5), a second triode (Q2), a third triode (Q3), and a first resistor (R1). The sources of the second MOS transistor (P2) and the third MOS transistor (P3) are connected to a reference voltage (VREF). The gates of the second MOS transistor (P2), the third MOS transistor (P3), a sixth MOS transistor (N6), and a seventh MOS transistor (P7) are connected together. The drain of the third MOS transistor (P3) is connected to its gate. The drain of the second MOS transistor (P2) is connected to the drain of the fourth MOS transistor (N4). The drain of the third MOS transistor (P3) is connected to the drain of the fifth MOS transistor (N5). The gates of the fourth MOS transistor (N4) and the fifth MOS transistor (N5) are connected together. The drain of the fourth MOS transistor (N4) is connected to its gate. The source of the fifth MOS transistor (N5) is connected to the first resistor (R1), and then connected to the first terminal of the third triode (Q3). The source of the fourth MOS transistor (N4) is connected to the first terminal of the second triode (Q2). The bases and the second terminals of the second triode (Q2) and the third triode (Q3) are both connected to a ground terminal (GNDA).

4. The anti-interference bandgap reference circuit according to claim 3, wherein: The second MOS transistor (P2) and the third MOS transistor (P3) are PMOS transistors, and the fourth MOS transistor (N4) and the fifth MOS transistor (N5) are NMOS transistors.

5. The anti-interference bandgap reference circuit according to claim 3, characterized in that: The output circuit includes a first MOS transistor (P1), a first triode (Q1), a second resistor (R2), a third resistor (R3), and a first capacitor (C1). The source of the first MOS transistor (P1) is connected to the reference voltage (VREF). The gate of the first MOS transistor (P1) is connected to the gates of the second MOS transistor (P2), the third MOS transistor (P3), the sixth MOS transistor (N6), and the seventh MOS transistor (P7). The drain of the first MOS transistor (P1) is connected to one end of the second resistor (R2). The other end of the second resistor (R2) is connected to the first terminal of the first triode (Q1). The base and the second terminal of the first triode (Q1) are both connected to the ground terminal (GNDA). The third resistor (R3) and the first capacitor (C1) are connected. The other end of the third resistor (R3) is connected to the drain of the first MOS transistor (P1). The other end of the first capacitor (C1) is connected to the ground terminal (GNDA). The connection point of the third resistor (R3) and the first capacitor (C1) is the output terminal (VBG).

6. The anti-interference bandgap reference circuit according to claim 5, characterized in that: The first MOS transistor (P1) is a PMOS transistor.

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