Display device

Abstract

A display device includes a display panel including a plurality of pixels, a data driver applying a data signal to the display panel, a scan driver including a plurality of scan driving stages and sequentially applying a scan signal to the display panel, a light emitting driver including a light emitting driving stage and sequentially applying a light emitting signal to the display panel, a controller controlling the scan driver, the light emitting driver, and the data driver, and a power voltage generator generating a power voltage including a high voltage and a low voltage and providing the high voltage of different sizes or the low voltage of different sizes to at least one of the plurality of scan driving stages and the light emitting driving stage. At this time, the power voltage generator generates a first high voltage, a first low voltage, a second high voltage smaller than the first high voltage, and a second low voltage greater than the first low voltage based on an input voltage.

Description

Technical Field

[0001] The present invention relates to a display device and a driving method for the display device, and more specifically, to a display device and a driving method for the display device for controlling a power supply voltage input to a driver. Background Technology

[0002] The display device includes multiple drivers, such as data drivers, scan drivers, and light-emitting drivers. Furthermore, the scan drivers and light-emitting drivers each include multiple driving stages for driving the display panel. In this case, each driving stage receives the same power supply voltage input and operates. That is, there is power consumption that is unnecessarily consumed by the multiple driving stages included in the scan drivers and light-emitting drivers. Therefore, it is necessary to reduce the power consumption unnecessarily consumed by the multiple driving stages included in the scan drivers and light-emitting drivers. Summary of the Invention

[0003] One object of the present invention is to provide a display device that can reduce the power consumed by the scanning driver and the light-emitting driver.

[0004] Another object of the present invention is to provide a driving method for a display device that can reduce the power consumed by the scanning driver and the light-emitting driver.

[0005] However, the purpose of this invention is not limited to the above-described purpose, and various extensions can be made without departing from the spirit and scope of this invention.

[0006] To achieve the aforementioned objective of the present invention, an embodiment of the present invention relates to a display device comprising: a display panel including a plurality of pixels; a data driver applying data signals to the display panel; a scan driver including a plurality of scan driving stages and sequentially applying scan signals to the display panel; a light-emitting driver including a light-emitting stage and sequentially applying light-emitting signals to the display panel; a controller controlling the scan driver, the light-emitting driver, and the data driver; and a power supply voltage generation unit generating a power supply voltage including a high voltage and a low voltage, and providing different magnitudes of the high voltage or different magnitudes of the low voltage to at least one of the plurality of scan driving stages and the light-emitting stage. In this case, the power supply voltage generation unit generates a first high voltage, a first low voltage, a second high voltage smaller than the first high voltage, and a second low voltage larger than the first low voltage based on the input voltage.

[0007] According to one embodiment, the power supply voltage generation unit may include: a voltage generation module for generating a first high voltage and a first low voltage based on the input voltage; and a voltage scaling module for scaling the first high voltage to the second high voltage and scaling the first low voltage to the second low voltage.

[0008] According to one embodiment, the plurality of scan driver levels may include a write scan driver level, a compensated scan driver level, an initialization scan driver level, and a bypass scan driver level.

[0009] According to one embodiment, the scan start signal and scan clock signal of at least one of the plurality of scan drive stages may switch between the second high voltage and the second low voltage.

[0010] According to one embodiment, the voltage scaling module may determine the magnitudes of the second high voltage and the second low voltage based on pre-stored data.

[0011] According to one embodiment, the power supply voltage generation unit may provide the second high voltage and the second low voltage to the compensation scan drive stage and the initialization scan drive stage.

[0012] According to one embodiment, the scan start signal and the scan clock signal of the compensation scan driver stage and the initialization scan driver stage may switch between the second high voltage and the second low voltage.

[0013] According to one embodiment, the power supply voltage generation unit may provide the first high voltage and the second low voltage to the write scan driver stage.

[0014] According to one embodiment, the scan start signal and the scan clock signal written to the scan driver level may switch between a first high voltage and a second low voltage.

[0015] According to one embodiment, the light emission start signal and the light emission clock signal of the light emission driving stage may switch between the second high voltage and the second low voltage.

[0016] According to one embodiment, the scan start signal and the scan clock signal of the bypass scan driver stage switch between the second high voltage and the second low voltage.

[0017] To achieve the aforementioned objective of the present invention, other embodiments of the present invention may include a driving method for a display device that may include: generating a first high voltage and a first low voltage based on an input voltage; scaling the first high voltage to a second high voltage smaller than the first high voltage, and scaling the first low voltage to a second low voltage larger than the first low voltage; and providing a high voltage or a low voltage of different magnitudes to at least one of a plurality of scanning driving stages and light-emitting driving stages.

[0018] According to one embodiment, the plurality of scan driver levels may include a write scan driver level, a compensated scan driver level, an initialization scan driver level, and a bypass scan driver level.

[0019] According to one embodiment, the scaling step may be based on pre-stored data to determine the magnitudes of the second high voltage and the second low voltage.

[0020] According to one embodiment, the step of providing different levels of high voltage or different levels of low voltage may involve providing the second high voltage and the second low voltage to the compensation scan driver stage and the initialization scan driver stage.

[0021] According to one embodiment, the scan start signal and scan clock signal of the compensation scan drive stage and the initialization scan drive stage may switch between the second high voltage and the second low voltage.

[0022] According to one embodiment, the step of providing different levels of high voltage or different levels of low voltage may be to provide the first high voltage and the second low voltage to the write scan driver stage.

[0023] According to one embodiment, the write scan driver stage may cause the scan start signal and the scan clock signal to switch between the first high voltage and the second low voltage.

[0024] According to one embodiment, the light-emitting driver stage may switch the light-emitting start signal and the light-emitting clock signal between the second high voltage and the second low voltage.

[0025] According to one embodiment, the step of providing different levels of high voltage or different levels of low voltage provides the second high voltage and the second low voltage to the compensation scan drive stage and the initialization scan drive stage.

[0026] (Invention Effects)

[0027] The display devices according to various embodiments of the present invention selectively output the required power supply voltage to the driving stages of the scan driver and the light-emitting driver, thereby minimizing the power wasted needlessly in driving the scan driver and the light-emitting driver. Therefore, the display device can improve the overall power consumption efficiency.

[0028] However, the effects of the present invention are not limited to those described above, and various extensions can be made without departing from the spirit and scope of the present invention. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the present invention.

[0030] Figure 2 It is shown that it includes Figure 1 The circuit diagram of the pixels in the display device.

[0031] Figure 3 It is shown that it includes Figure 1 A block diagram of an example of a power supply voltage generation unit in a display device.

[0032] Figure 4 This diagram illustrates an example of applying a power supply voltage to a scan driver and a light-emitting driver.

[0033] Figure 5a This is a block diagram illustrating a compensation scan drive stage according to an embodiment of the present invention.

[0034] Figure 5b This is a block diagram illustrating an embodiment of the initialization scan driver level according to the present invention.

[0035] Figure 6 This is a block diagram illustrating a write scan driver level according to an embodiment of the present invention.

[0036] Figure 7 This is a diagram illustrating other examples of applying power supply voltage to the scan driver and the light driver.

[0037] Figure 8 This is a block diagram illustrating a light-emitting driving stage according to an embodiment of the present invention.

[0038] Figure 9 This is a block diagram illustrating a bypass scan drive stage according to an embodiment of the present invention.

[0039] Figure 10 This is a sequence diagram illustrating the operation of a display device according to an embodiment of the present invention.

[0040] Figure 11 This is a block diagram illustrating an electronic device according to various embodiments of the present invention.

[0041] Figure 12 This demonstrates what is achieved by a smartphone. Figure 11 An example of an electronic device.

[0042] Symbol explanation:

[0043] 100: Display device; 110: Display panel; 130: Data driver; 150: Scan driver; 170: Light emission driver; 190: Controller; 200: Power supply voltage generation unit; 210: Voltage generation module; 220: Voltage scaling module. Detailed Implementation

[0044] Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same constituent elements in the drawings, and repeated descriptions of the same constituent elements are omitted.

[0045] Figure 1 This is a block diagram illustrating a display device 100 according to an embodiment of the present invention. Figure 2 It is shown that it includes Figure 1 Circuit diagram of pixel PX in display device 100. Figure 3 It is shown that it includes Figure 1 A block diagram of an example of the power supply voltage generation unit 200 in the display device 100.

[0046] Reference Figure 1 The display device 100 according to various embodiments of the present invention may include a display panel 110, a data driver 130 that provides data signals DS to the display panel 110, a scan driver 150 that provides write scan signals GW1 to GWN, compensation scan signals GC1 to GCN, initialization scan signals GI1 to GIN and bypass scan signals GB1 to GBN to the display panel 110, a light-emitting driver 170 that provides light-emitting signals EM1 to EMN to the display panel 110, a controller 190 that controls the data driver 130, the scan driver 150 and the light-emitting driver 170, and a power supply voltage generation unit 200 that provides power supply voltage to the scan driver 150 and the light-emitting driver 170.

[0047] Display panel 110 may include multiple data lines, multiple write scan lines, multiple compensation scan lines, multiple initialization scan lines, multiple bypass scan lines, multiple light emission lines, and multiple pixels PX connected to them. Display panel 110 may be an OLED display panel in which each pixel PX includes an organic light-emitting diode (OLED).

[0048] like Figure 2 As shown, in one embodiment, pixel PX1 may include a light-emitting element EE and a plurality of transistors T1 to T8. A first electrode of the light-emitting element EE may be connected to a sixth transistor T6, and a second electrode may be connected to a second power supply VSS. The light-emitting element EE may include an organic light-emitting diode or an inorganic light-emitting diode. The light-emitting element EE may generate light of a predetermined brightness in response to a driving current supplied from the first transistor T1.

[0049] A first transistor T1 may be connected between a first node N1 electrically connected to a first power supply VDD and a second node N2 electrically connected to a first electrode of a light-emitting element EE. The first transistor T1 generates a drive current and supplies it to the light-emitting element EE. The gate electrode of the first transistor T1 may be connected to a third node N3. The first transistor T1 functions as a drive transistor for pixel PX1.

[0050] The second transistor T2 may be coupled between the data line and the first node N1. The second transistor T2 may include a gate electrode for receiving the write scan signal GW(j).

[0051] The third transistor T3 can be connected between the second node N2 and the third node N3. The third transistor T3 may include a gate electrode for receiving the compensation scan signal GC(j). When the third transistor T3 is turned on, the first transistor T1 can be connected in diode mode. That is, the third transistor T3 can perform the writing of the data voltage VDATA to the first transistor T1 and the threshold voltage compensation.

[0052] The storage capacitor Cst is connected between the first power supply VDD and the third node N3. The storage capacitor Cst can store the voltage corresponding to the data voltage VDATA and the threshold voltage of the first transistor T1.

[0053] A fourth transistor T4 may be coupled between the third node N3 and the third power supply VINT. The fourth transistor T4 may include a gate electrode for receiving an initialization scan signal GI(j). In one embodiment, the initialization scan signal GI(j) may correspond to the compensation scan signal GC(j-1) of the previous pixel line. Depending on the conduction of the fourth transistor T4, the gate voltage of the first transistor T1 can be initialized by the voltage of the third power supply VINT. In one embodiment, the third power supply VINT may be set to a voltage lower than the minimum voltage of the data voltage VDATA.

[0054] The fifth transistor T5 may be connected between the first power supply VDD and the first node N1. The fifth transistor T5 may include a gate electrode for receiving the emitted light signal EM(j).

[0055] The sixth transistor T6 may be coupled between the second node N2 and the first electrode of the light-emitting element EE. The sixth transistor T6 may include a gate electrode for receiving the light-emitting signal EM(j).

[0056] The fifth transistor T5 and the sixth transistor T6 can be turned on during the gate-on period of the light-emitting signal EM(j) and turned off during the gate-off period.

[0057] A seventh transistor T7 may be coupled between the third power supply VINT and the first electrode of the light-emitting element EE. The seventh transistor T7 may include a gate electrode for receiving a bypass scan signal GB(j). In one embodiment, the bypass scan signal GB(j) may correspond to a write scan signal GW(j). However, this is exemplary; the bypass scan signal GB(j) may also correspond to a write scan signal GW(j-1) supplied to the previous pixel row or a write scan signal GW(j+1) supplied to the next pixel row.

[0058] The eighth transistor T8 may be connected between the high-level light-emitting power supply VEH and the first node N1. The eighth transistor T8 may include a gate electrode for receiving the bypass scan signal GB(j).

[0059] However, the descriptions of the written scan signal GW(j), the compensated scan signal GC(j), the initial scan signal GI(j), and the bypass scan signal GB(j) are merely for the purpose of explanation and are used to distinguish the scan signals provided to the different constituent elements within the pixel PX1. The function of each scan signal is not limited thereto.

[0060] In one embodiment, the first transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 can all be P-type low-temperature polycrystalline silicon (LTPS) thin-film transistors, and the third transistor T3 and the fourth transistor T4 can all be N-type oxide semiconductor thin-film transistors. Since N-type oxide semiconductor thin-film transistors have superior leakage current characteristics compared to P-type LTPS thin-film transistors, the third transistor T3 and the fourth transistor T4, serving as switching transistors, can be formed as N-type oxide semiconductor thin-film transistors. Therefore, the leakage current in the third transistor T3 and the fourth transistor T4 is significantly reduced, thereby lowering power consumption.

[0061] The data driver 130 can provide a data signal DS to a plurality of pixels PX based on image data DAT and a data control signal DCTRL received from the controller 190. In one embodiment, the data control signal DCTRL may include a horizontal start signal and a load signal, but is not limited thereto.

[0062] The scan driver 150 may, based on the scan control signal SCTRL received from the controller 190, sequentially provide write scan signals GW1 to GWN, compensated scan signals GC1 to GCN, initialization scan signals GI1 to GIN, and bypass scan signals GB1 to GBN to a plurality of pixels PX, on a pixel-row basis. In one embodiment, the scan control signal SCTRL may include a write scan start signal, a first write scan clock signal, a second write scan clock signal, a compensated scan start signal, a first compensated scan clock signal, a second compensated scan clock signal, an initialization scan start signal, a first initialization scan clock signal, a second initialization scan clock signal, a bypass scan start signal, a first bypass scan clock signal, and a second bypass scan clock signal, but is not limited thereto.

[0063] In one embodiment, such as Figure 1 As shown, the scan driver 150 may include multiple write scan driver stages GW_STG for sequentially outputting write scan signals GW1 to GWN, multiple compensation scan driver stages GC_STG for sequentially outputting compensation scan signals GC1 to GCN, multiple initialization scan driver stages GI_STG for sequentially outputting initialization scan signals GI1 to GIN, and multiple bypass scan driver stages GB_STG for sequentially outputting bypass scan signals GB1 to GBN. For example, the multiple write scan driver stages GW_STG may sequentially output the first write scan signal GW1 to the Nth write scan signal GWN to the pixel PX based on a write scan start signal, a first write scan clock signal, and a second write scan clock signal. Furthermore, the multiple compensation scan driver stages GC_STG may sequentially output the first compensation scan signal GC1 to the Nth compensation scan signal GCN to the pixel PX based on a compensation scan start signal, a first compensation scan clock signal, and a second compensation scan clock signal. Furthermore, multiple initialization scan driver stages GI_STG can sequentially output first initialization scan signals GI1 to Nth initialization scan signals GIN to pixel PX based on the initialization scan start signal, the first initialization scan clock signal, and the second initialization scan clock signal. Additionally, multiple bypass scan driver stages GB_STG can sequentially output first bypass scan signals GB1 to Nth bypass scan signals GBN to pixel PX based on the bypass scan start signal, the first bypass scan clock signal, and the second bypass scan clock signal.

[0064] On the other hand, Figure 1The illustration shows an example where write scan signals GW1 to GWN, compensation scan signals GC1 to GCN, initialization scan signals GI1 to GIN, and bypass scan signals GB1 to GBN are output through different driver stages GW_STG, GC_STG, GI_STG, and GB_STG. However, according to an embodiment, at least a portion of the write scan signals GW1 to GWN, compensation scan signals GC1 to GCN, initialization scan signals GI1 to GIN, and bypass scan signals GB1 to GBN may be output by the same driver stage.

[0065] The light-emitting driver 170 can sequentially provide light-emitting signals EM1 to EMN to a plurality of pixels PX based on control signals received from the controller 190. In one embodiment, the control signals of the light-emitting driver 170 may include a light-emitting start signal EM_FLM, a first light-emitting clock signal EM_CLK1, and a second light-emitting clock signal EM_CLK2, but are not limited thereto. In one embodiment, the light-emitting driver 170 may include a plurality of light-emitting driver stages EM_STG for sequentially outputting light-emitting signals EM1 to EMN.

[0066] In addition, Figure 1 The illustration shows an example where the scan driver 150 and the light-emitting driver 170 are configured only on one side of the display panel 110, but according to an embodiment, the scan driver 150 and the light-emitting driver 170 may be configured on both sides of the display panel 110.

[0067] The controller (e.g., a timing controller) 190 can receive image data DAT and control signals CTRL from an external host (e.g., a graphics processing unit (GPU) or a graphics card). In one embodiment, the control signal CTRL may include a master clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data strobe signal, etc., but is not limited thereto. The controller 190 can provide image data DAT and data control signals DCTRL to the data driver 130 to control the data driver 130, can provide scan control signals SCTRL to the scan driver 150 to control the scan driver 150, and can provide light emission start signal EM_FLM and light emission clock signals EM_CLK1 and EM_CLK2 to the light emission driver 170 to control the light emission driver 170.

[0068] Reference Figure 1 and Figure 3The power supply voltage generation unit 200 can generate a power supply voltage including a high voltage VGH and a low voltage VGL. Specifically, the power supply voltage generation unit 200 can receive an input voltage VIN and generate a high voltage VGH and a low voltage VGL for driving the scan driver 150 and the light-emitting driver 170. The power supply voltage generation unit 200 can provide the high voltage VGH and the low voltage VGL to the scan driver 150 and the light-emitting driver 170. The power supply voltage generation unit 200 can generate a first high voltage VGH1, a first low voltage VGL1, a second high voltage VGH2 smaller than the first high voltage VGH1, and a second low voltage VGL2 larger than the first low voltage VGL1 based on the input voltage VIN. The power supply voltage generation unit 200 may include: a voltage generation module 210, which generates a first high voltage VGH1 and a first low voltage VGL1; and a voltage scaling module 220, which scales the first high voltage VGH1 to a second high voltage VGH2 that is smaller than the first high voltage VGH1, and scales the first low voltage VGL1 to a second low voltage VGL2 that is larger than the first low voltage VGL1.

[0069] In one embodiment, the voltage generation module 210 can receive an input voltage VIN and generate a first high voltage VGH1 and a first low voltage VGL1 for driving the scan driver 150 and the light-emitting driver 170. The voltage generation module 210 can output the first high voltage VGH1 and the first low voltage VGL1 to the scan driver 150 and the light-emitting driver 170. Furthermore, the voltage generation module 210 can transmit the first high voltage VGH1 and the first low voltage VGL1 to the voltage scaling module 220. The voltage scaling module 220 can receive the transmission of the first high voltage VGH1 and the first low voltage VGL1 from the voltage generation module 210. The voltage scaling module 220 can scale the first high voltage VGH1 to a second high voltage VGH2, which is lower than the first high voltage VGH1. The voltage scaling module 220 can scale the first low voltage VGL1 to a second low voltage VGL2, which is higher than the first low voltage VGL1. The voltage scaling module 220 can output the second high voltage VGH2 and the second low voltage VGL2 to the scan driver 150 and the light-emitting driver 170.

[0070] At this time, the voltage scaling module 220 can determine the magnitudes of the second high voltage VGH2 and the second low voltage VGL2 based on pre-stored data. Specifically, the power supply voltage generation unit 200 can store a data sheet including optimal drive voltage information for each of the multiple scan drive stages and light emission drive stages related to the input voltage. The voltage scaling module 220 can determine the magnitudes of the second high voltage VGH2 and the second low voltage VGL2 based on the data stored in the data sheet, thereby scaling the first high voltage VGH1 and the first low voltage VGL1.

[0071] In one embodiment, the power supply voltage generation unit 200 can output voltages of different magnitudes to the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG. Specifically, the power supply voltage generation unit 200 can selectively output one of a first high voltage VGH1 and a second high voltage VGH2 to the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG, respectively. Furthermore, the power supply voltage generation unit 200 can selectively output one of a first low voltage VGL1 and a second low voltage VGL2 to the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG, respectively. For example, when the power supply voltage generation unit 200 outputs a first high voltage VGH1 and a first low voltage VGL1 to a portion of the write scan driver GW_STG, the compensation scan driver GC_STG, the initialization scan driver GI_STG, the bypass scan driver GB_STG, and the light emission driver EM_STG, the power supply voltage generation unit 200 can provide the first high voltage VGH1 and the first low voltage VGL1 output by the voltage generation module 210 to a portion of the write scan driver GW_STG, the compensation scan driver GC_STG, the initialization scan driver GI_STG, the bypass scan driver GB_STG, and the light emission driver EM_STG. For example, when the power supply voltage generation unit 200 outputs a second high voltage VGH2 and a second low voltage VGL2 to a portion of the write scan driver GW_STG, the compensated scan driver GC_STG, the initialization scan driver GI_STG, the bypass scan driver GB_STG, and the light emission driver EM_STG, the power supply voltage generation unit 200 can provide the second high voltage VGH2 and the second low voltage VGL2 scaled by the voltage scaling module 220 to a portion of the write scan driver GW_STG, the compensated scan driver GC_STG, the initialization scan driver GI_STG, the bypass scan driver GB_STG, and the light emission driver EM_STG.

[0072] As described above, the display device 100 of the present invention can selectively output the required power supply voltage to the multiple drive stages GW_STG, GC_STG, GI_STG, GB_STG, and EM_STG of the scan driver 150 and the light-emitting driver 170, thereby minimizing the power wasted needlessly in driving the scan driver 150 and the light-emitting driver 170. Therefore, the display device 100 can improve the overall power consumption efficiency.

[0073] Figure 4 This is a diagram illustrating an example of applying a power supply voltage to the scan driver 150 and the light-emitting driver 170. Figure 5a This is a block diagram illustrating a compensation scan driver level GC_STG according to an embodiment of the present invention. Figure 5b This is a block diagram illustrating the initialization scan driver level GI_STG according to an embodiment of the present invention. Figure 6 This is a block diagram illustrating a write scan driver level GW_STG according to an embodiment of the present invention.

[0074] Reference Figures 4 to 6 The power supply voltage generation unit 200 can output voltages of different magnitudes to the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG. Furthermore, the scan start signal and scan clock signal (or light emission start signal and light emission clock signal) of at least one of the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG can be switched between a second high voltage VGH2 and a second low voltage VGL2.

[0075] In one embodiment, the power supply voltage generation unit 200 can selectively output one of a first high voltage VGH1 and a second high voltage VGH2 to the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG, respectively. Furthermore, the power supply voltage generation unit 200 can selectively output one of a first low voltage VGL1 and a second low voltage VGL2 to the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG, respectively. For example, as... Figure 4 As shown, the power supply voltage generation unit 200 can output a first high voltage VGH1 and a first low voltage VGL1 to the bypass scan driver stage GB_STG and the light emission driver stage EM_STG, output a second high voltage VGH2 and a second low voltage VGL2 to the compensation scan driver stage GC_STG and the initialization scan driver stage GI_STG, and output a first high voltage VGH1 and a second low voltage VGL2 to the write scan driver stage GW_STG.

[0076] Reference Figure 5aThe compensation scan driver stage GC_STG can separate the voltage applied to the output terminal from the drive voltage inside the driver stage. At this time, a voltage different from the drive voltage inside the driver stage can be applied to the output terminal. For example, the compensation scan driver stage GC_STG may include a pull-down portion involved in pulling the output signal OUTPUT down to the second low voltage VGL2. The pull-down portion may include a tenth switching element S10. The compensation scan driver stage GC_STG may include a pull-up portion involved in pulling the output signal OUTPUT up to the second high voltage VGH2. The pull-up portion may include a ninth switching element S9. The first switching element S1 may transmit the compensation scan start signal GC FLM to the fourth node X4 in response to the first compensation scan clock signal GC CLK1. The fourth switching element S4 may control the connection between the first compensation scan clock signal GC CLK1 and the first node X1 in response to the signal from the fourth node X4. The fifth switching element S5 may control the connection between the first low voltage VGL1 and the first node X1 in response to the first compensation scan clock signal GC CLK1. The second switching element S2 can be connected in series between the second node X2 and the first high voltage VGH1. The third switching element S3 can respond to the second compensation scan clock signal GC CLK2 to control the connection between the eighth switching element S8 and the second node X2. The eighth switching element S8 can respond to the signal of the fourth node X4 to control the connection between the first high voltage VGH1 and the seventh node X7. The seventh switching element S7 can respond to the signal of the sixth node X6 to control the connection between the second compensation scan clock signal GC CLK2 and the fifth node X5. The sixth switching element S6 can respond to the second compensation scan clock signal GC CLK2 to control the connection between the fifth node X5 and the seventh node X7. The eleventh switching element S11 can respond to the first low voltage VGL1 to control the connection between the first node X1 and the sixth node X6. The twelfth switching element S12 can respond to the first low voltage VGL1 to control the connection between the fourth node X4 and the eighth node X8. The second capacitor C2 can be connected between the fifth node X5 and the sixth node X6, and the third capacitor C3 can be connected between the second node X2 and the third node X3. As described above, by separating the output voltage of the compensation scan driver stage GC_STG from the drive voltage inside the driver stage, and thus applying the second high voltage VGH2 and the second low voltage VGL2 to the output terminal, the power consumed needlessly in driving the compensation scan driver stage GC_STG can be minimized. Therefore, the display device 100 can improve the overall power consumption efficiency.

[0077] In one embodiment, the power supply voltage generation unit 200 can switch the compensation scan start signal GC FLM and the compensation scan clock signals GC CLK1 and GC CLK2 input to the compensation scan driver stage GC_STG between a second high voltage VGH2 and a second low voltage VGL2. In this case, the compensation scan start signal GC FLM and the compensation scan clock signals GC CLK1 and GC CLK2, which switch between the second high voltage VGH2 and the second low voltage VGL2, can be applied to the compensation scan driver stage GC_STG. Therefore, the power consumption caused by the compensation scan start signal and the compensation scan clock signal can be reduced in the compensation scan driver stage GC_STG, and thus the display device 100 can further reduce power consumption.

[0078] Reference Figure 5bThe initialization scan driver stage GI_STG can separate the voltage applied to the output terminal from the drive voltage inside the driver stage. At this time, a voltage different from the drive voltage inside the driver stage can be applied to the output terminal. For example, the initialization scan driver stage GI_STG may include a pull-down portion involved in pulling the output signal OUTPUT down to the second low voltage VGL2. The pull-down portion may include a tenth switching element S10. The initialization scan driver stage GI_STG may include a pull-up portion involved in pulling the output signal OUTPUT up to the second high voltage VGH2. The pull-up portion may include a ninth switching element S9. The first switching element S1 may transmit the initialization scan start signal GI FLM to the fourth node X4 in response to the first initialization scan clock signal GI CLK1. The fourth switching element S4 may control the connection between the first initialization scan clock signal GI CLK1 and the first node X1 in response to the signal from the fourth node X4. The fifth switching element S5 may control the connection between the first low voltage VGL1 and the first node X1 in response to the first initialization scan clock signal GI CLK1. The second switching element S2 can be connected in series between the second node X2 and the first high voltage VGH1. The third switching element S3 can respond to the second initialization scan clock signal GI CLK2 to control the connection between the eighth switching element S8 and the second node X2. The eighth switching element S8 can respond to the signal of the fourth node X4 to control the connection between the first high voltage VGH1 and the seventh node X7. The seventh switching element S7 can respond to the signal of the sixth node X6 to control the connection between the second initialization scan clock signal GI CLK2 and the fifth node X5. The sixth switching element S6 can respond to the second initialization scan clock signal GI CLK2 to control the connection between the fifth node X5 and the seventh node X7. The eleventh switching element S11 can respond to the first low voltage VGL1 to control the connection between the first node X1 and the sixth node X6. The twelfth switching element S12 can respond to the first low voltage VGL1 to control the connection between the fourth node X4 and the eighth node X8. The second capacitor C2 can be connected between the fifth node X5 and the sixth node X6, and the third capacitor C3 can be connected between the second node X2 and the third node X3. As described above, by separating the output voltage of the initialization scan driver stage GI_STG from the drive voltage inside the driver stage, and thus applying the second high voltage VGH2 and the second low voltage VGL2 to the output terminal, the power consumed needlessly during the driving of the initialization scan driver stage GI_STG can be minimized. Therefore, the display device 100 can improve the overall power consumption efficiency.

[0079] In one embodiment, the power supply voltage generation unit 200 can switch the initialization scan start signal GI FLM and the initialization scan clock signals GI CLK1 and GI CLK2 input to the initialization scan drive stage GI_STG between a second high voltage VGH2 and a second low voltage VGL2. In this case, the initialization scan start signal GI FLM and the initialization scan clock signals GICLK1 and GI CLK2, which switch between the second high voltage VGH2 and the second low voltage VGL2, can be applied to the initialization scan drive stage GI_STG. Therefore, the power consumption caused by the initialization scan start signal and the initialization scan clock signal can be reduced in the initialization scan drive stage GI_STG, and thus the display device 100 can further reduce power consumption.

[0080] Reference Figure 6In the write scan driver stage GW_STG, the first transistor M1 can transmit the write scan start signal GW FLM or the previous output signal POUT to the first node N1 in response to the first write scan clock signal GW CLK1 (or the second write scan clock signal GW CLK2 in the case of an even-numbered driver stage). The second transistor M2 can transmit the first high voltage VGH1 to the third node N3 in response to the voltage of the second node N2. The third transistor M3 can transmit the voltage of the third node N3 to the first node N1 in response to the second write scan clock signal GW CLK2 (or the first write scan clock signal GW CLK1 in the case of an even-numbered driver stage). The fourth transistor M4 can transmit the first write scan clock signal GW CLK1 (or the second write scan clock signal GW CLK2 in the case of an even-numbered driver stage) to the second node N2 in response to the voltage of the first node N1. The fifth transistor M5 can transmit the first write scan clock signal GW CLK1 (or the second write scan clock signal GW CLK2 in the case of an even-numbered driver stage) to the second node N2 in response to the voltage of the first node N1. The second low voltage VGL2 is transmitted to the second node N2. The sixth transistor M6, in response to the voltage of the second node N2, outputs a first high voltage VGH1 to the output node NO as an output signal OUT. The seventh transistor M7, in response to the voltage of the first node N1, outputs a second write scan clock signal GWCLK2 (or the first write scan clock signal GWCLK1 in the case of even-numbered drive stages) to the output node NO as an output signal OUT. Furthermore, a first capacitor C1 can be connected between the first high voltage VGH1 and the second node N2, and a second capacitor C2 can be connected between the first node N1 and the output node NO. Therefore, the write scan drive stage GW_STG is driven by receiving the second low voltage VGL2 as described above, thus minimizing the unnecessary power consumption during drive compared to the case where it is driven by receiving the first low voltage VGL1. Furthermore, as described above, when the power supply voltage generation unit 200 outputs a first high voltage VGH1 and a second low voltage VGL2 to the write scan driver stage GW_STG, the write scan start signal GW FLM and the write scan clock signals GW CLK1 and GW CLK2 of the write scan driver stage GW_STG can switch between the first high voltage VGH1 and the second low voltage VGL2. In this case, the power consumption caused by the write scan start signal GW FLM and the write scan clock signals GW CLK1 and GW CLK2 can be reduced in the write scan driver stage GW_STG, thus the display device 100 can further reduce power consumption.

[0081] That is, the display device 100 according to various embodiments of the present invention selectively outputs the required power supply voltage to the multiple drive stages GW_STG, GC_STG, GI_STG, GB_STG, and EM_STG of the scan driver 150 and the light-emitting driver 170, thereby minimizing the power wasted needlessly in driving the scan driver 150 and the light-emitting driver 170. Therefore, the display device 100 can improve the overall power consumption efficiency.

[0082] Figure 7 This is a diagram illustrating another example of applying a power supply voltage to the scan driver 150 and the light-emitting driver 170. Figure 8 This is a block diagram illustrating an embodiment of the light-emitting driving stage EM_STG according to the present invention. Figure 9 This is a block diagram illustrating a bypass scan driver level GB_STG according to an embodiment of the present invention.

[0083] Reference Figures 7 to 9 The power supply voltage generation unit 200 can output voltages of different magnitudes to the write scan driver GW_STG, the compensation scan driver GC_STG, the initialization scan driver GI_STG, the bypass scan driver GB_STG, and the light emission driver EM_STG. In addition, the scan start signal and scan clock signal, or the light emission start signal and light emission clock signal of at least one of the write scan driver GW_STG, the compensation scan driver GC_STG, the initialization scan driver GI_STG, the bypass scan driver GB_STG, and the light emission driver EM_STG can be switched between the second high voltage VGH2 and the second low voltage VGL2.

[0084] In one embodiment, the power supply voltage generation unit 200 may selectively output one of a first high voltage VGH1 and a second high voltage VGH2 to the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG, respectively. Furthermore, the power supply voltage generation unit 200 may selectively output one of a first low voltage VGL1 and a second low voltage VGL2 to the write scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG, respectively. For example, the power supply voltage generation unit 200 can output a first high voltage VGH1 and a first low voltage VGL1 to the bypass scan driver stage GB_STG and the light emission driver stage EM_STG, output a second high voltage VGH2 and a second low voltage VGL2 to the compensation scan driver stage GC_STG and the initialization scan driver stage GI_STG, and output a first high voltage VGH1 and a second low voltage VGL2 to the write scan driver stage GW_STG.

[0085] On the other hand, the scan start signal and scan clock signal, or the light emission start signal and light emission clock signal, of at least one of the scan driver stage GW_STG, the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, the bypass scan driver stage GB_STG, and the light emission driver stage EM_STG can be switched between the second high voltage VGH2 and the second low voltage VGL2. Specifically, the scan start signal and scan clock signal of the compensation scan driver stage GC_STG, the initialization scan driver stage GI_STG, and the bypass scan driver stage GB_STG can be switched between the second high voltage VGH2 and the second low voltage VGL2. Furthermore, the scan start signal and scan clock signal of the scan driver stage GW_STG can be switched between the first high voltage VGH1 and the second low voltage VGL2. Additionally, the light emission start signal and light emission clock signal of the light emission driver stage EM_STG can be switched between the second high voltage VGH2 and the second low voltage VGL2. For example, when the power supply voltage generation unit 200 outputs the second high voltage VGH2 and the second low voltage VGL2 to the compensation scan driver stage GC_STG, the compensation scan start signal GCFLM and the compensation scan clock signals GC CLK1 and GC CLK2 of the compensation scan driver stage GC_STG (refer to...) Figure 5a The voltage can be switched between a second high voltage VGH2 and a second low voltage VGL2. Furthermore, when the power supply voltage generation unit 200 outputs the second high voltage VGH2 and the second low voltage VGL2 to the initialization scan driver stage GI_STG, the initialization scan start signal GI FLM and the initialization scan clock signals GI CLK1 and GI CLK2 of the initialization scan driver stage GI_STG (see reference) are also generated. Figure 5b The voltage can be switched between a second high voltage VGH2 and a second low voltage VGL2. Furthermore, when the power supply voltage generation unit 200 outputs a first high voltage VGH1 and a second low voltage VGL2 to the write scan driver stage GW_STG, the write scan start signal GW FLM and the write scan clock signals GW CLK1 and GW CLK2 of the write scan driver stage GW_STG (see reference) Figure 6 The voltage can be switched between a first high voltage VGH1 and a second low voltage VGL2. In this case, the power consumption caused by the scan start signal and scan clock signal can be reduced in the scan drive stages GC_STG, GI_STG, and GW_STG, thus further reducing the power consumption of the display device 100. (Refer to...) Figure 8 and Figure 9 This describes the switching operation of the start signal and clock signal between the light-emitting driver stage and the bypass driver stage.

[0086] Reference Figure 8The light-emitting driver stage EM_STG may include a pull-down portion that participates in pulling down the output signal OUTPUT to the first low voltage VGL1. The pull-down portion may include a tenth switching element S10. The light-emitting driver stage EM_STG may include a pull-up portion that participates in pulling up the output signal OUTPUT to the first high voltage VGH1. The pull-up portion may include a ninth switching element S9. The first switching element S1 may transmit the light-emitting start signal EM FLM to the fourth node X4 in response to the first light-emitting clock signal EM CLK1. The fourth switching element S4 may control the connection between the first light-emitting clock signal EM CLK1 and the first node X1 in response to the signal of the fourth node X4. The fifth switching element S5 may control the connection between the first low voltage VGL1 and the first node X1 in response to the first light-emitting clock signal EM CLK1. The second switching element S2 may be connected in series between the second node X2 and the first high voltage VGH1. The third switching element S3 may control the connection between the eighth switching element S8 and the second node X2 in response to the second light-emitting clock signal EM CLK2. The eighth switching element S8, responding to the signal from the fourth node X4, controls the connection between the first high voltage VGH1 and the seventh node X7. The seventh switching element S7, responding to the signal from the sixth node X6, controls the connection between the second luminous clock signal EMCLK2 and the fifth node X5. The sixth switching element S6, responding to the second luminous clock signal EMCLK2, controls the connection between the fifth node X5 and the seventh node X7. The eleventh switching element S11, responding to the first low voltage VGL1, controls the connection between the first node X1 and the sixth node X6. The twelfth switching element S12, responding to the first low voltage VGL1, controls the connection between the fourth node X4 and the eighth node X8. The second capacitor C2 can be connected between the fifth node X5 and the sixth node X6, and the third capacitor C3 can be connected between the second node X2 and the third node X3.

[0087] In one embodiment, the power supply voltage generation unit 200 can switch the light emission start signal EM FLM and the light emission clock signals EM CLK1 and EM CLK2 input to the light emission driver stage EM_STG between a second high voltage VGH2 and a second low voltage VGL2. In this case, the light emission start signal EM FLM and the light emission clock signals EM CLK1 and EM CLK2, which switch between the second high voltage VGH2 and the second low voltage VGL2, can be applied to the light emission driver stage EM_STG. Therefore, the power consumption caused by the light emission start signal EM FLM and the light emission clock signals EM CLK1 and EM CLK2 can be reduced in the light emission driver stage EM_STG, and thus the display device 100 can reduce power consumption.

[0088] Reference Figure 9The bypass scan driver stage GB_STG may include a pull-down portion involved in pulling the output signal OUTPUT down to the first low voltage VGL1. The pull-down portion may include a tenth switching element S10. The bypass scan driver stage GB_STG may include an up portion involved in pulling the output signal OUTPUT up to the first high voltage VGH1. The up portion may include a ninth switching element S9. The first switching element S1 may transmit the bypass scan start signal GB FLM to the fourth node X4 in response to the first bypass scan clock signal GB CLK1. The fourth switching element S4 may control the connection between the first bypass scan clock signal GB CLK1 and the first node X1 in response to the signal from the fourth node X4. The fifth switching element S5 may control the connection between the first low voltage VGL1 and the first node X1 in response to the first bypass scan clock signal GB CLK1. The second switching element S2 may be connected in series between the second node X2 and the first high voltage VGH1. The third switching element S3, responding to the second bypass scan clock signal GBCLK2, controls the connection between the eighth switching element S8 and the second node X2. The eighth switching element S8, responding to the signal of the fourth node X4, controls the connection between the first high voltage VGH1 and the seventh node X7. The seventh switching element S7, responding to the signal of the sixth node X6, controls the connection between the second bypass scan clock signal GBCLK2 and the fifth node X5. The sixth switching element S6, responding to the second bypass scan clock signal GBCLK2, controls the connection between the fifth node X5 and the seventh node X7. The eleventh switching element S11, responding to the first low voltage VGL1, controls the connection between the first node X1 and the sixth node X6. The twelfth switching element S12, responding to the first low voltage VGL1, controls the connection between the fourth node X4 and the eighth node X8. The second capacitor C2 can be connected between the fifth node X5 and the sixth node X6, and the third capacitor C3 can be connected between the second node X2 and the third node X3.

[0089] In one embodiment, the power supply voltage generation unit 200 can switch the bypass scan start signal GB FLM and bypass scan clock signals GB CLK1 and GB CLK2 input to the bypass scan driver stage GB_STG between a second high voltage VGH2 and a second low voltage VGL2. In this case, the bypass scan start signal GB FLM and bypass scan clock signals GB CLK1 and GB CLK2, which switch between the second high voltage VGH2 and the second low voltage VGL2, can be applied to the bypass scan driver stage GB_STG. Therefore, the power consumption caused by the bypass scan start signal GB FLM and bypass scan clock signals GBCLK1 and GB CLK2 can be reduced in the bypass scan driver stage GB_STG, thereby reducing the power consumption of the display device 100.

[0090] That is, the display device 100 according to various embodiments of the present invention can selectively output the required power supply voltage to the multiple drive stages GW_STG, GC_STG, GI_STG, GB_STG, and EM_STG of the scan driver 150 and the light-emitting driver 170, thereby reducing the power wasted needlessly in driving the scan driver 150 and the light-emitting driver 170. Therefore, the display device 100 can improve the overall power consumption efficiency.

[0091] Figure 10 This is a sequence diagram illustrating the operation of a display device 100 according to an embodiment of the present invention.

[0092] Reference Figures 1 to 4 as well as Figure 10 The display device 100 can generate a first high voltage VGH1 and a first low voltage VGL1 based on the input voltage (S100), scale the first high voltage VGH1 to a second high voltage VGH2 that is smaller than the first high voltage VGH1, scale the first low voltage VGL1 to a second low voltage VGL2 that is larger than the first low voltage VGL1 (S200), and provide high voltages or low voltages of different sizes to at least one of a plurality of scan driving stages and light emission driving stages (S300).

[0093] In one embodiment, the display device 100 may generate a first high voltage VGH1 and a first low voltage VGL1 based on the input voltage (S100). Specifically, the voltage generation module 210 may receive the input voltage VIN and generate a high voltage VGH and a low voltage VGL for driving the scan driver 150 and the light-emitting driver 170. For example, the voltage generation module 210 may generate the first high voltage VGH1 and the first low voltage VGL1 and output the first high voltage VGH1 and the first low voltage VGL1 to the scan driver 150 and the light-emitting driver 170. In addition, the voltage generation module 210 may pass the first high voltage VGH1 and the first low voltage VGL1 to the voltage scaling module 220.

[0094] In one embodiment, the display device 100 can scale a first high voltage VGH1 to a second high voltage VGH2 that is smaller than the first high voltage VGH1, and scale a first low voltage VGL1 to a second low voltage VGL2 that is larger than the first low voltage VGL1 (S200). Specifically, the voltage scaling module 220 can receive the first high voltage VGH1 and the first low voltage VGL1 from the voltage generation module 210. The voltage scaling module 220 can scale the first high voltage VGH1 to a second high voltage VGH2 that is lower than the first high voltage VGH1. The voltage scaling module 220 can scale the first low voltage VGL1 to a second low voltage VGL2 that is larger than the first low voltage VGL1. The voltage scaling module 220 can output the second high voltage VGH2 and the second low voltage VGL2 to the scan driver 150 and the light-emitting driver 170. At this time, the voltage scaling module 220 can determine the size of the second high voltage VGH2 and the second low voltage VGL2 based on pre-stored data. Specifically, the power supply voltage generation unit 200 can store a data sheet containing optimal driving voltage information for each of the multiple scan driving stages and light-emitting driving stages related to the input voltage. The voltage scaling module 220 can determine the magnitude of the second high voltage VGH2 and the second low voltage VGL2 based on the data stored in the data sheet, and thereby scale the first high voltage VGH1 and the first low voltage VGL1.

[0095] In one embodiment, the display device 100 may provide different high voltages or different low voltages to at least one of a plurality of scan driving stages and light-emitting driving stages (S300). Specifically, the power supply voltage generation unit 200 may output voltages of different magnitudes to the write scan driving stage GW_STG, the compensated scan driving stage GC_STG, the initialization scan driving stage GI_STG, the bypass scan driving stage GB_STG, and the light-emitting driving stage EM_STG. The power supply voltage generation unit 200 may selectively output one of a first high voltage VGH1 and a second high voltage VGH2 to the write scan driving stage GW_STG, the compensated scan driving stage GC_STG, the initialization scan driving stage GI_STG, the bypass scan driving stage GB_STG, and the light-emitting driving stage EM_STG, respectively. Furthermore, the power supply voltage generation unit 200 may selectively output one of a first low voltage VGL1 and a second low voltage VGL2 to the write scan driving stage GW_STG, the compensated scan driving stage GC_STG, the initialization scan driving stage GI_STG, the bypass scan driving stage GB_STG, and the light-emitting driving stage EM_STG, respectively. Therefore, power consumption can be reduced by using the optimal voltage required by the multiple driver stages GW_STG, GC_STG, GI_STG, GB_STG, and EM_STG to drive the multiple driver stages respectively.

[0096] In one embodiment, the scan start signal and scan clock signal (or light emission start signal and light emission clock signal) of at least one of the write scan driver stage GW_STG, compensated scan driver stage GC_STG, initialization scan driver stage GI_STG, bypass scan driver stage GB_STG, and light emission driver stage EM_STG included in the display device 100 of the present invention can be switched between a second high voltage VGH2 and a second low voltage VGL2. Since the power consumption caused by the scan start signal and scan clock signal (or light emission start signal and light emission clock signal) is reduced in multiple driver stages, the display device 100 can further reduce power consumption. As described above, the display device 100 of the present invention can selectively output the required power supply voltage to the multiple driver stages GW_STG, GC_STG, GI_STG, GB_STG, and EM_STG of the scan driver 150 and the light emission driver 170, thereby minimizing the power wasted unnecessarily in driving the scan driver 150 and the light emission driver 170. Therefore, the display device 100 can improve the overall power consumption efficiency.

[0097] Figure 11 This is a block diagram illustrating an electronic device 1000 according to various embodiments of the present invention. Figure 12 This demonstrates what is achieved by a smartphone. Figure 11 A diagram of an example of an electronic device 1000.

[0098] Reference Figure 11 and Figure 12 The electronic device 1000 may include a processor 1010, a storage device 1020, a register device 1030, an input / output device 1040, a power supply 1050, and a display device 1060. In this case, the display device 1060 may be... Figure 1 The display device 100. Furthermore, the electronic device 1000 may also include various ports capable of communicating with graphics cards, sound cards, memory cards, USB devices, etc., or capable of communicating with other systems. In one embodiment, such as... Figure 12 As shown, electronic device 1000 can be implemented using a smartphone. However, this is exemplary, and electronic device 1000 is not limited thereto. For example, electronic device 1000 can also be implemented as a mobile phone, video phone, smart tablet, smartwatch, tablet PC, vehicle navigation system, computer monitor, laptop computer, head-mounted display device, etc.

[0099] Processor 1010 can perform specific calculations or tasks. According to embodiments, processor 1010 can be a microprocessor, central processing unit, application processor, etc. Processor 1010 can be connected to other components via address bus, control bus, and data bus. According to embodiments, processor 1010 can also be connected to an expansion bus such as a Peripheral Component Interconnect (PCI) bus. Storage device 1020 can store data required for the operation of electronic device 1000. For example, storage device 1020 may include non-volatile storage devices such as EPROM (Erasable Programmable Read-Only Memory), EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, PRAM (Phase Change Random Access Memory), RRAM (Resistance Random Access Memory), NFGM (Nano Floating Gate Memory), PoRAM (Polymer Random Access Memory), MRAM (Magnetic Random Access Memory), and FRAM (Ferroelectric Random Access Memory) and / or volatile storage devices such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and mobile DRAM. Register device 1030 may include solid-state drives (SSDs), hard disk drives (HDDs), CD-ROMs, etc. Input / output device 1040 may include input components such as a keyboard, keypad, touchpad, touchscreen, and mouse, and output components such as a speaker and printer. According to an embodiment, display device 1060 may also be included in input / output device 1040. Power supply 1050 provides the power required for the operation of electronic device 1000.The display device 1060 can be connected to other components via a bus or other communication link.

[0100] The display device 1060 can display images equivalent to the visual information of the electronic device 1000. In this case, the display device 1060 may include: a display panel including a plurality of pixels; a data driver that applies data signals to the display panel; a scan driver including a plurality of scan drive stages and sequentially applying scan signals to the display panel; a light-emitting driver including a light-emitting drive stage and sequentially applying light-emitting signals to the display panel; a controller that controls the scan driver, the light-emitting driver, and the data driver; and a power supply voltage generation unit that generates power supply voltages including high voltage and low voltage, and provides power supply voltages of different magnitudes to at least one of the plurality of scan drive stages and light-emitting drive stages. In this case, the power supply voltage generation unit may include: a voltage generation module that generates a first high voltage and a first low voltage based on the input voltage; and a voltage scaling module that scales the first high voltage to a second high voltage smaller than the first high voltage, and scales the first low voltage to a second low voltage larger than the first low voltage. The display devices according to various embodiments of the present invention can selectively output the required power supply voltage to the drive stages of the scan driver and the light-emitting driver, thereby minimizing the power consumed needlessly in the driving of the scan driver and the light-emitting driver. Therefore, display devices can improve overall power efficiency. However, this has already been described, so a repetition is omitted.

[0101] (Industry availability)

[0102] This invention is applicable to display devices and electronic devices including display devices. For example, it is applicable to high-resolution smartphones, mobile phones, smart tablets, smartwatches, tablet PCs, vehicle navigation systems, televisions, computer displays, laptops, etc.

[0103] The invention has been described above with reference to exemplary embodiments thereof. However, those skilled in the art should understand that various modifications and alterations may be made to the invention without departing from the spirit and scope of the invention as set forth in the claims.

Claims

1. A display device, comprising: The display panel includes multiple pixels; A data driver applies data signals to the display panel; The scan driver includes multiple scan drive stages and sequentially applies scan signals to the display panel; A light-emitting driver, including a light-emitting driving stage, sequentially applies light-emitting signals to the display panel; The controller controls the scan driver, the light-emitting driver, and the data driver; as well as The power supply voltage generation unit generates a power supply voltage including high voltage and low voltage, and provides different magnitudes of the high voltage or different magnitudes of the low voltage to at least one of the plurality of scan driving stages and the light emission driving stage. The power supply voltage generation unit generates a first high voltage, a first low voltage, a second high voltage smaller than the first high voltage, and a second low voltage larger than the first low voltage based on the input voltage. The scan start signal and scan clock signal of at least one of the plurality of scan drive stages switch between the second high voltage and the second low voltage.

2. The display device according to claim 1, wherein, The power supply voltage generation unit includes: A voltage generation module generates a first high voltage and a first low voltage based on the input voltage; and The voltage scaling module scales the first high voltage to the second high voltage and the first low voltage to the second low voltage.

3. The display device according to claim 2, wherein, The plurality of scan driver levels include a write scan driver level, a compensated scan driver level, an initialization scan driver level, and a bypass scan driver level.

4. The display device according to claim 3, wherein, The voltage scaling module determines the magnitudes of the second high voltage and the second low voltage based on pre-stored data.

5. The display device according to claim 3, wherein, The power supply voltage generation unit provides the second high voltage and the second low voltage to the compensation scan drive stage and the initialization scan drive stage.

6. The display device according to claim 5, wherein, The scan start signal and the scan clock signal of the compensation scan driver stage and the initialization scan driver stage switch between the second high voltage and the second low voltage.

7. The display device according to claim 5, wherein, The power supply voltage generation unit provides the first high voltage and the second low voltage to the write scan driver stage.

8. The display device according to claim 7, wherein, The scan start signal and the scan clock signal written to the scan driver level switch between the first high voltage and the second low voltage.

9. The display device according to claim 5, wherein, The light emission start signal and light emission clock signal of the light emission driver stage switch between the second high voltage and the second low voltage.

10. The display device according to claim 5, wherein, The scan start signal and the scan clock signal of the bypass scan driver stage switch between the second high voltage and the second low voltage.

Images