Memory device and method of operating the memory device

Abstract

Embodiments of the present disclosure relate to a memory device and a method of operating the memory device. A memory device includes: a plurality of memory cells; a threshold voltage distribution measurement component configured to measure a threshold voltage distribution of a first read operation for sensing data from programmed memory cells among the plurality of memory cells, and measure a threshold voltage distribution of a second read operation for sensing data from the programmed memory cells and output the data to the outside; a distribution offset compensation table generator configured to calculate an offset direction and an offset distance based on a result of comparing the threshold voltage distribution of the first read operation with the threshold voltage distribution of the second read operation, and generate a distribution offset compensation table based on the offset direction and the offset distance; and a read operation controller configured to perform a third read operation on a target memory cell based on the distribution offset compensation table.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0139629, filed with the Korean Intellectual Property Office on October 26, 2020, the entire disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a memory device and a method of operating the memory device. Background Art

[0004] A storage device is a device that stores data under the control of a host device (such as a computer or a smart phone). The storage device may include a memory device that stores data and a memory controller that controls the memory device. The memory device may be classified into a volatile memory device and a non-volatile memory device.

[0005] A volatile memory device may be a device that stores data only when powered and loses the stored data when the power supply is cut off. The volatile memory device may include: a static random access memory (SRAM), a dynamic random access memory (DRAM), etc.

[0006] A non-volatile memory device is a device that does not lose data even when the power supply is cut off. The non-volatile memory device includes: a read-only memory (ROM), a programmable ROM (PROM), an electrically programmable ROM (EPROM), an electrically erasable programmable ROM (EEPROM), a flash memory, etc. Summary of the Invention

[0007] A memory device according to an embodiment of the present disclosure may include: a plurality of memory cells; a threshold voltage distribution measurement component configured to measure a threshold voltage distribution of a first read operation for sensing data from programmed memory cells among the plurality of memory cells, and measure a threshold voltage distribution of a second read operation for sensing data from the programmed memory cells, and output data using a data output operation; a distribution offset compensation table generator configured to calculate an offset direction and an offset distance based on a result of comparing the threshold voltage distribution of the first read operation with the threshold voltage distribution of the second read operation, the offset direction indicating a direction in which the threshold voltage distribution of the second read operation is offset, the offset distance indicating a distance by which the threshold voltage distribution of the second read operation is offset based on the threshold voltage distribution of the first read operation, and generate a distribution offset compensation table based on the offset direction and the offset distance; and a read operation controller configured to perform a third read operation on a target memory cell among the plurality of memory cells based on the distribution offset compensation table.

[0008] A method of operating a memory device according to an embodiment of the present disclosure may include: performing a programming operation on a plurality of memory cells; measuring a threshold voltage distribution of a first read operation by performing a first read operation of sensing data from the plurality of memory cells; measuring a threshold voltage distribution of a second read operation by performing a second read operation of sensing data from the plurality of memory cells, and outputting data using a data output operation; calculating an offset direction and an offset distance based on a result of comparing the threshold voltage distribution of the first read operation with the threshold voltage distribution of the second read operation, the offset direction indicating a direction in which the threshold voltage distribution of the second read operation is offset, and the offset distance indicating a distance by which the threshold voltage distribution of the second read operation is offset based on the threshold voltage distribution of the first read operation; generating a distribution offset compensation table based on the offset direction and the offset distance; and performing a third read operation on a target memory cell based on the distribution offset compensation table. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. is a diagram illustrating a storage device according to an embodiment of the present disclosure.

[0010] Figure 2 FIG. is a diagram illustrating Figure 1 a memory device.

[0011] Figure 3 FIG. is a diagram illustrating Figure 2 an embodiment of a memory cell array.

[0012] Figure 4 FIG. is a circuit diagram illustrating any one of memory blocks BLK1 to BLKz, e.g., memory block BLKa, Figure 3 in.

[0013] Figure 5 FIG. is a circuit diagram illustrating another embodiment of any one of memory blocks BLK1 to BLKz, e.g., memory block BLKb, Figure 3 in.

[0014] Figure 6 FIG. is a diagram illustrating still another embodiment of any one of memory blocks BLK1 to BLKz, e.g., memory block BLKi, Figure 3 in.

[0015] Figure 7 FIG. is a diagram illustrating a first read operation, a second read operation, and a third read operation according to an embodiment of the present disclosure.

[0016] Figure 8A FIG. is a diagram illustrating a distribution offset compensation table including an evaluation time to be used for a third read operation according to an embodiment of the present disclosure.

[0017] Figure 8BIt is a diagram showing a distribution offset compensation table including read voltage levels to be used for a third read operation according to an embodiment of the present disclosure.

[0018] Figure 9A It is a diagram showing an example according to an embodiment of the present disclosure, in which the threshold voltage distribution corresponding to a second read operation is shifted higher than the threshold voltage distribution corresponding to a first read operation.

[0019] Figure 9B It is a diagram showing an evaluation time to be used for a second read operation according to an embodiment of the present disclosure.

[0020] Figure 9C It is a diagram showing read voltage levels to be used for a third read operation according to an embodiment of the present disclosure.

[0021] Figure 10A It is a diagram showing an example according to an embodiment of the present disclosure, in which the threshold voltage distribution corresponding to a second read operation is shifted lower than the threshold voltage distribution corresponding to a first read operation.

[0022] Figure 10B It is a diagram showing an evaluation time to be used for a second read operation according to an embodiment of the present disclosure.

[0023] Figure 10C It is a diagram showing read voltage levels to be used for a third read operation according to an embodiment of the present disclosure.

[0024] Figure 11 It is a flowchart showing a method of operating a memory device according to an embodiment of the present disclosure.

[0025] Figure 12 It is a flowchart showing a method of generating a distribution offset compensation table including an evaluation time to be used for a third read operation according to an embodiment of the present disclosure.

[0026] Figure 13 It is a flowchart showing a method of generating a distribution offset compensation table including read voltage levels to be used for a third read operation according to an embodiment of the present disclosure.

[0027] Figure 14 It is a diagram showing Figure 1 of a memory controller.

[0028] Figure 15 It is a block diagram showing a memory card system applying a storage device according to an embodiment of the present disclosure.

[0029] Figure 16 It is a block diagram showing a solid state drive (SSD) system applying a storage device according to an embodiment of the present disclosure.

[0030] Figure 17 is a block diagram showing a user system to which a storage device according to an embodiment of the present disclosure is applied. DETAILED DESCRIPTION

[0031] The description of the specific structures or functions of embodiments according to concepts disclosed in this specification or application is shown only for describing embodiments according to the concepts of the present disclosure. Embodiments according to the concepts of the present disclosure may be implemented in various forms, and the description is not limited to the embodiments described in this specification or application.

[0032] Embodiments of the present disclosure provide a memory device capable of compensating for an offset threshold voltage distribution during a sensing operation and a data output operation, and a method of operating the memory device.

[0033] According to the present technology, there is provided a memory device capable of compensating for an offset threshold voltage distribution during a sensing operation and a data output operation, and a method of operating the memory device.

[0034] Figure 1 is a diagram showing a storage device according to an embodiment of the present disclosure.

[0035] Reference Figure 1 , the storage device 50 may include a memory device 100 and a memory controller 200 that controls operations of the memory device. The storage device 50 may be a device that stores data under the control of a host 300, such as a cellular phone, a smartphone, an MP3 player, a laptop computer, a desktop computer, a gaming console, a television, a tablet computer, or an in-vehicle infotainment system.

[0036] According to a host interface as a communication method with the host 300, the storage device 50 may be manufactured as one of various types of storage devices. For example, the storage device 50 may be configured as any one of various types of storage devices (such as, an SSD, a multimedia card in the form of an MMC, an eMMC, an RS-MMC, and a micro-MMC, a secure digital card in the form of an SD, a mini-SD, and a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a personal computer memory card international association (PCMCIA) card type storage device, a peripheral component interconnect (PCI) card type storage device, a PCI express (PCI-E) card type storage device, a compact flash (CF) card, a smart media card, and a memory stick).

[0037] The storage device 50 can be fabricated in any one of various types of packages. For example, the storage device 50 can be fabricated in any one of various types of package types (such as, Package on Package (POP), System in Package (SIP), System on Chip (SOC), Multi-Chip Package (MCP), Chip on Board (COB), Wafer-Level Fabrication Package (WFP), and Wafer-Level Stacked Package (WSP)).

[0038] The memory device 100 can store data. The memory device 100 operates under the control of a memory controller 200. The memory device 100 can include a memory cell array (not shown) that includes a plurality of memory cells for storing data.

[0039] Each memory cell in the memory cell array can be configured as a single-level cell (SLC) that stores one data bit, a multi-level cell (MLC) that stores two data bits, a triple-level cell (TLC) that stores three data bits, or a quad-level cell (QLC) that can store four data bits.

[0040] The memory cell array (not shown) can include a plurality of memory blocks. One memory block can include a plurality of pages. In an embodiment, the page can be a unit for storing data or reading data stored in the memory device 100 in the memory device 100. The memory block can be a unit for erasing data.

[0041] In an embodiment, the memory device 100 can be a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), Low Power Double Data Rate 4 (LPDDR4) SDRAM, Graphics Double Data Rate (GDDR) SDRAM, Low Power DDR (LPDDR), Rambus Dynamic Random Access Memory (RDRAM), NAND flash memory, vertical NAND flash memory, NOR flash memory, Resistive Random Access Memory (RRAM), Phase Change Random Access Memory (PRAM), Magnetoresistive Random Access Memory (MRAM), Ferroelectric Random Access Memory (FRAM), Spin Transfer Torque Random Access Memory (STT-RAM), etc. In this specification, for ease of description, it is assumed that the memory device 100 is a NAND flash memory.

[0042] The memory device 100 is configured to receive a command CMD and an address ADDR from a memory controller 200 and access a region selected by the address in the memory cell array. The memory device 100 may perform an operation indicated by the command CMD on the region selected by the address ADDR. For example, the memory device 100 may perform a write operation (programming operation), a read operation, and an erase operation. During the programming operation, the memory device 100 may program data into the region selected by the address ADDR. During the read operation, the memory device 100 may read data from the region selected by the address ADDR. During the erase operation, the memory device 100 may erase the data stored in the region selected by the address ADDR.

[0043] In an embodiment, the memory device 100 may include: a threshold voltage distribution measurement component 131, a distribution offset compensation table generator 132, a distribution offset compensation table storage device 133, and a read operation controller 134.

[0044] The threshold voltage distribution measurement component 131 may measure a threshold voltage distribution indicating a result of performing a read operation.

[0045] In an embodiment, the threshold voltage distribution measurement component 131 may measure a threshold voltage distribution corresponding to a first read operation and a threshold voltage distribution corresponding to a second read operation. At this time, the first read operation may be an operation of sensing data from programmed memory cells among a plurality of memory cells. The second read operation may be an operation of sensing data from the programmed memory cells and outputting the data to the outside. Refer to Figure 7 for a description of the first read operation and the second read operation.

[0046] For example, the threshold voltage distribution measurement component 131 may perform a programming operation on a plurality of memory cells. In an embodiment, the threshold voltage distribution measurement component 131 may perform a programming operation on a plurality of memory cells in a single-level cell unit.

[0047] In addition, the threshold voltage distribution measurement component 131 may sense data from the programmed memory cells by performing a first read operation on the programmed memory cells. In an embodiment, the threshold voltage measurement component 131 may perform the first read operation in a single-level cell unit. Thereafter, the threshold voltage distribution measurement component 131 may calculate the number of failed bits of the data sensed by the first read operation. At this time, the number of failed bits may indicate the number of memory cells having a threshold voltage lower than the read voltage applied to the memory cells. The threshold voltage distribution measurement component 131 may measure the threshold voltage distribution corresponding to the first read operation based on the calculated number of failed bits.

[0048] In addition, the threshold voltage distribution measurement component 131 can sense data from the programmed memory cells by performing a second read operation on the programmed memory cells. At this time, the second read operation can be an operation performed to generate a distribution offset compensation table. In an embodiment, the threshold voltage measurement component 131 can perform the second read operation in units of single-level cells. Thereafter, the threshold voltage distribution measurement component 131 can calculate the number of failed bits of the data sensed by the second read operation. The threshold voltage distribution measurement component 131 can measure the threshold voltage distribution corresponding to the second read operation based on the calculated number of failed bits.

[0049] Meanwhile, in the above example, the threshold voltage distribution measurement component 131 measures the threshold voltage distribution by performing programming operations and read operations in units of single-level cells, but the present disclosure is not limited thereto. The threshold voltage distribution measurement component 131 can measure the threshold voltage distribution by performing programming operations and read operations in units of multi-level cells, triple-level cells, or quadruple-level cells.

[0050] The distribution offset compensation table generator 132 can generate a distribution offset compensation table. At this time, the distribution offset compensation table can include information for compensating for the offset phenomenon of the threshold voltage distribution that occurs during the third read operation. In an embodiment, the distribution offset compensation table can include at least one of an evaluation time and a read voltage level to be used for the third read operation. The third read operation can be an operation of sensing data from the programmed memory cells after the distribution offset compensation table is generated and outputting the data.

[0051] In an embodiment, the distribution offset compensation table generator 132 can generate the distribution offset compensation table based on the result of comparing the threshold voltage distribution corresponding to the first read operation with the threshold voltage distribution corresponding to the second read operation.

[0052] For example, the distribution offset compensation table generator 132 can compare the threshold voltage distribution corresponding to the first read operation with the threshold voltage distribution corresponding to the second read operation. Additionally, the distribution offset compensation table generator 132 can calculate an offset direction based on the comparison result, where the offset direction indicates the direction in which the threshold voltage distribution corresponding to the second read operation is offset based on the threshold voltage distribution corresponding to the first read operation. For example, the offset direction can indicate whether the threshold voltage distribution corresponding to the second read operation is offset to be higher or lower than the threshold voltage distribution corresponding to the first read operation. Additionally, the distribution offset compensation table generator 132 can calculate an offset distance based on the comparison result, where the offset distance indicates the distance by which the threshold voltage distribution corresponding to the second read operation is offset. Thereafter, the distribution offset compensation table generator 132 can generate a distribution offset compensation table based on the offset direction and the offset distance. For example, the distribution offset compensation table generator 132 can generate at least one of an evaluation time and a read voltage level to be used for a third read operation based on the offset direction and the offset distance.

[0053] Additionally, in an embodiment, the distribution offset compensation table generator 132 can generate a distribution offset compensation table based on a result of comparing the number of failed bits of data sensed by the first read operation with the number of failed bits of data sensed by the second read operation. For example, the distribution offset compensation table generator 132 can calculate an offset direction and an offset distance based on a result of comparing the number of failed bits of data sensed by the first read operation with the number of failed bits of data sensed by the second read operation. Thereafter, the distribution offset compensation table generator 132 can generate a distribution offset compensation table based on the offset direction and the offset distance.

[0054] The distribution offset compensation table storage device 133 can store the distribution offset compensation table.

[0055] The read operation controller 134 can control read operations. The read operations can include a first read operation, a second read operation, and a third read operation.

[0056] In an embodiment, the read operation controller 134 can perform a third read operation on a target memory cell based on the distribution offset compensation table. At this time, the target memory cell can be a memory cell on which a third read operation is to be performed according to a read command provided from the memory controller 200.

[0057] In an embodiment, the read operation controller 134 may perform a third read operation by using at least one of an evaluation time and a read voltage level included in a distribution offset compensation table. For example, the read operation controller 134 may perform an evaluation operation based on the evaluation time included in the distribution offset compensation table during the third read operation. As another example, the read operation controller 134 may perform the third read operation by using the read voltage level included in the distribution offset compensation table. In other words, the read operation controller 134 may compensate for the offset of the threshold voltage distribution generated by the third read operation by using the information included in the distribution offset compensation table.

[0058] The memory controller 200 may control the overall operation of the storage device 50.

[0059] When power is supplied to the storage device 50, the memory controller 200 may execute firmware (FW). When the memory device 100 is a flash memory device, the firmware (FW) may include a host interface layer (HIL) that controls communication with the host 300. The memory controller may include a flash translation layer (FTL) and a flash interface layer (FIL). The flash translation layer (FTL) controls communication between the host 300 and the memory device 100, and the flash interface layer (FIL) controls communication with the memory device 100.

[0060] In an embodiment, the memory controller 200 may receive data and a logical block address (LBA) from the host 300, and may transform the LBA into a physical block address (PBA), where the physical block address (PBA) indicates the address of the memory cells in the memory device 100 where the data is to be stored. In this specification, LBA, "logic address", and "logical address" may be used with the same meaning. In this specification, PBA and "physical address" may be used with the same meaning.

[0061] The memory controller 200 may control the memory device 100 to perform programming operations, read operations, erase operations, etc. according to requests from the host 300. During a programming operation, the memory controller 200 may provide a write command, a PBA, and data to the memory device 100. During a read operation, the memory controller 200 may provide a read command and a PBA to the memory device 100. During an erase operation, the memory controller 200 may provide an erase command and a PBA to the memory device 100.

[0062] In an embodiment, the memory controller 200 may generate commands, addresses, and data independently regardless of requests from the host 300, and send the commands, addresses, and data to the memory device 100. For example, the memory controller 200 may provide commands, addresses, and data for performing read operations and programming operations such as wear leveling, read recovery, garbage collection, etc. accompanying the read operations to the memory device 100.

[0063] In an embodiment, the memory controller 200 may control at least two or more memory devices 100. In this case, the memory controller 200 may control the memory devices 100 according to an interleaving method to improve operation performance. The interleaving method may be a method of controlling at least two memory devices 100 to operate overlapping each other.

[0064] The host 300 may use various communication methods (such as, Universal Serial Bus (USB), Serial ATA Attachment (SATA), Serial Attached SCSI (SAS), High-Speed Inter-Chip (HSIC), Small Computer System Interface (SCSI), Peripheral Component Interconnect (PCI), PCI Express (PCIe), Non-Volatile Memory Express (NVMe), Universal Flash Storage (UFS), Secure Digital (SD), Multimedia Card (MMC), Embedded MMC (eMMC), Dual In-line Memory Module (DIMM), Registered DIMM (RDIMM), and Load-Reduced DIMM (LRDIMM)) to communicate with the storage device 50.

[0065] Figure 2 is a diagram showing Figure 1 the memory device 100.

[0066] Referring Figure 2 to, the memory device 100 may include: a memory cell array 110, a peripheral circuit 120, and a control logic 130. The control logic 130 may be implemented as hardware, software, or a combination of hardware and software. For example, the control logic 130 may be a control logic circuit that operates according to an algorithm and / or a processor that executes control logic code.

[0067] The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to a row decoder 121 through row lines RL. The plurality of memory blocks BLK1 to BLKz may be connected to a page buffer group 123 through bit lines BL1 to BLm. Each memory block among the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. As an embodiment, the plurality of memory cells are non-volatile memory cells. Memory cells connected to the same word line may be defined as one page. Therefore, one memory block may include a plurality of pages.

[0068] The row lines RL may include: at least one source selection line, a plurality of word lines, and at least one drain selection line.

[0069] Each memory cell among the memory cells included in the memory cell array 110 may be configured to store a single-level cell (SLC) storing one data bit, a multi-level cell (MLC) storing two data bits, a triple-level cell (TLC) storing three data bits, or a quad-level cell (QLC) storing four data bits.

[0070] The peripheral circuit 120 may be configured to perform a programming operation, a read operation, or an erase operation on a selected area of the memory cell array 110 under the control of the control logic 130. The peripheral circuit 120 may drive the memory cell array 110. For example, the peripheral circuit 120 may apply various operation voltages to the row lines RL and the bit lines BL1 to BLm or release the applied voltages under the control of the control logic 130.

[0071] The peripheral circuit 120 may include: a row decoder 121, a voltage generator 122, a page buffer bank 123, a column decoder 124, and an input / output circuit 125.

[0072] The row decoder 121 is connected to the memory cell array 110 through the row lines RL. The row lines RL may include: at least one source selection line, a plurality of word lines, and at least one drain selection line. In an embodiment, the word lines may include normal word lines and dummy word lines. In an embodiment, the row lines RL may further include pipe selection lines.

[0073] The row decoder 121 is configured to operate in response to the control of the control logic 130. The row decoder 121 receives a row address RADD from the control logic 130.

[0074] The row decoder 121 is configured to decode the row address RADD received from the control logic 130. The row decoder 121 selects at least one memory block among the memory blocks BLK1 to BLKz according to the decoded address. Additionally, the row decoder 121 may select at least one word line in the selected memory block according to the decoded address to apply the voltage generated by the voltage generator 122 to at least one word line WL.

[0075] For example, during a programming operation, the row decoder 121 may apply a programming voltage to the selected word line and apply a programming pass voltage at a level lower than the programming voltage to the unselected word lines. During a programming verification operation, the row decoder 121 may apply a verification voltage to the selected word line and apply a verification pass voltage higher than the verification voltage to the unselected word lines. During a read operation, the row decoder 121 may apply a read voltage to the selected word line and apply a read pass voltage higher than the read voltage to the unselected word lines.

[0076] In an embodiment, an erase operation of the memory device 100 is performed in units of memory blocks. During the erase operation, the row decoder 121 may select one memory block according to the decoded address. During the erase operation, the row decoder 121 may apply a ground voltage to the word lines connected to the selected memory block.

[0077] The voltage generator 122 operates in response to the control of the control logic 130. The voltage generator 122 is configured to generate a plurality of voltages using an external power supply voltage applied to the memory device 100. Specifically, the voltage generator 122 may generate various operation voltages Vop for programming operations, read operations, and erase operations in response to an operation signal OPSIG. For example, the voltage generator 122 may generate a programming voltage, a verification voltage, a pass voltage, a read voltage, an erase voltage, etc. in response to the control of the control logic 130.

[0078] As an embodiment, the voltage generator 122 may generate an internal power supply voltage by adjusting the external power supply voltage. The internal power supply voltage generated by the voltage generator 122 is used as an operation voltage of the memory device 100.

[0079] As an embodiment, the voltage generator 122 may generate a plurality of voltages using an external power supply voltage or an internal power supply voltage.

[0080] For example, the voltage generator 122 may include a plurality of pumping capacitors that receive an internal power supply voltage, and may selectively activate the plurality of pumping capacitors in response to the control of the control logic 130 to generate a plurality of voltages.

[0081] The generated plurality of voltages may be provided to the memory cell array 110 through the row decoder 121.

[0082] The page buffer group 123 includes a first page buffer PB1 to an m-th page buffer PBm. The first page buffer PB1 to the m-th page buffer PBm are respectively connected to the memory cell array 110 through a first bit line BL1 to an m-th bit line BLm. The first page buffer PB1 to the m-th page buffer PBm operate in response to the control of the control logic 130. Specifically, the first page buffer PB1 to the m-th page buffer PBm may operate in response to a page buffer control signal PBSIGNALS. For example, the first page buffer PB1 to the m-th page buffer PBm may temporarily store data received through the first bit line BLx to the m-th bit line BLm, or may sense the voltage or current of the bit lines BL1 to BLm during a read operation or a verification operation. In an embodiment, m and x may be natural numbers.

[0083] Specifically, during a programming operation, when a programming pulse is applied to a selected word line, the first page buffer PB1 to the m-th page buffer PBm can transfer the data DATA received through the input / output circuit 125 to the memory cells selected through the first bit line BL1 to the m-th bit line BLm. The memory cells of the selected page are programmed according to the transferred data DATA. The memory cells connected to the bit lines to which a programming permission voltage (e.g., ground voltage) is applied can have an increased threshold voltage. The threshold voltage of the memory cells connected to the bit lines to which a programming inhibition voltage (e.g., power supply voltage) is applied can be maintained. During a programming verification operation, the first page buffer PB1 to the m-th page buffer PBm read page data from the selected memory cells through the first bit line BL1 to the m-th bit line BLm.

[0084] During a read operation, the first page buffer PB1 to the m-th page buffer PBm read the data DATA from the memory cells of the selected page through the first bit line BL1 to the m-th bit line BLm, and output the read data DATA to the input / output circuit 125 under the control of the column decoder 124.

[0085] During an erase operation, the first page buffer PB1 to the m-th page buffer PBm can float the first bit line BL1 to the m-th bit line BLm.

[0086] The column decoder 124 can transfer data between the input / output circuit 125 and the page buffer group 123 in response to a column address CADD. For example, the column decoder 124 can exchange data with the first page buffer PB1 to the m-th page buffer PBm through a data line DL, or can exchange data with the input / output circuit 125 through a column line CL.

[0087] The input / output circuit 125 can transfer the command CMD and the address ADDR received from the Figure 1 described memory controller 200 to the control logic 130, or can exchange data DATA with the column decoder 124.

[0088] The sense circuit 126 can generate a reference current in response to an enable bit signal VRYBIT during a read operation or a verification operation, and compare the comparison sense voltage VPB received from the page buffer group 123 with a reference voltage generated by the reference current to output a pass signal PASS or a fail signal FAIL.

[0089] The control logic 130 may output an operation signal OPSIG, a column address RADD, page buffer control signals PBSIGNALS, and an enable bit VRYBIT in response to a command CMD and an address ADDR to control the peripheral circuit 120. Additionally, the control logic 130 may determine whether a verification operation passes or fails in response to a pass signal PASS or a fail signal FAIL.

[0090] In an embodiment, the control logic 130 may include: a threshold voltage distribution measurement component 131, a distribution offset compensation table generator 132, a distribution offset compensation table storage device 133, and a read operation controller 134. At this time, the threshold voltage distribution measurement component 131, the distribution offset compensation table generator 132, the distribution offset compensation table storage device 133, and the read operation controller 134 may respectively indicate Figure 1 the threshold voltage distribution measurement component 131, the distribution offset compensation table generator 132, the distribution offset compensation table storage device 133, and the read operation controller 134.

[0091] Figure 3 is a diagram showing Figure 2 an embodiment of the memory cell array.

[0092] Referring to Figure 3 , the memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. Each memory block may have a three-dimensional structure. Each memory block includes a plurality of memory cells stacked on a substrate. Such a plurality of memory cells are arranged in the +X direction, +Y direction, and +Z direction. Referring to Figure 4 and Figure 5 describe the structure of each memory block.

[0093] Figure 4 is a circuit diagram showing Figure 3 any one of the memory blocks BLK1 to BLKz, i.e., memory block BLKa.

[0094] Referring to Figure 4 , the memory block BLKa includes a plurality of memory cell strings CS11 to CS1m and CS21 to CS2m. As an embodiment, each of the plurality of memory cell strings CS11 to CS1m and CS21 to CS2m may be formed in a "U" shape. In the memory block BLKa, m memory cell strings are arranged in the row direction (i.e., the +X direction). In Figure 4 , two memory cell strings are arranged in the column direction (i.e., the +Y direction). However, this is for ease of description, and it can be understood that three or more memory cell strings may be arranged in the column direction.

[0095] Each of the multiple memory cell strings CS11 to CS1m and CS21 to CS2m includes at least one source selection transistor SST, a first memory cell MC1 to an nth memory cell MCn, a pipeline transistor PT, and at least one drain selection transistor DST. In an embodiment, n may be a natural number.

[0096] Each of the selection transistors SST and DST and the memory cells MC1 to MCn may have a similar structure. As an embodiment, each of the selection transistors SST and DST and the memory cells MC1 to MCn may include: a channel layer, a tunnel insulating film, a charge storage film, and a blocking insulating film. As an embodiment, a pillar for providing a channel layer may be provided in each memory cell string. As an embodiment, a pillar for providing at least one element of a channel layer, a tunnel insulating film, a charge storage film, and a blocking insulating film may be provided in each memory cell string.

[0097] The source selection transistor SST of each memory cell string is connected between a common source line CSL and the memory cells MC1 to MCp. In an embodiment, p may be a natural number.

[0098] As an embodiment, the source selection transistors of the memory cell strings arranged in the same row are connected to a source selection line extending in the row direction, and the source selection transistors of the memory cell strings arranged in different rows are connected to different source selection lines. In Figure 4 this case, the source selection transistors of the memory cell strings CS11 to CS1m in the first row are connected to a first source selection line SSL1. The source selection transistors of the memory cell strings CS21 to CS2m in the second row are connected to a second source selection line SSL2.

[0099] As another embodiment, the source selection transistors of the memory cell strings CS11 to CS1m and CS21 to CS2m may be commonly connected to one source selection line.

[0100] The first memory cell MC1 to the nth memory cell MCn of each memory cell string are connected between the source selection transistor SST and the drain selection transistor DST.

[0101] The first memory cell MC1 to the nth memory cell MCn can be divided into the first memory cell MC1 to the pth memory cell MCp and the (p + 1)th memory cell MCp+1 to the nth memory cell MCn. The first memory cell MC1 to the pth memory cell MCp are sequentially arranged in a direction opposite to the +Z direction and are serially connected between the source selection transistor SST and the pipeline transistor PT. The (p + 1)th memory cell MCp+1 to the nth memory cell MCn are sequentially arranged in the +Z direction and are serially connected between the pipeline transistor PT and the drain selection transistor DST. The first memory cell MC1 to the pth memory cell MCp and the (p + 1)th memory cell MCp+1 to the nth memory cell MCn are connected to each other through the pipeline transistor PT. The gates of the first memory cell MC1 to the nth memory cell MCn of each memory cell string are respectively connected to the first word line WL1 to the nth word line WLn.

[0102] The gate of the pipeline transistor PT of each memory cell string is connected to the pipeline PL.

[0103] The drain selection transistor DST of each memory cell string is connected between the corresponding bit line and the memory cells MCp+1 to MCn. The memory cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the memory cell strings CS11 to CS1m in the first row are connected to the first drain selection line DSL1. The drain selection transistors of the memory cell strings CS21 to CS2m in the second row are connected to the second drain selection line DSL2.

[0104] The cell strings arranged in the column direction are connected to the bit lines extending in the column direction. In Figure 4 the first column, the memory cell strings CS11 and CS21 are connected to the first bit line BL1. The memory cell strings CS1m and CS2m in the mth column are connected to the mth bit line BLm.

[0105] The memory cells connected to the same word line in the memory cell strings arranged in the row direction configure a page. For example, in the memory cell strings CS11 to CS1m in the first row, the memory cells connected to the first word line WL1 configure a page. In the memory cell strings CS21 to CS2m in the second row, the memory cells connected to the first word line WL1 configure another page. The memory cell strings arranged in the row direction can be selected by selecting any one of the drain selection lines DSL1 and DSL2. A page of the selected memory cell string can be selected by selecting any one of the word lines WL1 to WLn.

[0106] As another embodiment, even bit lines and odd bit lines may be provided instead of the first bit line BL1 to the m-th bit line BLm. Additionally, even memory cell strings among the memory cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be respectively connected to the even bit lines, and odd memory cell strings among the memory cell strings CS11 to CS1m or CS21 to CS2m arranged in the row direction may be respectively connected to the odd bit lines.

[0107] As an embodiment, at least one of the first memory cell MC1 to the n-th memory cell MCn may be used as a dummy memory cell. For example, providing at least one dummy memory cell is to reduce the electric field between the source selection transistor SST and the memory cells MC1 to MCp. Alternatively, providing at least one dummy memory cell is to reduce the electric field between the drain selection transistor DST and the memory cells MCp+1 to MCn. As more dummy memory cells are provided, the reliability of the operations on the memory block BLKa is improved, however, the size of the memory block BLKa increases. As fewer memory cells are provided, the size of the memory block BLKa can be reduced, however, the reliability of the operations on the memory block BLKa can be reduced. In the embodiment, a may be a natural number.

[0108] To effectively control at least one dummy memory cell, each of the dummy memory cells in the dummy memory cells may have a desired threshold voltage. Before or after the erase operation on the memory block BLKa, a program operation may be performed for all the dummy memory cells or some of the dummy memory cells. When the erase operation is performed after the program operation, by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell, the dummy memory cell may have a desired threshold voltage.

[0109] Figure 5 is a circuit diagram showing Figure 3 another embodiment of any one of the memory blocks BLKb in the memory blocks BLK1 to BLKz. In the embodiment, b may be a natural number.

[0110] Reference Figure 5, the memory block BLKb includes a plurality of memory cell strings CS11’ to CS1m’ and CS21’ to CS2m’. Each of the plurality of memory cell strings CS11’ to CS1m’ and CS21’ to CS2m’ extends in the +Z direction. Each of the plurality of memory cell strings CS11’ to CS1m’ and CS21’ to CS2m’ includes: at least one source selection transistor SST, first memory cells MC1 to nth memory cells MCn, and at least one drain selection transistor DST stacked on a substrate (not shown) below the memory block BLK1’.

[0111] The source selection transistor SST of each memory cell string is connected between the common source line CSL and the memory cells MC1 to MCn. The source selection transistors of the memory cell strings arranged in the same row are connected to the same source selection line. The source selection transistors of the memory cell strings CS11’ to CS1m’ arranged in the first row are connected to the first source selection line SSL1. The source selection transistors of the memory cell strings CS21’ to CS2m’ arranged in the second row are connected to the second source selection line SSL2. As another embodiment, the source selection transistors of the memory cell strings CS11’ to CS1m’ and CS21’ to CS2m’ can be commonly connected to one source selection line.

[0112] The first memory cells MC1 to nth memory cells MCn of each memory cell string are connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the first memory cells MC1 to nth memory cells MCn are respectively connected to the first word line WL1 to the nth word line WLn.

[0113] The drain selection transistor DST of each memory cell string is connected between the corresponding bit line and the memory cells MC1 to MCn. The drain selection transistors of the memory cell strings arranged in the row direction are connected to the drain selection lines extending in the row direction. The drain selection transistors of the memory cell strings CS11’ to CS1m’ in the first row are connected to the first drain selection line DSL1. The drain selection transistors of the memory cell strings CS21’ to CS2m’ in the second row are connected to the second drain selection line DSL2.

[0114] As a result, Figure 5 the memory block BLKb has an equivalent circuit similar to that of Figure 4 the memory block BLKa, except that the pipeline transistor PT is excluded from each memory cell string.

[0115] As another embodiment, even bit lines and odd bit lines may be provided instead of the first bit line BL1 to the m-th bit line BLm. Additionally, even memory cell strings among the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be respectively connected to the even bit lines, and odd memory cell strings among the memory cell strings CS11' to CS1m' or CS21' to CS2m' arranged in the row direction may be respectively connected to the odd bit lines.

[0116] As an embodiment, at least one of the first memory cell MC1 to the n-th memory cell MCn may be used as a dummy memory cell. For example, providing at least one dummy memory cell reduces the electric field between the source select transistor SST and the memory cells MC1 to MCn. Alternatively, providing at least one dummy memory cell reduces the electric field between the drain select transistor DST and the memory cells MC1 to MCn. As more dummy memory cells are provided, the reliability of the operations on the memory block BLKb is improved. However, the size of the memory block BLKb increases. As fewer memory cells are provided, the size of the memory block BLKb can be reduced. However, the reliability of the operations on the memory block BLKb can be reduced.

[0117] To effectively control at least one dummy memory cell, each of the dummy memory cells in the dummy memory cells may have a desired threshold voltage. Before or after the erase operation on the memory block BLKb, a programming operation may be performed on all or some of the dummy memory cells. When the erase operation is performed after the programming operation, by controlling the voltage applied to the dummy word line connected to the corresponding dummy memory cell, the dummy memory cell may have a desired threshold voltage.

[0118] Figure 6 is a diagram showing Figure 3 yet another embodiment of any one of the memory blocks BLKi among the memory blocks BLK1 to BLKz

[0119] Reference Figure 6, a plurality of word lines arranged parallel to each other can be connected between a first selection line and a second selection line. Herein, the first selection line can be a source selection line SSL, and the second selection line can be a drain selection line DSL. More specifically, the memory block BLKi can include a plurality of memory cell strings ST connected between bit lines BL1 to BLm and a common source line CSL. The bit lines BL1 to BLm can be respectively connected to the memory cell strings ST, and the common source line CSL can be commonly connected to the memory cell strings ST. Since the memory cell strings ST can be configured to be the same as each other, the memory cell string ST connected to the first bit line BL1 is specifically described as an example.

[0120] The memory cell string ST can include: a source selection transistor SST, a plurality of memory cells MC1 to MC16, and a drain selection transistor DST connected in series between the common source line CSL and the first bit line BL1. One memory cell string ST can include at least one or more drain selection transistors among the drain selection transistors, and can include a source selection transistor SST and more memory cells MC1 to MC16 than the number shown in the figure.

[0121] The source of the source selection transistor SST can be connected to the common source line CSL, and the drain of the drain selection transistor DST can be connected to the first bit line BL1. The memory cells MC1 to MC16 can be connected in series between the source selection transistor SST and the drain selection transistor DST. The gates of the source selection transistors SST included in different memory cell strings ST can be connected to the source selection line SSL, the gates of the drain selection transistors DST can be connected to the drain selection line DSL, and the gates of the memory cells MC1 to MC16 can be connected to a plurality of word lines WL1 to WL16. A group of memory cells connected to the same word line among the memory cells included in different memory cell strings ST can be called a page PG. Therefore, the memory block BLKi can include pages PG of a plurality of word lines WL1 to WL16.

[0122] One memory cell can store one bit of data. This is generally referred to as SLC. In this case, one physical page PG can store one logical page (LPG) data. One logical page (LPG) data can include the same number of data bits as the cells included in one physical page PG.

[0123] One memory cell can store two or more bits of data. In this case, one physical page PG can store two or more logical page (LPG) data.

[0124] Figure 7FIG. is a diagram showing a first read operation, a second read operation, and a third read operation according to an embodiment of the present disclosure.

[0125] Figure 7 The memory cell array 110, page buffer bank 123, column decoder 124, and input / output circuit 125 of may respectively indicate Figure 2 the memory cell array 110, page buffer bank 123, column decoder 124, and input / output circuit 125 of.

[0126] In an embodiment, the memory device 100 may perform a sensing operation and a data output operation according to a read command of the memory controller 200.

[0127] In an embodiment, the sensing operation may be an operation of sensing data DATA from the memory cell array 110 based on an address corresponding to the read command and storing the sensed data DATA in any one of a plurality of page buffers included in the page buffer bank 123.

[0128] In an embodiment, the data output operation may be an operation of outputting the data DATA stored in the page buffer bank 123 to the outside through the column decoder 124 and the input / output circuit 125 according to the sensing operation. For example, the data output operation may be an operation of outputting the sensed data DATA to the memory controller 200.

[0129] In an embodiment, the first read operation may include a sensing operation.

[0130] In an embodiment, the second read operation and the third read operation may include a sensing operation and a data output operation. For example, the second read operation may be an operation performed to generate a distribution offset compensation table. The third read operation may be an operation performed after generating the distribution offset compensation table.

[0131] Meanwhile, in the case of a cache read operation, the sensing operation and the data output operation may be performed simultaneously. At this time, since the data output operation may affect the sensing operation, noise may be generated in the sensing operation. Therefore, the threshold voltage distribution corresponding to the cache read operation may be offset based on the threshold voltage distribution corresponding to the first read operation. In addition, the number of failed bits of the data sensed by the cache read operation may increase, and thus a read failure may occur. As used herein, the words "simultaneously" and "at the same time" mean that events occur over overlapping time intervals. For example, if a first event occurs within a first time interval and a second event occurs simultaneously within a second time interval, then the first interval and the second interval at least partially overlap each other such that there is a time when both the first event and the second event occur.

[0132] Thus, according to an embodiment of the present disclosure, a distribution offset compensation table can be generated based on a result of comparing a threshold voltage distribution corresponding to a first read operation with a threshold voltage distribution corresponding to a second read operation, and a third read operation can be performed using the generated distribution offset compensation table to compensate for the offset threshold voltage distribution.

[0133] Figure 8A FIG. is a diagram showing a distribution offset compensation table including an evaluation time to be used for a third read operation according to an embodiment of the present disclosure.

[0134] Reference Figure 8A , the distribution offset compensation table LUT may include an evaluation time Evaluation time to be used for a third read operation. At this time, the evaluation time Evaluation time may be increased to be greater than a reference evaluation time or decreased to be less than the reference evaluation time. In an embodiment, the reference evaluation time may be an evaluation time for an evaluation operation performed during a verification operation.

[0135] In an embodiment, the distribution offset compensation table generator 132 may generate a distribution offset compensation table LUT including an evaluation time Evaluation time based on a result of comparing a threshold voltage distribution corresponding to a first read operation with a threshold voltage distribution corresponding to a second read operation. The distribution offset compensation table LUT may be stored in the distribution offset compensation table storage device 133.

[0136] In an embodiment, the read operation controller 134 may perform a third read operation using the evaluation time Evaluation time included in the distribution offset compensation table LUT.

[0137] Figure 8B FIG. is a diagram showing a distribution offset compensation table including a read voltage level to be used for a third read operation according to an embodiment of the present disclosure.

[0138] Reference Figure 8B , the distribution offset compensation table LUT may include a read voltage level Read voltage level to be used for a third read operation. At this time, the read voltage level Read voltage level may be increased to be greater than a reference read voltage level or decreased to be less than the reference read voltage level. In an embodiment, the reference read voltage level may be a default read voltage. In an embodiment, the default read voltage may be a read voltage determined through a test during a manufacturing process of the memory device 100.

[0139] In an embodiment, the distribution offset compensation table generator 132 may generate a distribution offset compensation table LUT including a read voltage level based on a result of comparing a threshold voltage distribution corresponding to a first read operation with a threshold voltage distribution corresponding to a second read operation. The distribution offset compensation table LUT may be stored in the distribution offset compensation table storage device 133.

[0140] In an embodiment, the read operation controller 134 may perform a third read operation using the read voltage level included in the distribution offset compensation table LUT.

[0141] Figure 9A FIG. is a diagram showing an example according to an embodiment of the present disclosure, in which a threshold voltage distribution corresponding to a second read operation is shifted to be higher than a threshold voltage distribution corresponding to a first read operation.

[0142] In Figure 9A the horizontal axis indicates the threshold voltage of the memory cell, and the vertical axis indicates the number of memory cells.

[0143] In Figure 9A for ease of description, it is assumed that the memory cell is a SLC cell programmed to store one bit of data, but the present disclosure is not limited thereto.

[0144] Referring Figure 9A to, a threshold voltage distribution indicating a result of performing a first read operation at a reference read voltage level Vr on the programmed memory cell is shown by a solid line. In addition, a threshold voltage distribution indicating a result of performing a second read operation at the reference read voltage level Vr on the programmed memory cell is shown by a dashed line.

[0145] Specifically, the distribution offset compensation table generator 132 can compare the threshold voltage distribution corresponding to the second read operation with the threshold voltage distribution corresponding to the first read operation to determine that the threshold voltage distribution corresponding to the second read operation is offset to be higher than the threshold voltage distribution corresponding to the first read operation. Additionally, the distribution offset compensation table generator 132 can calculate an offset distance ΔS1 between the threshold voltage distribution corresponding to the second read operation and the threshold voltage distribution corresponding to the first read operation. For example, if the number of failed bits according to the first read operation is greater than the number of failed bits according to the second read operation, the threshold voltage distribution corresponding to the second read operation is offset to be higher than the threshold voltage distribution corresponding to the first read operation. The distribution offset compensation table generator 132 can determine the offset distance ΔS1 based on the difference between the number of failed bits according to the first read operation and the number of failed bits according to the second read operation. In this case, in order to compensate for the offset of the threshold voltage distribution generated during the third read operation, the read voltage level for the third read operation can be shifted to a first read voltage level V1 that is higher than the reference read voltage level Vr.

[0146] Figure 9B FIG. is a diagram showing an evaluation time to be used for a third read operation according to an embodiment of the present disclosure.

[0147] Specifically, Figure 9B FIG. is a diagram showing an evaluation time to be used for a third read operation when the threshold voltage distribution corresponding to the second read operation as shown in Figure 9A is offset to be higher than the threshold voltage distribution corresponding to the first read operation.

[0148] Referring to Figure 9A and Figure 9B , when the threshold voltage distribution corresponding to the second read operation is offset to be higher than the threshold voltage distribution corresponding to the first read operation, the distribution offset compensation table generator 132 can generate a distribution offset compensation table including an evaluation time increased to be greater than the reference evaluation time based on the offset distance. In an embodiment, the reference evaluation time can be the evaluation time tEV_verify of the evaluation operation performed during the verification operation.

[0149] For example, the distribution offset compensation table generator 132 can determine an evaluation time tEV_read that is increased to be greater than the evaluation time tEV_verify for the verification operation as the evaluation time to be used for the third read operation. At this time, the difference ΔT1 between the evaluation time tEV_verify for the verification operation and the increased evaluation time tEV_read can be determined based on the offset distance ΔS1.

[0150] Thereafter, the read operation controller 134 may perform an evaluation operation included in the third read operation using the increased evaluation time tEV_read.

[0151] Figure 9C is a diagram showing read voltage levels to be used for a third read operation according to an embodiment of the present disclosure.

[0152] Specifically, Figure 9C is a diagram showing read voltage levels to be used for a third read operation when the threshold voltage distribution corresponding to a second read operation is shifted to be higher than the threshold voltage distribution corresponding to a first read operation as Figure 9A shown.

[0153] Referring to Figure 9A and Figure 9C , when the threshold voltage distribution corresponding to the second read operation is shifted to be higher than the threshold voltage distribution corresponding to the first read operation, the distribution offset compensation table generator 132 may generate a distribution offset compensation table including read voltage levels higher than a reference read voltage level based on the offset distance. In an embodiment, the reference read voltage level may be a default read voltage level.

[0154] For example, the distribution offset compensation table generator 132 may determine a first read voltage level V1 higher than the reference read voltage level Vr as the read voltage level to be used for the third read operation. At this time, the difference between the reference voltage level Vr and the first read voltage level V1 (i.e., the offset distance ΔS1) may be determined based on the offset distance ΔS1.

[0155] Thereafter, the read operation controller 134 may perform the third read operation using the first read voltage level V1.

[0156] Figure 10A is a diagram showing an example according to an embodiment of the present disclosure, in which the threshold voltage distribution corresponding to a second read operation is shifted to be lower than the threshold voltage distribution corresponding to a first read operation.

[0157] In Figure 10A , the horizontal axis indicates the threshold voltage of the memory cells, and the vertical axis indicates the number of memory cells.

[0158] In Figure 10A , for ease of description, it is assumed that the memory cells are SLC cells programmed to store one bit of data, but the present disclosure is not limited thereto.

[0159] Referring to Figure 10A, a threshold voltage distribution indicating the result of performing a first read operation on a programmed memory cell at a reference read voltage level Vr is shown by a solid line. Additionally, a threshold voltage distribution indicating the result of performing a second read operation on the programmed memory cell at the reference read voltage level Vr is shown by a dashed line.

[0160] Specifically, the distribution offset compensation table generator 132 can compare the threshold voltage distribution corresponding to the second read operation with the threshold voltage distribution corresponding to the first read operation to determine that the threshold voltage distribution corresponding to the second read operation is offset to be lower than the threshold voltage distribution corresponding to the first read operation. Additionally, the distribution offset compensation table generator 132 can calculate an offset distance -ΔS2 between the threshold voltage distribution corresponding to the second read operation and the threshold voltage distribution corresponding to the first read operation. For example, if the number of failed bits according to the first read operation is lower than the number of failed bits according to the second read operation, the threshold voltage distribution corresponding to the second read operation is offset to be lower than the threshold voltage distribution corresponding to the first read operation. The distribution offset compensation table generator 132 can determine the offset distance -ΔS2 based on the difference between the number of failed bits according to the first read operation and the number of failed bits according to the second read operation. In this case, in order to compensate for the offset of the threshold voltage distribution generated during the third read operation, the read voltage level for the third read operation can be shifted to a second read voltage level V2 that is lower than the reference read voltage level Vr.

[0161] Figure 10B is a diagram showing the evaluation time to be used for a third read operation according to an embodiment of the present disclosure.

[0162] Specifically, Figure 10B is a diagram showing the evaluation time to be used for a third read operation when the threshold voltage distribution corresponding to the second read operation is offset to be lower than the threshold voltage distribution corresponding to the first read operation as shown Figure 10A .

[0163] Referring to Figure 10A and Figure 10B , when the threshold voltage distribution corresponding to the second read operation is offset to be lower than the threshold voltage distribution corresponding to the first read operation, the distribution offset compensation table generator 132 can generate a distribution offset compensation table including a reduction to less than the reference evaluation time based on the offset distance. In an embodiment, the reference evaluation time can be the evaluation time tEV_verify of the evaluation operation performed during the verification operation.

[0164] For example, the distribution offset compensation table generator 132 may determine an evaluation time tEV_read that is reduced to less than the evaluation time tEV_verify for the verification operation as the evaluation time to be used for the third read operation. At this time, the difference -ΔT2 between the evaluation time tEV_verify for the verification operation and the reduced evaluation time tEV_read may be determined based on the offset distance -ΔS2.

[0165] Thereafter, the read operation controller 134 may perform an evaluation operation included in the third read operation using the reduced evaluation time tEV_read.

[0166] Figure 10C FIG. is a diagram showing read voltage levels to be used for a third read operation according to an embodiment of the present disclosure.

[0167] Specifically, Figure 10C is a diagram showing read voltage levels to be used for a third read operation when the threshold voltage distribution corresponding to a second read operation is shifted lower than the threshold voltage distribution corresponding to a first read operation as shown in Figure 10A FIG.

[0168] Referring to Figure 10A and Figure 10C , when the threshold voltage distribution corresponding to the second read operation is shifted lower than the threshold voltage distribution corresponding to the first read operation, the distribution offset compensation table generator 132 may generate a distribution offset compensation table including read voltage levels lower than a reference read voltage level based on the offset distance. In an embodiment, the reference read voltage level may be a default read voltage level.

[0169] For example, the distribution offset compensation table generator 132 may determine a second read voltage level V2 lower than the reference read voltage level Vr as the read voltage level to be used for the third read operation. At this time, the difference (i.e., the offset distance -ΔS2) between the reference read voltage level Vr and the second read voltage level V2 may be determined based on the offset distance -ΔS2.

[0170] Thereafter, the read operation controller 134 may perform the third read operation using the second read voltage level V2.

[0171] Figure 11 FIG. is a flowchart showing a method of operating a memory device according to an embodiment of the present disclosure.

[0172] For example, Figure 11 the method shown in Figure 1 FIG. may be performed by the memory device 100 shown in

[0173] Referring to Figure 11, at step S1101, the memory device 100 may perform a programming operation on multiple memory cells.

[0174] In step S1103, the memory device 100 may measure a threshold voltage distribution corresponding to the first read operation by performing a first read operation of sensing data from multiple memory cells.

[0175] At this time, the memory device 100 may measure a threshold voltage distribution corresponding to the first read operation by calculating the number of failed bits of the data sensed by the first read operation on multiple memory cells.

[0176] In step S1105, the memory device 100 may measure a threshold voltage distribution corresponding to the second read operation by performing a second read operation of sensing data from multiple memory cells and outputting the data to the outside.

[0177] At this time, the memory device 100 may measure a threshold voltage distribution corresponding to the second read operation by calculating the number of failed bits of the data sensed by the second read operation on multiple memory cells.

[0178] In step S1107, the memory device 100 may generate a distribution offset compensation table based on a result of comparing the threshold voltage distribution corresponding to the first read operation with the threshold voltage distribution corresponding to the second read operation.

[0179] At this time, based on a result of comparing the threshold voltage distribution corresponding to the first read operation with the threshold voltage distribution corresponding to the second read operation, the memory device 100 may calculate an offset direction and an offset distance, the offset direction indicating a direction in which the threshold voltage distribution corresponding to the second read operation is offset, and the offset distance indicating a distance by which the threshold voltage distribution corresponding to the second read operation is offset based on the threshold voltage distribution corresponding to the first read operation.

[0180] In addition, the memory device 100 may generate a distribution offset compensation table based on the offset direction and the offset distance.

[0181] In step S1109, the memory device 100 may store the distribution offset compensation table.

[0182] In step S1111, the memory device 100 may perform a third read operation on a target memory cell based on the distribution offset compensation table.

[0183] At this time, the memory device 100 may perform the third read operation using at least one of an evaluation time and a read voltage level.

[0184] Figure 12It is a flowchart showing a method of generating a distribution offset compensation table including an evaluation time to be used for a third read operation according to an embodiment of the present disclosure.

[0185] For example, Figure 12 the method shown can be performed by Figure 1 the memory device 100 shown.

[0186] Referring to Figure 12 , in step S1201, the memory device 100 can compare the threshold voltage distribution corresponding to the second read operation with the threshold voltage distribution corresponding to the first read operation to determine whether the threshold voltage distribution corresponding to the second read operation is shifted to be higher than the threshold voltage distribution corresponding to the first read operation.

[0187] When the threshold voltage distribution corresponding to the second read operation is shifted to be higher than the threshold voltage distribution corresponding to the first read operation according to the determination result in step S1201, in step S1203, the memory device 100 can generate a distribution offset compensation table including an evaluation time increased to be greater than the reference evaluation time based on the offset distance.

[0188] When the threshold voltage distribution corresponding to the second read operation is not shifted to be higher than the threshold voltage distribution corresponding to the first read operation according to the determination result in step S1201, in step S1205, the memory device 100 can compare the threshold voltage distribution corresponding to the second read operation with the threshold voltage distribution corresponding to the first read operation to determine whether the threshold voltage distribution corresponding to the second read operation is shifted to be lower than the threshold voltage distribution corresponding to the first read operation.

[0189] When the threshold voltage distribution corresponding to the second read operation is shifted to be lower than the threshold voltage distribution corresponding to the first read operation according to the determination result in step S1205, in step S1207, the memory device 100 can generate a distribution offset compensation table including an evaluation time decreased to be less than the reference evaluation time based on the offset distance.

[0190] When the threshold voltage distribution corresponding to the second read operation is not shifted to be lower than the threshold voltage distribution corresponding to the first read operation according to the determination result in step S1205, the operation of generating the distribution offset compensation table can be ended.

[0191] Figure 13 It is a flowchart showing a method of generating a distribution offset compensation table including a read voltage level to be used for a third read operation according to an embodiment of the present disclosure.

[0192] For example, Figure 13 the method shown can be performed by Figure 1is executed by the memory device 100 shown.

[0193] Reference Figure 13 , in step S1301, the memory device 100 may compare the threshold voltage distribution corresponding to the second read operation with the threshold voltage distribution corresponding to the first read operation to determine whether the threshold voltage distribution corresponding to the second read operation is shifted to be higher than the threshold voltage distribution corresponding to the first read operation.

[0194] When the threshold voltage distribution corresponding to the second read operation is shifted to be higher than the threshold voltage distribution corresponding to the first read operation according to the determination result in step S1301, in step S1303, the memory device 100 may generate a distribution offset compensation table including read voltage levels higher than the reference read voltage level based on the offset distance.

[0195] When the threshold voltage distribution corresponding to the second read operation is not shifted to be higher than the threshold voltage distribution corresponding to the first read operation according to the determination result in step S1301, in step S1305, the memory device 100 may compare the threshold voltage distribution corresponding to the second read operation with the threshold voltage distribution corresponding to the first read operation to determine whether the threshold voltage distribution corresponding to the second read operation is shifted to be lower than the threshold voltage distribution corresponding to the first read operation.

[0196] When the threshold voltage distribution corresponding to the second read operation is shifted to be lower than the threshold voltage distribution corresponding to the first read operation according to the determination result in step S1305, in step S1307, the memory device 100 may generate a distribution offset compensation table including read voltage levels lower than the reference read voltage level based on the offset distance.

[0197] When the threshold voltage distribution corresponding to the second read operation is not shifted to be lower than the threshold voltage distribution corresponding to the first read operation according to the determination result in step S1305, the operation of generating the distribution offset compensation table may be ended.

[0198] Figure 14 is a diagram showing Figure 1 the memory controller.

[0199] Reference Figure 1 and Figure 14 , the memory controller 200 may include: a processor 220, a RAM 230, an error correction circuit 240, a ROM 260, a host interface 270, and a flash interface 280.

[0200] The processor 220 may control the overall operation of the memory controller 200. The RAM 230 may be used as buffer memory, cache memory, operating memory, etc. of the memory controller 200.

[0201] The error correction circuit 240 may perform error correction. The error correction circuit 240 may perform error correction coding (ECC coding) based on data to be written to the memory device 100 through the flash memory interface 280. The error correction coded data may be transmitted to the memory device 100 through the flash memory interface 280. The error correction circuit 240 may perform error correction decoding (ECC decoding) on the data received from the memory device 100 through the flash memory interface 280. For example, the error correction circuit 240 may be included in the flash memory interface 280 as a component of the flash memory interface 280.

[0202] The ROM 260 may store various information required to operate the memory controller 200 in the form of firmware.

[0203] The memory controller 200 may communicate with external devices (e.g., the host 300, the application processor, etc.) through the host interface 270.

[0204] The memory controller 200 may communicate with the memory device 100 through the flash memory interface 280. The memory controller 200 may send commands, addresses, control signals, etc. to the memory device 100 and receive data through the flash memory interface 280. For example, the flash memory interface 280 may include a NAND interface.

[0205] Figure 15 is a block diagram showing a memory card system of a storage device applying an embodiment of the present disclosure.

[0206] Reference Figure 15 , the memory card system 2000 includes a memory controller 2100, a memory device 2200, and a connector 2300.

[0207] The memory controller 2100 is connected to the memory device 2200. The memory controller 2100 is configured to access the memory device 2200. For example, the memory controller 2100 may be configured to control read operations, write operations, erase operations, and background operations of the memory device 2200. The memory controller 2100 is configured to provide an interface between the memory device 2200 and the host. The memory controller 2100 is configured to drive firmware for controlling the memory device 2200. The memory controller 2100 may be equivalently implemented as the memory controller 200 described with reference to Figure 1 The memory controller 2200 may be identically implemented as the memory device 100 described with reference to Figure 2 described.

[0208] For example, the memory controller 2100 may include components such as a random access memory (RAM), a processor, a host interface, a memory interface, and an error corrector.

[0209] The memory controller 2100 may communicate with an external device through the connector 2300. The memory controller 2100 may communicate with an external device (e.g., a host) according to a specific communication standard. For example, the memory controller 2100 is configured to communicate with an external device through at least one communication standard among various communication standards such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe. For example, the connector 2300 may be defined by at least one of the above various communication standards.

[0210] For example, the memory device 2200 may be composed of various non-volatile memory elements such as electrically erasable programmable ROM (EEPROM), NAND flash memory, NOR flash memory, phase change RAM (PRAM), resistive RAM (ReRAM), ferroelectric RAM (FRAM), and spin transfer torque magnetic RAM (STT-MRAM).

[0211] The memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card. For example, the memory controller 2100 and the memory device 2200 may be integrated into one semiconductor device to configure a memory card such as a PC card (Personal Computer Memory Card International Association (PCMCIA)), a CompactFlash card (CF), a SmartMedia card (SM or SMC), a Memory Stick, a Multimedia Card (MMC, RS-MMC, MMCmicro, or eMMC), an SD card (SD, miniSD, microSD, or SDHC), and a Universal Flash Storage (UFS).

[0212] Figure 16 is a block diagram of a solid state drive (SSD) system showing an application of a storage device according to an embodiment of the present disclosure.

[0213] Reference Figure 16, the SSD system 3000 includes a host 3100 and an SSD 3200. The SSD 3200 exchanges signals SIG with the host 3100 through a signal connector 3001 and receives power PWR through a power connector 3002. The SSD 3200 includes an SSD controller 3210, a plurality of flash memories 3221 to 322n, an auxiliary power device 3230, and a buffer memory 3240.

[0214] According to an embodiment of the present disclosure, the SSD controller 3210 may perform the functions of the memory controller 200 described with reference to Figure 1 description.

[0215] The SSD controller 3210 may control the plurality of flash memories 3221 to 322n in response to the signal SIG received from the host 3100. For example, the signal SIG may be a signal based on the interface between the host 3100 and the SSD 3200. For example, the signal SIG may be a signal defined by at least one interface among interfaces such as Universal Serial Bus (USB), Multimedia Card (MMC), Embedded MMC (eMMC), Peripheral Component Interconnect (PCI), PCI Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronics (IDE), FireWire, Universal Flash Storage (UFS), Wi-Fi, Bluetooth, and NVMe).

[0216] The auxiliary power device 3230 is connected to the host 3100 through the power connector 3002. The auxiliary power device 3230 may receive power PWR from the host 3110 and may be charged. When the power supply from the host 3100 is not smooth, the auxiliary power device 3230 may provide power to the SSD 3200. For example, the auxiliary power device 3230 may be placed inside the SSD 3200 or may be placed outside the SSD 3200. For example, the auxiliary power device 3230 may be placed on the motherboard and may provide auxiliary power to the SSD 3200.

[0217] The buffer memory 3240 serves as a buffer memory for the SSD 3200. For example, the buffer memory 3240 may temporarily store data received from the host 3100 or data received from the plurality of flash memories 3221 to 322n, or may temporarily store metadata (e.g., mapping table) of the flash memories 3221 to 322n. The buffer memory 324 may include volatile memories such as DRAM, SDRAM, DDR SDRAM, LPDDR SDRAM, and GRAM, or non-volatile memories such as FRAM, ReRAM, STT-MRAM, and PRAM.

[0218] Figure 17 is a block diagram showing a user system to which a storage device according to an embodiment of the present disclosure is applied.

[0219] Referring Figure 17 , the user system 4000 includes: an application processor 4100, a memory module 4200, a network module 4300, a storage module 4400, and a user interface 4500.

[0220] The application processor 4100 may drive components, an operating system (OS), user programs, etc. included in the user system 4000. For example, the application processor 4100 may include a controller, an interface, a graphics engine, etc. that control components included in the user system 4000. The application processor 4100 may be provided as a system on a chip (SoC).

[0221] The memory module 4200 may be used as a main memory, an operating memory, a buffer memory, or a cache memory of the user system 4000. The memory module 4200 may include volatile random access memories (such as DRAM, SDRAM, DDR SDRAM, DDR2 SDRAM, DDR3 SDRAM) or non-volatile random access memories (such as PRAM, ReRAM, MRAM, and FRAM). For example, the application processor 4100 and the memory module 4200 may be encapsulated based on a package on package (POP) and provided as one semiconductor package.

[0222] The network module 4300 may communicate with external devices. For example, the network module 4300 may support wireless communications (such as code division multiple access (CDMA), global system for mobile communications (GSM), wideband CDMA (WCDMA), CDMA-2000, time division multiple access (TDMA), long term evolution, WiMAX, WLAN, UWB, Bluetooth, and Wi-Fi). For example, the network module 4300 may be included in the application processor 4100.

[0223] The storage module 4400 may store data. For example, the storage module 4400 may store data received from the application processor 4100. Alternatively, the storage module 4400 may send the data stored in the storage module 4400 to the application processor 4100. For example, the storage module 4400 may be implemented as a non-volatile semiconductor memory element (such as phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), NAND flash, NOR flash, and 3D NAND flash). For example, the storage module 4400 may be provided as a removable storage device (removable drive) (such as a memory card) and an external drive of the user system 4000.

[0224] For example, the storage module 4400 may include a plurality of non-volatile memory devices, and the plurality of non-volatile memory devices may operate in the same manner as the memory device 100 described with reference to Figure 1 the description. The storage module 4400 may operate in the same manner as the storage device 50 described with reference to Figure 1 the description.

[0225] The user interface 4500 may include an interface for inputting data or instructions to the application processor 4100 or for outputting data to an external device. For example, the user interface 4500 may include a user input interface (such as a keyboard, keypad, button, touch panel, touch screen, touchpad, touch ball, camera, microphone, gyro sensor, vibration sensor, and piezoelectric element). The user interface 4500 may include a user output interface (such as a liquid crystal display (LCD), an organic light emitting diode (OLED) display device, an LED, a speaker, and a monitor).

Claims

1. A memory device, comprising: a plurality of memory cells; a threshold voltage distribution measurement component that measures a threshold voltage distribution of a first read operation for sensing data from programmed memory cells among the plurality of memory cells, and measures a threshold voltage distribution of a second read operation for sensing the data from the programmed memory cells and outputs the data using a data output operation; a distribution offset compensation table generator that calculates an offset direction and an offset distance based on a result of comparing the threshold voltage distribution of the first read operation with the threshold voltage distribution of the second read operation, the offset direction indicating a direction in which the threshold voltage distribution of the second read operation is offset, the offset distance indicating a distance by which the threshold voltage distribution of the second read operation is offset based on the threshold voltage distribution of the first read operation, and generates a distribution offset compensation table based on the offset direction and the offset distance; and a read operation controller that performs a third read operation on a target memory cell among the plurality of memory cells based on the distribution offset compensation table.

2. The memory device according to claim 1, wherein the threshold voltage distribution measurement component measures the threshold voltage distribution of the first read operation by calculating a number of failed bits of data sensed on the programmed memory cells by the first read operation, and measures the threshold voltage distribution of the second read operation by calculating a number of failed bits of the data sensed on the programmed memory cells by the second read operation.

3. The memory device according to claim 1, wherein the third read operation is an operation of sensing the data from the programmed memory cells and outputting the data using the data output operation after the distribution offset compensation table is generated.

4. The memory device according to claim 1, wherein the distribution offset compensation table includes at least one of an evaluation time and a read voltage level to be used for the third read operation.

5. The memory device according to claim 4, wherein when the threshold voltage distribution of the second read operation is offset to be higher than the threshold voltage distribution of the first read operation, the distribution offset compensation table generator generates the distribution offset compensation table including an evaluation time increased to be greater than a reference evaluation time based on the offset distance.

6. The memory device according to claim 4, wherein when the threshold voltage distribution of the second read operation is offset to be lower than the threshold voltage distribution of the first read operation, the distribution offset compensation table generator generates the distribution offset compensation table including an evaluation time decreased to be less than a reference evaluation time based on the offset distance.

7. The memory device according to claim 4, wherein when the threshold voltage distribution of the second read operation is shifted to be higher than the threshold voltage distribution of the first read operation, the distribution offset compensation table generator generates the distribution offset compensation table including read voltage levels higher than a reference read voltage level based on the offset distance.

8. The memory device according to claim 4, wherein when the threshold voltage distribution of the second read operation is shifted to be lower than the threshold voltage distribution of the first read operation, the distribution offset compensation table generator generates the distribution offset compensation table including read voltage levels lower than a reference read voltage level based on the offset distance.

9. The memory device according to claim 4, wherein the read operation controller performs the third read operation using at least one of the evaluation time and the read voltage level.

10. The memory device according to claim 1, further comprising: A distribution offset compensation table storage for storing the distribution offset compensation table.

11. A method of operating a memory device, the method comprising: Performing a programming operation on a plurality of memory cells; Measuring a threshold voltage distribution of the first read operation by performing a first read operation of sensing data from the plurality of memory cells; Measuring a threshold voltage distribution of the second read operation by performing a second read operation of sensing the data from the plurality of memory cells and outputting the data using a data output operation; Calculating an offset direction and an offset distance based on a result of comparing the threshold voltage distribution of the first read operation with the threshold voltage distribution of the second read operation, the offset direction indicating a direction in which the threshold voltage distribution of the second read operation is shifted, and the offset distance indicating a distance by which the threshold voltage distribution of the second read operation is shifted based on the threshold voltage distribution of the first read operation; Generating a distribution offset compensation table based on the offset direction and the offset distance; And Performing a third read operation on a target memory cell based on the distribution offset compensation table.

12. The method according to claim 11, wherein measuring the threshold voltage distribution of the first read operation comprises: Measuring the threshold voltage distribution of the first read operation by calculating a number of failed bits of the data sensed by the first read operation on the plurality of memory cells.

13. The method according to claim 11, wherein measuring the threshold voltage distribution of the second read operation comprises: Measuring the threshold voltage distribution of the second read operation by calculating a number of failed bits of the data sensed by the second read operation on the plurality of memory cells.

14. The method according to claim 11, wherein the distribution offset compensation table includes at least one of an evaluation time and a read voltage level to be used for the third read operation.

15. The method according to claim 14, wherein generating comprises: When the threshold voltage distribution of the second read operation is shifted to be higher than the threshold voltage distribution of the first read operation, generating the distribution offset compensation table including an evaluation time increased to be greater than a reference evaluation time based on the offset distance.

16. The method according to claim 14, wherein generating comprises: When the threshold voltage distribution of the second read operation is shifted to be lower than the threshold voltage distribution of the first read operation, a distribution shift compensation table including an evaluation time reduced to less than a reference evaluation time is generated based on the shift distance.

17. The method according to claim 14, wherein generating comprises: When the threshold voltage distribution of the second read operation is shifted to be higher than the threshold voltage distribution of the first read operation, a distribution shift compensation table including a read voltage level higher than a reference read voltage level is generated based on the shift distance.

18. The method according to claim 14, wherein generating comprises: When the threshold voltage distribution of the second read operation is shifted to be lower than the threshold voltage distribution of the first read operation, a distribution shift compensation table including a read voltage level lower than a reference read voltage level is generated based on the shift distance.

19. The method according to claim 14, wherein performing comprises: Use at least one of the evaluation time and the read voltage level to perform the third read operation.

20. The method according to claim 11, further comprising storing the distribution shift compensation table.

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