An assembly method for a stacked structure of a high-temperature co-fired ceramic BGA package

Abstract

The present invention discloses an assembly method for a stacked structure of a high-temperature co-fired ceramic BGA package. The method is as follows: Mount a bare chip onto the surface of a transitional carrier to form a chip-carrier composite block, and then mount it onto the surface of a packaging substrate; Connect the chip to the conductive wiring through wire bonding; Seal the metal cover plate of the packaging substrate; Conduct a seal qualification test on the packaging substrate, as well as high-temperature aging and electrical tests; Pre-tin the top and bottom pads of the packaging substrate; Use a stencil printing mold to print solder paste on the bottom of the packaging substrate; Position the ball placement mold and place metal connection balls on the bottom of the packaging substrate; Inspect the bottom and inside of the packaging substrate; Use a stencil printing mold to print solder paste on the top of the packaging substrate; Stack each layer of packaging substrate from bottom to top in a clamping device; Reflow solder the stacked package structure and perform vapor phase cleaning; Inspect the chips inside the packaging substrate and the bottom metal connection balls. The method of the present invention has good reliability and yield rate.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and in particular to an assembly method for a stacked structure of a high-temperature co-fired ceramic BGA package. Background Art

[0002] With the substantial improvement in the integration of high-frequency integrated circuits, traditional single-chip packaging or two-dimensional multi-chip modules can no longer meet the requirements of high-density packaging. The resulting system-in-package technology requires directly integrating semiconductor integrated circuit chips with various functions and materials inside the package. High-temperature co-fired ceramic (HTCC), as a reliable, stable, and weather-resistant electrical functional material, is often used to manufacture circuit substrates until a complete packaging structure is formed, and signal integrity is achieved through multi-layer wiring and the method of setting isolation grooves, such as a circuit board disclosed in Patent CN113573463A. Further, Patent CN112466864A discloses a three-dimensional stacked microwave module based on high-temperature co-fired ceramic. The packaging substrate manufactured by HTCC can be provided with metal layers for soldering on the upper and lower surfaces, and two or more packages can be stacked through metal connection balls. The problems existing in the above circuit packaging structure and its manufacturing method are as follows:

[0003] (1) The metal connection balls between the packaging layers are not correctly selected according to the structure and chemical composition of the pad metal layer on the surface of the packaging substrate, which easily leads to metal fatigue at the connection interface under continuous thermal cycling stress.

[0004] (2) Using unreasonable metal connection balls and soldering materials, and unable to correctly select the process temperature gradient and soldering method during manufacturing, it is easy to cause serious manufacturing defects such as metal connection ball offset, collapse, and bridging short circuit during multi-layer packaging stacking, significantly reducing the yield.

[0005] (3) Failing to design the correct soldering material or the die for metal ball distribution according to the pad pitch, the outer dimension, and material characteristics of the metal connection ball, and also unable to formulate reasonable die usage parameters based on the die, it is easy to cause serious defects such as insufficient volume or excessive overflow of the soldering material and metal connection ball offset, affecting the consistency of the stacked structure.

[0006] (4) No detailed limitation is made on the control of the critical dimensional deviation of the interlayer interconnection of the packaging stacked structure, and it is impossible to exclude non-conforming usage requirements and manufacturing deviations, which easily causes the packaging stacked structure to be unable to complete multi-layer precise interconnection, and further easily affects the transmission quality of high-frequency signals. Summary of the Invention

[0007] The object of the present invention is to provide an assembly method for a high-temperature co-fired ceramic BGA package stacked structure with reasonable process parameters, high reliability, high yield, and small deviation in quality consistency.

[0008] The technical solution for achieving the object of the present invention is: an assembly method for a high-temperature co-fired ceramic BGA package stacked structure, comprising the following steps:

[0009] Step 1: Mount the bare chips obtained by wafer dicing onto the surface of a transitional carrier of the same size by means of soldering or conductive adhesive bonding to form a chip-carrier composite block.

[0010] Step 2: Mount the chip-carrier composite block formed in Step 1 onto the corresponding position on the surface of the HTCC package substrate a2 by means of soldering or conductive adhesive bonding.

[0011] Step 3: Connect the chips to the conductive wirings inside the package substrate a2 by wire bonding.

[0012] Step 4: Seal the metal cover plate of the package substrate a2 by means of laser pulse welding or resistance micro-gap welding.

[0013] Step 5: First perform a helium mass spectrometry leak detection test on the package substrate a2, and then perform high-temperature aging and electrical tests.

[0014] Step 6: Pre-tin the top and bottom pads a3 of the package substrate a2 that has passed the test in Step 5, and then level the surface of the pads with a front-end flat tin remover.

[0015] Step 7: Flip the package substrate a2 so that the bottom of the package substrate faces up, print a tin-lead eutectic alloy solder paste on the bottom of the package substrate a2 using a stencil printing mold a1, and demold after printing.

[0016] Step 8: Keep the bottom of the package substrate a2 facing up, position the ball mounting mold a4 above the bottom of the package substrate a2, and use a method of applying a slight horizontal vibration during sowing to place the metal connection balls a5 on the surface of the bottom pads a3 of the package substrate a2 through the mold and make them contact the solder paste, and demold after completion.

[0017] Step 9: Keep the bottom of the package substrate a2 facing up, perform reflow soldering on the entire package substrate a2 through a hot air or infrared reflow device, and then cool to complete ball solidification.

[0018] Step 10: Keep the bottom of the package substrate a2 facing up, spray and clean the bottom of the package substrate a2 after ball solidification to remove contaminants.

[0019] Step 11: Randomly sample and statistically analyze the ball height and eccentricity of the metal connection balls a5 at the bottom of the encapsulation substrate a2 using a three-dimensional measuring microscope, and then use an X-ray non-destructive testing device to check whether there is chip damage inside the encapsulation substrate a2;

[0020] Step 12: Flip the encapsulation substrate a2 so that the top of the encapsulation substrate a2 faces upward, use a stencil a1 to print a tin-lead eutectic alloy solder paste on the bottom of the encapsulation substrate a2, and demold after printing;

[0021] Step 13: Keep the top of the encapsulation substrate a2 facing upward, and stack the encapsulation substrates a2 of each layer in sequence from bottom to top into a clamping device;

[0022] Step 14: Use an optical instrument to verify that the edges of the encapsulation substrates a2 of each layer are aligned;

[0023] Step 15: Subject the qualified encapsulation stack structure verified in Step 14 to reflow soldering through a hot air reflow device, and then cool to complete the connection of the encapsulation substrates a2 of each layer;

[0024] Step 16: Perform vapor phase cleaning on the completed connection encapsulation stack structure to remove contaminants;

[0025] Step 17: Use an X-ray non-destructive testing device to check whether there is chip damage inside the encapsulation substrate a2, and verify that the alignment deviation of the metal connection balls a5 of each layer meets the requirements.

[0026] Furthermore, the metal connection balls a5 between the encapsulation substrates a2 of each layer are made of a lead-tin-antimony hypoeutectic alloy, and the metal connection balls a5 are soldered to the surface pads of the encapsulation substrate a2 using a tin-lead eutectic alloy.

[0027] Furthermore, in Step 9, the peak temperature range on the surface of the encapsulation substrate a2 during the soldering process is 223°C to 232°C, the holding time above 120°C during the soldering process is 55 to 95 seconds, and the holding time above 190°C is 20 to 45 seconds.

[0028] Furthermore, in Step 15, the peak temperature range on the surface of the encapsulation substrate a2 during the soldering process is 208°C to 218°C, the holding time above 100°C during the soldering process is 55 to 115 seconds, and the holding time above 185°C is 25 to 50 seconds.

[0029] Furthermore, in Step 7, the center of the opening of the stencil a1 coincides with the center of the surface pad a3 at the bottom of the encapsulation substrate a2, the opening diameter D1 is the same as the diameter D2 of the pad a3, and the relationship between the thickness T1 of the stencil a1 and the diameter D1 of the printed round hole satisfies the formula T1 = n × D1, where n is a variable value, and the relationship between n and the pad pitch P is

[0030] Further, in step 8, the center of the opening of the ball-planting mold a4 coincides with the center of the pad a3 on the bottom surface of the encapsulation substrate a2. The diameter D3 of the mold opening and the diameter D4 of the metal connection ball a5 satisfy the formula D3 = D4 + K. When D4 < 0.5 mm, K = 0.05 - 0.06 mm. When D4 ≥ 0.5 mm, K = 0.08 - 0.10 mm. The relationship between the thickness T2 of the ball-planting mold a4 and the diameter D4 of the metal connection ball a5 satisfies the formula T2 = 0.6 × D4. The horizontal deviation of the mold positioning is not greater than K. After the mold a4 is positioned, the height H2 from the bottom surface of the encapsulation substrate a2 is H2 = D4 - T2 + 1.25 × K.

[0031] Further, in step 11, the random sampling and statistical method for the height and eccentricity of the metal connection ball a5 is as follows: the sampling order extends counterclockwise in a spiral from the center of the bottom of the encapsulation substrate a2 to the edge. The sampling ratio is 1% - 2.5%. The deviation between the maximum and minimum values of the ball height is less than or equal to 20% of the ball diameter, and the maximum deviation of the ball from the center of the pad is less than or equal to 10% of the ball diameter.

[0032] Compared with the prior art, the remarkable advantages of the present invention are: (1) By using pre-tinning, the connection strength between the metal connection ball and the pad of the encapsulation substrate is increased by more than 20%, and the impact resistance is significantly improved; (2) By using a tin-lead eutectic alloy to weld a lead-tin-antimony hypoeutectic alloy metal connection ball, the material performance characteristics are more matched with the encapsulation substrate, and the fatigue resistance is significantly improved; (3) The reasonable temperature gradient distribution and high-temperature duration parameters greatly reduce the thermal shock inside the encapsulation substrate, and at the same time avoid defects such as metal connection ball offset, collapse, and bridging short circuit; (4) By defining the mold specifications and usage parameters, the one-time yield and quality consistency are improved, and rework and repair are reduced; (5) The assembled encapsulation stack structure can be directly welded on the surface of the printed circuit board with reference to the welding method of ordinary CBGA components, which is convenient for application. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is a flowchart of the assembly method of the high-temperature co-fired ceramic BGA encapsulation stack structure of the present invention.

[0034] Figure 2 It is a sectional view of the cooperation mode of the stencil printing mold and the high-temperature co-fired ceramic BGA encapsulation substrate.

[0035] Figure 3 It is a sectional view of the cooperation mode of the ball-planting mold and the high-temperature co-fired ceramic BGA encapsulation substrate.

[0036] Figure 4 It is a schematic sectional view of a two-layer encapsulation stack structure assembled according to an exemplary embodiment of the present invention.

[0037] Reference numerals: a1 - stencil printing mold, a2 - high-temperature co-fired ceramic BGA package substrate, a3 - surface pads of the package substrate, a4 - ball placement mold, a5 - metal connection balls, D1 - diameter of the round hole of the stencil printing mold, D2 - diameter of the surface pads, D3 - diameter of the opening of the ball placement mold, D4 - diameter of the metal connection balls, T1 - thickness of the stencil printing mold, T2 - thickness of the ball placement mold, H2 - height from the surface of the package substrate after mold positioning, P - pad pitch, b1 - upper package metal cover plate, b2 - internal chip of the upper package, b3 - internal transitional carrier of the upper package, b4 - metal leads, b5 - upper package substrate, b6 - bottom pads of the upper package, b7 - bottom metal connection balls of the upper package, c1 - lower package metal cover plate, c2 - internal chip of the lower package, c3 - internal transitional carrier of the upper package, c5 - lower package substrate, c6 - bottom pads of the lower package, c7 - bottom metal connection balls of the lower package, c8 - top pads of the lower package. Detailed implementation mode

[0038] The following will describe in detail the preferred implementation mode of the present invention with reference to the accompanying drawings.

[0039] Combined with Figures 1 to 3 , an assembly method for a high-temperature co-fired ceramic BGA package stacking structure of the present invention includes the following steps:

[0040] Step 1: Mount the bare chips separated from the wafer onto the surface of a transitional carrier of the same size by means of soldering or conductive adhesive bonding to form a chip-carrier composite block.

[0041] Step 2: Mount the chip-carrier composite block formed in Step 1 onto the corresponding position on the surface of the HTCC package substrate a2 by means of soldering or conductive adhesive bonding.

[0042] Step 3: Connect the chips to the conductive wiring inside the package substrate a2 through wire bonding.

[0043] Step 4: Seal the metal cover plate of the package substrate a2 by means of laser pulse welding or resistance micro-gap welding.

[0044] Step 5: First, perform a helium mass spectrometry leak detection test on the package substrate a2. A leak rate of 1.0×10 -6 Pa·m 3 / s to 5.0×10 -8 Pa·m 3 / s is regarded as qualified for sealing, and then high-temperature aging and electrical tests are carried out.

[0045] Step 6: Apply pre-tinning to the top and bottom pads a3 of the packaged substrate a2 that has passed the test in Step 5. For example, for pre-tinning, apply solder paste of a tin-lead eutectic alloy by dot coating or stencil printing, and then heat it to 185°C - 195°C to melt. Then, level the surface of the pads with a flat-tipped desoldering tool.

[0046] Step 7: Flip the packaged substrate a2 so that the bottom of the packaged substrate a2 faces upward. Use a stencil a1 to print solder paste of a tin-lead eutectic alloy on the bottom of the packaged substrate a2. After printing, demold.

[0047] Further, the center of the opening of the stencil a1 coincides with the center of the surface pad a3 on the bottom of the packaged substrate a2, and the diameter D1 of the opening is the same as the diameter D2 of the pad. The relationship between the thickness T1 of the stencil a1 and the diameter D1 of the stencil opening satisfies the formula T1 = n×D1, where n is a variable value, and the relationship between n and the pad pitch P is

[0048] Step 10: Keep the bottom of the packaged substrate a2 facing upward, position the ball placement die a4 above the bottom of the packaged substrate a2, and use a method of applying a slight horizontal vibration during sowing to place the metal connection balls a5 on the surface of the bottom pads a3 of the packaged substrate a2 through the die and make them contact the solder paste. After completion, demold;

[0049] Further, the center of the opening of the ball placement die a4 coincides with the center of the surface pad a3 on the bottom of the packaged substrate a2. The relationship between the diameter D3 of the die opening and the diameter D4 of the metal connection ball a5 satisfies the formula D3 = D4 + K. When D4 < 0.5mm, K = 0.05 - 0.06mm; when D4 ≥ 0.5mm, K = 0.08 - 0.10mm. The relationship between the thickness T2 of the ball placement die a4 and the diameter D4 of the metal connection ball satisfies the formula T2 = 0.6×D4. The horizontal deviation of the die positioning is not more than K, and the height H2 of the die a4 from the bottom surface of the packaged substrate a2 after positioning is H2 = D4 - T2 + (1.25×K).

[0050] Step 9: Keep the bottom of the packaged substrate a2 facing upward, perform reflow soldering on the entire packaged substrate a2 through a hot air or infrared reflow device, and then cool to complete ball solidification;

[0051] Further, during the soldering process, the peak temperature range on the surface of the packaged substrate is 223°C - 232°C. The holding time above 120°C during the soldering process is 55 - 95 seconds, and the holding time above 190°C is 20 - 45 seconds.

[0052] Step 10: Keep the bottom of the packaged substrate a2 facing upward, and perform spray cleaning on the bottom of the packaged substrate a2 after ball solidification to remove contaminants.

[0053] Step 11: Randomly sample and statistically analyze the ball height and eccentricity of the metal connection balls a5 at the bottom of the encapsulated substrate a2 using a three-dimensional measuring microscope, and then use an X-ray non-destructive testing device to check whether there is chip damage inside the encapsulated substrate a2;

[0054] Further, the sampling order is to expand counterclockwise in a spiral from the center of the bottom of the encapsulated substrate to the edge, and the sampling ratio is 1% - 2.5%. If the deviation between the maximum and minimum values of the ball height is less than or equal to 20% of the ball diameter, and the maximum deviation of the ball from the center of the pad is less than or equal to 10% of the ball diameter, the ball fixing is considered qualified.

[0055] Step 12: Flip the encapsulated substrate a2 so that the top of the encapsulated substrate a2 faces upward, and use a stencil a1 to print a tin-lead eutectic alloy solder paste on the bottom of the encapsulated substrate a2. After printing, demold.

[0056] Further, the thickness and round hole diameter of the stencil are the same as those of the mold used in Step 7.

[0057] Step 13: Keep the top of the encapsulated substrate a2 facing upward, and stack the encapsulated substrates a2 layer by layer from bottom to top in the clamping device in the stacking order.

[0058] Step 14: Use an optical instrument to verify that the positions of the encapsulated substrates a2 in each layer are aligned, and the edge alignment deviation between layers is ≤ 0.1 mm.

[0059] Step 15: Subject the encapsulated stack structure verified in Step 14 to reflow soldering through a hot air reflow device, and then cool to complete the connection of the encapsulated substrates a2 in each layer;

[0060] Further, during the reflow soldering process, the peak temperature range on the surface of the encapsulated substrate is 208°C - 218°C, the maintenance time above 100°C during the soldering process is 55 - 115 seconds, and the maintenance time above 185°C is 25 - 50 seconds.

[0061] Step 16: Perform vapor phase cleaning on the completed connected encapsulated stack structure to remove contaminants.

[0062] Step 17: Use an X-ray non-destructive testing device to check whether there is chip damage inside the encapsulated substrate a2, and verify that the alignment deviation of the metal connection balls a5 in each layer meets the requirements. For example, verify that the alignment deviation of the metal connection balls in each layer is not greater than 10% of the ball diameter.

[0063] Embodiment

[0064] As Figure 4As shown in the figure, the stacked package structure assembled in this embodiment includes two relatively independent hierarchical packages composed of high-temperature co-fired ceramic substrates b5 and c5. The upper package is provided with circular pads b6 with a pitch of 1.0 mm and a diameter of 0.4 mm at the bottom. The lower package is provided with pads c8 at the top that are the same as the pads at the bottom of the upper package. The lower package is provided with a larger number of circular pads c6 at the bottom. The pitch and diameter of the pads c6 at the bottom of the lower package are exactly the same as those of the pads c8 at the top of the upper package, but the distribution positions are different. Metal covers b1 and c1 are respectively provided on the upper surfaces directly above the upper package substrate b5 and the lower package substrate c5. One or more chips b2, c2 and transitional carriers b3, c3 directly below the chips are respectively provided inside each layer of the package. A plurality of metal leads b4 are also provided inside each layer of the package substrate for electrical connection.

[0065] The implementation steps of the assembly method of the high-temperature co-fired ceramic BGA package stacked structure in this embodiment are as follows:

[0066] (1) Bond the chip b2 inside the upper package to the surface of the transitional carrier b3 inside the upper package with conductive adhesive to form a chip-carrier composite block. The chip c2 inside the lower package can also be bonded to the surface of the transitional carrier c3 inside the lower package in the same way to form a similar chip-carrier composite block;

[0067] (2) Bond the chip-carrier composite block to the inside of the upper package substrate b5 and the lower package substrate c5 with conductive adhesive;

[0068] (3) Bond the metal leads b4 to the inside of the upper package substrate b5 and the lower package substrate c5 by ultrasonic thermocompression to achieve electrical connection of the chips;

[0069] (4) Seal the upper package substrate b5 and the lower package substrate c5 respectively by laser pulse welding with the upper package metal cover b1 and the lower package metal cover c1;

[0070] (5) Perform helium mass spectrometry leak detection tests on the upper package substrate b5 and the lower package substrate c5, and measure that the leak rate meets 1.0×10 -7 Pa·m 3 / s to 5.0×10 -7 Pa·m 3 / s, and then perform electrical tests after aging at 85°C;

[0071] (6) Pre-tin the top and bottom pads of the upper package substrate b5 and the lower package substrate c5 that pass the test. The pre-tinning is carried out by dotting or stencil printing solder-pb eutectic alloy solder paste and then heating to 190°C to melt, and then leveling the surface of the pads with a front-end flat desoldering tool;

[0072] (7) Flip the upper encapsulation substrate b5 and the lower encapsulation substrate c5 so that the bottom faces upward, and use the stencil a1 to print the tin-lead eutectic alloy solder paste on the bottom of the encapsulation substrate, as Figure 2 shown. The center of the opening of the stencil a1 coincides with the center of the pad a3 on the bottom surface of the encapsulation substrate a2. The diameter D1 of the opening is 0.4 mm, and the thickness T1 of the stencil a1 is 0.15 mm;

[0073] (8) Keep the upper encapsulation substrate b5 and the lower encapsulation substrate c5 with the bottom faces upward, position the ball placement die a4 above the bottom of the encapsulation substrate, as Figure 3 shown. The center of the opening of the ball placement die a4 coincides with the center of the pad a4 on the bottom surface of the encapsulation substrate a3. The diameter D3 of the opening of the die is 0.58 mm, the thickness T2 of the ball placement die a4 is 0.3 mm, the horizontal deviation of the die positioning is not more than 0.08 mm, and the height H2 from the die to the bottom surface of the encapsulation substrate a2 after positioning is 0.3 mm. Adopt the method of applying slight vibration in the horizontal direction during spreading to place the metal connection balls of lead-tin-antimony hypoeutectic alloy (lead content 85%, tin content 5%, antimony content 10%) on the surface of the pads at the bottom of the encapsulation substrate through the die and make contact with the solder paste, and then demold after completion;

[0074] (9) Keep the upper encapsulation substrate b5 and the lower encapsulation substrate c5 with the bottom faces upward, and perform reflow soldering on the whole encapsulation substrate through a hot air reflow device. The peak temperature range on the surface of the encapsulation substrate during the soldering process is 225 °C. The holding time above 120 °C during the soldering process is 60 seconds, and the holding time above 190 °C is 25 seconds, and then cool to complete ball solidification;

[0075] (10) Keep the upper encapsulation substrate b5 and the lower encapsulation substrate c5 with the bottom faces upward, and perform spray cleaning on the bottom of the encapsulation substrate after ball solidification to remove contaminants;

[0076] (11) Randomly sample and statistically analyze the ball height and ball eccentricity of the metal connection balls b7 and c7 at the bottom of the upper encapsulation substrate b5 and the lower encapsulation substrate c5 using a three-dimensional measurement microscope. The sampling sequence extends from the center of the bottom of the encapsulation substrate counterclockwise in a spiral manner towards the edge, and the sampling ratio is 1.5%. The deviation between the maximum and minimum values of the ball height is less than or equal to 20% of the ball diameter, and the maximum deviation of the ball from the center of the pad is less than or equal to 10% of the ball diameter. Then use an X-ray non-destructive testing device to check that there is no chip damage inside the encapsulation substrate;

[0077] (12) Flip the lower encapsulation substrate c5 so that the top of the encapsulation substrate faces upward, and use a stencil to print the tin-lead eutectic alloy solder paste on the bottom of the encapsulation substrate c5. The thickness of the stencil is 0.15 mm, the diameter of the round hole is 0.4 mm, and the center position of the round hole coincides exactly with the center of the pad c8 at the top of the lower layer;

[0078] (13) Keep the upper encapsulation substrate b5 and the lower encapsulation substrate c5 with their tops facing upward, and stack them in the clamping device in the order of first installing the lower encapsulation substrate c5 and then loading the upper encapsulation substrate b5.

[0079] (14) Use an optical instrument to verify that the edge alignment deviation between the upper encapsulation substrate b5 and the lower encapsulation substrate c5 is ≤ 0.1 mm.

[0080] (15) The packaged stacked structure is subjected to reflow soldering through a hot air reflow device. During the soldering process, the peak temperature range on the surface of the encapsulation substrate is 210 °C, the holding time above 100 °C during the soldering process is 75 seconds, and the holding time above 185 °C is 30 seconds.

[0081] (16) Carry out vapor phase cleaning on the completed connected packaged stacked structure to remove contaminants.

[0082] (17) Use an X-ray non-destructive testing device to check that there is no chip damage inside the encapsulation substrate, and verify that the alignment deviation of each layer of metal connection balls is not greater than 10% of the ball diameter.

[0083] Through the above steps, the assembly of the two-layer high-temperature co-fired ceramic BGA packaged stacked structure can be completed. Each step can be selected for manual or mechanical operation according to actual needs, and the qualified rate of the whole process is relatively high. The completed packaged stacked structure can be directly soldered on the surface of the printed circuit board as a whole.

[0084] Compared with the prior art, the present invention has the characteristics of impact resistance, fatigue resistance, reasonable temperature gradient, and few interlayer connection defects, has good reliability and yield, and can be used for the manual or mechanized assembly of high-temperature co-fired ceramic BGA packaged stacked structures in the field of integrated circuit packaging technology.

[0085] Although the present invention has been described in detail with reference to the drawings and specific embodiments, those skilled in the art should understand that the present invention is not limited to the above embodiments and implementation manners. Without departing from the spirit and scope of the present invention, those skilled in the art can make various changes and substitutions, and the scope of the present invention is defined in the appended claims.

Claims

1. An assembly method for a stacked structure of a high-temperature co-fired ceramic BGA package, characterized in that, Including the following steps: Step 1: Mount the bare chips separated from the wafer onto the surface of a transitional carrier of the same size by means of soldering or conductive adhesive bonding to form a chip-carrier composite block; Step 2: Mount the chip-carrier composite block formed in Step 1 onto the corresponding position on the surface of the HTCC packaging substrate (a2) by means of soldering or conductive adhesive bonding; Step 3: Connect the chips to the conductive wirings inside the packaging substrate (a2) by wire bonding; Step 4: Seal the metal cover plate of the packaging substrate (a2) by laser pulse welding or resistance micro-gap welding; Step 5: First conduct a helium mass spectrometry leak detection test on the packaging substrate (a2), and then conduct high-temperature aging and electrical tests; Step 6: Pre-tin the top and bottom pads (a3) of the qualified packaging substrate (a2) tested in Step 5, and then level the pad surfaces with a front-end flat tin remover; Step 7: Flip the packaging substrate (a2) so that the bottom of the packaging substrate faces up, use a stencil (a1) to print a tin-lead eutectic alloy solder paste on the bottom of the packaging substrate (a2), and demold after printing; Step 8: Keep the bottom of the packaging substrate (a2) facing up, position the ball mounting die (a4) above the bottom of the packaging substrate (a2), and by means of applying a slight horizontal vibration during sowing, place the metal connection balls (a5) on the surface of the bottom pads (a3) of the packaging substrate (a2) through the die and make them contact the solder paste, and demold after completion; Step 9: Keep the bottom of the packaging substrate (a2) facing up, conduct reflow soldering on the whole packaging substrate (a2) through a hot air or infrared reflow device, and then cool to complete ball solidification; Step 10: Keep the bottom of the packaging substrate (a2) facing up, spray and clean the bottom of the packaging substrate (a2) after ball solidification to remove contaminants; Step 11: Randomly sample and statistically analyze the ball height and eccentricity of the metal connection balls (a5) at the bottom of the packaging substrate (a2) using a three-dimensional measuring microscope, and then use an X-ray non-destructive testing device to check whether there is chip damage inside the packaging substrate (a2); Step 12: Flip the packaging substrate (a2) so that the top of the packaging substrate (a2) faces up, use a stencil (a1) to print a tin-lead eutectic alloy solder paste on the bottom of the packaging substrate (a2), and demold after printing; Step 13: Keep the top of the packaging substrate (a2) facing up, and stack the packaging substrates (a2) of each layer into a clamping device in sequence from bottom to top; Step 14: Use an optical instrument to verify the edge alignment of the packaging substrates (a2) of each layer; Step 15: Conduct reflow soldering on the qualified packaging stack structure verified in Step 14 through a hot air reflow device, and then cool to complete the connection of the packaging substrates (a2) of each layer; Step 16: Conduct vapor phase cleaning on the completed connected packaging stack structure to remove contaminants; Step 17: Use an X-ray non-destructive testing device to check whether there is chip damage inside the packaging substrate (a2), and verify that the alignment deviation of the metal connection balls (a5) of each layer meets the requirements; In step 7, the center of the opening of the stencil (a1) coincides with the center of the pad (a3) on the bottom surface of the packaging substrate (a2). The opening diameter D1 is the same as the pad (a3) diameter D2. The relationship between the thickness T1 of the stencil (a1) and the diameter D1 of the stencil round hole satisfies the formula T1 = n × D1, where n is a variable value, and the relationship between n and the pad pitch P is In step 8, the center of the opening of the ball planting mold (a4) coincides with the center of the pad (a3) on the bottom surface of the packaging substrate (a2). The diameter D3 of the mold opening and the diameter D4 of the metal connecting ball (a5) satisfy the formula D3 = D4 + K. When D4 < 0.5 mm, K = 0.05 - 0.06 mm. When D4 ≥ 0.5 mm, K = 0.08 - 0.10 mm. The relationship between the thickness T2 of the ball planting mold (a4) and the diameter D4 of the metal connecting ball (a5) satisfies the formula T2 = 0.6 × D4. The horizontal deviation of the mold positioning is not greater than K. After the mold (a4) is positioned, the height H2 from the bottom surface of the packaging substrate (a2) is H2 = D4 - T2 + (1.25 × K).

2. The assembly method of the high-temperature co-fired ceramic BGA package stacking structure according to claim 1, characterized in that The metal connecting balls (a5) between the packaging substrates (a2) of each layer are made of lead-tin-antimony hypoeutectic alloy. The metal connecting balls (a5) and the pads on the surface of the packaging substrate (a2) are welded with tin-lead eutectic alloy.

3. The assembling method of the high-temperature co-fired ceramic BGA package stacking structure according to claim 1, characterized in that, In step 9, the peak temperature range on the surface of the packaging substrate (a2) during the welding process is 223°C - 232°C. The holding time above 120°C during the welding process is 55 - 95 seconds, and the holding time above 190°C is 20 - 45 seconds.

4. The assembling method of the high-temperature co-fired ceramic BGA package stacking structure according to claim 1, characterized in that In step 15, the peak temperature range on the surface of the packaging substrate (a2) during the welding process is 208°C - 218°C. The holding time above 100°C during the welding process is 55 - 115 seconds, and the holding time above 185°C is 25 - 50 seconds.

5. The assembly method of the high-temperature co-fired ceramic BGA package stacking structure according to claim 1, characterized in that In step 11, the random sampling and statistical method for the height and eccentricity of the metal connecting balls (a5) is as follows: the sampling order extends from the center of the bottom of the packaging substrate (a2) counterclockwise in a spiral manner towards the edge. The sampling ratio is 1% - 2.5%. The deviation between the maximum and minimum values of the ball height is less than or equal to 20% of the ball diameter, and the maximum deviation of the ball from the center of the pad is less than or equal to 10% of the ball diameter.

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