Integrated chip, ferroelectric field effect transistor device and method of forming the same

Abstract

The present disclosure relates to a ferroelectric field effect transistor device. The ferroelectric field effect transistor device includes a ferroelectric structure having a first side and a second side. A gate structure is disposed along the first side of the ferroelectric structure, and an oxide semiconductor is disposed along the second side of the ferroelectric structure. The oxide semiconductor has a first semiconductor type. A source region and a drain region are disposed on the oxide semiconductor. The gate structure is laterally between the source region and the drain region. A polarization enhancement structure is disposed on the oxide semiconductor between the source region and the drain region. The polarization enhancement structure includes a semiconductor material or an oxide semiconductor material having a second semiconductor type different from the first semiconductor type. Embodiments of the invention also relate to integrated chips and methods of forming ferroelectric field effect transistor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to an integrated chip, a ferroelectric field-effect transistor device, and a method for forming the same. Background Technology

[0002] Many modern electronic devices include non-volatile memory. Non-volatile memory is electronic memory that can store data both when powered on and when not powered on. A promising candidate for next-generation non-volatile memory is ferroelectric random access memory (FeRAM). FeRAM has a relatively simple structure and is compatible with complementary metal-oxide-semiconductor (CMOS) logic manufacturing processes. Summary of the Invention

[0003] According to an embodiment of the present invention, a ferroelectric field-effect transistor device is provided, comprising: a ferroelectric structure having a first side and a second side; a gate structure disposed along the first side of the ferroelectric structure; an oxide semiconductor disposed along the second side of the ferroelectric structure and having a first semiconductor type; a source region and a drain region disposed on the oxide semiconductor, wherein the gate structure is laterally located between the source region and the drain region; and a polarization enhancement structure disposed on the oxide semiconductor between the source region and the drain region, and comprising a semiconductor material or an oxide semiconductor material having a second semiconductor type different from the first semiconductor type.

[0004] According to an embodiment of the present invention, an integrated chip is also provided, comprising: a gate structure disposed above a substrate; a ferroelectric structure disposed on the gate structure; an oxide semiconductor separated from the gate structure by the ferroelectric structure and having a first semiconductor type; a source region disposed on the oxide semiconductor; and a polarization enhancement structure disposed on the oxide semiconductor and having a second semiconductor type different from the first semiconductor type.

[0005] According to an embodiment of the present invention, a method for forming a ferroelectric field-effect transistor device is also provided, comprising: forming a ferroelectric field-effect transistor stack including a polarization enhancement structure, the polarization enhancement structure being disposed on an oxide semiconductor separated from a gate structure by the ferroelectric structure, wherein the oxide semiconductor has a semiconductor type different from the polarization enhancement structure; forming a dielectric layer on the polarization enhancement structure; performing a first patterning process to form a source opening exposing the oxide semiconductor; and forming a conductive material within the source opening. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components can be arbitrarily increased or decreased.

[0007] Figure 1 Cross-sectional views of some embodiments of ferroelectric field-effect transistor (FeFET) devices with polarization enhancement structures configured to expand memory windows are shown.

[0008] Figures 2A-2D Cross-sectional views are shown illustrating some embodiments of the operation of a FeFET device with a polarization enhancement structure.

[0009] Figure 2E A graph showing an exemplary memory window illustrating a FeFET device with a polarization enhancement structure is displayed.

[0010] Figures 3A-3B Cross-sectional views of some embodiments of FeFET devices with different types of polarization enhancement structures are shown.

[0011] Figure 4A An exemplary schematic diagram of a FeFET memory circuit with a memory array (which includes FeFET devices, each with a polarization enhancement structure) is shown.

[0012] Figure 4B Show Figure 4A A cross-sectional view of an exemplary embodiment of a FeFET device within a memory array.

[0013] Figures 5A-5B Some alternative embodiments of FeFET devices with polarization enhancement structures are shown.

[0014] Figures 6A-6D Examples of integrated chips including FeFET devices with polarization enhancement structures are shown.

[0015] Figure 7 Cross-sectional views of some alternative embodiments of FeFET devices with polarization enhancement structures are shown.

[0016] Figure 8 Cross-sectional views of some alternative embodiments of an integrated chip including a FeFET device with a polarization enhancement structure are shown.

[0017] Figures 9-19 Cross-sectional views of some embodiments of a method for forming an integrated chip including a FeFET device with a polarization enhancement structure are shown.

[0018] Figure 20Flowcharts illustrating some embodiments of methods for forming an integrated chip including a FeFET device with a polarization enhancement structure are shown. Detailed Implementation

[0019] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify the invention. These are, of course, merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the formed first component is in direct contact with the second component, and may also include embodiments where additional components may be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various embodiments. Such repetition is merely for brevity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0020] Furthermore, for ease of description, spatial relation terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. Spatial relation terms are intended to include different orientations of the device in use or operation other than those described in the figures. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relation descriptors used herein may be interpreted accordingly.

[0021] A ferroelectric field-effect transistor (FeFET) is a type of ferroelectric random access memory (FeRAM) device comprising ferroelectric material disposed between a conductive gate structure and a channel region disposed between source and drain regions. During operation of the FeFET device, applying a gate voltage to the gate structure generates an electric field that causes a dipole moment to form within the ferroelectric material. Depending on the value of the gate voltage, the direction of the dipole moment (i.e., polarization) can be in one of two opposite directions. Since the threshold voltage of the FeFET device (e.g., the minimum gate-source voltage that forms the conductive path between the source and drain regions) depends on the polarization within the ferroelectric material, different polarizations effectively divide the threshold voltage of the FeFET device into two distinct values ​​corresponding to different data states.

[0022] For example, in an n-type FeFET (e.g., a FeFET device having a channel region with n-type doping), a positive gate voltage creates an electric field that imparts a first polarization to the ferroelectric material pointing towards the channel region and causes electrons to accumulate within the channel region. These electrons enhance the first polarization within the ferroelectric material and impart a first threshold voltage to the FeFET device corresponding to a first data state (e.g., logic "1"). Alternatively, a negative gate voltage creates an electric field that imparts a second polarization to the ferroelectric material pointing towards the gate structure and causes holes to accumulate within the channel region. These holes enhance the second polarization within the ferroelectric material and impart a second threshold voltage to the FeFET device corresponding to a second data state (e.g., logic "0"). The difference between the first and second thresholds defines the memory window of the FeFET device (e.g., the difference between the threshold voltages corresponding to the first and second data states).

[0023] The channel region of a FeFET device can be a semiconductor material (e.g., silicon, germanium, etc.). However, it has been recognized that using oxide semiconductors as the channel region of a FeFET device allows for good performance (e.g., high endurance, low access time, etc.). It has also been recognized that the memory window of a FeFET device using oxide semiconductors is relatively small. This is because oxide semiconductors cannot accumulate large numbers of different types of charge carriers (e.g., holes and electrons). For example, while the channel region comprising an n-type oxide semiconductor can accumulate electrons to enhance polarization within the ferroelectric material when a positive gate voltage is applied to the gate structure, the n-type oxide semiconductor cannot accumulate holes to enhance polarization within the ferroelectric material when a negative gate voltage is applied to the gate structure. Therefore, a negative gate voltage applied to the gate structure will polarize the ferroelectric material, but when the negative gate voltage is removed, the ferroelectric material will revert to residual polarization. This residual polarization will reduce the memory window of the FeFET device (e.g., to half the memory window of a FeFET device with a channel region of semiconductor material).

[0024] In some embodiments, this disclosure relates to an integrated chip having a FeFET device, comprising a polarization enhancement structure configured to increase a memory window. In some embodiments, the integrated chip includes a gate structure disposed on a first side of a ferroelectric material and an oxide semiconductor comprising a first semiconductor type (e.g., an n-type semiconductor) disposed along a second side opposite to the ferroelectric material. Source and / or drain regions are disposed on the oxide semiconductor, and a polarization enhancement structure comprising a second semiconductor type (e.g., a p-type semiconductor) is disposed on the oxide semiconductor (e.g., between the source and drain regions). During operation, the gate structure is configured to generate an electric field that polarizes the ferroelectric material. When the electric field causes the ferroelectric material to have a first polarization along a first direction, first-type charge carriers accumulate within the oxide semiconductor and enhance and / or strengthen the first polarization. When the electric field causes the ferroelectric material to have a second polarization along a second direction, second-type charge carriers will not accumulate within the oxide semiconductor, but second-type charge carriers within the polarization enhancement structure will function to enhance and / or strengthen the second polarization. By utilizing second-type charge carriers within the polarization-enhanced structure to enhance and / or strengthen the second polarization, the threshold voltage difference between different data states will increase, thereby enabling FeFET devices to have a larger memory window.

[0025] Figure 1 Cross-sectional views of some embodiments of a ferroelectric field-effect transistor (FeFET) device 100 having a polarization enhancement structure configured to expand the memory window are shown.

[0026] FeFET device 100 includes a ferroelectric structure 104 having a first side 104a and a second side 104b. An oxide semiconductor 106 is disposed along the first side 104a of the ferroelectric structure 104. The oxide semiconductor 106 includes a first semiconductor type (e.g., an n-type semiconductor). A source region 108 and a drain region 110 are also disposed on the first side 104a of the ferroelectric structure 104 and are separated from the ferroelectric structure 104 by the oxide semiconductor 106. A gate structure 102 is disposed along the second side 104b of the ferroelectric structure 104. In some embodiments, the gate structure 102 may be at least partially laterally located between the source region 108 and the drain region 110.

[0027] A polarization enhancement structure 112 is disposed on an oxide semiconductor 106. In some embodiments, the polarization enhancement structure 112 may be disposed between a source region 108 and a drain region 110. In some such embodiments, the polarization enhancement structure 112 extends continuously between a first sidewall contacting the source region 108 and a second sidewall contacting the drain region 110. The polarization enhancement structure 112 includes and / or is a semiconductor (e.g., a semiconductor material or an oxide semiconductor material) having a second semiconductor type (e.g., a p-type semiconductor) different from the first semiconductor type. For example, in some embodiments, the oxide semiconductor 106 includes an n-type semiconductor (e.g., a semiconductor with more free electrons than holes), while the polarization enhancement structure 112 includes a p-type semiconductor (e.g., a semiconductor with more holes than free electrons). In other embodiments, the oxide semiconductor 106 includes a p-type semiconductor, while the polarization enhancement structure 112 includes an n-type semiconductor.

[0028] During operation, the gate voltage V G A gate voltage V is applied to the gate structure 102. G First-type charge carriers 114 accumulate along the surface of the gate structure 102 facing the ferroelectric structure 104. The first-type charge carriers 114 (e.g., holes or electrons) form an electric field that polarizes the ferroelectric structure 104 to have polarization 116. This depends on the gate voltage V. G The value of the polarization 116 within the ferroelectric structure 104 can vary. For example, the positive gate voltage V... G This can result in a first polarization representing a first data state (e.g., "0"), while the negative gate voltage V G This can lead to a second polarization representing a second data state (e.g., "1").

[0029] The electric field will also cause second-type charge carriers 118a or 118b (e.g., electrons or holes) to accumulate in the oxide semiconductor 106 or the polarization enhancement structure 112. The second-type charge carriers 118a or 118b will enhance the polarization 116 within the ferroelectric structure 104. For example, when the ferroelectric structure 104 has a first polarization, the electric field can cause the second-type charge carriers 118a to accumulate in the oxide semiconductor 106 and enhance the first polarization. However, when the ferroelectric structure 104 has a second polarization, the electric field may not be able to cause the second-type charge carriers 118a to accumulate in the oxide semiconductor 106. Because the electric field may not be able to cause the second-type charge carriers 118a to accumulate within the oxide semiconductor 106, the charge carriers within the oxide semiconductor 106 will not have a significant effect on the second polarization. However, the electric field can cause the second-type charge carriers 118b to accumulate along the lower surface of the polarization enhancement structure 112 and enhance the second polarization. By enhancing the second polarization by incorporating the second type of charge carrier 118b within the polarization enhancement structure 112, the difference between threshold voltages representing different data states increases, and the associated memory window of the FeFET device 100 increases.

[0030] Figures 2A-2D A cross-sectional view is shown illustrating exemplary operation of an n-type FeFET device (e.g., a FeFET device having a channel region comprising an n-type oxide semiconductor).

[0031] like Figure 2A Cross-sectional view 200 and Figure 2B As shown in cross-sectional view 210, the n-type FeFET device includes a ferroelectric structure 104 disposed between a gate structure 102 and an oxide semiconductor 106 comprising an n-type oxide semiconductor. A source region 108 and a drain region 110 are disposed on the oxide semiconductor 106. A polarization enhancement structure 112 comprising a p-type semiconductor is also disposed on the oxide semiconductor 106 between the source region 108 and the drain region 110.

[0032] like Figure 2A As shown in cross-sectional view 200, during programming (PRG) operation, the positive gate voltage V is... G1 A bias voltage is applied to the gate structure 102, but not to the drain region 110 (e.g., V). D =0 or V D =Floating). Positive gate voltage V G1Positive charge carriers 202 (i.e., holes) accumulate on the surface of the gate structure 102 facing the ferroelectric structure 104. The positive charge carriers 202 form an electric field that polarizes the ferroelectric structure 104 to a first polarization 204 corresponding to a first data state (e.g., "1"). The electric field further causes negative charge carriers 206 to accumulate within the oxide semiconductor 106. The negative charge carriers 206 enhance the first polarization 204 within the ferroelectric structure 104, thereby providing a first threshold voltage for the FeFET device. The positive charge carriers 202 within the ferroelectric structure 104 can also push away positive charge carriers within the polarization enhancement structure 112, thereby depleting the polarization enhancement structure 112 and preventing current flow within it.

[0033] like Figure 2B As shown in cross-sectional view 210, during the read operation, the positive gate voltage V is... G2 The drain voltage V is applied to the gate structure 102 and the drain voltage V D A positive gate voltage V is applied to the drain region 110. G2 and drain voltage V D Make the first drain current I D1 The current flows between the source region 108 and the drain region 110 and toward a readout circuit (e.g., a sense amplifier) ​​(not shown), configured to read a first data state from the FeFET device. The first drain current I... D1 It has a first value that depends on a first threshold voltage of the FeFET device (and therefore on the first polarization 204). In various embodiments, the readout circuit may be coupled to either the source region 108 or the drain region 110. In some embodiments, the drain voltage V D It can be a positive voltage. In some such embodiments, a source voltage V greater than or equal to 0 volts can be used. S It is applied to the source region 108. In some embodiments, the source voltage V... S It can be greater than the drain voltage V. D In other embodiments, the source voltage V S It can be less than the drain voltage V D In some embodiments, the positive gate voltage V G2 It can be greater than or equal to the drain voltage V. D In other embodiments (not shown), the drain voltage V D It can be a negative voltage. In some such embodiments, the source voltage V can be greater than the drain voltage (e.g., approximately equal to 0V, greater than 0V, etc.). S It is applied to the source region 108.

[0034] like Figure 2C As shown in cross-sectional view 214, during the erase (ERS) operation, the negative gate voltage V is...G3 A bias voltage is applied to the gate structure 102, but not to the drain region 110 (e.g., V). D =0 or V D =Floating). Negative gate voltage V G3 Negative charge carriers 216 accumulate along the surface of the gate structure 102 facing the ferroelectric structure 104. The negative charge carriers 216 form an electric field that polarizes the ferroelectric structure 104 to a second polarization 218 corresponding to a second data state (e.g., logic "0"). The electric field further reduces the accumulation of negative charge carriers within the oxide semiconductor 106, but does not cause the accumulation of positive charge carriers within the oxide semiconductor 106. Instead, the electric field causes positive charge carriers 220 to accumulate along the bottom of the polarization enhancement structure 112. The positive charge carriers 220 enhance the second polarization 218 within the ferroelectric structure 104, thereby providing a second threshold voltage for the FeFET device.

[0035] like Figure 2D As shown in cross-sectional view 222, during the read operation, the positive gate voltage V is... G2 The drain voltage V is applied to the gate structure 102 and the drain voltage V D A positive gate voltage V is applied to the drain region 110. G2 and drain voltage V D Make the second drain current I D2 The second drain current I flows between the source region 108 and the drain region 110 and toward a readout circuit (e.g., a sense amplifier) ​​(not shown), configured to read a second data state from the FeFET device 100. D2 It has a second value that depends on the second threshold voltage of the FeFET device (and therefore on the second polarization 218).

[0036] Figure 2E A graph showing an exemplary memory window illustrating a FeFET device is provided.

[0037] As shown in graph 224, when the FeFET device is storing a first data state (e.g., logic "1"), the FeFET device will have a threshold voltage corresponding to the drain current shown in line 226. When the FeFET device is storing a second data state (e.g., logic "0"), the FeFET device will have a threshold voltage corresponding to the drain current shown in line 228. The first memory window 230 corresponds to the difference between lines 226 and 228. In contrast, a FeFET device without a polarization enhancement structure that is storing a second data state (e.g., logic "0") will have a threshold voltage corresponding to the drain current shown in line 232. The second memory window 234, corresponding to the difference between lines 226 and 232, is smaller than the first memory window 230.

[0038] Although a description of FeFET devices with n-type oxide semiconductors has been provided Figures 2A-2E However, it should be understood that the disclosed FeFET devices are not limited to such embodiments. Figures 3A-3B Cross-sectional views of various embodiments of FeFET devices with different oxide semiconductor types are shown.

[0039] Figure 3A A cross-sectional view of an n-type FeFET device 300 having an n-type oxide semiconductor is shown.

[0040] The n-type FeFET device 300 includes a ferroelectric structure 104 disposed between a gate structure 102 and an n-type oxide semiconductor 302. A source region 108 and a drain region 110 are disposed on the n-type oxide semiconductor 302 and separated by a p-type semiconductor 304 (e.g., a p-type semiconductor material and / or a p-type oxide semiconductor material). During operation, the gate structure 102 is configured based on a gate voltage V applied to the gate structure 102. G An electric field is generated. If the positive gate voltage V is... G When applied to the gate structure 102, negative charge carriers 306 accumulate within the n-type oxide semiconductor 302. If a negative gate voltage V is applied... G When applied to the gate structure 102, a large number of positive charge carriers will not accumulate in the n-type oxide semiconductor 302, but positive charge carriers 308 will accumulate in the p-type semiconductor 304.

[0041] Figure 3B A cross-sectional view of a p-type FeFET device 310 having a p-type oxide semiconductor is shown.

[0042] The p-type FeFET device 310 includes a ferroelectric structure 104 disposed between a gate structure 102 and a p-type oxide semiconductor 312. A source region 108 and a drain region 110 are disposed on the p-type oxide semiconductor 312 and separated by an n-type semiconductor 314 (e.g., an n-type semiconductor material and / or an n-type oxide semiconductor material). During operation, the gate structure 102 is configured based on a gate voltage V applied to the gate structure 102. G An electric field is generated. If the negative gate voltage V is applied... G When applied to the gate structure 102, positive charge carriers 316 accumulate within the p-type oxide semiconductor 312. If the positive gate voltage V... G When applied to the gate structure 102, a large number of negative charge carriers will not accumulate in the p-type oxide semiconductor 312, but negative charge carriers 318 will accumulate in the n-type semiconductor 314.

[0043] Figure 4AAn exemplary schematic diagram of a FeFET memory circuit 400 having FeFET devices, each including a polarization enhancement structure, is shown.

[0044] FeFET memory circuit 400 includes FeFET memory array 402, which includes multiple FeFET devices 404. 1,1 -404 n,m Multiple FeFET devices 404 1,1 -404 n,m Arranged in rows and / or columns within the FeFET memory array 402. Multiple FeFET devices 404 within each row. 1,x -404 n,x Operablely coupled to word line WL x (x=1-m). Multiple FeFET devices 404 in the column. x,1 -404 x,m Operablely coupled to bit line BL x (x = 1 - n) and source line SL x (x = 1 - n).

[0045] Figure 4B This illustrates multiple FeFET devices within a memory array (e.g., Figure 4A 404 1,1 -404 n,m This is a cross-sectional view of an exemplary embodiment of the FeFET device 418. The FeFET device 418 includes a ferroelectric structure 104 disposed between a gate structure 102 and an oxide semiconductor 106. A polarization enhancement structure 112 is disposed on the oxide semiconductor 106 between a source region 108 and a drain region 110. The gate structure 102 is coupled to a word line WL. x The source region 108 is coupled to the source line SL. x Furthermore, the drain region 110 is coupled to the bit line BL. x .

[0046] Refer again Figure 4A Word lines WL1-WL m Bit line BL1-BL n and source polar lines SL1-SL n Coupled to control circuitry 406. In some embodiments, control circuitry 406 includes elements coupled to word lines WL1-WL m The word line decoder 410 is coupled to bit lines BL1-BL1. n Bit line decoder 408 and source line SL1-SL n The source-line decoder 412. In some embodiments, the control circuit 406 further includes components coupled to bit lines BL1-BL2. n or source line SL1-SLn The sensing amplifier 414. In some embodiments, the control circuit 406 further includes a control unit 416 configured to send address information S to the word line decoder 410, the bit line decoder 408, and / or the source line decoder 412. ADR This enables the control circuit 406 to selectively access multiple FeFET devices 404. 1,1 -404 n,m One or more of them.

[0047] For example, during operation, control unit 416 is configured to provide address information S to word line decoder 410, bit line decoder 408, and source line decoder 412. ADR Based on address information S ADR The word line decoder 410 is configured to direct word lines WL1-WL m One of them selectively applies a bias voltage. Simultaneously, the bit line decoder 408 is configured to selectively apply the bias voltage to bit lines BL1-BL2. n One of the, and / or the source line decoder 412, is configured to selectively apply a bias voltage to the source lines SL1-SL. n One of them. Through the word lines WL1-WL m Bit line BL1-BL n and / or source lines SL1-SL n By applying a bias voltage to the select line, the FeFET memory circuit 400 can be operated to write and / or retrieve different data states from multiple FeFET devices 404. 1,1 -404 n,m Read data status.

[0048] Figure 5A Cross-sectional views of some alternative embodiments of the FeFET device 500 with a polarization enhancement structure are shown. Although Figure 5A The illustration shows an FeFET device having an oxide semiconductor vertically stacked on a ferroelectric structure and a polarization enhancement structure vertically stacked on the upper surface of the oxide semiconductor. However, it should be understood that in other alternative embodiments (e.g., in a 3D-FeFET device), the oxide semiconductor may be arranged along and / or below the sidewalls of the ferroelectric structure and / or the polarization enhancement structure may be arranged along and / or below the sidewalls of the oxide semiconductor.

[0049] The FeFET device 500 includes a ferroelectric structure 104 disposed between a gate structure 102 and an oxide semiconductor 106. A source region 108 and a drain region 110 are disposed on the oxide semiconductor 106 and separated by a polarization enhancement structure 112. The ferroelectric structure 104 includes a material having a dielectric crystal exhibiting polarization with a direction controllable by an electric field. For example, in some embodiments, the ferroelectric structure 104 may include hafnium oxide (HfO2), hafnium zinc oxide (HfZnO2), etc. In some embodiments, the oxide semiconductor 106 may include a first semiconductor type. For example, in some embodiments, the oxide semiconductor 106 may include an n-type oxide semiconductor, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In other embodiments, the oxide semiconductor 106 may include a p-type oxide semiconductor, such as tin oxide (SnO), nickel oxide (NiO), copper oxide (Cu2O), etc.

[0050] In some embodiments, the polarization enhancement structure 112 may be arranged along the opposite side of the source region 108 and along the opposite side of the drain region 110. In some such embodiments, in Figure 5B Exemplary top view 506 (along) Figure 5A As shown in the cross-section line A-A', the polarization enhancement structure 112 can extend continuously around the source region 108 and the drain region 110 in a closed loop. In some embodiments, the polarization enhancement structure 112 extends along... Figure 5A The cross-sectional view shows a continuous first width 508 extending through the source region 108 and the drain region 110, while the oxide semiconductor 106, when viewed along the cross-sectional view, continuously extends a larger second width 510.

[0051] In some embodiments, the oxide semiconductor 106 and the polarization enhancement structure 112 may be configured to have low (e.g., substantially zero) source-drain currents when the FeFET device 500 is in a "off" state (e.g., when a 0V gate voltage is applied to the gate structure 102). In some such embodiments, the polarization enhancement structure 112 and / or the oxide semiconductor 106 may have less than or equal to about 1x10⁻⁶. 19 at / cm -3 Less than or equal to approximately 1 x 10 18 at / cm -3 Less than or equal to approximately 1 x 10 19 at / cm -3Or other similar doping concentrations. In some additional embodiments, the oxide semiconductor 106 and the polarization enhancement structure 112 may each have a thickness in the range of about 1 nanometer (nm) and about 10 nm, about 5 nm and about 20 nm, about 5 nm and about 15 nm, or other similar values. The thickness and / or doping concentration of the polarization enhancement structure 112 and / or the oxide semiconductor 106 provide good on-off modulation for the FeFET device 500 and reduce the current flowing through the oxide semiconductor 106 and the polarization enhancement structure 112 when a 0V gate voltage is applied to the gate structure 102.

[0052] In some embodiments, the polarization enhancement structure 112 may include and / or be one or more semiconductor materials and / or semiconductor oxide materials having a second semiconductor type different from the first semiconductor type of the oxide semiconductor 106. In some embodiments, the polarization enhancement structure 112 may include p-type semiconductors, such as p-doped silicon, p-doped germanium, tin oxide (SnO), nickel oxide (NiO), copper oxide (Cu2O), tungsten diselenide (WSe2), tungsten distelluride (WTe2), molybdenum distelluride (MoTe2), etc. In other embodiments, the polarization enhancement structure 112 may include n-type semiconductors, such as n-doped silicon, n-doped germanium, indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In some embodiments, the polarization enhancement structure 112 may have a substantially uniform doping concentration. In other embodiments, the polarization enhancement structure 112 may have a gradient doping concentration that decreases from the lower surface of the polarization enhancement structure 112 facing the oxide semiconductor 106 to the upper surface of the polarization enhancement structure 112 away from the oxide semiconductor 106.

[0053] In some embodiments, gate structure 102 may include a conductive material. In some embodiments, the conductive material of gate structure 102 may have a metal work function configured to increase the threshold voltage of FeFET device 500, thereby further mitigating the current flowing through oxide semiconductor 106 and polarization enhancement structure 112 when FeFET device 500 is in an “off” state (e.g., when a 0V gate voltage is applied to gate structure 102). In some embodiments, the conductive material of gate structure 102 may have a metal work function between about 4.0 electron volts (eV) and about 5.0 eV, i.e., about 4.5 eV or other similar values. In some such embodiments, the Fermi level of gate structure 102 may be between the Fermi levels of oxide semiconductor 106 and polarization enhancement structure 112. In some embodiments, gate structure 102 may include titanium, titanium nitride, tungsten, tungsten nitride, copper, gold, zinc, aluminum, etc.

[0054] In some embodiments, dielectric layer 502 is disposed over polarization enhancement structure 112. In some such embodiments, source region 108 and drain region 110 extend through dielectric layer 502 and polarization enhancement structure 112 to contact oxide semiconductor 106. In some embodiments, dielectric layer 502 may include oxide (e.g., silicon oxide, silicon dioxide, etc.), nitride (e.g., silicon nitride), carbide (e.g., silicon carbide), etc. In some embodiments, source region 108 and drain region 110 may have an uppermost surface that is substantially coplanar with the upper surface of dielectric layer 502 (e.g., coplanar within the tolerances of CMP process). Therefore, source region 108 and / or drain region 110 may extend a non-zero distance 504 within oxide semiconductor 106 such that oxide semiconductor 106 extends along the lower surface and sidewalls of source region 108 and / or drain region 110. In some embodiments, the non-zero distance 504 may be in the range of about 1 Å and about 10 Å, about 5 Å and about 20 Å, or other similar values. In some embodiments, the source region 108 and the drain region 110 may include and / or be metals such as titanium, titanium nitride, tungsten, tungsten nitride, copper, gold, zinc, aluminum, etc.

[0055] In various embodiments, the disclosed FeFET devices may have different structures. Figures 6A-6D Some embodiments of FeFET devices with different structures are shown. It will be understood that... Figures 6A-6D The embodiments described herein are merely examples of possible structures of the disclosed FeFET device with polarization enhancement structure, and other FeFET device structures also fall within the scope of this disclosure.

[0056] Figure 6A Cross-sectional views of some embodiments of an integrated chip 600 including a FeFET device with a polarization enhancement structure are shown.

[0057] The integrated chip 600 includes a FeFET device having a gate structure 102 disposed above the upper surface of a substrate 602. In some embodiments, a dielectric isolation structure 603 is disposed above the substrate 602 and separates the gate structure 102 from the substrate 602. A ferroelectric structure 104 is disposed on the gate structure 102, an oxide semiconductor 106 is disposed on the ferroelectric structure 104, and a polarization enhancement structure 112 is disposed on the oxide semiconductor 106. In some embodiments, the gate structure 102 extends laterally directly below the ferroelectric structure 104 beyond one or more outermost sidewalls of the ferroelectric structure 104. In some embodiments, the outermost sidewalls of the ferroelectric structure 104 are substantially aligned with the outermost sidewalls of the oxide semiconductor 106 and the polarization enhancement structure 112. In some embodiments, the gate structure 102 may further include inner sidewalls 102s located directly above the gate structure 102 and substantially aligned with the outermost sidewalls of the ferroelectric structure 104. In such an embodiment, the gate structure 102 may have a first thickness directly below the ferroelectric structure 104 and a smaller second thickness outside the ferroelectric structure 104.

[0058] A dielectric layer 502 is disposed over the gate structure 102, the ferroelectric structure 104, the oxide semiconductor 106, and the polarization enhancement structure 112. A source region 108 and a drain region 110 extend through the dielectric layer 502 and the polarization enhancement structure 112 to contact the oxide semiconductor 106. In some embodiments, a gate contact 604 also extends through the dielectric layer 502 to contact the gate structure 102.

[0059] In some embodiments, the gate structure 102 may have an outermost sidewall tilted at a first angle θ1, as measured outside the gate structure 102 and relative to the upper surface of the substrate 602. In various embodiments, the first angle θ1 may be in the range of about 92° to about 105°. In some embodiments, the ferroelectric structure 104, the oxide semiconductor 106, and / or the polarization enhancement structure 112 may have an outermost sidewall tilted at a second angle θ2, as measured relative to the upper surface of the substrate 602. In various embodiments, the second angle θ2 may be in the range of about 92° to about 105°. In some embodiments, the first angle θ1 may be different from the second angle θ2.

[0060] Multiple additional interconnects 606 are disposed within an interlayer dielectric (ILD) structure 608 disposed above the dielectric layer 502. In some embodiments, the ILD structure 608 includes multiple stacked ILD layers 610a-610b separated by one or more etch stop layers 612a-612b. In some embodiments, the multiple stacked ILD layers 610a-610b may include one or more of the following: silicon dioxide, silicon nitride, carbon-doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), porous dielectric materials, etc. In various embodiments, the one or more etch stop layers 612a-612b may include carbides (e.g., silicon carbide, silicon oxynitride, etc.), nitrides (e.g., silicon nitride, silicon oxynitride, etc.), etc.

[0061] Figure 6B Cross-sectional views of some alternative embodiments of an integrated chip 614 including a FeFET device with a polarization enhancement structure are shown.

[0062] Integrated chip 614 includes a FeFET device having a gate structure 102, the gate structure including a doped region disposed along an upper surface 602u of substrate 602. A ferroelectric structure 104 is disposed on the upper surface 602u of substrate 602 and directly above substrate 602. An oxide semiconductor 106 is disposed on the ferroelectric structure 104, and a polarization enhancement structure 112 is disposed on the oxide semiconductor 106. In some embodiments, the gate structure 102 extends laterally directly below the ferroelectric structure 104 beyond one or more outermost sidewalls of the ferroelectric structure 104. In some embodiments, one or more isolation structures 616 are disposed within substrate 602 along opposite sides of the gate structure 102. The one or more isolation structures 616 are configured to provide electrical isolation between the gate structure 102 and adjacent gate structures (not shown). In some embodiments, the one or more isolation structures 616 may include a shallow trench isolation (STI) structure.

[0063] A dielectric layer 502 is disposed over the gate structure 102, the ferroelectric structure 104, the oxide semiconductor 106, and the polarization enhancement structure 112. A source region 108 and a drain region 110 extend through the dielectric layer 502 and the polarization enhancement structure 112 to contact the oxide semiconductor 106. In some embodiments, a gate contact 604 also extends through the dielectric layer 502 to contact the gate structure 102.

[0064] Figure 6C Cross-sectional views of some alternative embodiments of an integrated chip 618 including a FeFET device with a polarization enhancement structure are shown.

[0065] The integrated chip 600 includes a dielectric isolation structure 603 disposed above a substrate 602. A FeFET device is disposed above the dielectric isolation structure 603. The FeFET device includes a polarization enhancement structure 112 disposed on the dielectric isolation structure 603 and an oxide semiconductor 106 disposed on the polarization enhancement structure 112. A ferroelectric structure 104 is disposed on the upper surface of the oxide semiconductor 106 opposite to the substrate 602. In some embodiments, the oxide semiconductor 106 and / or the polarization enhancement structure 112 extend laterally beyond the opposite outermost sidewall of the ferroelectric structure 104.

[0066] A dielectric layer 502 is disposed above the FeFET device. A source region 108 and a drain region 110 extend through the dielectric layer 502 to contact the oxide semiconductor 106. In some embodiments, the source region 108 and the drain region 110 may extend completely through the oxide semiconductor 106 to contact the polarization enhancement structure 112. A gate structure 102 also extends through the dielectric layer 502 to contact the ferroelectric structure 104. The source region 108, the drain region 110, and the gate structure 102 are coupled to a plurality of additional interconnects 606 disposed within an ILD structure 608 disposed above the dielectric layer 502.

[0067] Figure 6D Three-dimensional views are shown of some alternative embodiments of an integrated chip 620 including a FeFET device with a polarization enhancement structure.

[0068] The integrated chip 620 includes a lower dielectric layer 622 disposed above a substrate 602. A gate structure 102 is disposed on the lower dielectric layer 622, and a dielectric layer 502 is disposed on the gate structure 102. A ferroelectric structure 104 is disposed on the sidewalls of the lower dielectric layer 622, the gate structure 102, and the dielectric layer 502. An oxide semiconductor 106 is disposed along the sidewall of the ferroelectric structure 104 opposite to the gate structure 102. A source region 108 and a drain region 110 are disposed on the side of the oxide semiconductor 106. A polarization enhancement structure 112 is disposed between the source region 108 and the drain region 110 and along the side of the oxide semiconductor 106.

[0069] Figure 7 Cross-sectional views of some alternative embodiments of the FeFET device 700 with polarization enhancement structure are shown.

[0070] The FeFET device 700 includes a ferroelectric structure 104 disposed between a gate structure 102 and an oxide semiconductor 106. A source region 108 and a drain region 110 are disposed on the oxide semiconductor 106 and separated by a polarization enhancement structure 112. In some embodiments, the polarization enhancement structure 112 may be arranged along opposite sides of the source region 108 and opposite sides of the drain region 110. In some embodiments, the polarization enhancement structure 112 includes a horizontal extension 112h extending along the upper surface of the oxide semiconductor 106 and one or more vertical extensions 112v projecting outward from the upper surface of the horizontal extension 112h. In some embodiments, the one or more vertical extensions 112v extend along the sidewalls of the source region 108 and / or the drain region 110.

[0071] A dielectric layer 502 is disposed above the polarization enhancement structure 112. The dielectric layer 502 extends along the upper surface and sidewalls of the polarization enhancement structure 112. In some embodiments, the dielectric layer 502 can be separated from the source region 108 and the drain region 110 by the polarization enhancement structure 112. In some embodiments, the dielectric layer 502 can extend to the uppermost surface of the polarization enhancement structure 112. In some embodiments, the dielectric layer 502, the polarization enhancement structure 112, the source region 108, and the drain region 110 have substantially coplanar (e.g., coplanar within the tolerances of the CMP process) uppermost surfaces.

[0072] Figure 8 Some alternative embodiments of an integrated chip 800 including a FeFET device with a polarization enhancement structure are shown.

[0073] The integrated chip 800 includes an embedded memory region 802 and a logic region 806. The embedded memory region 802 includes a FeFET device 803 disposed on a first side 602a of a substrate 602. The FeFET device 803 includes a ferroelectric structure 104 disposed on a gate structure 102, an oxide semiconductor 106 disposed on the ferroelectric structure 104, and a polarization enhancement structure 112 disposed on the oxide semiconductor 106. A source region 108 and a drain region 110 extend through the polarization enhancement structure 112 to contact the oxide semiconductor 106. In some embodiments, a contact etch stop layer (CESL) 805 may be disposed over the FeFET device 803.

[0074] In some embodiments, one or more isolation structures 804 may be disposed within a substrate 602 on the opposite side of the FeFET device 803. The isolation structure 804 may include one or more dielectric materials disposed within trenches defined by the inner surface of the substrate 602. In some embodiments, the isolation structure 804 may include a shallow trench isolation (STI) structure. In some such embodiments, the isolation structure 804 may include the same isolation structure that extends continuously around the periphery of the FeFET device 803 in a closed loop.

[0075] Logic region 806 includes a transistor device 808 disposed on a first side 602a of substrate 602. Transistor device 808 includes a source region 810, a drain region 812 separated from the source region 810 by a channel region, and a gate structure 815 located above the channel region. In some embodiments, transistor device 808 may include a high-k metal gate (HKMG) transistor. In such embodiments, gate structure 815 may include a metal gate electrode 816 (e.g., including aluminum, ruthenium, palladium, etc.) and a gate dielectric 814 including a high-k dielectric (e.g., including aluminum oxide, hafnium oxide, etc.). In other embodiments, gate structure 815 may include a polysilicon gate electrode and a gate dielectric including an oxide (e.g., silicon dioxide). In some embodiments, insulating sidewall spacers 818 may be disposed along opposite sides of gate structure 815. Source region 810, drain region 812, and gate structure 815 are coupled to a plurality of interconnects 820 surrounded by dielectric layer 502.

[0076] Figures 9-19 Cross-sectional views 900-1900 illustrate some embodiments of methods for forming an integrated chip including a FeFET device with a polarization enhancement structure. Although described... Figures 9-19 It's related to the method, but it should be understood. Figures 9-19 The disclosed structure is not limited to this method, but can exist independently of this method.

[0077] like Figure 9As shown in cross-sectional view 900, a gate layer 902 is formed. In some embodiments, the gate layer 902 may be formed over a substrate 602. In various embodiments, the substrate 602 may be any type of semiconductor body (e.g., silicon, SiGe, SOI, etc.) such as a semiconductor wafer and / or one or more dies located on the wafer, and any other type of semiconductor and / or epitaxial layer associated therewith. The gate layer 902 may include one or more conductive materials. In some embodiments, the one or more conductive materials may include and / or be metals such as titanium, titanium nitride, tungsten, tungsten nitride, copper, gold, zinc, aluminum, etc. In some embodiments, the one or more conductive materials may have a work function between about 4.0 electron volts (eV) and about 5.0 eV, i.e., about 4.5 eV or other similar values. In various embodiments, the gate layer 902 may be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, etc.).

[0078] like Figure 10 As shown in cross-sectional view 1000, a ferroelectric layer 1002 may be formed above the gate layer 902. The ferroelectric layer 1002 may include one or more ferroelectric materials. In some embodiments, the one or more ferroelectric materials may include hafnium oxide, hafnium zinc oxide, etc. In various embodiments, the ferroelectric layer 1002 may be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, etc.).

[0079] like Figure 11 As shown in cross-sectional view 1100, an oxide semiconductor layer 1102 is formed above the ferroelectric layer 1002. The oxide semiconductor layer 1102 may include one or more oxide semiconductor materials having a first type of semiconductor (e.g., an n-type semiconductor with electrons as the primary charge carriers or a p-type semiconductor with holes as the primary charge carriers). In some embodiments, the one or more oxide semiconductor materials may include one or more n-type oxide semiconductors, such as indium gallium zinc oxide (IGZO), indium gallium zinc tin oxide (IGZTO), indium tungsten oxide (IWO), indium tungsten zinc oxide (IWZO), indium zinc oxide (IZO), zinc oxide (ZnO), etc. In other embodiments, the one or more oxide semiconductor materials may include one or more p-type oxide semiconductors, such as tin oxide (SnO), nickel oxide (NiO), copper oxide (Cu2O), NaNbO2, etc. In various embodiments, the oxide semiconductor layer 1102 may be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, etc.).

[0080] like Figure 12As shown in cross-sectional view 1200, one or more polarization enhancement layers 1202 may be formed over the oxide semiconductor layer 1102. The one or more polarization enhancement layers 1202 may include one or more semiconductors (e.g., semiconductor materials and / or oxide semiconductor materials) having a second type of semiconductor different from the first type of semiconductor of the oxide semiconductor layer 1102. In some embodiments, wherein the oxide semiconductor layer 1102 includes an n-type oxide semiconductor, the one or more polarization enhancement layers 1202 may include one or more p-type semiconductors, such as p-doped silicon, p-doped germanium, tin oxide (SnO), nickel oxide (NiO), copper oxide (Cu2O), tungsten diselenide (WSe2), tungsten distelluride (WTe2), molybdenum distelluride (MoTe2). In other embodiments, wherein the oxide semiconductor layer 1102 includes a p-type oxide semiconductor, the one or more polarization enhancement layers 1202 may include one or more n-type semiconductors, such as n-doped silicon, n-doped germanium, zinc oxide (ZnO), etc. In various embodiments, one or more polarization enhancement layers 1202 may be formed by one or more deposition processes (e.g., ALD, CVD, PE-CVD, etc.). In some embodiments, one or more polarization enhancement layers 1202 may be inherently doped, while in other embodiments, one or more polarization enhancement layers 1202 may be doped by an implantation process.

[0081] like Figure 13 As shown in cross-sectional view 1300, a first patterning process is performed to pattern one or more polarization enhancement layers (e.g., Figure 12 1202), oxide semiconductor layer (e.g., Figure 12 1102) and ferroelectric layers (e.g., Figure 12 (1002). The first patterning process removes one or more polarization enhancement layers (e.g., Figure 12 A portion of 1202) is used to form polarization enhancement structure 112, removing oxide semiconductor layer (e.g., Figure 12 A portion of 1102) is used to form oxide semiconductor 106, and the ferroelectric layer (e.g., Figure 12 A portion of the gate structure 102 is used to form the ferroelectric structure 104, and the upper surface of the gate structure 102 is exposed. In some embodiments, the first patterning process may also remove a portion of the gate structure 102.

[0082] In some embodiments, based on one or more polarization enhancement layers (e.g., Figure 12A first masking structure 1304 is formed over a first patterning process that selectively exposes one or more polarization enhancement layers, oxide semiconductor layers, and ferroelectric layers to the first etchant 1302. In some embodiments, the first masking structure 1304 may include a photosensitive material (e.g., photoresist). In other embodiments, the first masking structure 1304 may include a dielectric masking layer (e.g., silicon oxide, silicon dioxide, etc.), a hard mask, etc. In some embodiments, the first etchant 1302 may include a dry etchant (e.g., having fluorine chemicals, chlorine chemicals, etc.). In other embodiments, the first etchant 1302 may include a wet etchant (e.g., including hydrofluoric acid, potassium hydroxide, etc.).

[0083] like Figure 14 As shown in cross-sectional view 1400, a second patterning process is performed to selectively etch the gate layer (e.g., Figure 13 The process involves forming a gate structure 102 and a FeFET stack 1402. In some embodiments, a second patterning process can be performed by selectively exposing the gate layer to a second etchant 1404, based on a second masking structure 1406 formed over the polarization enhancement structure 112 and the gate layer. In some embodiments, the second masking structure 1406 may include a photosensitive material (e.g., photoresist). In some embodiments, the second etchant 1404 may include a dry etchant (e.g., having fluorinated chemicals, chlorinated chemicals, etc.). In other embodiments, the second etchant 1404 may include a wet etchant (e.g., including hydrofluoric acid, potassium hydroxide, etc.).

[0084] like Figure 15 As shown in cross-sectional view 1500, a dielectric layer 502 is formed over the FeFET stack 1402. The dielectric layer 502 extends along the upper surface and sidewalls of the FeFET stack 1402. In various embodiments, the dielectric layer 502 can be formed by one or more deposition processes (e.g., ALD process, CVD process, PE-CVD process, etc.).

[0085] like Figure 16 As shown in cross-sectional view 1600, a third patterning process is performed to pattern the dielectric layer 502 and form source contact holes 1602a and drain contact holes 1602b. In some embodiments, the source contact holes 1602a and drain contact holes 1602b extend through the dielectric layer 502 and the polarization enhancement structure 112 to expose the upper surface of the oxide semiconductor 1106. In some embodiments, according to the third masking structure 1604, the third patterning process is performed by selectively exposing the dielectric layer 502 to a third etchant 1606. In some embodiments, the third etchant 1606 may include a dry etchant (e.g., having fluorinated chemicals, chlorinated chemicals, etc.).

[0086] like Figure 17 As shown in cross-sectional view 1700, a fourth patterning process is performed to pattern the dielectric layer 502 and form the gate contact via 1702. In some embodiments, according to the fourth masking structure 1704, the fourth patterning process is performed by selectively exposing the dielectric layer 502 to a fourth etchant. In some embodiments, the fourth etchant 1706 may include a dry etchant (e.g., having fluorinated chemicals, chlorinated chemicals, etc.). In some alternative embodiments (not shown), the same patterning process can be used to form the source contact via 1602a, the drain contact via 1602b, and the gate contact via 1702. In such embodiments, the source contact via 1602a, the drain contact via 1602b, and the gate contact via 1702 may be formed simultaneously.

[0087] like Figure 18 As shown in cross-sectional view 1800, conductive material is formed within source contact via 1602a, drain contact via 1602b, and gate contact via 1702. In some embodiments, the conductive material may include a metal, such as copper, tungsten, cobalt, etc. In some embodiments, the conductive material may be deposited by one or more of deposition and plating processes. In some embodiments, a deposition process may be used to form a seed layer of conductive material, followed by a plating process to fill the source contact via 1602a, drain contact via 1602b, and gate contact via 1702. After the conductive material is formed, a planarization process may be performed to remove excess conductive material from above the dielectric layer and form source region 108, drain region 110, and gate contact 604.

[0088] like Figure 19 As shown in cross-sectional view 1900, one or more additional interconnects 606 may be formed within the interlayer dielectric (ILD) structure 608 disposed above the dielectric layer 502. In some embodiments, the one or more additional interconnects 606 may include one or more BEOL (back-end process) interconnects, MEOL (intermediate process) interconnects, conductive contacts, and interconnects. In some embodiments, one or more additional interconnects may be formed by a mosaic process (e.g., a single mosaic process or a dual mosaic process).

[0089] Figure 20 Flowcharts illustrating some embodiments of a method 2000 for forming an integrated chip including a FeFET device with a polarization enhancement structure are shown.

[0090] While the disclosed method 2000 is shown and described herein as a series of steps or events, it should be understood that the order of these steps or events shown should not be construed as limiting. For example, some steps may occur in a different order and / or simultaneously with other steps or events besides those shown and / or described herein. Furthermore, it is not required that all shown steps are used to implement one or more aspects or embodiments described herein. Moreover, one or more of the steps described herein may be performed in one or more separate steps and / or stages.

[0091] In step 2002, a ferroelectric layer is formed on the gate layer. Figure 10 Cross-sectional view 1000 is shown, corresponding to some embodiments of step 2002.

[0092] At step 2004, an oxide semiconductor layer is formed on the ferroelectric layer. The oxide semiconductor layer has a first type of semiconductor (e.g., an n-type semiconductor with electrons as the majority carriers). Figure 11 Cross-sectional view 1100 is shown, corresponding to some embodiments of step 2004.

[0093] At step 2006, one or more polarization enhancement layers are formed on the oxide semiconductor layer. The one or more polarization enhancement layers have a second type of semiconductor (e.g., a p-type semiconductor with holes as majority carriers) that is different from the first type of semiconductor. Figure 12 Cross-sectional view 1200 is shown, corresponding to some embodiments of step 2006.

[0094] At step 2008, one or more of the following are patterned: a polarization enhancement layer, an oxide semiconductor layer, a ferroelectric layer, and a gate layer, to form a FeFET stack having a ferroelectric structure between the gate structure and the oxide semiconductor. Figures 13-14 Cross-sectional views 1300-1400 are shown for some embodiments corresponding to step 2008.

[0095] At step 2010, a dielectric layer is formed over the FeFET stack. Figure 15 Cross-sectional view 1500 is shown, corresponding to some embodiments of step 2010.

[0096] At step 2012, one or more additional patterning processes are performed to form source contact holes and / or drain contact holes that extend through the dielectric layer and expose the oxide semiconductor. Figure 16 Cross-sectional view 1600 is shown, corresponding to some embodiments of step 2012.

[0097] In step 2014, conductive material is formed in the source contact hole and / or drain contact hole. Figure 18Cross-sectional view 1800 is shown, corresponding to some embodiments of step 2014.

[0098] At step 2016, one or more additional interconnects are formed within the ILD structure formed above the dielectric layer. Figure 19 Cross-sectional view 1900 is shown, corresponding to some embodiments of step 2016.

[0099] Therefore, in some embodiments, this disclosure relates to an integrated chip including a ferroelectric field-effect transistor (FeFET) device having a polarization enhancement structure disposed over an oxide semiconductor configured to serve as a channel. The oxide semiconductor has a first semiconductor type (e.g., n-type or p-type) different from the second semiconductor type (e.g., p-type or n-type) of the polarization enhancement structure.

[0100] In some embodiments, this disclosure relates to a ferroelectric field-effect transistor (FeFET) device. The FeFET device includes: a ferroelectric structure having a first side and a second side; a gate structure disposed along the first side of the ferroelectric structure; an oxide semiconductor disposed along the second side of the ferroelectric structure and having a first semiconductor type; a source region and a drain region disposed on the oxide semiconductor, the gate structure being laterally located between the source region and the drain region; and a polarization enhancement structure disposed on the oxide semiconductor between the source region and the drain region, and comprising a semiconductor material or an oxide semiconductor material having a second semiconductor type different from the first semiconductor type. In some embodiments, the FeFET device further includes a dielectric layer disposed on the polarization enhancement structure, the source region and the drain region extending through the dielectric layer and the polarization enhancement structure. In some embodiments, the first semiconductor type is an n-type semiconductor, and the second semiconductor type is a p-type semiconductor. In some embodiments, the polarization enhancement structure is disposed along opposite sides of the source region and opposite sides of the drain region. In some embodiments, the oxide semiconductor includes one or more of indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, and zinc oxide. In some embodiments, the polarization enhancement structure has an uppermost surface that extends continuously between a first sidewall of the source region and a second sidewall of the drain region. In some embodiments, the source region is coupled to a source line, the drain region is coupled to a bit line, and the gate structure is coupled to a word line. In some embodiments, the FeFET device further includes: a dielectric layer disposed on an upper surface of the gate structure, the upper surface of the gate structure extending continuously directly from below the ferroelectric structure to a laterally outer side of the ferroelectric structure; and a gate contact extending through the dielectric layer to contact the gate structure. In some embodiments, the gate structure is disposed along a first side of the substrate, the gate structure being vertically disposed between the first side of the substrate and the ferroelectric structure. In some embodiments, the FeFET device further includes a transistor device disposed along the first side of the substrate. In some embodiments, the polarization enhancement structure extends continuously with a first width along a cross-section extending through the source and drain regions, wherein, when viewed along the cross-section, the oxide semiconductor extends continuously with a second width, the second width being greater than the first width.

[0101] In other embodiments, this disclosure relates to an integrated chip. The integrated chip includes: a gate structure disposed above a substrate; a ferroelectric structure disposed on the gate structure; an oxide semiconductor separated from the gate structure by the ferroelectric structure and having a first semiconductor type; a source region disposed on the oxide semiconductor; and a polarization enhancement structure disposed on the oxide semiconductor and having a second semiconductor type different from the first semiconductor type. In some embodiments, the source region is metal. In some embodiments, the integrated chip further includes a drain region disposed on the oxide semiconductor, the uppermost surface of the polarization enhancement structure extending continuously between the sidewalls of the source region and the drain region. In some embodiments, the gate structure includes a material having a Fermi level between the Fermi level of the oxide semiconductor and the Fermi level of the polarization enhancement structure. In some embodiments, the oxide semiconductor and the polarization enhancement structure each have a value less than about 1 × 10⁻⁶. 18 at / cm -3 The doping concentration.

[0102] In other embodiments, this disclosure relates to a method of forming a FeFET device. The method includes: forming a FeFET stack having a polarization enhancement structure disposed on an oxide semiconductor separated from a gate structure by a ferroelectric structure, the oxide semiconductor having a semiconductor type different from the polarization enhancement structure; forming a dielectric layer on the polarization enhancement structure; performing a first patterning process to form a source opening exposing the oxide semiconductor; and forming a conductive material within the source opening. In some embodiments, the method further includes performing a planarization process to remove excess conductive material over the dielectric layer. In some embodiments, the oxide semiconductor includes an n-type semiconductor, and the polarization enhancement structure includes a p-type semiconductor. In some embodiments, the oxide semiconductor includes indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, or zinc oxide.

[0103] The foregoing has described components of several embodiments, enabling those skilled in the art to better understand the various embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on the present invention to achieve the same objectives and / or realize the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made therein without departing from the spirit and scope of this disclosure.

Claims

1. A ferroelectric field-effect transistor device, comprising: A ferroelectric structure having a first side and a second side; A gate structure is disposed along the second side of the ferroelectric structure; An oxide semiconductor is disposed along a first side of the ferroelectric structure and has a first conductivity type; A source region and a drain region are disposed on the oxide semiconductor, wherein the gate structure is laterally located between the source region and the drain region; A polarization enhancement structure is disposed on the oxide semiconductor between the source region and the drain region, and includes a semiconductor material having a second conductivity type different from the first conductivity type; and A dielectric layer is disposed on the polarization enhancement structure, wherein the source region and the drain region extend through the dielectric layer and the polarization enhancement structure.

2. The ferroelectric field-effect transistor device according to claim 1, wherein, The source region is metal.

3. The ferroelectric field-effect transistor device according to claim 1, wherein, The first conductivity type is an n-type semiconductor, and the second conductivity type is a p-type semiconductor.

4. The ferroelectric field-effect transistor device according to claim 1, wherein, The polarization enhancement structure is arranged on opposite sides of the source region in the lateral direction, and on opposite sides of the drain region in the lateral direction.

5. The ferroelectric field-effect transistor device according to claim 1, wherein, The oxide semiconductor includes one or more of indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, and zinc oxide.

6. The ferroelectric field-effect transistor device according to claim 1, wherein, The polarization enhancement structure has an uppermost surface that extends continuously between the first sidewall of the source region and the second sidewall of the drain region.

7. The ferroelectric field-effect transistor device according to claim 1, wherein, The source region is coupled to the source line, the drain region is coupled to the bit line, and the gate structure is coupled to the word line.

8. The ferroelectric field-effect transistor device according to claim 1, wherein, The dielectric layer is further disposed on the upper surface of the gate structure, wherein the upper surface of the gate structure extends continuously from below the ferroelectric structure to the lateral outer side of the ferroelectric structure; and The gate contact extends through the dielectric layer to contact the gate structure.

9. The ferroelectric field-effect transistor device according to claim 1, in, The gate structure is disposed along a first side of the substrate; and The gate structure is vertically disposed between the first side of the substrate and the ferroelectric structure.

10. The ferroelectric field-effect transistor device according to claim 9, further comprising: A transistor device is arranged along a first side of the substrate.

11. The ferroelectric field-effect transistor device according to claim 1, in, The polarization enhancement structure extends continuously with a first width along a cross-section extending through the source region and the drain region; and When viewed along the cross-section, the oxide semiconductor continuously extends a second width, which is greater than the first width.

12. An integrated chip, comprising: The gate structure is arranged above the substrate; A ferroelectric structure is arranged on the gate structure; An oxide semiconductor, separated from the gate structure by the ferroelectric structure and having a first conductivity type; The source region is disposed on the oxide semiconductor; A polarization enhancement structure is disposed on the oxide semiconductor and has a second conductivity type different from the first conductivity type; as well as A dielectric layer is disposed on the polarization enhancement structure, wherein the source region extends through the dielectric layer and the polarization enhancement structure.

13. The integrated chip according to claim 12, wherein, The source region is metal.

14. The integrated chip according to claim 12, further comprising: A drain region is disposed on the oxide semiconductor, wherein the uppermost surface of the polarization enhancement structure extends continuously between the sidewalls of the source region and the drain region.

15. The integrated chip according to claim 12, wherein, The gate structure includes a material having a Fermi level between the Fermi level of the oxide semiconductor and the Fermi level of the polarization-enhanced structure.

16. The integrated chip according to claim 12, wherein, The oxide semiconductor and the polarization enhancement structure each have a density less than 1 × 10⁻⁶. 18 at / cm -3 The doping concentration.

17. A method for forming a ferroelectric field-effect transistor device, comprising: A ferroelectric field-effect transistor stack is formed, the polarization enhancement structure being disposed on an oxide semiconductor separated from the gate structure by the ferroelectric structure, wherein the oxide semiconductor has a different conductivity type than the polarization enhancement structure; A dielectric layer is formed on the polarization enhancement structure; Perform a first patterning process to form a source opening exposing the oxide semiconductor through the dielectric layer and the polarization enhancement structure; and Conductive material is formed within the source opening that passes through the dielectric layer and the polarization enhancement structure.

18. The method of claim 17, further comprising: A planarization process is performed to remove excess conductive material from above the dielectric layer.

19. The method of claim 17, wherein, The oxide semiconductor includes an n-type semiconductor, and the polarization enhancement structure includes a p-type semiconductor.

20. As described in claim 17, wherein, The oxide semiconductor includes indium gallium zinc oxide, indium gallium zinc tin oxide, indium tungsten oxide, indium tungsten zinc oxide, indium zinc oxide, or zinc oxide.

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