Multilayer thin film stacking of diffractive optical elements

Abstract

This application relates to a multilayer thin-film stack of diffractive optical elements. The optical element may include a substrate. The optical element may include a first antireflective structure formed on the substrate for a specific wavelength range. The optical element may include at least one layer disposed on a portion of the first antireflective structure. The optical element may include a second antireflective structure formed on the at least one layer for the specific wavelength range. The depth between a first surface of the first antireflective structure and a second surface of the second antireflective structure, a first refractive index of the first antireflective structure, a second refractive index of the second antireflective structure, and a third refractive index of at least one layer can be selected to form a diffractive optical element associated with a specific phase delay for a specific wavelength.

Description

[0001] This application is a divisional application of the application filed on August 15, 2018, with application number 201810926942.0 and invention title "Multilayer Thin Film Stacking of Diffractive Optical Elements". Technical Field

[0002] This disclosure relates to thin film stacks. More specifically, some aspects of this disclosure relate to a multilayer thin film stack for a diffractive optical element (DOE) that provides a specific phase delay between etched and unetched regions of the multilayer thin film stack and provides an anti-reflection coating for a specific wavelength range. background

[0003] Diffractive optical elements (DOEs) can be used to guide light beams. For example, DOEs such as diffractive lenses, spot array illuminators, spot generators, and Fourier array generators can be used to split, shape, and focus light beams. DOEs can be integrated into multicast switches, wavelength-selective switches, gesture recognition systems, motion sensing systems, and more.

[0004] Multi-level surface relief profiles can be selected for surface-relief DOEs. For example, a two-level (sometimes called "binary") surface relief profile can be selected for a surface-relief DOE. Multi-level surface relief profiles can be selected to approximate a continuous surface relief profile, enabling the fabrication of DOEs using photolithography and / or etching processes. Two-level film stacks can be used to produce single-order binary DOEs, such as diffractive lenses. Some materials used for DOEs may require etching depths greater than a threshold, resulting in a threshold etching time for fabricating the DOE.

[0005] Overview

[0006] The implementation of this application mainly includes the following aspects:

[0007] (1) An optical element may include a substrate. The optical element may include a first antireflective structure formed on the substrate for a specific wavelength range. The optical element may include at least one layer disposed on a portion of the first antireflective structure. The optical element may include a second antireflective structure formed on the at least one layer for a specific wavelength range. The depth between a first surface of the first antireflective structure and a second surface of the second antireflective structure, a first refractive index of the first antireflective structure, a second refractive index of the second antireflective structure, and a third refractive index of the at least one layer may be selected to form a diffractive optical element associated with a specific phase delay of a specific wavelength.

[0008] (2) The optical element according to (1), wherein the first anti-reflection structure is formed on a first side of the substrate; and the optical element further includes an anti-reflection coating formed on a second side of the substrate.

[0009] (3) The optical element according to (1), wherein the first anti-reflection structure is an etch stop portion for etching the second anti-reflection structure.

[0010] (4) The optical element according to (1), wherein at least one of the first anti-reflection structure, the second anti-reflection structure or the at least one layer is formed by thin film deposition.

[0011] (5) The optical element according to (1), wherein the first antireflective structure comprises a first silicon layer and a first silicon dioxide layer; wherein the at least one layer comprises a second silicon layer; wherein the second antireflective structure comprises a second silicon dioxide layer; and wherein the specific wavelength range is between approximately 840 nm and 860 nm.

[0012] (6) The optical element according to (1), wherein the first antireflective structure, the second antireflective structure and the at least one layer are formed of alternating layers of silicon and silicon dioxide.

[0013] (7) The optical element according to (1), wherein the first anti-reflection structure, the second anti-reflection structure and the at least one layer are formed of alternating layers of silicon hydride and silicon dioxide.

[0014] (8) The optical element according to (1), wherein the first anti-reflection structure is formed by a first layer of a first material and a second layer of a second material; wherein the at least one layer is formed by a third layer of the first material; and wherein the second anti-reflection structure is formed by the first layer, the second layer, the third layer, a fourth layer of the second material and a fifth layer of the first material.

[0015] (9) The optical element according to (1), wherein the first antireflective structure is formed on a first side of the substrate; and the optical element further comprises: a third antireflective structure formed on a second side of the substrate for another specific wavelength; at least one additional layer disposed on a portion of the third antireflective structure; and a fourth antireflective structure formed on the other at least one layer for the other specific wavelength.

[0016] (10) The optical element according to (1), wherein the first anti-reflection structure and the second anti-reflection structure form a two-level relief profile.

[0017] (11) The optical element according to (1), wherein the first antireflective structure comprises a first silicon layer and a first silicon dioxide layer; wherein the at least one layer comprises a second silicon layer; wherein the second antireflective structure comprises a second silicon dioxide layer; and wherein the specific wavelength range is between approximately 930 nm and 950 nm.

[0018] (12) The optical element according to (1), wherein the first antireflective structure comprises a first silicon layer and a first silicon dioxide layer; wherein the at least one layer comprises a second silicon layer and a second silicon dioxide layer; wherein the second antireflective structure comprises a third silicon layer; and wherein the specific wavelength is between approximately 1540 nm and 1560 nm.

[0019] (13) The optical element according to (1), wherein the specific wavelength is between approximately 840 nanometers and 940 nanometers.

[0020] (14) The optical element according to (1), wherein the depth is between λ / 4 and λ / 2, where λ represents the specific wavelength.

[0021] (15) The optical element according to (1), wherein the effective refractive index of the optical element is between 2.0 and 3.0.

[0022] (16) The optical element according to (1), wherein the specific phase delay is a π phase delay.

[0023] (17) The optical element according to (1), wherein the particular phase delay is a non-π phase delay.

[0024] (18) A method may include depositing multiple layers on a wafer. The deposition may form a first antireflective structure with respect to a specific wavelength beneath a second antireflective structure with respect to that specific wavelength. The method may include etching a subset of the multiple layers to form a two-level relief profile. The etching may form a diffractive optical element associated with a specific phase delay for a specific wavelength between the first and second antireflective structures.

[0025] (19) The method according to (18) further includes: cutting the wafer into a plurality of diffractive optical elements.

[0026] (20) According to the method of (18), wherein the second anti-reflective structure is formed on top of the first anti-reflective structure.

[0027] (21) According to the method of (18), wherein at least one layer is formed between the first anti-reflective structure and the second anti-reflective structure.

[0028] (22) A method may include depositing a plurality of thin films onto a wafer using a thin film deposition technique. Depositing the plurality of thin films may include depositing a first antireflective structure with respect to a specific wavelength, and depositing a second antireflective structure with respect to the specific wavelength after depositing the first antireflective structure. The method may include patterning a mask based on a defined set of transition points defining a plurality of regions of the wafer. The method may include etching a subset of the thin films in the plurality of thin films based on the mask to form a two-level relief profile. Etching may form diffractive optical elements associated with a π-phase delay at a specific wavelength between the first and second antireflective structures. The method may include removing the mask.

[0029] (23) The method according to (22) further includes: cutting the wafer into a plurality of diffractive optical elements.

[0030] (24) The method according to (22) further includes: forming an additional diffractive optical element on the other side of the wafer, the additional diffractive optical element being associated with a π phase delay of the specific wavelength between the third and fourth antireflection structures of the other diffractive optical elements.

[0031] (25) According to the method of (22), wherein at least one layer is formed between the first anti-reflective structure and the second anti-reflective structure. Attached Figure Description

[0032] Figure 1 This is a schematic diagram of the example implementation described in this article;

[0033] Figure 2A and 2B This is a simplified diagram of the features related to the example implementation described in this article;

[0034] Figure 3A and 3B This is a simplified diagram of the features related to the example implementation described in this article;

[0035] Figures 4A-4C This is a simplified diagram of the example implementation described in this article;

[0036] Figure 5 This is a flowchart of an example process for configuring the example implementation described in this article;

[0037] Figure 6A and 6B Is with Figure 5 A simplified diagram illustrating the example implementation related to the example process shown;

[0038] Figure 7 This is a flowchart of an example process for creating the example implementation described in this article; and

[0039] Figure 8A and 8B Is with Figure 7 A simplified diagram of the example implementation related to the example process shown. Detailed description

[0040] The following example implementation is described in detail with reference to the accompanying drawings. The same reference numerals in different drawings may refer to the same or similar elements.

[0041] Diffractive optical elements (DOEs) can be fabricated using photolithography and / or etching processes. For example, to approximate a continuous surface relief profile, a multi-level surface relief profile can be selected for the DOE, and the surface of the DOE can be etched or patterned to form the multi-level surface relief profile. The multi-level surface relief profile can be used to generate a phase delay for the light beam passing through the DOE. For a single-order binary DOE, such as a diffractive lens, a diffraction efficiency of approximately 40% can be obtained using a binary-level surface relief profile. However, this diffraction efficiency can be less than a threshold, which is necessary for the use of DOEs in optical systems such as optical communication systems, gesture recognition systems, motion detection systems, etc. Furthermore, in some systems, reducing the 0th order of the optical system may be advantageous to avoid eye damage, for example, in gesture recognition systems.

[0042] Some implementations described herein can provide two-stage DOEs with threshold diffraction efficiency. For example, some implementations described herein can provide two-stage (also called “binary”) DOEs with threshold feature dimensions (e.g., a threshold amount of wavelength) to provide π phase delay between the portions of the DOE. Furthermore, the DOE can be associated with an etching depth to create a selected surface relief profile smaller than a threshold, resulting in a reduced aspect ratio, reduced etching time, and / or reduced manufacturing cost (relative to other techniques for manufacturing DOEs). Additionally, the layers of the DOE can provide anti-reflective properties, provide integrated etch stops, and may include materials selected for a specific operating wavelength range of the DOE, etc. Some implementations described herein can provide methods for configuring and / or manufacturing DOEs. Based on the use of thin-film deposition techniques, phase delay can be controlled with greater precision, which can reduce the 0th order of the optical system. For example, thin-film deposition techniques can be associated with tolerances of less than 1%, less than 0.5%, less than 0.2%, less than 0.1%, etc. Other manufacturing techniques with similar controlled tolerances can also be used to construct the DOEs described herein.

[0043] Figure 1 This is a schematic diagram 100 of the example implementation described in this article. Figure 1 An example of dot generation using a surface-embossed DOE grating and a converging lens as a dot illuminator (sometimes called a dot generator) is shown.

[0044] like Figure 1 As shown, the incident plane wave 110 with wavelength λ0 points towards the surface-relief DOE grating 120. In some implementations, the surface-relief DOE grating 120 may be a DOE with a multi-level surface relief profile, such as a two-level DOE (sometimes referred to as a binary DOE). In some implementations, the surface-relief DOE grating 120 may include, for example, alternating layers of silicon (Si) and silicon dioxide (SiO2), alternating layers of silicon hydride (Si:H) and silicon dioxide, etc. In some implementations, the layers of the surface-relief DOE grating 120 may be configured to provide anti-reflection functionality in both etched and unetched areas of the surface-relief DOE grating 120. In some implementations, the layers of the surface-relief DOE grating 120 (e.g., a silicon dioxide layer) may provide an etch-stop function during the fabrication of the surface-relief DOE grating 120. In some implementations, the incident plane wave 110 can have a wavelength range from approximately 800 nanometers (nm) to approximately 1100 nanometers, approximately 800 nanometers to approximately 1000 nanometers, approximately 830 nanometers to approximately 1000 nanometers, approximately 850 nanometers to approximately 1000 nanometers, approximately 915 nanometers to approximately 1000 nanometers, approximately 940 nanometers to approximately 1000 nanometers, etc. Additional details regarding the surface-embossed DOE grating 120 are described in this document.

[0045] like Figure 1 As further shown, the surface-embossed DOE grating 120 diffracts the incident plane wave 110 and guides the wavefront 130 (e.g., the diffraction order of the incident plane wave 110) to the converging lens 140. The converging lens 140 is separated from the focal plane 160 by a focal length 150. In some implementations, example implementation 100 can be used in a gesture recognition system, and the focal plane 160 can be the target of gesture recognition. Alternatively or concurrently, the focal plane 160 can be an object (e.g., for a motion sensing system), a communication target (e.g., for an optical communication system), etc.

[0046] like Figure 1 As further shown, the orientation of the wavefront 130 is altered by the converging lens 140 to form a wavefront 170, which is then guided to the focal plane 160, thereby forming a multi-dot pattern at the focal plane 160. In some implementations, a surface-embossed DOE grating 120 can be used to create a one-dimensional dot pattern. In some implementations, the surface-embossed DOE grating 120 can be used to create a two-dimensional dot pattern. Thus, the surface-embossed DOE grating can be used as a dot illuminator to create a dot pattern at the focal plane 160 based on the incident plane wave 110, thereby enabling gesture recognition systems, motion sensing systems, optical communication systems, etc.

[0047] As mentioned above, Figure 1This is provided as an example only. Other examples are possible and may differ from those provided. Figure 1 Example of the description.

[0048] Figure 2A and 2B These are simplified diagrams 200 and 250, respectively, relating to characteristics related to DOE. For example... Figure 2A As shown in the diagram, and through the simplified diagram 200, the continuous relief profile can be quantized into a series of discrete levels so that photolithography and / or etching processes can be used to manufacture DOE.

[0049] like Figure 2A Furthermore, as shown by reference numeral 202, a continuous relief profile can be associated with approximately 100% diffraction efficiency (for a single-order configuration) and can provide a phase delay that increases by 2π from the second spacing position dx relative to the first spacing position 0. As shown by reference numeral 204, the continuous relief profile can be approximated by a two-level relief profile (sometimes referred to as a binary relief profile). A two-level binary relief profile can be associated with approximately 40.5% diffraction efficiency (for a single-order configuration) and can provide a π phase delay relative to the first region of the DOE from spacing position 0 to spacing position 0.5dx, and in the second region of the DOE from spacing position 0.5dx to spacing position dx.

[0050] like Figure 2A Furthermore, as shown by reference numeral 206, the continuous relief profile can be approximated by a 4-order relief profile. The 4-order relief profile can be associated with approximately 81% diffraction efficiency (for a single-order configuration) and can provide a π / 2 phase delay relative to the first region of the DOE from 0 to 0.25 dx, a second region of the DOE from a spacing position of 0.25 dx to a spacing position of 0.5 dx, a π phase delay relative to the first region of the DOE, a third region of the DOE from 0.5 dx to 0.75 dx, and a 3π / 2 phase delay relative to the first region of the DOE, a fourth region of the DOE from 0.75 dx to dx.

[0051] like Figure 2AFurthermore, as shown by reference numeral 208, the continuous relief profile can be approximated by an 8-level relief profile. An 8-level relief profile can be associated with approximately 95% diffraction efficiency (for a single-order configuration) and can provide a phase delay in increments of π / 4 in the regions of the DOE (e.g., π / 4 in the second region from 0.125dx to 0.25dx relative to the first region from 0 to 0.125dx; π / 2 in the third region from 0.25dx to 0.375dx; 3π / 4 in the fourth region from 0.375dx to 0.5dx; and so on). In some implementations, another configuration with a different diffraction efficiency can be used. For example, configurations of 2nd, 4th, 10th, 100th, thousands of orders, etc., relative to the single-order configuration, can be used to increase diffraction efficiency. In this case, for example, for + / -100 orders, for a two-level relief profile, approximately 65% ​​to 80% diffraction efficiency can be obtained.

[0052] like Figure 2B Furthermore, as shown in simplified diagram 250, a two-level relief profile can be used for a DOE having multiple unetched regions 252 and etched regions 254. In some implementations, the unetched regions 252 may be associated with a π phase delay relative to the etched regions 254. In some implementations, the unetched regions 252 may be associated with a thin film refractive index n for the silicon (Si) air interface. tf In some implementations, the etched region 254 may be associated with no phase delay. In other words, the unetched region 252 is associated with a π phase delay relative to the etched region 254. In some implementations, the etched region 254 is associated with the refractive index n of the substrate (e.g., silicon) to air interface. 空气 Associated. In some implementations, each group of etched regions 254 and unetched regions 252 can be associated together with a width dx, and the DOE can be associated with a total width of N*dx, where N is an integer value representing the number of groups of etched regions 254 and unetched regions 252 (e.g., 1, 2, 3, 4, 5, etc.).

[0053] As mentioned above, Figure 2A and 2B This is provided as an example only. Other examples are possible and may differ from those provided. Figure 2A and 2B Example of the description.

[0054] Figure 3A and 3B This is a simplified diagram relating to the characteristics of DOE. It shows the DOE 300. Figure 3A Corresponding to Figure 2B The DOE in the document has a two-level relief profile, which can be configured to provide a π phase delay.

[0055] like Figure 3A As shown, DOE 300 may include a substrate 305. In some implementations, substrate 305 may be a glass substrate, a fused silica substrate, etc. For example, substrate 305 may be approximately 200 mm thick and have a refractive index n 衬底 The substrate is a fused silica substrate with a thickness of 1.45. In some implementations, an anti-reflective coating 310 may be disposed on the surface of the substrate 305. For example, as... Figure 3A As shown, a set of alternating silicon and silicon dioxide layers may be disposed on the top surface of substrate 305 and patterned to form an embossed profile, as described herein, and an anti-reflective coating 310 may cover the bottom surface of substrate 305.

[0056] like Figure 3A As further shown, a set of silicon layers 315 and a set of silicon dioxide layers 320 can be disposed on the top surface of the substrate 305. For example, silicon layer 315-1 can be disposed on the substrate 305, and silicon dioxide layer 320-1 can be disposed on silicon layer 315-1. Silicon layer 315-1 and silicon dioxide layer 320-1 can form a pair of matching layers 325-1. Similarly, silicon layer 315-2 can be disposed on silicon dioxide layer 320-2, and a pair of matching layers 325-2 can be formed. As shown, silicon layer 315-3 can be disposed between matching layers 325-1 and matching layers 325-2.

[0057] In some implementations, matching layers 325-1 and 325-2 may form an anti-reflective coating to increase the transmittance of the DOE 300. In some implementations, the DOE 300 may be exposed to an air interface. For example, the first surface of the DOE 300 (e.g., the surfaces of matching layers 325-1 and 325-2) and the second surface of the DOE 300 (e.g., the surface of the anti-reflective coating 310) may be exposed to a refractive index n. 空气 The air interface is 1.0. The relief depth h can be calculated based on the following equation:

[0058]

[0059] Where λ0 is the nominal illumination wavelength of the DOE (e.g., DOE 300). To reduce the relief depth, a material with a relatively high refractive index, such as silicon, can be chosen. In some implementations, this can result in a relief depth h of approximately 0.5 micrometers (μm) for the etching (e.g., etch 330). In some implementations, the relief depth can be between approximately λ / 4 and λ / 2, where λ represents the specific wavelength at which a particular phase delay is obtained, such as a wavelength of approximately 940 nm, a wavelength between 840 nm and 940 nm, etc., at which a π phase delay is obtained, for example, for an effective refractive index between 2.0 and 3.0, an effective refractive index of 2.2, etc. In some implementations, the layers can be matched with refractive indices to increase the transmittance of the DOE 300. For example, silicon layer 315 and silicon dioxide layer 320 can be selected based on corresponding refractive indices of 3.5 and 1.45, respectively, within threshold amounts between 3.1 and 3.9 and between 1.4 and 1.5. In this way, based on reducing the relief depth relative to other DOEs, some of the implementations described in this article can improve manufacturing tolerances.

[0060] like Figure 3B Furthermore, as shown in Figure 350, other materials can be selected for the thin-film coating material, such as tantalum pentoxide (Ta2O5) and silicon nitride (Si3N4), which can have a refractive index of approximately 2.0. As further shown in Figure 350, based on the use of a silicon thin film for the DOE 300 layer, the relief depth of each of the two-level, four-level, eight-level, or continuous relief profiles is reduced compared to other material selections. For example, for a π phase retardation in a two-level relief profile with a nominal illumination wavelength of 1550 nm, silicon dioxide can be associated with a relief depth of approximately 1.55 μm, tantalum pentoxide and silicon nitride can be associated with a relief depth of approximately 0.78 μm, and silicon can be associated with a relief depth of approximately 0.31 μm.

[0061] As mentioned above, Figure 3A and 3B This is provided as an example only. Other examples are possible and may differ from those provided. Figure 3A and 3B Example of the description.

[0062] Figures 4A-4C This is a simplified diagram of an example implementation of DOE 400 / 400' / 400". Figure 4A As shown, DOE 400 includes a substrate 405, an anti-reflective coating 410, a set of silicon layers 415-1 to 415-3 and a set of silicon dioxide layers 420-1 to 420-2.

[0063] like Figure 4AAs further shown by reference numeral 425, the silicon dioxide layer 420-1 may be an etch stop layer to enable etching to create a π phase delay. For example, an etching process may be performed such that unetched stacks 430-1 and 430-2 remain unetched, and etched stacks 435-1 and 435-2 are etched to a threshold relief depth 440 to provide a π phase delay between the etched stacks 435-1 and 435-2 and the unetched stacks 430-1 and 430-2. In some implementations, multiple etch processes using multiple tools may be performed to etch the DOE 400. For example, the DOE 400 may be fabricated using a first silicon etch with a silicon dioxide layer as an etch stop, a first silicon dioxide etch with a silicon layer as an etch stop, and a second silicon etch with another silicon dioxide layer as an etch stop (e.g., using a deep reactive ion (DRIE) etching tool), etc.

[0064] In some implementations, the layers of DOE 400 can form a set of anti-reflective structures. For example, layers 420-1 and 415-1 can form a first anti-reflective structure for a specific wavelength range, and layers 415-2 and 420-2 can form a second anti-reflective structure for the same wavelength range, thus forming a two-level relief profile. Alternatively or additionally, layer 415-2 can form the second anti-reflective structure. The second anti-reflective structure can be formed on the first anti-reflective structure (e.g., in the unetched stack 430), and the first anti-reflective structure (e.g., layer 420-1) can be an etch stop for forming the second anti-reflective structure. In some implementations, at least one layer, such as layer 415-3, or both layers 415-3 and 420-2, can be between the first and second anti-reflective structures. This allows for modification of the etched area to alter the characteristics of DOE 400 without changing its transmittance. In some implementations, the first and second anti-reflective structures may not be separated by layers. In some implementations, layer 415-3 can provide an additional function for the DOE 400, such as a function other than a specific phase delay (e.g., π phase delay) and anti-reflection functionality. In some implementations, the anti-reflection structures of the DOE 400 collectively form the DOE.

[0065] In some implementations, each layer can be associated with a specific thickness. For example, layer 1 (e.g., silicon layer 415-1) can be associated with a thickness of approximately 209 nanometers (nm); layer 2 (e.g., silicon dioxide layer 420-1) can be associated with a thickness of 162 nm; layer 3 (e.g., silicon layer 415-3) (if present) can be associated with a thickness of 238 nm; layer 4 (e.g., silicon dioxide layer 420-2) (if present) can be associated with a thickness of 254 nm; and layer 5 (e.g., silicon layer 415-2) (if present) can be associated with a thickness of 20 nm. In some implementations, DOE 400 can be associated with a specific pitch 445 (sometimes referred to as a period) dx. For example, the pitch 445 can be from approximately 1 micrometer to 1000 micrometers. In some implementations, a capping layer can be formed on the fifth layer (e.g., another silicon dioxide layer), which can improve robustness during dicing of the wafer including the substrate 405.

[0066] In some implementations, the thickness of the layers of DOE 400, the size of the spacing 445, the antireflective structure, and / or the refractive index of its layers can be selected to induce a specific phase delay (e.g., π phase delay) at a specific wavelength where the antireflective structure provides antireflective functionality. For example, a first antireflective structure may be associated with a first (effective) refractive index of 1.5, a second antireflective structure may be associated with a second (effective) refractive index of 3.5, and a set of layers between the first and second antireflective structures (e.g., layer 415-3) may be associated with a third (effective) refractive index of 3.5. Additionally or alternatively, the specific wavelength may include a wavelength range between approximately 1540 nm and 1560 nm. As indicated by reference numeral 450, a set of intensity levels (e.g., intensity levels -2, -1, 0, 1, 2, etc.) are provided by DOE 400 based on incident light directed to a first side of substrate 405.

[0067] like Figure 4B As shown, DOE 400' includes a first diffractive optical element formed on a first side of substrate 405 and a second diffractive optical element formed on a second side of substrate 405. Each diffractive optical element includes a set of silicon layers 415-1 to 415-3 and a set of silicon dioxide layers 420-1 to 420-2. As indicated by reference numerals 455-1 and 455-2, based on incident light toward DOE 400', the second diffractive optical element guides a first set of intensity levels through substrate 405 to the first diffractive optical element, thereby providing a second set of intensity levels from DOE 400'. In this way, substrate 405 maintains the alignment of the first and second diffractive optical elements, thereby reducing the difficulty of maintaining alignment compared to other techniques (such as free-space optics or the use of pick-and-place machines).

[0068] like Figure 4C As shown, the DOE 400” includes a first antireflective structure formed on the surface of a substrate 405 and a second antireflective structure formed on a portion of the surface of the first antireflective structure (e.g., no one or more layers are formed between the first and second antireflective structures). For example, the first and second antireflective structures can provide antireflective functionality for specific wavelengths (e.g., a wavelength range between 930 nm and 950 nm) and can provide specific phase delays (e.g., π phase delays) at specific wavelengths. In some implementations, the layers of the DOE 400” can be associated with specific thicknesses. For example, layer 1 can be associated with a thickness of approximately 121 nm, layer 2 can be associated with a thickness of approximately 107 nm, layer 3 can be associated with a thickness of approximately 130 nm, layer 4 can be associated with a thickness of approximately 258 nm, and so on.

[0069] Although some implementations described in this article are based on a specific number of layers, such as 4 or 5 layers, other numbers of layers are also possible, such as 6 layers (e.g., 6 alternating silicon / silicon dioxide layers), 7 layers, 10 layers, 20 layers, etc.

[0070] As mentioned above, Figures 4A-4C This is provided as an example only. Other examples are possible and may differ from those provided. Figures 4A-4C Example of the description.

[0071] Figure 5 This is a flowchart of example procedure 500 used to configure DOE. In some implementations, Figure 5 One or more processing blocks can be executed by the client device. In some implementations, Figure 5 One or more processing blocks can be executed by another device or a group of devices that are separate from or include the client device (e.g., server device). Figure 6A and 6B Is with Figure 5 The example process 500 shown is a simplified diagram of the example implementation method 600.

[0072] like Figure 5 As shown, process 500 may include determining the materials for the stack (block 505). For example, the client device may determine the materials for the stack. In some implementations, the client device may receive input identifying the materials used for the stack. For example, during the design of the DOE, the designer may select a set of coating materials based on a set of design criteria. In some implementations, this set of coating materials may include silicon, silicon hydride, silicon dioxide, tantalum pentoxide, silicon nitride, combinations thereof, etc. In some implementations, this set of design criteria may include the wavelength range of the DOE, the refractive index of the material, the transmittance of the material, etc. In some implementations, the stack may be a multi-layer stack. For example, as... Figure 6A As shown, the stack can be a five-layer stack of alternating silicon and silicon dioxide thin films disposed on a fused silica substrate, glass substrate, etc.

[0073] like Figure 5 As further shown, process 500 may include determining the reflectivity of the stacked unpatterned thin film regions (block 510). For example, the client device may determine the reflectivity of the stacked unpatterned thin film regions. In some implementations, the client device may receive input identifying the reflectivity of a first region and a second region. For example, a designer may determine the reflectivity of a first region of the stack, comprising a substrate and a first pair of alternating silicon and silicon dioxide thin film layers, such as... Figure 6A As shown by reference numeral 605 in the attached figure. This first region can be referred to as ARO. In this case, the designer can determine the reflectivity of the stacked second region, which includes a substrate, a first pair of alternating silicon and silicon dioxide thin film layers, a silicon thin film layer, and a second pair of alternating silicon and silicon dioxide thin film layers, as shown in the figure. Figure 6A As indicated by reference numeral 610 in the attached figure. This second region can be referred to as AR. π Based on AR0 and AR π As separate, unpatterned stacks, AR0 and AR can be determined using thin-film theory. π The reflectivity, transmittance, and phase delay are measured, enabling global optimization to be used with improved efficiency compared to optimization calculations using diffraction theory. This reduces the utilization of computational resources by client devices for optimizing the configuration of the DOE compared to other techniques.

[0074] like Figure 5 As further shown, process 500 may include defining a function (block 515) for minimizing the reflectivity of the stacked regions. For example, the client device may define a function for minimizing the reflectivity of the stacked regions. In some implementations, this function may be a value function, a cost function, etc. For example, the client device may receive an input of an identifier function such that optimization of the function (e.g., minimization) results in a reduction in the reflectivity of the stacked regions, with the phase delay of π maintained between AR0 and ARπ. In this way, the client device can increase the transmittance over a specific wavelength range to a threshold level, such as at least approximately 80%, approximately 90%, approximately 95%, approximately 99%, etc.

[0075] like Figure 5 As further shown, process 500 may include selecting a layer for thickness optimization (block 520). For example, the client device may select at least one layer for thickness optimization. In some implementations, the client device may receive input identifying at least one layer. For example, a designer may select an optimization layer. Figure 6AThe thickness of layer 3 shown is (e.g., the silicon layer sandwiched between matching layers 1 and 2 and matching layers 4 and 5), and the thicknesses of layers 1, 2, 4, and 5 can be specified to optimize the reflectivity of the DOE relative to the thickness of layer 3. In some implementations, the layer thickness can be determined based on a set of equations:

[0076]

[0077] k = 2π / λ0,

[0078] Where Δφ represents the selected phase delay (e.g., π), k represents a constant value (e.g., for layer 3), and h i The depth of relief in layer i, n i Let λ represent the refractive index of layer i, and λ0 represent the nominal illumination wavelength of the DOE. Thus, the client device can calculate, for example, the thickness of layer 3, to obtain a selected phase delay based on the thicknesses of the other layers of the DOE.

[0079] like Figure 5 As further shown, process 500 may include selecting a layer thickness for optimization (block 525). For example, the client device may select a layer thickness for optimization. In some implementations, the client device may randomly select the thickness. For example, the client device may use a random selection procedure to select the layer thicknesses of layers 1, 2, 4, and 5 in order to determine the layer thickness of layer 3. In some implementations, the client device may use a non-random selection procedure, such as an optimization procedure, to select the thickness.

[0080] like Figure 5 As further shown, process 500 may include applying an optimization procedure (block 530). For example, the client device may apply an optimization procedure. In some implementations, the client device may use simulated annealing to optimize the reflectivity of the DOE. For example, the client device may execute a simulated annealing procedure and a steepest descent algorithm procedure to optimize the cost function used to configure the layer thickness to optimize (e.g., minimize) the reflectivity. In some implementations, the client device may execute the optimization procedure until a threshold criterion is met (e.g., calculating threshold levels of transmittance, such as transmittance greater than 50%, transmittance greater than 80%, transmittance greater than 90%, transmittance greater than 95%, transmittance greater than 99%, transmittance greater than 99.5%, etc.).

[0081] like Figure 5 As further shown, process 500 may include configuration of the results of the analysis and optimization procedure (block 535). For example, the client device may determine the transition points of the DOE to determine the surface relief profile. Figure 6AFurthermore, as shown by reference numeral 615 in the attached figure, the optimization results can identify the optimization characteristics of the DOE. In some implementations, the client device can analyze the configurations where even-order and zero-order orders are suppressed (which may be referred to as even-order missing (EOM) configurations). For example, as... Figure 6A and 6B As shown, the client device can perform diffraction theory analysis to determine the relief profile of the DOE of the 1x4 lattice generator. In this case, the DOE includes a relief profile with a period 620 having a set of transition points 625. For example, transition point 625-1 may be located at 0 dx, 625-2 at 0.054 dx, 625-3 at 0.277 dx, and 625-4 at 0.5 dx, where dx represents the width of the period 620. In some implementations, the client device can receive information identifying the transition points based on the configuration of the lattice illuminator including the DOE. In some implementations, the client device can automatically determine the transition points based on the configuration of the lattice illuminator. See further reference. Figure 6A and 6B As shown, each transition point corresponds to the transition between the minimum and maximum relief depth, and to the transition between the minimum (0) and maximum (π) phase delay.

[0082] In some implementations, the client device can perform electromagnetic diffraction theory analysis. For example, the client device can determine the diffraction efficiencies of the transverse electrical (TE) polarization and transverse magnetic (TM) polarization of the beam. Based on the TE polarization diffraction efficiencies and the TM polarization diffraction efficiencies satisfying a first threshold (i.e., greater than the first threshold or within a threshold of continuous relief profile diffraction efficiencies, such as within 10%, within 5%, within 2%, etc.), and based on the zero-order diffraction efficiencies satisfying a second threshold (i.e., less than the second threshold, such as less than 10%, less than 5%, less than 2%, etc.), the client device can determine that the DOE configuration meets a set of design criteria.

[0083] like Figure 5 As further shown, process 500 may include providing output (block 540). For example, the client device may provide output identifying the configuration of the DOE (e.g., embossed outline) to enable the manufacture of the DOE. In some implementations, the client device may store the output identifying the configuration, provide the output identifying the configuration to the server device to trigger the manufacture of the DOE, etc.

[0084] although Figure 5 An example block of process 500 is shown, but in some implementations, it is different. Figure 5 Compared to the blocks described in the previous section, process 500 may include additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Additionally or alternatively, two or more blocks of process 500 may be executed in parallel. As described above, Figure 6A and 6B This is provided as an example only. Other examples are possible and may differ from those provided. Figure 6A and 6B Example of the description.

[0085] Figure 7 This is a flowchart of example process 700 used to manufacture DOE. Figure 8A and 8B Is with Figure 7 The example process 700 shown is a simplified diagram of the example implementation method 800.

[0086] like Figure 7 As shown, process 700 may include depositing a set of layers (block 710) on a substrate. For example, as Figure 8A As shown by reference numeral 810, multiple thin films, such as a set of silicon and silicon dioxide layers, can be deposited on a substrate, such as a glass substrate or a fused silica substrate, to deposit a first antireflective structure for a specific wavelength and a second antireflective structure for a specific wavelength. In some implementations, the set of layers may include a first pair of silicon and silicon dioxide layers, a silicon layer, and a second pair of silicon and silicon dioxide layers deposited on the substrate. In some implementations, an antireflective coating may be deposited on another surface of the substrate, such that the substrate is disposed between the antireflective coating and the alternating silicon and silicon dioxide layers. In some implementations, the antireflective structure may be deposited on a first side and a second side of the substrate. In some implementations, another set of materials may be used for at least one layer, such as a tantalum pentoxide-based material, a silicon nitride-based material, etc.

[0087] like Figure 7 As further shown, process 700 may include depositing a mask onto one of the layers in the group (block 720). For example, as Figure 8A As shown, and as indicated by reference numeral 820 in the figure, the mask layer can be deposited on the silicon layer of the second pair of silicon and silicon dioxide layers, such that the mask layer covers the silicon layer. In some implementations, the material used for the mask can be selected such that the mask is selectively correlated with a threshold or with the threshold resistivity of the silicon etching and silicon dioxide etching.

[0088] like Figure 7 As further shown, process 700 may include a patterned mask (block 730). For example, as Figure 8A As shown, and as described by reference numeral 830, the mask layer can be patterned based on the configuration of the DOE. In this case, the mask layer can be patterned such that the mask covering the portion of the DOE relative to FIG. 4 corresponds to the unetched stack 430, and the mask layer is removed such that the portion of the DOE relative to FIG. 4 corresponds to the etched stack 435. In this case, the mask pattern can be determined based on the configuration of the DOE, as described herein regarding... Figure 5 As described. For example, patterning masks based on determined transition points of the DOE.

[0089] like Figure 7 As further shown, process 700 may include etching a subset of layers based on a patterned mask to form an embossed profile (block 740). For example, as Figure 8B As shown, and indicated by reference numeral 840, a portion of a set of layers not covered by a patterned mask can be removed using silicon etching, silicon dioxide etching, etc. In this case, an embossed outline is formed within a subset of the set of layers. In some implementations, etching is performed to remove less than the entire set of layers. For example, referring to FIG4, etching is performed to remove portions of layers 3-5. In this case, the silicon dioxide (e.g., layer 2) can have an etch stop function applied to the DOE.

[0090] like Figure 7 As further shown, process 700 may include mask removal (block 750). For example, as Figure 8B As shown, and indicated by reference numeral 850, the mask can be removed. In this case, the set of layers remains on the patterned substrate to provide a π phase delay between the DOE portions of the subset of layers that have been removed and the DOE portions of the subset of layers that have not been removed.

[0091] like Figure 7 As further shown, process 700 may include performing wafer polishing based on mask removal (block 760). For example, the DOE may be tested, the DOE may be diced into multiple discrete DOEs (e.g., a wafer patterned with multiple DOEs may be diced into multiple discrete DOEs), and the DOE may be packaged for inclusion in an optical device. In some implementations, the wafer may be a 200 mm x 0.725 mm wafer.

[0092] In this way, compared to other technologies that include etching silicon dioxide wafers to create surface relief contours and coating the surface relief contours with an anti-reflective coating, providing a wafer coated with an anti-reflective film layer reduces the number of manufacturing steps. Furthermore, compared to other technologies, the reduction in the number of steps can lower costs and reduce supply chain complexity.

[0093] although Figure 7 An example block of process 700 is shown, but in some implementations, it is different. Figure 7 Compared to the blocks described above, process 700 may include additional blocks, fewer blocks, different blocks, or blocks with different arrangements. Additionally or alternatively, two or more blocks of process 700 may be executed in parallel. As described above, Figure 8A and8B This is provided as an example only. Other examples are possible and may differ from those provided. Figure 8A and 8B Example of the description.

[0094] In this way, DOEs can be designed and / or fabricated with thin-film stacks of alternating silicon layers (e.g., silicon hydride layers) and silicon dioxide layers etched into two-level relief profiles. Furthermore, the layers of the DOE can be designed to provide anti-reflection properties, integrated etch-stop properties, etc. Additionally, the design can be executed using thin-film deposition processes, which allows control of zero-order power. In some implementations, computational techniques based on non-diffraction theory can be used to design the DOE, thereby reducing processing resources required to determine the DOE design. Furthermore, by using thin-film deposition and etching techniques, the number of fabrication steps in manufacturing the DOE can be reduced, thus reducing time and cost compared to other techniques used to manufacture DOEs.

[0095] The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations are possible based on the above disclosure, or can be derived from the practice of the implementation.

[0096] Some implementations described in this article incorporate thresholds. As used in this article, a threshold can refer to a value greater than the threshold, more than the threshold, higher than the threshold, greater than or equal to the threshold, less than the threshold, less than the threshold, lower than the threshold, less than or equal to the threshold, or equal to the threshold.

[0097] It will be apparent that the systems and / or methods described herein can be implemented in various forms, including hardware, firmware, or a combination of hardware and software. The actual dedicated control hardware or software code used to implement these systems and / or methods is not a limitation on this implementation. Therefore, the operation and behavior of the systems and / or methods are described herein without reference to dedicated software code—it should be understood that software and hardware can be designed to implement the systems and / or methods based on the description herein.

[0098] Although specific combinations of features are set forth in the claims and / or disclosed in the specification, these combinations are not intended to limit the disclosure of possible implementations. In fact, many of these features may be combined in a manner not specifically set forth in the claims and / or disclosed in the specification. Although each dependent claim listed below may be directly dependent on only one claim, the disclosure of possible implementations may include: each dependent claim combined with each other claim in the claim group.

[0099] Elements, actions, or instructions used herein should not be construed as critical or necessary unless explicitly stated otherwise. Furthermore, as used herein, the articles “a” and “an” are intended to include one or more items and are interchangeable with “one or more.” Additionally, as used herein, the term “set” is intended to include one or more items (e.g., related items, unrelated items, a combination of related and unrelated items, etc.) and is interchangeable with “one or more.” The term “one” or similar language is used when only one item is intended. Furthermore, as used herein, the terms “has,” “have,” “having,” etc., are intended to be open-ended terms. Additionally, the phrase “based on” is intended to mean “at least partially based on” unless otherwise explicitly stated.

Claims

1. A method for configuring a diffractive optical element (DOE), comprising: Determine the materials to be used for the stacking of the DOE; Determine the reflectivity of the stacked unpatterned and patterned thin film regions; Define a function to minimize the reflectivity of the stacked unpatterned thin film regions and the patterned thin film regions; At least one layer of the stack is selected for thickness optimization; Select one or more layer thicknesses for the thickness optimization; Apply a thickness optimization procedure to at least one layer; Configuration for analyzing the results of the thickness optimization procedure; as well as Based at least in part on the analysis, output identifying the DOE configuration is provided. The height difference between the unpatterned thin film region and the patterned thin film region creates a specific phase delay with respect to a specific wavelength.

2. The method according to claim 1, wherein, Determining the material of the stack includes receiving input that identifies the material of the stack.

3. The method according to claim 1, wherein, Determining the reflectivity includes: Receive a first input indicating the first reflectivity of a first region identifying the unpatterned thin film region; and A second input is received, representing the second reflectivity of a second region that identifies the patterned thin film region.

4. The method according to claim 3, wherein, The first region includes a substrate and a first pair of alternating silicon and silicon dioxide thin film layers.

5. The method according to claim 4, wherein, The second region includes the substrate, the first pair of alternating silicon and silicon dioxide thin film layers, a silicon thin film layer, and a second pair of alternating silicon and silicon dioxide thin film layers.

6. The method according to claim 5, wherein, The optimization of the function results in a reduction in reflectivity while maintaining the specific phase delay between the first and second regions.

7. The method according to claim 5, wherein, The at least one layer includes the silicon thin film layer.

8. The method according to claim 1, wherein, The optimization of the function results in a reduction in reflectivity while maintaining the specific phase delay.

9. The method according to claim 8, wherein, The specific phase delay is π.

10. The method according to claim 1, wherein, Selecting the one or more layer thicknesses for thickness optimization includes at least one of the following: The one or more layer thicknesses are selected via a random procedure, or The thickness of one or more layers is selected through an optimization process.

11. The method according to claim 1, wherein, The application of the thickness optimization procedure includes: Simulated annealing and steepest descent algorithms are used to optimize the cost function and configure at least one layer thickness to minimize the reflectivity.

12. The method according to claim 1, wherein, The application of the thickness optimization procedure includes: Apply the thickness optimization procedure until the transmittance threshold level is met.

13. The method according to claim 1, wherein, The configuration for analyzing the results of the thickness optimization procedure includes: The transition points of the DOE are determined to define the surface relief profile of the DOE. Each of the transition points corresponds to a transition between the minimum and maximum relief depth.

14. The method according to claim 1, wherein, The configuration for analyzing the results of the thickness optimization procedure includes: The results of the thickness optimization procedure are analyzed, and the even-order and zero-order orders are suppressed.

15. The method according to claim 1, wherein, The configuration for analyzing the results of the thickness optimization procedure includes: Perform electromagnetic diffraction theoretical analysis to determine at least one of the following: The transverse electrical (TE) polarization portion of the beam associated with the DOE, or The diffraction efficiency of the transverse magnetic (TM) polarization portion of the beam.

16. An apparatus for configuring a diffractive optical element (DOE), comprising: One or more memory units; as well as One or more processors, said one or more processors being coupled to said one or more memories, said one or more processors being configured to: Determine the materials to be used for the stacking of the DOE; Determine the reflectivity of the stacked unpatterned and patterned thin film regions; Define a function to minimize the reflectivity of the stacked unpatterned thin film regions and the patterned thin film regions; Select at least one layer of the stack for thickness optimization; Select one or more layer thicknesses for the thickness optimization; Apply a thickness optimization procedure to at least one layer; Configuration for analyzing the results of the thickness optimization procedure; as well as Based at least in part on the analysis, output identifying the DOE configuration is provided. The height difference between the unpatterned thin film region and the patterned thin film region creates a specific phase delay with respect to a specific wavelength.

17. The device according to claim 16, wherein, The one or more processors are configured to determine the material in the stack. Receive an input identifying the material in the stack.

18. The device according to claim 16, wherein, The one or more processors are used to determine the reflectivity, and the one or more processors are configured to: Receive a first input indicating the first reflectance of a first region that identifies the unpatterned thin film region; as well as A second input is received, representing the second reflectivity of a second region that identifies the patterned thin film region.

19. The device according to claim 18, wherein, The first region includes a substrate and a first pair of alternating silicon and silicon dioxide thin film layers.

20. The device according to claim 19, wherein, The second region includes the substrate, the first pair of alternating silicon and silicon dioxide thin film layers, a silicon thin film layer, and a second pair of alternating silicon and silicon dioxide thin film layers.

21. The device according to claim 20, wherein, The optimization of the function results in a reduction in reflectivity while maintaining the specific phase delay between the first and second regions.

22. The device according to claim 20, wherein, The at least one layer includes the silicon thin film layer.

23. The device according to claim 16, wherein, The optimization of the function results in a reduction in reflectivity while maintaining the specific phase delay.

24. The device according to claim 21, wherein, The specific phase delay is π.

25. The device according to claim 16, wherein, The one or more processors are configured to select the one or more layer thicknesses for thickness optimization. The one or more layer thicknesses are selected via a random procedure, or The thickness of one or more layers is selected through an optimization process.

26. The device according to claim 16, wherein, The one or more processors are used to apply the thickness optimization procedure, and the one or more processors are configured to: Simulated annealing and steepest descent algorithms are used to optimize the cost function and configure at least one layer thickness to minimize the reflectivity.

27. The device according to claim 16, wherein, The one or more processors are used to apply the thickness optimization procedure, and the one or more processors are configured to: Apply the thickness optimization procedure until the transmittance threshold level is met.

28. The device according to claim 16, wherein, The configuration of the one or more processors for analyzing the results of the thickness optimization procedure, wherein the one or more processors are configured to: The transition points of the DOE are determined to define the surface relief profile of the DOE. Wherein, each of the transition points corresponds to: The transition between the minimum and maximum relief depth.

29. The device according to claim 16, wherein, The configuration of the one or more processors for analyzing the results of the thickness optimization procedure, wherein the one or more processors are configured to: The results of the thickness optimization procedure are analyzed, and the even-order and zero-order orders are suppressed.

30. The device according to claim 16, wherein, The configuration of the one or more processors for analyzing the results of the thickness optimization procedure, wherein the one or more processors are configured to: Perform electromagnetic diffraction theoretical analysis to determine at least one of the following: The transverse electrical (TE) polarization portion of the beam associated with the DOE, or The diffraction efficiency of the transverse magnetic (TM) polarization portion of the beam.

Images