Programming command processing method and apparatus

Abstract

The application provides a programming command processing method and device. The provided method for processing a programming command comprises the following steps: sending an address to an NVM chip and moving data in a memory to the NVM chip; releasing the data in the memory before the NVM chip indicates that the data is successfully recorded in the address; and querying the state of the NVM chip to obtain a processing result of the programming command, and sending part of the programming command to the NVM chip to instruct the NVM chip to program the data in the page cache in response to the state of the NVM chip indicating that the processing of the programming command fails.

Description

Technical Field

[0001] This application relates to storage technology, and more specifically, to programming commands for processing NVM chips. Background Technology

[0002] Figure 1 A block diagram of a solid-state storage device (SSD) is shown. The SSD 102 is coupled to a host computer to provide storage capabilities. The host computer and the SSD 102 can be coupled in various ways, including but not limited to connections via SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIe (Peripheral Component Interconnect Express), NVMe (NVM Express), Ethernet, Fibre Channel, and wireless communication networks. The host computer can be an information processing device capable of communicating with the storage device via the above methods, such as a personal computer, tablet computer, server, laptop computer, network switch, router, cellular phone, or personal digital assistant. Storage device 102 includes interface 103, control unit 104, one or more NVM chips 105, and DRAM (Dynamic Random Access Memory) 110.

[0003] NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic Random Access Memory), and RRAM (Resistive Random Access Memory) are common types of NVM.

[0004] Interface 103 is compatible with exchanging data with the host via methods such as SATA, IDE, USB, PCIe, NVMe, SAS, Ethernet, and Fibre Channel.

[0005] The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110. It is also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, etc. The control unit 104 can be implemented in various ways, including software, hardware, firmware, or a combination thereof. For example, the control unit 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application Specific Integrated Circuit), or a combination thereof. The control unit 104 may also include a processor or controller, in which software executes to manipulate the hardware of the control unit 104 to process I / O (Input / Output) commands. The control unit 104 can also be coupled to the DRAM 110 and can access the data in the DRAM 110. FTL tables and / or cached I / O command data can be stored in the DRAM.

[0006] The control unit 104 includes a flash interface controller (or media interface controller, flash channel controller), which is coupled to the NVM chip 105 and issues commands to the NVM chip 105 in accordance with the interface protocol of the NVM chip 105 to operate the NVM chip 105, and receives the command execution results output from the NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

[0007] A memory target is one or more logic units (LUNs) within a NAND flash memory package that share a common CE (Chip Enable) signal. A NAND flash memory package may include one or more dies. Typically, a logic unit corresponds to a single die. A logic unit may include multiple planes. Multiple planes within a logic unit can be accessed in parallel, while multiple logic units within a NAND flash memory chip can execute commands and report status independently of each other.

[0008] Data is typically stored and retrieved in pages on storage media, while data is erased in blocks. A block (also called a physical block) contains multiple pages. Pages on a storage medium (called physical pages) have a fixed size, such as 17664 bytes. Physical pages can also have other sizes.

[0009] In solid-state storage devices, the FTL (Flash Translation Layer) is used to maintain the mapping information from logical addresses to physical addresses. Logical addresses constitute the storage space of the solid-state storage device as perceived by upper-layer software such as the operating system. Physical addresses are the addresses used to access the physical storage units of the solid-state storage device. In related technologies, intermediate address formats can also be used for address mapping. For example, a logical address can be mapped to an intermediate address, and then the intermediate address can be further mapped to a physical address.

[0010] The table structure that stores the mapping information from logical addresses to physical addresses is called the FTL table. The FTL table is an important metadata in solid-state storage devices. Typically, the data items in the FTL table record the address mapping relationships in the solid-state storage device at the data page level.

[0011] The FTL table consists of multiple FTL table entries (or entries). In one case, each FTL table entry records the mapping between a logical page address and a physical page. In another case, each FTL table entry records the mapping between multiple consecutive logical page addresses and multiple consecutive physical pages. In yet another case, each FTL table entry records the mapping between logical block addresses and physical block addresses. And still another case, the FTL table records the mapping between logical block addresses and physical block addresses, and / or the mapping between logical page addresses and physical page addresses.

[0012] A large block comprises physical blocks from multiple logical units (LUNs), also known as groups of logical units. Each logical unit can provide a physical block for a large block. For example, in... Figure 2 The schematic diagram of the large blocks shown depicts large blocks constructed on every 16 logical units (LUNs). Each large block comprises 16 physical blocks, each originating from one of the 16 logical units (LUNs). Figure 2 In the example, block 0 comprises physical blocks 0 from each of the 16 logical units (LUNs), while block 1 comprises physical blocks 1 from each logical unit (LUN). Blocks can also be constructed in a variety of other ways.

[0013] For example, page stripes are constructed within a large block, where physical pages with the same physical address within each logical unit (LUN) constitute a "page stripe". Figure 2 In this context, physical pages P0-0, P0-1, ..., and P0-x constitute page stripe 0. Physical pages P0-0, P0-1, ..., P0-14 are used to store user data, while physical pages P0-x are used to store checksum data calculated based on all user data within the stripe. Similarly, Figure 2In this example, physical pages P2-0, P2-1, ..., and P2-x constitute page stripe 2. The physical page used to store verification data can be located anywhere within the page stripe. As another example, in Chinese patent application number 201710752321.0... Figure 3A and its instruction manual Figure 3A The relevant description provides another way to construct large blocks.

[0014] Figure 3A This is a schematic diagram of programming commands for a prior art NVM chip. Control components (e.g., Figure 1 The control unit 104 sends programming commands, including instructions, addresses, and data, to the NVM chip via pins, writing data into the NVM chip. Figure 3 shows the programming commands, which consist of multiple clock cycles. In Figure 3, the cycle time on the left comes first, and the cycle time on the right comes second. Within each cycle, a set of signals is transmitted to the NVM chip via the DQ pin. The "Cycle Type" row in Figure 3 shows the type (or meaning) of the signal transmitted in each cycle, and the "DQ" row shows the value of the signal transmitted in each cycle.

[0015] Taking a programming command as an example, the programming command consists of three parts: address, data, and status. In the address part of the programming command, the "80h" pin on the DQ pin serves as an indicator, followed by multiple (e.g., 5) cycles of address indication (by C1, C2, R1, R2, and R3). These addresses indicate the address of the NVM chip to be written to. Next, the data to be written (represented by D0, D1, ..., Dn) is transmitted to the NVM chip, and the signal "10h" indicates the end of data transmission. After receiving the "10h" command, the NVM chip begins executing the programming operation. The control unit 104 then queries the status of the NVM chip by issuing a "70h" command to the NVM chip, and the NVM chip returns a status to the control unit. The status indicates whether the programming command has been successfully executed.

[0016] Figure 3B This diagram illustrates the execution of programming commands by the control unit. The control unit is coupled to one or more NVM chips via flash memory channels. The NVM chips include page caches for caching data to be programmed or read from the NVM chips. The control unit also includes memory (SRAM, for example). The memory stores the data to be written to the NVM chips. Figure 3B(The data within the dashed box in SRAM is used to indicate this). To perform a programming operation, the control unit sends the address portion of the programming command to the NVM chip based on the physical address to be written to. Next, the control unit transfers data from memory to the NVM chip as the data portion of the programming command. In response to the completion of the data transfer, the data is stored in the NVM chip's page cache. The control unit also sends a command to the NVM chip to check if the programming operation is complete. If the status provided by the NVM chip indicates that the programming operation is not yet complete, the control unit checks the NVM chip's status again later until it confirms that the programming operation is complete and releases the data from memory. If the status indicates that the programming operation failed, the control unit re-issues the programming command to the NVM chip using the data in memory. Generally, after the NVM chip receives the command indicating that the data transfer is complete and the programming operation begins ("10h"), it takes a certain period of time (denoted as "t") for the programming operation to be processed and completed.

[0017] Optionally, the control unit is coupled to multiple NVM chips, each of which can process programming commands in parallel. Thus, the control unit can simultaneously issue programming commands to each of the multiple LUNs. Summary of the Invention

[0018] To improve the performance of solid-state storage devices, the control unit processes multiple programming commands simultaneously. The data to be written to the NVM chip for each programming command is stored in memory (e.g., ...). Figure 3B The data to be written to the NVM chip is stored in the SRAM. The programming command takes a relatively long time (e.g., 1ms) from initiation to the completion status of the programming operation. During this time, the data is stored in the memory. This requires a large enough memory capacity to accommodate multiple simultaneous programming commands, and the memory utilization is low, as the corresponding storage space is only released after the programming operation is completed.

[0019] According to a first aspect of this application, a method for processing a first programming command according to the first aspect of this application is provided, comprising: sending an address to an NVM chip, moving data from a memory to the NVM chip; releasing the data from the memory before the NVM chip indicates that the data has been successfully recorded at the address; and querying the status of the NVM chip to obtain the processing result of the programming command.

[0020] According to the method of processing programming commands according to the first aspect of this application, a method of processing programming commands according to the first aspect of this application is provided, further comprising: in response to moving data in memory to an NVM chip, backing up the data in a second memory; and in response to the status indication of the NVM chip indicating that the programming command processing has failed, generating a second address, sending the second address to the NVM chip, and sending the backed-up data to the NVM chip.

[0021] According to the method for processing programming commands according to the first aspect of this application, a method for processing programming commands according to the first aspect of this application is provided, further comprising: in response to a status indication of the NVM chip indicating that the programming command processing has failed, sending a portion of the programming command to the NVM chip to instruct the NVM chip to program the data in the page cache.

[0022] According to the third method of processing programming commands according to the first aspect of this application, a fourth method of processing programming commands according to the first aspect of this application is provided, wherein some programming commands include a second address but do not include the data to be programmed.

[0023] A method for processing programming commands according to a third method of the first aspect of this application is provided, wherein a portion of the programming commands instructs the NVM chip to generate a second address based on the address.

[0024] According to one of the methods for processing programming commands according to the third to fifth aspects of the first aspect of this application, a sixth method for processing programming commands according to the first aspect of this application is provided, wherein some programming commands further indicate the address of the data to be programmed in the page cache.

[0025] According to the method for processing a first programming command according to the first aspect of this application, a method for processing a seventh programming command according to the first aspect of this application is provided, further comprising: in response to a status indication of an NVM chip indicating a programming command processing failure, reading the data from the page cache of the NVM chip; sending a second address to the NVM chip, sending the read data to the NVM chip; and querying the status of the NVM chip again to obtain the processing result of the programming operation of recording the data at the second address.

[0026] According to the second method of processing programming commands according to the first aspect of this application, an eighth method of processing programming commands according to the first aspect of this application is provided, further comprising: in response to a status indication of the NVM chip indicating a programming command processing failure, also moving backed-up data to the memory, and moving backed-up data from the memory to the NVM chip.

[0027] A method for processing programming commands according to the second processing programming command of the first aspect of this application is provided, wherein the backed-up data is moved from the second memory to the NVM chip.

[0028] According to the third, eighth, or ninth method of processing programming commands according to the first aspect of this application, a tenth method of processing programming commands according to the first aspect of this application is provided, which further includes: querying the state of the NVM chip again to obtain the processing result of the programming operation of recording the data at the second address.

[0029] According to the first, seventh, or tenth method of processing programming commands according to the first aspect of this application, an eleventh method of processing programming commands according to the first aspect of this application is provided, further comprising: in response to a status indication of an NVM chip indicating that the programming command processing has failed, reading redundant data from the page strip to which the programming address of the failed programming command belongs, and restoring the data; sending a second address to the NVM chip, and sending the restored data to the NVM chip.

[0030] According to the eleventh method for processing programming commands according to the first aspect of this application, a twelfth method for processing programming commands according to the first aspect of this application is provided, further comprising: querying the state of the NVM chip again to obtain the processing result of the programming operation of recording the data at a second address.

[0031] According to a second aspect of this application, a method for processing a first programming command according to the second aspect of this application is provided, comprising: sending an address to an NVM chip; moving data from a memory to the NVM chip; allowing other data to be written into the memory space storing the data before the NVM chip indicates that the data has been successfully recorded at the address; and querying the status of the NVM chip to obtain the processing result of the programming command.

[0032] According to a third aspect of this application, a solid-state storage device according to the third aspect of this application is provided, including a control unit and an NVM chip, wherein the control unit performs any one of the methods according to the first and second aspects of this application.

[0033] According to a fourth aspect of this application, a control component according to the fourth aspect of this application is provided for performing any of the methods in the first and second aspects of this application. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings.

[0035] Figure 1 This is a block diagram of a solid-state storage device in related technologies;

[0036] Figure 2 These are large schematic diagrams of related technologies;

[0037] Figure 3A This is a schematic diagram of programming commands for existing NVM chips;

[0038] Figure 3B A schematic diagram illustrating the control unit executing programmed commands is shown;

[0039] Figure 4A A schematic diagram illustrating the processing of programming commands according to an embodiment of this application is shown;

[0040] Figure 4B Showing Figure 4A In one embodiment, a flowchart for processing programming commands is provided.

[0041] Figure 5A This is a schematic diagram of programming commands according to yet another embodiment of this application;

[0042] Figure 5B This is a flowchart of processing programming commands according to yet another embodiment of this application;

[0043] Figure 6A This is a schematic diagram of a control component executing programming commands according to another embodiment of this application;

[0044] Figure 6B Showing Figure 6A In the embodiments, a flowchart for processing programming commands; and

[0045] Figure 7 A flowchart illustrating the processing of programming commands according to yet another embodiment of this application is shown. Detailed Implementation

[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0047] Figure 4A A schematic diagram illustrating the processing of programming commands according to an embodiment of this application is shown.

[0048] The control unit is coupled to multiple NVM chips. The control unit also includes memory (e.g., SRAM). The memory stores data to be programmed into the NVM chips. The control unit issues programming commands to the NVM chips and transfers data from the memory to the NVM chips. The NVM chips receive the data and store it in their page cache. In response to recognizing the completion of the data transfer and being instructed to begin programming (e.g., receiving a "10h" command), the NVM chips write the data from the page cache to the physical address provided by the control unit.

[0049] According to this application Figure 4AIn this embodiment, the control unit, upon transmitting the data to be programmed to the NVM chip during a programming command, releases the memory space previously occupied by the transmitted data. This frees up the memory space to be allocated for storing data for other programming commands, or other data. Consequently, memory utilization is improved, and the time each programming command occupies memory is significantly reduced.

[0050] If the control unit detects that the NVM chip has successfully completed the programming operation, it can issue other operation commands to the NVM chip. If the control unit detects that the NVM chip has failed to complete the programming operation, it reallocates storage space in the memory. It then issues a read page cache command or a read command to the NVM chip to read the data from the NVM chip's page cache and store it in the allocated storage space. It also issues another programming command, indicating the new physical address to which the programming command should be written, moving the data from the newly allocated storage space to the NVM chip's page cache, and instructing the NVM chip to begin the programming operation (e.g., via the "10h" command). The control unit also checks the execution status of the NVM chip's programming operation until it confirms that the programming operation has been successfully completed.

[0051] Figure 4B Showing Figure 4A In one embodiment, a flowchart for processing programming commands is provided.

[0052] To execute programming commands, the control unit sends programming commands to the NVM chip. The control unit generates a physical address for the data to be programmed and sends this physical address to the NVM chip in the programming command. The control unit also sends the memory (e.g., ...) Figure 4A The data to be programmed in the SRAM is transferred to the NVM chip (410) as part of the programming command. In response to the data to be programmed being transferred to the NVM chip, the control unit releases the memory space occupied by this data (420), so that this memory space can be allocated to other programming command data. The control unit queries the NVM chip for the execution result of the programming operation corresponding to the programming command (430).

[0053] If the programming operation is successful, the processing of the current programming command is complete, and the control unit can continue to process other programming commands (returning to step 410). If the current programming command processing fails, the control unit reallocates storage space in the memory (450) and issues a read command or a page cache read command to the NVM chip to read the data to be programmed from the NVM chip's page cache, and stores the read data in the newly allocated storage space in the memory (460). Then, returning to step 410, the control unit regenerates the programming command and sends the data from the newly allocated storage space in the memory to the NVM chip via the new programming command. The control unit also provides a new physical address to the NVM chip in the new programming command to instruct the NVM chip to write the data to be programmed to the new physical address. Optionally, if the programming operation corresponding to the new programming command still fails, steps 450 and 460 are repeated, and a new programming command is initiated via step 410.

[0054] Optionally, the memory is located outside the control unit but coupled to it. For example, the memory is DRAM and has a higher... Figure 4A The SRAM in it has a larger capacity.

[0055] Figure 5A This is a schematic diagram of programming commands according to yet another embodiment of this application.

[0056] according to Figure 5A The programming commands in the embodiment (referred to as partial programming commands for clarity) are the same as... Figure 3B Compared to traditional programming commands, the data portion has been removed. Some programming commands now include an address portion, indicated by the signal "80h" and subsequent addresses (C1, C2, R1, R2, and R3). The address portion indicates the physical address of the NVM chip, where the data to be programmed is written. In response to receiving the address portion of the programming command, the NVM chip records the physical address.

[0057] Next, the control unit transmits the programming command "10h" to the NVM chip without transmitting the data to be programmed. Command "10h" instructs the NVM chip to begin programming, and that the data to be programmed is data in the NVM chip's page cache. It is understood that command "10h" is merely an example; commands with other values ​​can be used to instruct the NVM chip to begin programming, and that the data to be programmed is located in the page cache. In response to receiving command "10h," the NVM chip begins programming, writing the data from the page cache to the physical address of the previously recorded programming command. The NVM chip also maintains the execution status of the programming operation to indicate whether the programming operation is in progress, successful, or failed.

[0058] After a period of time, the control unit sends a command (indicated by "70h") to the NVM chip to query the status of the NVM chip and obtains the execution status of the programming operation from the obtained status.

[0059] Optionally, some programming commands may include an instruction to use page cached data as the data to be programmed before the "10h" command. For example, consecutive commands "11h" and "10h" may be used to instruct the use of page cached data as the data to be programmed. Alternatively, a separate command "12h," distinct from the programming commands, may be used to instruct the use of page cached data as the data to be programmed.

[0060] In an optional implementation, the NVM chip also provides a page cache release command. The control unit issues a page cache release command to the NVM chip to indicate that the data in its page cache can be discarded (e.g., entering a low-power sleep mode). The data in the page cache is maintained until the NVM chip receives the page cache data.

[0061] In the still optional implementation, the address portion of the programming command is simplified. Figure 5A In the programming command, the address portion includes a physical address of 5 cycles (e.g., 40 bits). In an optional implementation, the programming command instructs the NVM chip to generate a new physical address based on the physical address of the previous command. For example, the page address of the new physical address is obtained by incrementing (e.g., adding 1) the page address of the previous command. This reduces the clock cycles required to transmit the programming command and lowers the processing latency of the programming command.

[0062] In yet another alternative implementation, the NVM chip's page cache has a large size, for example, capable of accommodating multiple physical pages. Partial programming commands indicate the storage address of the data to be programmed in the page cache, causing the NVM chip to record a portion of the data from the page cache into the physical address through a programming operation. Optionally, the programming commands also indicate to the NVM chip the address of the page cache used to store the data to be programmed.

[0063] Figure 5B This is a flowchart of processing programming commands according to yet another embodiment of this application.

[0064] To execute programming commands, the control unit sends programming commands to the NVM chip. The control unit generates a physical address for the data to be programmed and sends this physical address to the NVM chip in the programming command. The control unit also moves the data to be programmed from memory to the NVM chip (510) as part of the programming command. In response to the data being moved to the NVM chip, the control unit releases the memory space occupied by this data (520), making this memory space available for other programming command data. The control unit queries the NVM chip for the execution result of the programming operation corresponding to the programming command (530).

[0065] If the programming operation is successful, the processing of the current programming command is complete, and the control unit can continue to process other programming commands (return to step 510). If the current programming command is found to have failed, the control unit sends a request to the NVM chip based on... Figure 5A The partial programming command (550) is shown. The partial programming command instructs the NVM chip to program the data in the page cache, recording the data in the page cache into the new physical address of the NVM chip indicated by the partial programming command. Optionally, the control unit generates a new physical address for the partial programming command and sends it to the NVM chip. Still optionally, the partial programming command instructs the NVM chip to generate a new physical address based on the physical address of a previous programming command; for example, the page address of the new physical address is obtained by incrementing (e.g., adding 1) the page address of the previous command.

[0066] In response to receiving a partial programming command, the NVM chip initiates a programming operation on the data in the page cache to write it to the new physical address indicated by the partial programming command. In response to issuing the partial programming command, the control unit queries the NVM chip for the execution result of the programming command. If the partial programming command fails again, the control unit can issue another partial programming command to the NVM chip until the NVM chip indicates that the partial programming command was executed successfully.

[0067] Figure 6A This is a schematic diagram of a control component executing programming commands according to another embodiment of this application.

[0068] The control unit is coupled to multiple NVM chips. The control unit includes memory (e.g., SRAM). The control unit is also coupled to external DRAM. The external DRAM may have a larger capacity or higher storage density than the SRAM memory.

[0069] The memory stores the data to be programmed into the NVM chip. The control unit issues a programming command to the NVM chip and transfers the data from the memory to the NVM chip. In response to recognizing the completion of the data transfer and being instructed to begin the programming operation (e.g., receiving a "10h" command), the NVM chip writes the data in the page cache to the physical address provided by the control unit.

[0070] According to this application Figure 6A In this embodiment, as the data to be programmed is transferred to the NVM chip, the control unit also transfers the data to be transferred to the DRAM and releases the memory space occupied by the transferred data. This memory space can then be allocated to store data for other programming commands, or other data. The data in the DRAM serves as backup data for use in case the NVM chip fails. Thus, memory utilization is improved, and the time each programming command occupies memory is significantly reduced.

[0071] If the control unit detects that the NVM chip has successfully completed the programming operation, it can issue other operation commands to the NVM chip. If the control unit detects that the NVM chip has failed to complete the programming operation, it reallocates storage space in the memory and moves the data to be programmed from DRAM to the allocated storage space in the memory. It then issues another programming command, indicating the new physical address to be written to the NVM chip, moves the data from the newly allocated storage space to the NVM chip, and instructs the NVM chip to begin the programming operation (e.g., via the "10h" command). The control unit also checks the execution status of the NVM chip's programming operation until it confirms that the programming operation has been successfully completed.

[0072] Optionally, if the control unit detects that the NVM chip has failed to perform a programming operation, it does not need to reallocate storage space in the memory. Instead, during the process of issuing a programming command to the NVM chip again, the data to be programmed stored in the DRAM is moved to the NVM chip. This eliminates the need to move data from the DRAM to the SRAM memory.

[0073] Figure 6B Showing Figure 6A In one embodiment, a flowchart for processing programming commands is provided.

[0074] To execute programming commands, the control unit sends programming commands to the NVM chip. The control unit generates a physical address for the data to be programmed and sends this physical address to the NVM chip in the programming command. The control unit also sends the memory (e.g., ...) Figure 6A The data to be programmed in the SRAM (Simplified RAM) is moved to the NVM chip as part of the programming commands, and the data to be programmed in the control unit is moved to external memory (e.g., SRAM). Figure 6A The DRAM (610) is used as backup data. In response to the data to be programmed being moved to the NVM chip, the control unit releases the memory space occupied by this data (620), so that this memory space can be allocated to other programming command data. The control unit queries the NVM chip for the execution result of the programming operation corresponding to the programming command (630).

[0075] If the programming operation is successful, the processing of the current programming command is complete, and the control unit can continue to process other programming commands (return to step 610). If the current programming command processing fails, the control unit sends a programming command to the NVM chip again and transmits the backup data in the external memory as the data to be programmed to the NVM chip (650). Optionally, the backup data in the external memory is directly transmitted to the NVM chip. As another implementation, the backup data in the external memory is first moved by the control unit to the SRAM, and then moved from the SRAM to the NVM chip. Then, return to step 630 to check the execution result of the programming operation. If the programming operation still fails, repeat steps 650 and 630.

[0076] Figure 7 A flowchart illustrating the processing of programming commands according to another embodiment of this application is shown, in order to further reduce the memory usage in processing programming commands.

[0077] To execute programming commands, the control unit sends programming commands to the NVM chip. The control unit generates a physical address for the data to be programmed and sends this physical address to the NVM chip in the programming command. The control unit also sends the memory (e.g., ...) Figure 6A The data to be programmed in the SRAM (Simplified RAM) is moved to the NVM chip (710) as part of the programming commands. In response to the data being moved to the NVM chip, the control unit releases the memory space occupied by this data (720), so that this memory space can be allocated to other programming command data. Figure 7 In one embodiment, after the data to be programmed into the NVM chip is transmitted to the NVM chip, the control unit releases the storage space occupied by the data, excluding backup data.

[0078] The control unit queries the execution result of the programming operation corresponding to the programming command indicated by the NVM chip (730).

[0079] If the programming operation is executed successfully, the processing of the current programming command is complete, and the control unit can continue to process other programming commands (return to step 710). If it is found that the processing of the current programming command has failed, the control unit retrieves the data from the page strip containing the physical address of the programming command (see also...). Figure 2 The control unit reads data from the page strip to restore the data to be written in the current programming command. It also moves the data restored from the page strip to the NVM chip (750) in the newly generated programming command. Then, it returns to step 730 to query the execution result of the programming operation. If the programming operation still fails, steps 750 and 730 are repeated.

[0080] According to embodiments of this application, a program stored on a readable medium is also provided, which, when run by the controller of a solid-state storage device, causes the solid-state storage device to execute any of the processing methods provided in embodiments of this application.

[0081] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application. Clearly, those skilled in the art can make various alterations and variations to this application without departing from its spirit and scope. Thus, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for a control unit of a solid-state storage device to process programming commands to be sent to an NVM chip, the control unit including an SRAM, the control unit being coupled to a plurality of NVM chips and a DRAM, the DRAM being external to the NVM chips, wherein... The NVM chip includes a page cache, characterized in that the method includes: The address is sent to the NVM chip, and the data in the SRAM is moved to the NVM chip; wherein, the NVM chip receives the data and stores it in the page cache; in response to recognizing that the data transfer is complete and indicating the start of the programming operation, the NVM chip writes the data in the page cache to the address provided by the control unit; In response to moving data from the SRAM to the NVM chip, the data is moved to the DRAM to back up the data in the DRAM, and the data in the SRAM is released; as well as Query the status of the NVM chip to obtain the processing results of the programming commands; In response to the status indication of the NVM chip indicating that the programming command processing has failed, there is no need to reallocate storage space in the SRAM; and a second address is generated and sent to the NVM chip to send the programming command to the NVM chip again, and the backup data in the DRAM is directly moved to the NVM chip.

2. The method according to claim 1, wherein, The programming command instructs the NVM chip to generate a second address based on the given address.

3. The method according to claim 2, wherein, The second address is obtained by incrementing the address.

4. The method according to any one of claims 1-3, further comprising: The status of the NVM chip is queried again to obtain the processing result of the programming operation that records the data at the second address.

5. The method according to any one of claims 1-3, further comprising: In response to receiving a page cache release command, release the data cached in the page cache.

6. A method for a control unit of a solid-state storage device to process programming commands to be sent to an NVM chip, the control unit including an SRAM, the control unit being coupled to a plurality of NVM chips and a DRAM, the DRAM being external to the NVM chips, wherein... The NVM chip includes a page cache, characterized in that the method includes: The address is sent to the NVM chip, and the data in the SRAM is moved to the NVM chip; wherein, the NVM chip receives the data and stores it in the page cache; in response to recognizing that the data transfer is complete and indicating the start of the programming operation, the NVM chip writes the data in the page cache to the address provided by the control unit; In response to the data transfer from the SRAM to the NVM chip, the data is transferred to the DRAM to back up the data in the DRAM; Before the NVM chip indicates that the data has been successfully recorded at the address, the memory space in the SRAM storing the data can be written with other data; and Query the status of the NVM chip to obtain the processing results of the programming commands; In response to the status indication of the NVM chip indicating that the programming command processing has failed, there is no need to reallocate storage space in the SRAM; and a second address is generated and sent to the NVM chip to send the programming command to the NVM chip again, and the backup data in the DRAM is directly moved to the NVM chip.

7. A control component for performing the method according to any one of claims 1-6.

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