Task scheduling circuit, method, electronic device and computer readable storage medium

Abstract

Embodiments of the present disclosure disclose a task scheduling circuit, a method, an electronic device and a computer readable storage medium. The task scheduling circuit comprises a core resource storage circuit, a task package scheduling circuit and a control circuit. The core resource storage circuit is configured to store state information and computing power level of each processing core. The task package scheduling circuit is configured to obtain a task package of a task to be executed, the task package comprising at least one task instruction of the same task and computing power requirement of the task package, confirm an idle processing core from the core resource storage circuit according to the computing power level and the computing power requirement, and send the task package to the idle processing core. The control circuit is configured to receive state information of the idle processing core and instruct the task package scheduling circuit to work according to the state information. The task scheduling circuit schedules the task package according to the state information and the computing power level of the processing core, thereby solving the technical problem of low scheduling efficiency in the prior art.

Description

Technical Field

[0001] This disclosure relates to the field of processors, and more particularly to a task scheduling circuit, method, electronic device, and computer-readable storage medium. Background Technology

[0002] With the development of science and technology, human society is rapidly entering the intelligent era. A key characteristic of the intelligent era is the increasing variety and volume of data people acquire, coupled with ever-growing demands for faster data processing. Chips are the cornerstone of task scheduling, fundamentally determining our data processing capabilities. From an application perspective, chips mainly follow two paths: one is the general-purpose chip path, such as CPUs (Central Processing Units), which offer great flexibility but have relatively low effective computing power when processing algorithms in specific domains; the other is the dedicated chip path, such as TPUs (Tensor Processing Units), which can exert high effective computing power in certain specific domains, but their processing capabilities are relatively poor or even incapable of handling more general and flexible domains. Because the data in the intelligent era is diverse in type and enormous in quantity, chips are required to possess both extremely high flexibility to handle different and rapidly evolving algorithms in various domains, and extremely strong processing capabilities to quickly process massive and rapidly increasing amounts of data.

[0003] In neural network computing, multi-core or many-core chips are frequently used. In this multi-core (many-core) architecture, each core has a certain degree of independent processing capability and a relatively large internal memory space to store its own program, data, and weights.

[0004] Ensuring that numerous cores can efficiently utilize their computing power is crucial to the overall performance of a chip. The computing power of each core depends on various factors, such as task scheduling and allocation, chip architecture, core structure, and core circuitry. Among these, task scheduling and allocation is a critical factor. If tasks are scheduled and allocated reasonably, the effective computing power of each core can be fully utilized; otherwise, the effective computing power of each core will be reduced.

[0005] The following schemes are generally used in existing technologies to handle the scheduling of kernel tasks:

[0006] like Figure 1The diagram illustrates a task scheduling scheme using a scheduler. In this scheme, the scheduler receives instructions from the instruction source and then transmits these instructions to each processing core according to a certain strategy, such as sequence. Each processing core executes the same instructions on different data. Each processing core can have a relatively simple structure, such as SIMD (Single Instruction Multiple Data), which shares control circuitry and registers, or a more complex structure with some autonomy, such as SIMT (Single Instruction Multiple Threads), which has independent control circuitry and registers. However, this scheme is generally used for instruction-level scheduling, which can only schedule one or a few instructions at a time. When large tasks need to be completed, frequent scheduling is required, reducing scheduling efficiency. Furthermore, this scheme is generally suitable for single-task scenarios; when executing multiple tasks, each core needs to reuse the scheduler, which also reduces scheduling efficiency. Summary of the Invention

[0007] This summary section is provided to briefly introduce the concepts, which will be described in detail in the detailed description section below. This summary section is not intended to identify key or essential features of the claimed technical solution, nor is it intended to limit the scope of the claimed technical solution.

[0008] To address the technical problems of inflexible task scheduling and complex control in existing technologies for processing kernels, this disclosure proposes the following technical solution:

[0009] In a first aspect, embodiments of this disclosure provide a task scheduling circuit, including:

[0010] Nuclear resource storage circuitry, task packet scheduling circuitry, and control circuitry; among which,

[0011] The core resource storage circuit is used to store the status information and computing power level of each processing core;

[0012] The task package scheduling circuit is used to receive a task package of a task to be executed, wherein the task package includes at least one task instruction for the same task and the computing power requirement of the task package; to identify an idle processing core from the core resource storage circuit according to the computing power level and the computing power requirement; and to send the task package to the idle processing core.

[0013] A control circuit is used to receive the status information of the idle processing core and instruct the task package scheduling circuit to work according to the status information.

[0014] Furthermore, the core resource storage circuit is used to store the status and computing power level of each processing core, including:

[0015] The nuclear resource storage circuit is used to store a nuclear resource table and the computing power level corresponding to the nuclear resource table. The nuclear resource table includes a processing core identifier and a processing core status bit corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.

[0016] Furthermore, the core resource storage circuit is used to store a computing power index table and multiple core resource tables, wherein processing cores belonging to different core resource tables have different computing power levels, and processing cores belonging to the same core resource table have the same computing power level, wherein the same computing power level means that the computing power is the same or similar; wherein the computing power index table is used to represent the computing power level corresponding to each core resource table.

[0017] Furthermore, the control circuit is used to instruct the task package scheduling circuit to operate based on the status information, including:

[0018] When the status information of each processing core belonging to the same core resource table is busy, the control circuit is used to instruct the task package scheduling circuit not to perform a read of the core resource table according to the status information;

[0019] When the status information of any of the processing cores belonging to the same core resource table is idle, the control circuit is used to instruct the task packet scheduling circuit to continue receiving subsequent task packets according to the status information; or,

[0020] When the status information of each of the processing cores is busy, the control circuit instructs the task package scheduling circuit to enter a waiting state based on the status information.

[0021] Furthermore, the task package scheduling circuit is also used to: modify the status information of the idle processing core in the core resource storage circuit, and send the status information to the control circuit.

[0022] Furthermore, the task package scheduling circuit is used to modify the status information of the idle processing core in the core resource storage circuit and send the status information to the control circuit, including:

[0023] After the idle processing core completes the task package, the state information of the idle processing core in the core resource storage circuit is modified to an idle state; or

[0024] Before or after sending the task packet to the idle processing core, the state of the idle processing core is changed to busy.

[0025] Furthermore, the control circuit is also used to modify the state information of the processing core stored in the control circuit.

[0026] Furthermore, the task scheduling circuit also includes a task instruction caching circuit, which includes a task instruction caching queue corresponding to each processing core, and each member in the task package caching queue is used to cache the task instructions in the task package corresponding to the processing core.

[0027] Furthermore, the task package includes: the task number of the task package, the task package number, the computing power requirement of the task package, and at least one task instruction.

[0028] Secondly, embodiments of this disclosure provide a task scheduling method for use in a system including at least two processing cores, the method comprising:

[0029] Obtain a task package to be executed, wherein the task package includes at least one task instruction for the same task and the computing power requirement of the task package;

[0030] An idle processing core is determined based on the computing power requirements of the task package and the computing power levels of the at least two processing cores;

[0031] Send the task package to the idle processing core;

[0032] The scheduling process of the task package is controlled based on the status information of the idle processing core.

[0033] Furthermore, the status information of the processing core is stored in a core resource table, wherein the core resource table corresponds to the computing power level, and the core resource table includes a processing core identifier and a processing core status bit corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.

[0034] Furthermore, the computing power level is stored in a computing power index table, and the status information of the processing core is stored in multiple core resource tables. Processing cores belonging to different core resource tables have different computing power levels, while processing cores belonging to the same core resource table have the same computing power level. The same computing power level indicates that the computing power is the same or similar. The computing power index table is used to represent the computing power level corresponding to each core resource table.

[0035] Furthermore, the process of controlling the scheduling of the task package based on the status information of the idle processing core includes:

[0036] When the status information of each processing core belonging to the same core resource table is busy, the control circuit is used to instruct the task package scheduling circuit not to perform a read of the core resource table according to the status information;

[0037] When the status information of any of the processing cores belonging to the same core resource table is idle, the control circuit is used to instruct the task packet scheduling circuit to continue receiving subsequent task packets according to the status information; or,

[0038] When the status information of each of the processing cores is busy, the control circuit instructs the task package scheduling circuit to enter a waiting state based on the status information.

[0039] Furthermore, the method also includes: modifying the status information of the idle processing cores in the core resource table.

[0040] Furthermore, modifying the status information of the idle processing cores in the core resource table includes:

[0041] After the idle processing core completes the task package, the state information of the idle processing core in the core resource storage circuit is modified to an idle state; or

[0042] Before or after sending the task packet to the idle processing core, the state of the idle processing core is changed to busy.

[0043] Furthermore, sending the task package to the idle processing core includes: sending the task instructions in the task package to the task instruction cache queue corresponding to the idle processing core.

[0044] Thirdly, embodiments of this disclosure provide a chip, including at least one task scheduling circuit as described in any one of the first aspects.

[0045] Fourthly, embodiments of this disclosure provide an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement any of the task scheduling methods described in the second aspect above.

[0046] Fifthly, embodiments of this disclosure provide a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute any of the task scheduling methods described in the second aspect above.

[0047] In a sixth aspect, embodiments of this disclosure provide a computer program product, characterized in that it includes computer instructions, wherein when the computer instructions are executed by a computing device, the computing device can execute any of the task scheduling methods described in the second aspect above.

[0048] In a seventh aspect, embodiments of this disclosure provide a computing device, characterized in that it includes any of the chips described in the fourth aspect.

[0049] This disclosure provides a task scheduling circuit, method, electronic device, and computer-readable storage medium. The task scheduling circuit includes a core resource storage circuit, a task package scheduling circuit, and a control circuit. The core resource storage circuit stores the status information and computing power level of each processing core. The task package scheduling circuit receives task packages containing at least one task instruction for the same task and the computing power requirement of the task package. It then identifies an idle processing core from the core resource storage circuit based on the computing power level and sends the task package to the idle processing core. The control circuit receives the status information of the idle processing core and instructs the task package scheduling circuit to operate based on the status information. This task scheduling circuit solves the problem of low scheduling efficiency in the prior art by scheduling task packages using the status information and computing power level of the processing cores.

[0050] The above description is merely an overview of the technical solution disclosed herein. In order to better understand the technical means of this disclosure and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this disclosure more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0051] The above and other features, advantages, and aspects of the embodiments of this disclosure will become more apparent from the accompanying drawings and the following detailed description. Throughout the drawings, the same or similar reference numerals denote the same or similar elements. It should be understood that the drawings are schematic, and the originals and elements are not necessarily drawn to scale.

[0052] Figure 1 This is a schematic diagram of existing technology;

[0053] Figure 2 This is a schematic diagram of the structure of the task scheduling circuit provided in an embodiment of the present disclosure;

[0054] Figure 3 A flowchart illustrating the task scheduling method provided in this embodiment of the disclosure;

[0055] Figure 4 A schematic diagram of an example of a task scheduling circuit provided in an embodiment of this disclosure;

[0056] Figure 5 A timing diagram of an example of a task scheduling circuit provided in an embodiment of this disclosure. Detailed Implementation

[0057] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0058] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0059] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0060] It should be noted that the concepts of "first" and "second" mentioned in this disclosure are used only to distinguish different devices, modules or units, and are not used to limit the order of functions performed by these devices, modules or units or their interdependencies.

[0061] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0062] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0063] Figure 2 This is a schematic diagram of the structure of a task scheduling circuit provided in an embodiment of this disclosure. The task scheduling circuit is used in a system including at least two processing cores, such as... Figure 2 As shown, the task scheduling circuit 200 includes:

[0064] Nuclear resource storage circuit 201, task packet scheduling circuit 202, and control circuit 203;

[0065] The core resource storage circuit 201 is used to store the status and computing power level of each processing core;

[0066] The task package scheduling circuit 202 is used to receive a task package to be executed, wherein the task package includes at least one task instruction for the same task and the computing power requirement of the task package; to identify an idle processing core from the core resource storage circuit according to the computing power level and the computing power requirement; and to send the task package to the idle processing core.

[0067] The control circuit 203 is used to receive the status information of the idle processing core and instruct the task package scheduling circuit to work according to the status information.

[0068] Through the aforementioned task scheduling circuit, tasks can be assigned to different types of processing cores based on computing power levels, ensuring that each task finds a suitable processing core for execution. This allows for the fastest possible task completion based on computing power requirements while maximizing chip performance. Furthermore, the task scheduling circuit schedules task packets to processing cores based on their status information. Each task packet contains at least one instruction for the same task. This eliminates the need for processing cores to consider data dependencies between tasks when executing the instructions in a task packet, thus improving the parallel performance of multiple processing cores and reducing the complexity of designing solutions to dependencies. Processing cores can continuously execute at least one instruction from the same task packet, avoiding frequent communication between the processing core and the task scheduling circuit, improving processing core operating efficiency, reducing the load on the on-chip network, and lowering power consumption.

[0069] Optionally, the core resource storage circuit 201 is used to store the status information and computing power level of each processing core, including: the core resource storage circuit 201 is used to store the core resource table RT_Ri and the computing power level T_Ri corresponding to the core resource table, wherein the core resource table includes a processing core identifier and a processing core status bit corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.

[0070] In this optional embodiment, the status information of the processing core is stored in the core resource storage circuit in the form of a core resource table RT_Ri. Processing cores in the same core resource table have the same or similar computing power levels. The core resource table includes a processing core identifier Ci_j and a processing core status bit Si_j corresponding to the processing core identifier Ci_j. For example, the processing core identifier Ci_j is the number of the processing core in the system including at least two processing cores, where i is the number of the core resource table and j is the label of the processing core in the core resource table. The value of the processing core status Si_j is 0 or 1, where 0 indicates that the processing core is in an idle state and can execute tasks; and 1 indicates that the processing core is in a busy state and is executing tasks.

[0071] Further, optionally, the core resource storage circuit 201 is used to store a computing power index table and multiple core resource tables RT_Ri, wherein the computing power level of processing cores belonging to different core resource tables is different, and the computing power level of processing cores belonging to the same core resource table is the same, wherein the same computing power level means that the computing power is the same or similar; wherein the computing power index table is used to represent the computing power level corresponding to each core resource table.

[0072] Optionally, the task scheduling circuit 200 further includes a task packet caching circuit 204, which is used to cache task packets received from the task source. The task packet includes one or more instructions for the same task. The task can be a complete task, such as a complete neural network like ResNet50 or BERT; or, the task can be a subtask of a complete task, such as a complete operation like convolution in ResNet50; the task or subtask includes one or more task instructions. The task source issues tasks to the task scheduling circuit 200 in the form of task packets. The same task can be divided into multiple task packets and sent sequentially to the task scheduling circuit to form a task packet stream. Each task packet includes a task number, a task packet number, and at least one task instruction. Table 1 below shows the data format of the task packet:

[0073] T_ID T_R P_ID P_body

[0074] (Table 1)

[0075] Where T_ID represents the task number, each task has a unique task number, and task packages belonging to the same task have the same task number; T_R represents the computing power requirement of the task package, the larger the number, the higher the computing power requirement, where the computing power requirement represents the computing power of the processing cores required to execute the task package, and the method of representing the computing power requirement in this disclosure is the same as the computing power level; P_ID represents the task package number, which represents the task package number in the task with the T_ID number; P_body represents the task package content, that is, the task instructions of the task or subtask.

[0076] Optionally, the task package scheduling circuit 202 is used to read the task package from the task package cache circuit 204. After reading the task package, the computing power requirement T_Ri of the task package is read from the task package. Based on the task computing power requirement T_Ri, a core resource table RT_Ri with a computing power level that meets the task computing power requirement is determined from the core resource storage circuit 201, and an idle processing core is determined in the core resource table RT_Ri. Optionally, the processing core identifier corresponding to the processing core in the idle state is queried through the core resource table RT_Ri. For example, the core resource table RT_Ri is as follows:

[0077]

[0078]

[0079] After reading the task package, the task package scheduling circuit 202 queries the core resource table RT_Ri and finds that the processing cores i_3 and i_4 are in an idle state.

[0080] When there are multiple idle processing cores, an idle processing core can be determined according to a pre-set scheduling strategy. For example, an idle processing core can be determined according to the order of the processing core identifiers.

[0081] After identifying an idle processing core, the task packet is sent to the idle processing core so that the idle processing core executes the task instructions in the task packet. For example, in the above example, processing core i_3 is identified as the idle processing core according to the order of its identifiers, and the task packet is sent to processing core i_3.

[0082] Alternatively, a random scheduling strategy can be used, whereby all idle processing cores are first identified, and then the task packet is randomly sent to one of the processing cores. It is understood that the above scheduling strategies are merely examples and do not constitute a limitation of this disclosure.

[0083] Optionally, the task package scheduling circuit 202 is further configured to: modify the status information of the processing core in the core resource storage circuit, and send the status information to the control circuit. After sending the task package to the idle processing core, the task package scheduling circuit 202 is configured to modify the status information of the idle processing core in the core resource table RT_Ri. Specifically, the task package scheduling circuit 202 modifies the status of the idle processing core in the core resource table RT_Ri to a busy state. As in the example above, if processing core i_3 is determined to be an idle processing core, the value of the status corresponding to processing core i_3 can be modified to 1 before or after the task package is sent to processing core i_3, to indicate that processing core 3 is executing a task. The task package scheduling circuit 202 sends the status information to the control circuit so that the control circuit instructs the task package scheduling circuit to work.

[0084] Optionally, the task package scheduling circuit 202 is used to modify the status information of the processing core in the core resource storage circuit, including: after the idle processing core finishes executing the task package, modifying the status information of the idle processing core in the core resource storage circuit to an idle state; or before or after sending the task package to the idle processing core, modifying the status of the idle processing core to a busy state. Optionally, after the idle processing core finishes executing the task package, it sends a message indicating that the task package has been completed. After receiving the message indicating that the task package has been completed, the task package scheduling circuit 202 modifies the status information of the idle core in the core resource storage circuit to an idle state. After the task package scheduling circuit 202 identifies an idle processing core, before or after sending the task package to the idle processing core, it modifies the status information of the idle core in the core resource storage circuit to a busy state. After modifying the status information of the idle processing core, the task package scheduling circuit 202 also sends the status information to the control circuit, so that the control circuit instructs the task scheduling circuit on subsequent operations.

[0085] Optionally, the modification of the state information of the idle processing core in the nuclear resource storage circuit to an idle state can also be performed by the control circuit 203. When the control circuit receives a message from the idle processing core indicating that the task package has been completed, it sets the state information of the idle processing core in the nuclear resource storage circuit to an idle state based on the message.

[0086] Optional, such as Figure 2 As shown, the task scheduling circuit 202 modifies the state of the idle processing core to a busy state through the signal ST[M:1]. For example, after determining that i_3 in RT_Ri is an idle processing core, i in the signal ST[M:1] is set to 1, and the state information Si_3 of i_3 is set to 1 through this signal, that is, busy state.

[0087] Optional, such as Figure 2 As shown, the control circuit 203 modifies the state of the idle processing core to an idle state through the signal RST[M:1]. For example, when processing core i_3 finishes executing the instructions in the task package, it returns the information that the task package has been completed to the control circuit 203. The control circuit determines that the processing core i_3 is the processing core in RT_Ri based on the identifier of the processing core i_3. Then, the control circuit sets i in the signal RST[M:1] to 0, and sets the state information Si_3 of i_3 to 0 through this signal, that is, the idle state.

[0088] Optionally, the control circuit 203 is used to instruct the task package scheduling circuit to operate according to the status information, including:

[0089] When the status information of each processing core belonging to the same core resource table is busy, the control circuit is used to instruct the task package scheduling circuit not to perform a read of the core resource table according to the status information;

[0090] When the status information of any of the processing cores belonging to the same core resource table is idle, the control circuit is used to instruct the task packet scheduling circuit to continue receiving subsequent task packets according to the status information; or,

[0091] When the status information of each of the processing cores is busy, the control circuit instructs the task package scheduling circuit to enter a waiting state based on the status information.

[0092] Optionally, 1 represents the state of the processing core as busy, and 0 represents the state of the processing core as idle. CB[M:1] represents the information of idle processing cores in each core resource table, where CB[i] indicates whether there are idle processing cores in the core resource table RT_Ri. CB[i] = 0 indicates that there are idle processing cores in the core resource table RT_Ri, and CB[i] = 1 indicates that all processing cores in the core resource table RT_Ri are busy. The value of CB[i] is obtained by performing logical operations on the state values ​​of all processing cores in the core resource table RT_Ri, that is, calculating CB[i] = Si_1 ∩ Si_2 … Si_j … Si_n. When CB[i] = 1, it means that all processing cores in the core resource table RT_Ri are busy, and there are no available idle processing cores. At this time, the task packet scheduling circuit will not search for idle processing cores in the core resource table RT_Ri because all cores in this core resource table are in a working state. If CB[i] = 0, it means that at least one processing core in the core resource table is in an idle state. The task packet scheduling circuit 202 can search for an idle processing core from the core resource table, where 0 <i<M,0<j<N M And i,j,M,N M All values ​​are integers. When CB[M:1] = 1, it indicates that there are no idle processing cores in any of the core resource tables. At this time, the task package scheduling circuit 202 enters a waiting state until a processing core is idle. At this time, at least one CB[i] = 0. The task package scheduling circuit 202 can continue to read the task package and obtain an idle processing core of the corresponding computing power level according to the computing power requirement. Optionally, when there is no idle processing core in the core resource table of the computing power level corresponding to the computing power requirement of the task package, the task package scheduling circuit 202 starts searching for an idle processing core from the core resource table with the highest computing power level until an idle processing core is found, and then sends the task package to the idle processing core.

[0093] Optionally, the control circuit 203 is further configured to modify the state information of the processing core stored in the control circuit. In this optional embodiment, the control circuit 203 also stores a copy of the same processing core state information as that in the core resource storage circuit, which avoids the control circuit 203 from repeatedly retrieving the processing core state information from the core resource storage circuit, thus preventing frequent reads of the core resource storage circuit. In this optional embodiment, the control circuit 203 receives state information sent by the task package scheduling circuit 202 to modify the processing core state information stored in the control circuit 203 itself; or, the control circuit 203 receives information indicating that the task package has been completed from the processing core that has completed the task package to modify the processing core state information stored in the control circuit 203 itself. In this way, the value of CB[M:1] can be calculated using the state information of the processing core stored in the control circuit 203 itself, and the task package scheduling circuit can be instructed to work based on the value of CB[M:1].

[0094] Optionally, the task scheduling circuit 200 further includes a task instruction cache circuit 205, which includes a task instruction cache queue corresponding one-to-one with each processing core. Each member of the task package cache queue is used to cache task instructions in the task package corresponding to the processing core. Figure 2 As shown, the task instruction cache circuit 205 includes a task instruction cache queue IQi_j, where IQi_j corresponds to Ci_j. When the task package scheduling circuit 202 determines an idle processing core Ci_j, it sends the task instructions from the read task package to the task instruction cache queue IQi_j corresponding to Ci_j. Then, Ci_j retrieves the task instructions from the task instruction cache queue and executes them to complete the corresponding task or subtask.

[0095] Figure 3 This is a flowchart illustrating a task scheduling method provided in an embodiment of the present disclosure. The task scheduling method is used in a system including at least two processing cores, and includes:

[0096] Step S301: Read the task package to be executed, wherein the task package includes at least one task instruction for the same task and the computing power requirement of the task package;

[0097] Step S302: Identify an idle processing core based on the computing power requirement and the computing power level of the at least two processing cores;

[0098] Step S303: Send the task package to the idle processing core;

[0099] Step S304: Control the scheduling process of the task package according to the status information of the idle processing core.

[0100] Furthermore, the status information of the processing core is stored in a core resource table, wherein the core resource table corresponds to the computing power level, and the core resource table includes a processing core identifier and a processing core status bit corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.

[0101] Furthermore, the computing power level is stored in a computing power index table, and the status information of the processing core is stored in multiple core resource tables. Processing cores belonging to different core resource tables have different computing power levels, while processing cores belonging to the same core resource table have the same computing power level. The same computing power level indicates that the computing power is the same or similar. The computing power index table is used to represent the computing power level corresponding to each core resource table.

[0102] Furthermore, the process of controlling the scheduling of the task package based on the status information of the idle processing core includes:

[0103] When the status information of each processing core belonging to the same core resource table is busy, the control circuit is used to instruct the task package scheduling circuit not to perform a read of the core resource table according to the status information;

[0104] When the status information of any of the processing cores belonging to the same core resource table is idle, the control circuit is used to instruct the task packet scheduling circuit to continue receiving subsequent task packets according to the status information; or,

[0105] When the status information of each of the processing cores is busy, the control circuit instructs the task package scheduling circuit to enter a waiting state based on the status information.

[0106] Furthermore, the method also includes: modifying the status information of the idle processing cores in the core resource table.

[0107] Furthermore, modifying the status information of the idle processing cores in the core resource table includes:

[0108] After the idle processing core completes the task package, the state information of the idle processing core in the core resource storage circuit is modified to an idle state; or

[0109] Before or after sending the task packet to the idle processing core, the state of the idle processing core is changed to busy.

[0110] Furthermore, sending the task package to the idle processing core includes: sending the task instructions in the task package to the task instruction cache queue corresponding to the idle processing core.

[0111] It is understood that the task scheduling method is executed by the task scheduling circuit, and the specific implementation of each step can be found in the description of the task scheduling circuit, which will not be repeated here.

[0112] Figure 4 This is an example of a task scheduling circuit described in an embodiment of this disclosure. Figure 4 As shown, in this example, the task scheduling circuit is used in a system including two processing cores, C1_1 and C2_1. The computing power level of C1_1 is 1, and the computing power level of C2_1 is 2. The task scheduling circuit includes a task package cache circuit TB, a task package scheduling circuit TS, a control circuit Ctrl, core resource tables RT_R1 and RT_R2, and a task instruction cache queue IQ1_1 corresponding to processing core C1_1 and a task instruction cache queue IQ2_1 corresponding to processing core C2_1.

[0113] In this example, the task source includes four tasks T1, T2, T3, and T4, with IDs 1, 2, 3, and 4 respectively. T1 and T2 require 1 unit of computing power, while T3 and T4 require 2 units. Each task includes a task package, and each task package contains at least one task instruction from the task's program. The specific contents of the task package include:

[0114] T_ID T_R P_ID P_body 1 1 1 Program 1 2 1 1 Program2 3 2 1 Program3 4 2 1 Program4

[0115] In this context, Program1, Program2, Program3, and Program4 represent at least one task instruction from T1, T2, T3, and T4, respectively.

[0116] In the core resource table, the core identifier occupies one byte, where the high 4 bits are used to identify the group number of the computing power group to which the processing core belongs or the core resource table number, and the low 4 bits are used to identify the number of the processing core in its computing power group or core resource table. The status bit of the processing core is represented by 1 bit of data, where 0 indicates an idle state and 1 indicates a busy state.

[0117] Because the computational requirements of the above tasks differ, and the computational power levels of the two processing cores also differ, the completion times of the four tasks are different. The timing diagrams for C1_1 and C2_1 executing the four tasks are as follows: Figure 5 As shown.

[0118] Combination Figure 4 and Figure 5 The process by which the task scheduling circuit schedules the four tasks is as follows:

[0119] The task source sends the task packets of the four tasks to the task packet cache circuit TB of the task scheduling circuit in sequence.

[0120] TS reads task packets from the TB in sequence.

[0121] The first task package is the task package of the task with T_ID 1. Since T_R = 1, an idle processing core is searched from RT_R1, which corresponds to computing power level 1. TS searches for an idle processing core in the core resource table RT_R1. Since S1_1 = 0, it is determined that the processing core C1_1 is idle. TS sets the status S1_1 corresponding to the processing core C1_1 to 1, and notifies Ctrl that the status S1_1 of the processing core C1_1 is 1. The task instruction of T1 is stored in the instruction queue IQ1_1 corresponding to the processing core C1. IQ1_1 sends the task instruction of T1 to the processing core C1_1. Ctrl generates control signal CB[1] = 1.

[0122] TS sequentially reads the second task package from TB, namely the task package T2; the computing power requirement level of task T2 is also TR=1, therefore, it searches for an idle processing core in RT_R1 corresponding to computing power level 1. Since CB[1]=1 at this time, TS continues to search for an idle processing core in RT_R2. Since S2_1=0 at this time, it sequentially searches for an idle processing core in the core resource table RT_R2. When it is determined that the processing core C2_1 is idle, TS sets the status S2_1 corresponding to the processing core C2_1 to 1, and notifies Ctrl that the status S2_1 of the processing core C2_1 is 1, and stores the task instruction of T2 in the instruction queue IQ2_1 corresponding to the processing core C2_1. IQ2_1 sends the task instruction of T2 to the processing core C2_1, and Ctrl generates a control signal CB[2]=1.

[0123] TS sequentially reads the third task packet from TB, namely the task packet T3; at this time, since all processing cores are busy, CB[1] = 1, CB[2] = 1, so TS enters the waiting state.

[0124] Task T1 and Task T2 have the same computing power requirements. However, C2_1 has a higher computing power level than C1_1. Therefore, C2_1 completes the task package of Task T2 first and sends a message that the task package has been completed to Ctrl. Ctrl sets the state S2_1 of C2_1 to 0 and sets CB[2] to 0.

[0125] The computing power requirement of task T3 is 2. It should look for an idle processing core in TR_R2. However, TS detects that CB[2] = 0 and CB[1] = 1, that is, only C2_1 is idle. Regardless of the computing power requirement of T3, TS searches for idle processing cores in the kernel resource table RT_R2 in sequence. When it is determined that the processing core C2_1 is idle, TS sets the status S2_1 corresponding to the processing core C2_1 to 1. At the same time, it notifies Ctrl that the status S2_1 of the processing core C2_1 is 1, and stores the task instruction of T3 into the instruction queue IQ2_1 corresponding to the processing core C2_1. IQ2_1 sends the task instruction of T3 to the processing core C2_1. Ctrl generates the control signal CB[2] = 1.

[0126] TS sequentially reads the fourth task packet, namely the T4 task packet, from TB; at this time, since all processing cores are busy, TS enters a waiting state.

[0127] Assuming that T1 finishes execution before T3, C1_1 sends a message that the task package has finished executing to Ctrl. Ctrl sets the state S1_1 of C1_1 to 0 and sets CB[1] to 0.

[0128] TS detects CB[1] = 0 and CB[2] = 1, so it sequentially searches for idle processing cores in the kernel resource table RT_R1. When it is determined that processing core C1_1 is idle, TS sets the status S1_1 corresponding to processing core C1_1 to 1, and notifies Ctrl that the status S1_1 of processing core C1_1 is 1. It also stores the task instruction of T4 into the instruction queue IQ1_1 corresponding to processing core C1_1, and IQ1_1 sends the task instruction of T4 to processing core C1_1.

[0129] After that, since there are no other task packages in TB, TS no longer reads task packages from TB and enters an idle state.

[0130] Afterwards, processing core C2_1 completes task T3 and sends a message indicating that the task has been completed to the Ctrl. After receiving the message indicating that the task has been completed, the Ctrl changes the state of processing core C2_1 to S2_1 = 0.

[0131] Afterwards, processing core C1_1 completes task T4 and sends a message indicating that the task has been completed to the Ctrl. After receiving the message indicating that the task has been completed, the Ctrl changes the state of processing core C1_1 to S1_1 = 0.

[0132] At this point, all four tasks have been completed. The system is now awaiting new task packages to execute.

[0133] In the example above, since there is only one set of available processing cores in the system when task packages T3 and T4 are read, it is not necessary to obtain the corresponding processing cores based on the computing power requirements of T3 and T4. In a system with more processing cores, more processing cores that meet the computing power requirements can be provided. When all processing cores that meet the computing power requirements are busy, the idle processing cores can be queried sequentially from the highest computing power level to execute the task package. This will not be elaborated further here.

[0134] This disclosure also provides a chip including at least one task scheduling circuit as described in any of the above embodiments.

[0135] This disclosure also provides an electronic device, including: a memory for storing computer-readable instructions; and one or more processors for executing the computer-readable instructions, such that the processors, when running, implement any of the task scheduling methods described in the embodiments.

[0136] This disclosure also provides a non-transitory computer-readable storage medium, characterized in that the non-transitory computer-readable storage medium stores computer instructions for causing a computer to execute any of the task scheduling methods described in the foregoing embodiments.

[0137] This disclosure also provides a computer program product, characterized in that it includes computer instructions, which, when executed by a computing device, can execute any of the task scheduling methods described in the foregoing embodiments.

[0138] This disclosure also provides a computing device, characterized in that it includes any of the chips described in the embodiments.

[0139] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0140] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0141] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0142] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

Claims

1. A task scheduling circuit for use in a system comprising at least two processing cores, characterized in that, include: Nuclear resource storage circuitry, task packet scheduling circuitry, and control circuitry; among which, The core resource storage circuit is used to store the status information and computing power level of each processing core; The task package scheduling circuit is used to acquire a task package to be executed, wherein the task package includes at least one task instruction for the same task and the computing power requirement of the task package; to identify an idle processing core from the core resource storage circuit according to the computing power level and the computing power requirement; and to send the task package to the idle processing core, wherein the idle processing core is used to continuously execute at least one task instruction in the task package. A control circuit is used to receive the status information of the idle processing core and instruct the task package scheduling circuit to work according to the status information.

2. The task scheduling circuit as described in claim 1, characterized in that, The core resource storage circuit is used to store the status information and computing power level of each processing core, including: The nuclear resource storage circuit is used to store a nuclear resource table and the computing power level corresponding to the nuclear resource table. The nuclear resource table includes a processing core identifier and a processing core status bit corresponding to the processing core identifier; wherein the processing core status bit is used to indicate an idle state or a busy state.

3. The task scheduling circuit as described in claim 2, characterized in that: The core resource storage circuit is used to store a computing power index table and multiple core resource tables. Processing cores belonging to different core resource tables have different computing power levels, while processing cores belonging to the same core resource table have the same computing power level. The same computing power level means that the computing power is the same or similar. The computing power index table is used to represent the computing power level corresponding to each core resource table.

4. The task scheduling circuit as described in claim 3, characterized in that, The control circuit is used to instruct the task package scheduling circuit to operate according to the status information, including: When the status information of each processing core belonging to the same core resource table is busy, the control circuit is used to instruct the task package scheduling circuit not to perform a read of the core resource table according to the status information; When the status information of any of the processing cores belonging to the same core resource table is idle, the control circuit is used to instruct the task packet scheduling circuit to continue receiving subsequent task packets according to the status information; or, When the status information of each of the processing cores is busy, the control circuit instructs the task package scheduling circuit to enter a waiting state based on the status information.

5. The task scheduling circuit as described in any one of claims 1-4, characterized in that, The task packet scheduling circuit is also used for: Modify the status information of the idle processing core in the nuclear resource storage circuit, and send the status information to the control circuit.

6. The task scheduling circuit as described in claim 5, characterized in that, The task package scheduling circuit is used to modify the status information of the idle processing core in the core resource storage circuit, and send the status information to the control circuit, including: After the idle processing core completes the task package, the state information of the idle processing core in the core resource storage circuit is modified to an idle state; or Before or after sending the task package to the idle processing core, the state of the idle processing core is changed to busy.

7. The task scheduling circuit as described in claim 6, characterized in that, The control circuit is also used for: Modify the state information of the processing core stored in the control circuit.

8. The task scheduling circuit as described in any one of claims 1-4, characterized in that, The task scheduling circuit further includes: A task instruction caching circuit includes a task instruction caching queue corresponding to each processing core, and each member in the task package caching queue is used to cache the task instructions in the task package corresponding to the processing core.

9. The task scheduling circuit as described in any one of claims 1-4, characterized in that, The task package includes: the task number of the task package, the task package number, the computing power requirement of the task package, and at least one task instruction.

10. A task scheduling method, used in the task scheduling circuit according to any one of claims 1-9, characterized in that, include: Obtain a task package to be executed, wherein the task package includes at least one task instruction for the same task and the computing power requirement of the task package; An idle processing core is determined based on the computing power requirements of the task package and the computing power levels of the at least two processing cores. The idle processing core is used to continuously execute at least one task instruction in the task package. Send the task package to the idle processing core; The scheduling process of the task package is indicated based on the status information of the idle processing core.

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