Programming method, system, device and computer-readable storage medium

Abstract

The present invention discloses a programming method, system, and device. The programming method includes: obtaining programming data in a cache and a target area in a multi-bit non-volatile memory corresponding to the programming data; selecting a voltage level from a plurality of voltage levels as a target voltage level; performing programming verification on all storage cells corresponding to the programming data in the target area according to the programming data, the target voltage level, and the correspondence between the programming data and the addresses of the storage cells in the target area; when there are storage cells that fail the programming verification, programming all storage cells in the target area according to the programming data in the cache and the target voltage level. Because all storage cells in the target area are operated according to the selected target voltage level during programming verification and programming, the number of switching times of the analog voltage added to the storage array can be reduced, thereby reducing power consumption during programming and reducing programming time.

Description

Technical Field

[0001] The present invention relates to the field of storage technology, and in particular to a programming method, system, device and computer-readable storage medium. Background Art

[0002] Non-volatile memory is a memory that integrates a large number of storage units to store data. Conventional non-volatile memory uses one storage unit to store 1 bit of data, which is called SLC (Single-Level Cell). Non-volatile memory that uses one storage unit to store 2 bits of data is called MLC (Multi-Level Cell). The more data a storage unit can store, the smaller the area of ​​the memory chip with the same capacity, and the lower the cost.

[0003] Although the use of multi-bit non-volatile memory can reduce the area of ​​memory chips of the same capacity and thus reduce costs, existing multi-bit non-volatile memories have the problem of frequent switching (powering on and off) of the analog voltage applied to the memory array during programming, resulting in high power consumption and long programming time. Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] Embodiments of the present invention provide a programming method, system, device, and computer storage medium that can reduce programming power consumption and programming time by reducing the number of switching times of analog voltages applied to a storage array during programming of a multi-bit non-volatile memory.

[0006] In a first aspect, an embodiment of the present invention provides a programming method applied to a multi-bit non-volatile memory having multiple voltage levels, the programming method comprising:

[0007] Acquire programming data in a cache and a target area in the multi-bit non-volatile memory corresponding to the programming data;

[0008] Selecting a voltage level from the plurality of voltage levels as a target voltage level;

[0009] performing program verification on all memory cells corresponding to the programming data in the target area according to the programming data, the target voltage level, and a correspondence between the programming data and addresses of the memory cells in the target area;

[0010] When there are memory cells that fail the programming verification, all memory cells in the target area are programmed according to the programming data in the cache and the target voltage level.

[0011] In a second aspect, an embodiment of the present invention provides a programming system applied to a multi-bit non-volatile memory having multiple voltage levels, the programming system comprising:

[0012] A storage module is a storage cell array for storing data;

[0013] A selection module selects the storage unit that currently needs to be programmed or verified by address decoding;

[0014] a comparator module, configured to output a comparison result according to the threshold voltage of the storage element in the storage unit selected by the selection module and the voltage reference value or the current reference value;

[0015] A reference module, configured to provide the comparator module with a corresponding voltage reference value or current reference value for the programming verification;

[0016] a cache module, configured to store programming data and the comparison result;

[0017] an operation module, configured to update the programming data corresponding to the current storage unit according to the comparison result;

[0018] a programming module, configured to program the storage unit selected by the selection module according to the programming data in the cache module, the comparison result, and the target gear voltage of the simulation module;

[0019] An analog module, configured to provide a target voltage level to the programming selection module and provide a corresponding analog voltage to a memory cell of a memory unit in the memory module;

[0020] The programming control module is used to execute the programming method described in the first aspect.

[0021] In a third aspect, an embodiment of the present invention provides a programming device, which is applied to a multi-bit non-volatile memory, wherein the multi-bit non-volatile memory has multiple voltage levels, includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the programming method as described in the first aspect.

[0022] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the programming method as described in the first aspect.

[0023] An embodiment of the present invention provides a programming method, which is applied to a multi-bit non-volatile memory having multiple voltage levels and has at least the following beneficial effects:

[0024] Acquire programming data in a cache and a target area in the multi-bit non-volatile memory corresponding to the programming data;

[0025] Selecting a voltage level from the plurality of voltage levels as a target voltage level;

[0026] performing program verification on all memory cells corresponding to the programming data in the target area according to the programming data, the target voltage level, and a correspondence between the programming data and addresses of the memory cells in the target area;

[0027] When there are memory cells that fail the programming verification, all memory cells in the target area are programmed according to the programming data in the cache and the target voltage level.

[0028] By obtaining programming data in a cache and the target area in the multi-bit non-volatile memory corresponding to the programming data, the data to be programmed and the target area to be programmed are determined, and then a voltage level is selected from multiple voltage levels as a target voltage level. Then, based on the programming data, the target voltage level, and the correspondence between the programming data and the addresses of the storage cells in the target area, programming verification is performed on all storage cells in the target area corresponding to the programming data. Finally, a judgment is performed to determine whether there are any storage cells that fail the programming verification. If there are any storage cells that fail the programming verification, all storage cells in the target area are programmed based on the programming data in the cache and the target voltage level. Because all storage cells in the target area are operated based on the selected target voltage level during programming verification and programming, the number of switching times of the analog voltage applied to the storage array can be reduced, thereby reducing power consumption during the programming process and reducing programming time.

[0029] Other features and advantages of the present invention will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present invention. The purposes and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the description, claims and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The accompanying drawings are used to provide a further understanding of the technical solution of the present invention and constitute a part of the specification. Together with the examples of the present invention, they are used to explain the technical solution of the present invention and do not constitute a limitation to the technical solution of the present invention.

[0031] Figure 1 1 is a schematic diagram of threshold voltage distribution corresponding to four logic states provided by an embodiment of the present invention;

[0032] Figure 2 is an overall method flow chart of a programming method provided by one embodiment of the present invention;

[0033] Figure 3 is a detailed flowchart of step S300 provided by an embodiment of the present invention;

[0034] Figure 4 This is a flowchart of how to verify a storage unit according to a target voltage level according to an embodiment of the present invention;

[0035] Figure 5 This is a flowchart of processing an unsuccessful first programming verification provided by one embodiment of the present invention;

[0036] Figure 6 An embodiment of the present invention provides a flowchart of a process after a threshold voltage of a storage element is greater than a voltage of a target gear position and corresponds to a first voltage;

[0037] Figure 7 is a detailed flowchart of step S200 provided by an embodiment of the present invention;

[0038] Figure 8 This is a flowchart of the process before one cycle of "program verification-programming" provided by one embodiment of the present invention;

[0039] Figure 9 is a schematic diagram of system functional modules of a programming system provided by an embodiment of the present invention;

[0040] Figure 10 It is a structural diagram of a programming device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0042] Non-volatile memory is a memory that integrates a large number of storage units to store data. Conventional non-volatile memory uses one storage element to store 1 bit of data, which is called SLC; non-volatile memory that uses one storage element to store 2 bits of data is called MLC. The more data a storage element can store, the smaller the area of ​​the memory chip with the same capacity, and the lower the cost.

[0043] Although the use of multi-bit non-volatile memory can reduce the area of ​​memory chips of the same capacity and thus reduce costs, existing multi-bit non-volatile memories have the problem of frequent switching (powering on and off) of the analog voltage applied to the memory array during programming, resulting in high power consumption and long programming time.

[0044] Based on this, embodiments of the present invention provide a programming method, system, device, and computer storage medium that can reduce the number of analog voltage switches applied to a storage array during the programming process of a multi-bit non-volatile memory, thereby reducing programming power consumption and shortening programming time.

[0045] In SLC, a memory cell only stores 1 bit of data, so the memory cell in SLC has only two logical states, "0" or "1", and correspondingly, the memory cell in SLC has only two threshold voltage distributions, while in MLC, a memory cell can store 2 bits of data, so the memory cell in MLC can have four logical states, "11", "10", "01" and "00", and four corresponding threshold voltage distributions, where, refer to Figure 1In one embodiment of the present invention, the logic state "11" corresponds to VD0, the storage element with the logic state of "11" is the storage element that has been erased, and Vref0 is the erase voltage reference value; the logic state "10" corresponds to VD1, the storage element with the logic state of "10" is the storage element that has been programmed in the first gear, and Vref1 is the first gear programming reference value; the logic state "01" corresponds to VD2, the storage element with the logic state of "01" is the storage element that has been programmed in the second gear, and Vref2 is the first gear programming reference value; the logic state "00" corresponds to VD3, the storage element with the logic state of "00" is the storage element that has been programmed in the third gear, and Vref3 is the first gear programming reference value. Here, the threshold voltage of the storage element with a logic state of "11" is smaller than the threshold voltage of the storage element with a logic state of "10", the threshold voltage of the storage element with a logic state of "10" is smaller than the threshold voltage of the storage element with a logic state of "01", and the threshold voltage of the storage element with a logic state of "01" is smaller than the threshold voltage of the storage element with a logic state of "00". It is worth mentioning that the first gear programming can be understood as programming with the selected target voltage gear as the first gear, and the second gear programming and the third gear programming are the same, which will not be repeated here. It can be understood that the correspondence between the logical state and the threshold voltage is not limited in the embodiment of the present invention, and those skilled in the art can make a choice according to actual conditions. Furthermore, the present invention does not limit the number of bits stored in the storage element of the multi-bit non-volatile memory. For example, the programming method of the embodiment of the present invention can be applied to MLC, and can also be applied to a multi-bit non-volatile memory TLC (Triple-Level Cell) in which one storage element can store 3 bits of data. In order to better understand the present invention, MLC is used as an example for explanation below. In addition, it is stipulated that the target voltage level of the following first-level programming and first-level programming verification is both the first level, the target voltage level of the second-level programming and second-level programming verification is both the second level, and the target voltage level of the third-level programming and third-level programming verification is both the third level.

[0046] The storage cells of multi-bit non-volatile memories store more data than those of SLCs, which can reduce the area of ​​memory chips of the same capacity and thus reduce costs. For example, to store the data "00100100", MLC only needs 4 storage cells to complete the storage, while SLC needs 8 storage cells to complete the corresponding storage. However, the existing multi-bit non-volatile memories have the following problems: during the programming process, the analog voltage applied to the storage array needs to be frequently switched (powered on and off), resulting in high power consumption and long programming time during the programming process. SLC does not have the above problems because the storage cells of SLC can only store 1 bit of data. Therefore, the corresponding logical state is only one of the two logical states of "0" and "1". Generally speaking, when performing "program verification-programming" on the target area of ​​the memory, the target area must be erased first to ensure that the subsequently written data will not be affected by the previously written data. The entire "program verification-programming" can be divided into a programming verification stage and a programming stage. In the programming verification stage, when all the storage cells in the target area pass the programming verification, programming is not performed and the cycle ends. When there are storage cells in the target area that fail the programming verification, the programming stage is entered; in the programming stage, when the programming of the storage cells in the target area is completed, the program returns to the programming verification stage. And suppose that the logic state of each storage element in the target area after erasure is "1", then in the process of "program verification-programming", if it is detected that the programming data corresponds to 1, the storage element corresponding to the data will not be operated. Therefore, the analog voltage of SLC does not need to be frequently switched in the process of "program verification-programming". However, the logic state corresponding to the storage element of MLC is one of the four logic states of "11", "10", "01" and "00". Therefore, after the target area is erased, suppose that the logic state of each storage element in the target area after erasure is "11", then in the process of "program verification-programming", the storage elements corresponding to "10", "01" and "00" in the programming data need to be operated.

[0047] Furthermore, in the prior art, if the first gear programming verification is performed first in the programming verification stage, the programming verification can be understood as the threshold voltage in the storage element is greater than or equal to the voltage corresponding to the target voltage gear. If the first gear programming verification is performed, it can be understood as the threshold voltage in the storage element is greater than or equal to the voltage corresponding to the target voltage gear. Figure 1Vref1 in the program is verified by the first gear programming for the storage element corresponding to the programming data of "10", "01", and "00". However, if the storage element corresponding to the programming data of "01" passes the first gear programming verification when the target area is subjected to the first gear programming verification, the existing technical solution will perform the second gear programming verification on the storage element. Similarly, if the storage element corresponding to the programming data of "00" passes the first gear programming verification when the target area is subjected to the first gear programming verification, the second gear programming verification is performed. After the storage element passes the second gear programming verification, the third gear programming verification is performed. Then, whether to enter the programming stage is determined based on the result of the programming verification of the entire target area. If the programming stage is entered, it is also Similarly, if the existing technical solution performs first-level programming first, then when the programming data is "01", the corresponding storage element is programmed in the second level, and when the programming data is "00", the corresponding storage element is programmed in the second level, and then the third level is programmed, and then the programming stage is returned. From the above technical solution, it can be seen that the existing technical solution causes multiple switching after the analog voltage of the storage array is added. For example, in the programming verification stage, after verifying that the storage element corresponding to the programming data is "01", it is necessary to discharge power from the second level to return to the first level to verify that the next programming data is not "11". The number of unnecessary switching times not only increases the power consumption of the entire "programming verification-programming", but also increases the time of "programming verification-programming".

[0048] Based on the above problems, an embodiment of the present invention proposes a programming method applied to a multi-bit non-volatile memory having multiple voltage levels. Figure 2 , programming methods include:

[0049] Step S100, obtaining programming data in the cache and a target area in the multi-bit non-volatile memory corresponding to the programming data;

[0050] Step S200, selecting a voltage level from a plurality of voltage levels as a target voltage level;

[0051] Step S300, performing program verification on all memory cells corresponding to the programming data in the target area according to the programming data, the target voltage level, and the correspondence between the programming data and the addresses of the memory cells in the target area;

[0052] Step S400 : When there are memory cells that fail the programming verification, all memory cells in the target area are programmed according to the programming data in the cache and the target voltage level.

[0053] It is worth mentioning that there is no memory cell that fails programming verification, which can be understood as referring to Figure 1, the threshold voltage of the storage element corresponding to the programming data "11" is distributed in VD0, the target voltage gear is the first gear, the threshold voltage of the storage element corresponding to the programming data "10", "01", and "00" is greater than or equal to Vref1, the target voltage gear is the second gear, the threshold voltage of the storage element corresponding to the programming data "01" and "00" is greater than or equal to Vref2, and finally, the target voltage gear is the third gear, the threshold voltage of the storage element corresponding to the programming data "00" is greater than or equal to Vref3.

[0054] Furthermore, it is understood that before performing programming verification, the programming data in the cache and the target area to be written into the multi-bit non-volatile memory must be obtained, and step S100 is executed.

[0055] It is conceivable that before performing “program verification-programming” on the target area, a voltage level must be selected from a plurality of voltage levels as a target voltage level, and step S200 is executed.

[0056] Furthermore, according to the programming data, the target voltage level, and the correspondence between the programming data and the addresses of the storage cells in the target area, programming verification is performed on all the storage cells corresponding to the programming data in the target area. For example, if the programming data is one of "10", "01" and "00", if the target voltage level is the first level, the storage element corresponding to the programming data is subjected to first level programming verification; if the target voltage level is the second level, the storage element corresponding to the programming data of "01" or "00" is subjected to second level programming verification, and step S300 is executed.

[0057] Furthermore, when there are storage cells that fail the programming verification, the programming stage is entered, and all storage cells in the target area are programmed according to the programming data in the cache and the target voltage level, and step S400 is executed. It is worth noting that in step S400, when there are storage cells that fail the programming verification, it can be understood that when there are storage elements in the storage cells that fail the programming verification.

[0058] It can be imagined that the difference between the embodiment of the present invention and the prior art is that after the embodiment of the present invention selects a target voltage level, each programming verification and each programming are performed in units of target areas, while in the prior art, each programming verification and each programming are performed in units of storage elements. It can be imagined that a storage unit is a collection of storage elements, and one storage unit corresponds to one address, and a target area is generally a collection of addresses. Therefore, if the relevant programming verification or programming is performed in units of storage elements, the analog voltage will produce a lot of unnecessary switching during the programming process. For example, if the data in the cache is "a=11100100; b=11100100;", then the prior art performs programming verification on the target area, and the switching that occurs can be understood as "10-01-00 -10-01-00", 5 switches occurred, while by using the programming method of the embodiment of the present invention, the switching that occurred can be understood as "10-01-00" occurring 2 switches, and the number of switches is fixed. For example, if the programming data in the cache is increased, such as "a=11100100; b=11100100; c=11100100", the prior art performs programming verification on the target area, and the switching that occurs is "10-01-00-10-01-00-10-01-00", which occurs 8 switches, while by using the programming method of the embodiment of the present invention, the switching that occurs is "10-01-00", which is still 2 times. Therefore, the programming method of the embodiment of the present invention can reduce the number of analog voltage switching times during the programming process of a multi-bit non-volatile memory, thereby reducing programming power consumption and programming time.

[0059] Further, refer to Figure 3 In step S300, the detailed steps are as follows:

[0060] Step S510, determining a starting memory cell in a target area according to the starting data of the programming data;

[0061] In step S520 , the address of the starting memory cell is used as the starting address, and programming verification is performed on all memory cells in the target area in sequence according to the target voltage level in an address increasing manner.

[0062] It is understandable that the target area may be larger than the area corresponding to the programming data in the cache. Therefore, it is necessary to first determine the starting storage unit in the target area based on the starting data of the programming data, determine the area for programming verification, execute step S510, and then use the address of the starting storage unit as the starting address, in an address incrementing manner, perform programming verification on all storage cells in the target area in turn according to the target voltage level selected previously, and execute step S520.

[0063] In the process of executing step S520, refer to Figure 4The specific steps for programming and verifying the storage unit according to the target voltage level are as follows:

[0064] Step S610, when the first voltage is greater than or equal to the voltage corresponding to the target voltage level, performing programming verification on the memory cell of the memory unit according to the target voltage level, the first voltage being a threshold voltage of programming data corresponding to the memory cell;

[0065] Step S620, when the threshold voltages of all memory cells are greater than or equal to the voltage corresponding to the target voltage level, it is determined that the memory cells pass the programming verification;

[0066] Step S630 : When the threshold voltage of a memory cell is lower than the voltage corresponding to the target voltage level, it is determined that the memory cell fails the programming verification.

[0067] The first voltage in step S610 can be understood as the threshold voltage of the programming data corresponding to the memory element, referring to Figure 1 For example, when the programming data corresponding to the storage element is "10", the first voltage is the voltage distributed in VT1, and the first voltage is greater than or equal to Vref1. Therefore, when the target voltage gear is the first gear, step S610 is executed. When the first voltage of the storage element in the storage unit is greater than or equal to the voltage corresponding to the first gear, that is, the programming data corresponding to the storage element is any one of "10", "01", and "00", the first gear programming verification is performed on the storage element. Therefore, step S610 can be understood as obtaining all storage elements in the storage unit whose first voltage is greater than the voltage corresponding to the target voltage gear, and performing programming verification on the above storage elements according to the target voltage gear. Further, after executing step S610, it is determined whether the storage unit is passed by executing steps S620 and S630. The programming verification is performed according to the target voltage gear. For example, if the target voltage gear is the first gear, after executing step S610, all storage elements in the storage unit whose first voltage is greater than the voltage corresponding to the target voltage gear are obtained, and the first gear programming verification is performed on the above storage elements. Step S620 is executed. When the threshold voltages of the acquired storage elements are greater than or equal to the voltage corresponding to the first gear, it is determined that the storage unit has passed the first gear programming verification. Step S630 is executed. When there is a storage element in the acquired storage elements whose threshold voltage is less than the voltage corresponding to the first gear, it is determined that the storage unit has not passed the first gear programming verification, that is, there is a storage element corresponding to the programming data "10", "01", or "00" whose threshold voltage is less than the voltage corresponding to the first gear, then the storage unit has not passed the first gear programming verification.

[0068] It can be imagined that after a programming verification is performed on the target area according to the target voltage level, in order to reduce the operation area of ​​the next programming stage and the operation area of ​​the next programming verification performed according to the target voltage level, steps S610 to S630 can be performed in the traversal of step S520 to find the storage unit that fails the programming verification according to the target voltage level and is the first storage unit that fails the programming verification according to the target voltage level, and the address of the storage unit is recorded as the address of the first verification failure, and the first verification failure address is used as the starting address of the current programming according to the target voltage level and the starting address of the next programming verification, so that after a programming verification is performed on the target area according to the target voltage level, in order to reduce the operation area of ​​the next programming stage and the operation area of ​​the next programming verification performed according to the target voltage level, the execution time and power consumption of the entire "programming verification-programming" can be reduced. Therefore, when it is determined that the storage unit does not pass the programming verification and is the first storage unit that fails the programming verification, refer to Figure 5 , perform the following steps:

[0069] Step S700: Record the address of the storage unit as a first verification failure address.

[0070] It can be understood that in order to further reduce the execution time and power consumption of the entire "program verification-programming", the threshold voltage of the storage element in the storage unit can be greater than or equal to the voltage corresponding to the target voltage gear, and the programming data corresponding to the storage element whose threshold voltage corresponds to the first voltage can be updated during the programming verification stage. For example, if the target voltage gear is the first gear, when the programming data in the storage unit is "10", the threshold voltage of the storage element corresponding to the storage unit is greater than Vref1, and the first voltage is distributed in VT1, so the threshold voltage of the storage element corresponds to the first voltage, so the programming data corresponding to the storage element is updated, and when the programming data in the storage unit is "01", the threshold voltage of the storage element corresponding to the storage unit is greater than Vref1, but the first voltage is distributed in VT1. VT2, the threshold voltage of the storage element does not necessarily correspond to the first voltage, so the programming data corresponding to the storage element is not updated, and when the programming data in the storage unit is "00" and the threshold voltage of the corresponding storage element is greater than Vref1, the processing is the same. The threshold voltage corresponding to the storage element is distributed in VT3. The threshold voltage of the storage element does not necessarily correspond to the first voltage, so the programming data corresponding to the storage element is not updated. It is worth noting that updating the programming data corresponding to the storage element can be understood as updating the programming data corresponding to the storage element to "11". Because the programming data is "11", the embodiment of the present invention does not operate the storage element corresponding to the programming data, so the execution time and power consumption of the entire "programming verification-programming" are reduced. Therefore, when the threshold voltage of the storage element in the storage unit is greater than or equal to the voltage corresponding to the target voltage gear, and the threshold voltage of the storage element corresponds to the first voltage, refer to Figure 6, perform the following steps:

[0071] Step S800: updating the programming data corresponding to the storage element.

[0072] Furthermore, in one embodiment of the present invention, referring to Figure 7 , step S200 can be refined into the following steps:

[0073] Step S900 : selecting a voltage level from a plurality of voltage levels as a target voltage level according to the magnitudes of the threshold voltages corresponding to the voltage levels in ascending order.

[0074] A voltage range is selected from multiple voltage ranges as the target voltage range according to the size of the threshold voltage corresponding to the voltage range from small to large. It can be imagined that in the programming verification stage in "programming verification-programming", if the target voltage range is programmed and verified from small to large, such as first performing the first range programming verification on the target area, then performing the second range programming verification, and finally performing the third range programming verification, then after the first range programming verification, the analog voltage can be boosted to the second range voltage based on the voltage of the first range programming verification, and after the second range programming verification, the analog voltage can also be boosted to the third range voltage based on the voltage of the second range programming verification. Therefore, the switching time of the programming verification stage can be shortened, and the power consumption of the programming verification stage can be reduced. The execution of the programming stage also follows the same principle, so it will not be repeated.

[0075] It is conceivable that, referring to Figure 8 Before step S400, the following steps are also included:

[0076] Step S1000 , adjusting programming voltage parameters and programming time parameters for programming at a target voltage level.

[0077] It can be understood that when programming with the selected target voltage level, the programming voltage parameters and programming time parameters will affect the programming time and power consumption. If the programming voltage parameters are too large, the power consumption will increase. If the programming voltage parameters are too small, the programming time parameters will increase. Therefore, in a cycle of "programming verification-programming", before the programming stage, the programming voltage parameters and programming time parameters for programming with the target voltage level will be adjusted separately according to the results of the programming verification stage, so that the parameter settings for each cycle are optimal; these related parameters are selected from the optimal value data group obtained in advance according to the test, and step S1000 can also be understood as a step. If the target voltage level is the first level, the programming voltage parameter V1 and programming time parameter T1 set in the programming verification stage of "programming verification-programming" do not pass the programming verification according to the first level, then in the programming stage, another set of programming voltage parameters V2 and programming time parameters T2 are selected from the optimal value data group obtained in advance by the test to replace V1 and T1 accordingly.

[0078] The programming method of the embodiment of the present invention is described below with a practical example. This embodiment is divided into a programming verification phase and a programming phase. The programming verification phase is further divided into a first gear programming verification phase, a second gear programming verification phase, and a third gear programming verification phase. The programming phase is also divided into a first gear programming phase, a second gear programming phase, and a third gear programming phase.

[0079] The programming method of the embodiment of the present invention is applied to MLC, first obtaining a programming instruction, then using a cache to obtain programming data input by a user, obtaining a programming start address of a programming target area according to the programming data input by the user, i.e., an address of a starting storage unit determined according to the start data and a programming end address, and selecting a voltage range as a target voltage range according to the size of a threshold voltage corresponding to the voltage range from large to small, so the order of selecting the target voltage range is the first range, the second range, and the third range, the first range programming verification stage: setting the programming start address as the first failure verification address of the first range, and starting from the first failure verification address of the first range to the programming end address, judging whether the storage unit corresponding to the current address passes the first range programming verification according to the target voltage range being the first range. First, obtain the programming data of the storage element in the storage unit corresponding to the current address in the cache. If the storage element of the storage unit contains storage elements corresponding to the programming data "10", "01", and "00", that is, there is a storage element whose first voltage is greater than or equal to the voltage corresponding to the first gear, perform the first gear programming verification on the storage unit, and obtain the storage element corresponding to the programming data "10", "01", and "00" in the storage unit, and perform the first gear programming verification on the above storage element. When the storage element passes the first gear programming verification and the first voltage of the storage element corresponds to the threshold voltage of the storage element, the programming data corresponding to the storage element is updated to "11". In the next step, if the above storage elements of the storage unit have passed the first gear programming verification, If the first gear programming verification is performed, it is determined that the storage unit has passed the first gear programming verification. Otherwise, if there is a storage unit that has not passed the first gear programming verification, it is determined that the storage unit has not passed the first gear programming verification. If the storage unit corresponding to the current address has not passed the first gear programming verification, it is determined whether the storage unit is a storage unit that has not been successfully programmed in the first gear programming verification. If the storage unit corresponding to the current address is a storage unit that has not been successfully programmed in the first gear programming verification, the address of the storage unit is recorded as the first verification failure address of the first gear, and it is determined whether the current address is the end address. When it is determined that the current address is the programming end address, the second gear programming verification stage is entered, otherwise the current address is incremented.

[0080] Second gear programming verification stage: set the programming start address as the first failure verification address of the second gear, and start from the first failure verification address of the second gear to the programming end address, and judge whether the storage unit corresponding to the current address has passed the second gear programming verification according to the target voltage gear being the second gear. First, obtain the programming data of the storage element in the storage unit corresponding to the current address in the cache. If the storage element of the storage unit contains storage elements corresponding to the programming data of "01" and "00", that is, there is a storage element whose first voltage is greater than or equal to the voltage corresponding to the second gear, perform second gear programming verification on the storage unit, and obtain the storage element corresponding to the programming data of "01" and "00" in the storage unit, and perform second gear programming verification on the above storage element. When the storage element passes the second gear programming verification and the first voltage of the storage element corresponds to the threshold voltage of the storage element, then update the programming data corresponding to the storage element to "11". In the next step, if the above storage elements of the storage unit have passed the second gear programming verification, it is determined that the storage unit has passed the second gear programming verification; otherwise, if there is a storage unit that has not passed the second gear programming verification, it is determined that the storage unit has not passed the second gear programming verification; if the storage unit corresponding to the current address has not passed the second gear programming verification, it is determined whether the storage unit is a storage unit that has not been successfully verified for the first second gear programming; if the storage unit corresponding to the current address is a storage unit that has not been successfully verified for the first second gear programming, the address of the storage unit is recorded as the first verification failure address of the second gear, and it is determined whether the current address is the end address; when it is determined that the current address is the programming end address, the third gear programming verification stage is entered, otherwise the current address is incremented.

[0081] The third gear programming verification stage: set the programming start address as the first failure verification address of the third gear, and start from the first failure verification address of the third gear to the programming end address, and judge whether the storage unit corresponding to the current address has passed the third gear programming verification according to the target voltage gear being the third gear. First, obtain the programming data of the storage element in the storage unit corresponding to the current address in the cache. If the storage element of the storage unit contains the storage element corresponding to the programming data of "00", that is, there is a storage element whose first voltage is greater than or equal to the voltage corresponding to the third gear, perform the third gear programming verification on the storage unit, and obtain the storage element corresponding to the programming data of "00" in the storage unit, and perform the third gear programming verification on the above storage element. When the storage element passes the third gear programming verification and the first voltage of the storage element corresponds to the threshold voltage of the storage element, the programming data corresponding to the storage element is updated to "11". In the next step, if the above storage elements of the storage unit all pass the third gear programming verification, it is determined that the storage unit has passed the third gear programming verification, and vice versa. In other words, if there is a storage element that fails the third-level programming verification, it is determined that the storage unit fails the third-level programming verification. If the storage unit corresponding to the current address fails the third-level programming verification, it is determined whether the storage unit is a storage unit that failed the first third-level programming verification. If the storage unit corresponding to the current address is a storage unit that failed the first third-level programming verification, the address of the storage unit is recorded as the first verification failure address of the third level, and it is determined whether the current address is the programming end address. When the current address is not the end address, the current address is incremented. When the current address is the programming end address, it is determined whether the programming data in the cache are all updated to "11" or the storage units from the programming start address to the programming end address have passed the programming verification of the first, second, and third levels. When the data in the cache are all updated to "11" or the storage units from the programming start address to the programming end address have passed the programming verification of the first, second, and third levels, the implementation example of the present invention ends, otherwise it enters the programming stage.

[0082] Before executing the programming stage, the programming voltage parameters and programming time parameters of the target gear are adjusted respectively according to the results of the previous first gear programming verification, the results of the second gear programming verification, and the results of the third gear programming verification. That is, if there are storage cells that fail the first gear programming verification, the programming voltage parameters and programming time of the first gear are adjusted to improve the pass rate of the next first gear programming verification. The adjustment of other gears is the same, so it will not be repeated here.

[0083] First gear programming stage: from the beginning of the first verification failure address of the first gear to the end of the programming address, the current address is programmed in the first gear according to the target voltage gear. If the programming data corresponding to the storage element in the storage unit corresponding to the current address is "10", "01", or "00", then the storage element with the programming data of "10", "01", or "00" in the storage unit, that is, the storage element with the first voltage greater than the voltage corresponding to the first gear, is programmed in the first gear to determine whether the current address is the end of programming address. If the current address is the end of programming address, the second gear programming stage is entered, otherwise the current address is incremented.

[0084] Second gear programming stage: from the beginning of the first verification failure address of the second gear to the end of the programming address, the current address is programmed in the second gear according to the target voltage gear of the second gear. If the programming data corresponding to the storage element in the storage unit corresponding to the current address is "01" or "00", then the storage element with the programming data of "01" or "00" in the storage unit, that is, the storage element with the first voltage greater than the voltage corresponding to the second gear, is programmed in the first gear to determine whether the current address is the end of programming address. If the current address is the end of programming address, the third gear programming stage is entered, otherwise the current address is incremented.

[0085] The third gear programming stage: starting from the first verification failure address of the third gear to the programming end address, the current address is programmed in the third gear according to the target voltage gear of the third gear. If the programming data corresponding to the storage element in the storage unit corresponding to the current address is "00", the storage element with the programming data "00" in the storage unit, that is, the storage element with the first voltage greater than the voltage corresponding to the third gear, is programmed in the third gear to determine whether the current address is the programming end address. If the current address is not the programming end address, the current address is incremented. If the current address is the programming end address, the program returns to the programming verification stage.

[0086] Reference Figure 9The present invention also provides a programming system for a multi-bit non-volatile memory having multiple voltage levels. The programming system includes: a storage module 110, which is a memory cell array for storing data; a selection module 120, which selects a memory cell that currently needs to be program-verified or programmed by address decoding; a comparator module 130, which is configured to output a comparison result based on the threshold voltage of a memory cell in the memory cell selected by the selection module and a voltage reference value or a current reference value; a reference module 140, which is configured to provide the comparator module with a corresponding voltage reference value or current reference value for the programming verification; a cache module 150, which is configured to store programming data and the comparison result; an operation module 160, which is configured to update the programming data corresponding to the current memory cell based on the comparison result; a programming module 170, which programs the memory cell selected by the selection module based on the programming data in the cache module, the comparison result, and the target level voltage of the simulation module; an simulation module 180, which is configured to provide a target level voltage to the programming selection module and provide a corresponding analog voltage to the memory cell in the memory cell of the storage module; and a programming control module. Figure 9 Not shown, used to execute the aforementioned programming method.

[0087] It can be understood that in one embodiment of the present invention, the analog module provides a corresponding analog voltage to the storage element of the storage unit in the storage module 110 to obtain the threshold voltage of the storage element. It can be understood that after the storage element is added with the analog voltage, the current value of the threshold voltage corresponding to the storage element is obtained. Then it can be imagined that the reference module 140 provides the comparator module 130 with the current reference value corresponding to the corresponding voltage reference value, and the comparator module 130 can judge whether the threshold voltage of the storage element is greater than or equal to the voltage reference value based on the current value of the threshold voltage corresponding to the storage element obtained above and the current reference value.

[0088] An embodiment of the present invention also provides a programming device, which is applied to a multi-bit non-volatile memory, which has multiple voltage levels and includes at least one processor and a memory for communicating with the at least one processor; the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the aforementioned programming method.

[0089] Reference Figure 10, taking the example that the control processor 1001 and the memory 1002 in the programming device 1000 can be connected via a bus. The memory 1002, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer executable programs. In addition, the memory 1002 may include a high-speed random access memory, and may also include a non-transitory memory, such as at least one disk memory, a flash memory device, or other non-transitory solid-state memory device. In some embodiments, the memory 1002 may optionally include a memory remotely located relative to the control processor 1001, and these remote memories may be connected to the programming device 1000 via a network. Examples of the above-mentioned networks include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0090] Those skilled in the art will understand that Figure 10 The device structure shown in the figure does not constitute a limitation on the programming device 1000, and may include more or fewer components than shown in the figure, or combine certain components, or arrange the components differently.

[0091] The embodiment of the present invention further provides a computer-readable storage medium, which stores computer-executable instructions. The computer-executable instructions are executed by one or more control processors, for example, Figure 10 The execution of one of the control processors 1001 can cause the one or more control processors to execute the programming method in the above method embodiment, for example, to execute the above described Figure 2 Steps S100 to S400 of the method, Figure 3 Steps S510 to S520 of the method, Figure 4 Steps S610 to S630 of the method, Figure 5 Method step S700, Figure 6 Method step S800, Figure 7 Method step S900 and Figure 8 Method step S1000 in .

[0092] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, i.e., they may be located in one place or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of this embodiment.

[0093] Those skilled in the art will appreciate that all or some of the steps and systems in the method disclosed above can be implemented as software, firmware, hardware, and appropriate combinations thereof. Some physical components or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor, or a microprocessor, or implemented as hardware, or implemented as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, and the computer-readable medium can include computer storage media (or non-transitory media) and communication media (or temporary media). As known to those skilled in the art, the term computer storage media is included in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data) and is volatile and non-volatile, removable, and non-removable. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory, or other memory technology, CD-ROM, digital versatile disks (DVD), or other optical disk storage, magnetic cassettes, magnetic tapes, disk storage, or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, as is well known to those skilled in the art, communication media typically embodies computer-readable instructions, data structures, program modules, or other data in a modulated data signal such as a carrier wave or other transport mechanism, and may include any information delivery media.

[0094] The above is a specific description of the preferred implementation of the present application, but the present application is not limited to the above implementation mode. Technical personnel familiar with the field can also make individual equivalent modifications or substitutions without violating the spirit of the present application. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present application.

Claims

1. A programming method, applied to a multi-bit non-volatile memory, wherein the multi-bit non-volatile memory has multiple voltage levels, the programming method comprising: Acquire programming data in a cache and a target area in the multi-bit non-volatile memory corresponding to the programming data; selecting a voltage level from the plurality of voltage levels as a target voltage level in ascending order of the threshold voltages corresponding to the voltage levels; performing program verification on all memory cells corresponding to the programming data in the target area according to the programming data, the target voltage level, and a correspondence between the programming data and addresses of the memory cells in the target area; When all voltage levels are selected as target voltage levels and programming verification is performed, determining whether the memory cells in the target area pass the programming verification according to each programming verification result; When there are storage cells that fail the programming verification, the starting address of the storage cells that fail the verification is determined, and the storage cells in the target area are programmed according to the programming data in the cache in ascending order of the threshold voltage corresponding to the voltage level, starting from the starting address and ending at the programming end address.

2. The programming method according to claim 1, wherein: The performing program verification on all the memory cells corresponding to the programming data in the target area according to the programming data, the target voltage level, and the correspondence between the programming data and the addresses of the memory cells in the target area includes: determining a starting memory cell in the target area according to starting data of the programming data; The address of the starting memory cell is used as the starting address, and the programming verification is performed sequentially on all memory cells in the target area according to the target voltage level in an address increment manner.

3. The programming method according to claim 2, wherein: The method of performing the programming verification on the storage unit includes: When the first voltage is greater than or equal to the voltage corresponding to the target voltage level, performing the programming verification on the memory element of the memory unit according to the target voltage level, the first voltage being a threshold voltage of the programming data corresponding to the memory element; When the threshold voltages of all the memory cells are greater than or equal to the voltage corresponding to the target voltage level, it is determined that the memory cell passes the programming verification; When there is a memory cell whose threshold voltage is lower than the voltage corresponding to the target voltage level, it is determined that the memory cell fails the programming verification.

4. The programming method according to claim 3, wherein: When it is determined that a storage cell fails the programming verification and is the first storage cell that fails the programming verification, the address of the storage cell is recorded as the first verification failure address, and the first verification failure address is used as the starting address for the programming this time according to the target voltage level and the starting address for the next programming verification.

5. The programming method according to claim 3, wherein: When the threshold voltage of a memory cell in a memory unit is greater than or equal to the voltage corresponding to the target voltage level, and the threshold voltage of the memory cell corresponds to the first voltage, the programming data corresponding to the memory cell is updated.

6. The programming method according to claim 1, wherein: Before programming all the memory cells in the target area according to the programming data in the cache and the target voltage level when there are memory cells that fail the programming verification, the method further includes: Adjust the programming voltage parameters and programming time parameters for programming at the target voltage level.

7. A programming system, applied to a multi-bit non-volatile memory, wherein the multi-bit non-volatile memory has multiple voltage levels, characterized in that: The programming system comprises: A storage module is a storage cell array for storing data; A selection module selects the storage unit that currently needs to be programmed or verified by address decoding; a comparator module, configured to output a comparison result according to the threshold voltage of the storage element in the storage unit selected by the selection module and the voltage reference value or the current reference value; A reference module, configured to provide the comparator module with a corresponding voltage reference value or current reference value for the programming verification; a cache module, configured to store programming data and the comparison result; an operation module, configured to update the programming data corresponding to the current storage unit according to the comparison result; a programming module, configured to program the storage unit selected by the selection module according to the programming data in the cache module, the comparison result, and the target gear voltage of the simulation module; An analog module, configured to provide a target voltage level to the programming selection module and provide a corresponding analog voltage to a memory cell of a memory unit in the memory module; A programming control module, configured to execute the programming method according to any one of claims 1 to 6.

8. A programming device, applied to a multi-bit non-volatile memory, wherein the multi-bit non-volatile memory has multiple voltage levels, characterized in that: comprising at least one processor and a memory for communicatively coupling with the at least one processor; The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the programming method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer-executable instructions, and the computer-executable instructions are used to enable a computer to execute the programming method according to any one of claims 1 to 6.

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