A semiconductor device and a manufacturing method thereof

Abstract

The application provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a sacrificial film layer stacked above a substrate, and a capacitor hole penetrating through the sacrificial film layer from top to bottom. A landing pad is formed in the substrate, and the capacitor hole is in communication with the landing pad. A lower electrode is further included, which comprises a portion formed in the capacitor hole and in contact with the landing pad, and a portion extending upward along the sidewall of the capacitor hole and exposed outside the capacitor hole. The lower electrode is composed of the portion in the capacitor hole and the portion extending upward along the sidewall of the capacitor hole and exposed outside the capacitor hole by retaining part of the sacrificial film layer. Since the sacrificial film layer is partially retained, it surrounds the lower portion of the lower electrode, supports the lower electrode, prevents the lower electrode from tilting, and prevents the capacitor from collapsing when a dielectric layer and an upper electrode are deposited on the lower electrode in subsequent processes.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor device and its manufacturing method. Background Technology

[0002] A capacitor is a component that can store electrical charge and energy. Different voltages can be applied to the two electrodes of a capacitor, causing it to store different amounts of charge. Based on this, capacitors can be used to store different types of data. Therefore, the quality of a capacitor directly affects the data storage performance of semiconductor devices.

[0003] To improve memory drive performance, the capacitance of capacitors needs to be increased. A common way to increase capacitor capacitance is to increase the capacitor's height. However, increasing the capacitor's height leads to an increase in its aspect ratio. An increased aspect ratio can cause problems such as capacitor tilting, bending, or even collapse during the wet cleaning process. Summary of the Invention

[0004] This invention provides a semiconductor device and a method for manufacturing the same, used to prevent capacitors from tilting, bending, or collapsing.

[0005] In a first aspect, the present invention provides a semiconductor device including a sacrificial film layer stacked on top of a substrate and a capacitor via extending downward through the sacrificial film layer. A landing pad is formed in the substrate, and the capacitor via communicates with the landing pad. The semiconductor device further includes a lower electrode comprising a portion formed within the capacitor via and in contact with the landing pad, and a portion extending upward along the sidewall of the capacitor via and exposed outside the capacitor via.

[0006] In the above scheme, by retaining a portion of the sacrificial film layer, the lower electrode consists of a portion inside the capacitor aperture and a portion extending upwards along the sidewall of the aperture and exposed outside the aperture. Because the sacrificial film layer is partially retained, it surrounds the lower portion of the lower electrode, providing support and preventing tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode, the sacrificial film layer surrounding the lower portion also prevents bending deformation of the lower electrode, thereby preventing capacitor collapse. In application, because the sacrificial film layer surrounding the lower portion supports the lower electrode, the capacitor structure is relatively robust, allowing for a suitable increase in the aspect ratio of the stacked capacitor to increase capacitance and improve storage performance.

[0007] In one specific embodiment, a first etch barrier layer is stacked on the sacrificial film layer; the capacitor via penetrates the first etch barrier layer and the sacrificial film layer sequentially from top to bottom and then communicates with the landing pad. This allows for the removal of part of the sacrificial film layer and the retention of part of the sacrificial film layer during the manufacturing process, forming a lower electrode consisting of two parts: inside and outside the capacitor via.

[0008] In one specific embodiment, a second etch barrier layer is also stacked between the sacrificial film layer and the substrate, and the capacitor via passes through the first etch barrier layer, the sacrificial film layer, and the second etch barrier layer sequentially from top to bottom before connecting to the landing pad. By stacking the second etch barrier layer between the sacrificial film layer and the substrate, subsequent etching or cleaning operations can be prevented from affecting the substrate, ensuring substrate quality.

[0009] In one specific embodiment, the materials of the first etch barrier layer and the second etch barrier layer are SiN, SiBN or SiCN, in order to improve the barrier effect during etching.

[0010] In one specific embodiment, the height of the portion of the lower electrode located inside the capacitor hole is h1, and the height of the portion of the lower electrode exposed outside the capacitor hole is h2; wherein, (h1+h2)×50%≤h1≤(h1+h2)×70%. This ensures the supporting effect of the retained sacrificial film layer on the lower electrode, while simultaneously increasing the capacitance of the capacitor.

[0011] In one specific embodiment, the lower electrode is cylindrical in shape; its bottom wall contacts the landing pad, and a portion of its sidewall contacts the sidewall of the capacitor aperture, with a portion exposed outside the aperture. An upper electrode and a dielectric layer insulating the lower electrode from the upper electrode are formed on the bottom wall, inner sidewall, and the exposed portion of the sidewall of the lower electrode. By providing capacitor structures on both the inner and outer sides of the lower electrode, the capacitance of the capacitor is increased, thereby improving storage performance.

[0012] In one specific implementation, the semiconductor device is a dynamic random access memory (DRAM) to prevent the capacitor in the DRAM from collapsing due to tilting, bending, or other reasons related to the lower electrode.

[0013] In a second aspect, the present invention also provides a method for manufacturing a semiconductor device, the method comprising: providing a substrate in which a landing pad is formed; forming a sacrificial film layer covering the substrate above the substrate; etching the sacrificial film layer from top to bottom to form a capacitor hole communicating with the landing pad; forming a lower electrode in the capacitor hole that contacts the landing pad; and removing a portion of the sacrificial film layer so that the lower electrode is partially located inside the capacitor hole and partially exposed outside the capacitor hole.

[0014] In the above scheme, by retaining a portion of the sacrificial film layer, the lower electrode consists of a portion inside the capacitor aperture and a portion extending upwards along the sidewall of the aperture and exposed outside the aperture. Because the sacrificial film layer is partially retained, it surrounds the lower portion of the lower electrode, providing support and preventing tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode, the sacrificial film layer surrounding the lower portion also prevents bending deformation of the lower electrode, thereby preventing capacitor collapse. In application, because the sacrificial film layer surrounding the lower portion supports the lower electrode, the capacitor structure is relatively robust, allowing for a suitable increase in the aspect ratio of the stacked capacitor to increase capacitance and improve storage performance.

[0015] In one specific embodiment, a first etch barrier layer is formed inside the sacrificial film layer, and the capacitor via extends from top to bottom through the sacrificial film layer and the first etch barrier layer before communicating with the landing pad. Removing a portion of the sacrificial film layer, so that the lower electrode portion is located inside the capacitor via and partially exposed outside, specifically involves removing the portion of the sacrificial film layer above the first etch barrier layer, so that the lower electrode portion is located inside the capacitor via and partially exposed outside. This facilitates the removal of a portion of the sacrificial film layer and the retention of a portion of the sacrificial film layer during the manufacturing process, forming a lower electrode composed of both the portion inside and the portion outside the capacitor via.

[0016] In one specific embodiment, removing the portion of the sacrificial film layer above the first etch barrier layer, so that the lower electrode portion is located inside the capacitor hole and partially exposed outside the capacitor hole, specifically involves etching the portion of the sacrificial film layer above the first etch barrier layer using plasma etching or wet etching, thereby improving the removal efficiency of the portion of the sacrificial film layer above the first etch barrier layer.

[0017] In one specific embodiment, before forming a sacrificial film layer covering the substrate on top of the substrate, the manufacturing method further includes forming a second etch barrier layer covering the substrate on the substrate. Etching the sacrificial film layer from top to bottom to form a capacitor via communicating with the landing pad specifically involves etching the sacrificial film layer, the first etch barrier layer, and the second etch barrier layer from top to bottom to form the capacitor via communicating with the landing pad. By stacking the second etch barrier layer between the sacrificial film layer and the substrate, subsequent etching or cleaning operations can be prevented from affecting the substrate, ensuring substrate quality.

[0018] In one specific embodiment, forming a lower electrode that contacts the landing pad within the capacitor via includes: depositing a lower electrode material layer on the sacrificial film layer and on the bottom and inner wall of the capacitor via; and removing the portion of the lower electrode material layer located outside the capacitor via using plasma etching or wet etching to form the lower electrode. This facilitates the removal of the portion of the lower electrode material layer located outside the capacitor via. Attached Figure Description

[0019] Figure 1a This is a schematic diagram of one step in the manufacturing process of a capacitor in the prior art;

[0020] Figure 1b This is a schematic diagram of another step in the manufacturing process of capacitors in the prior art;

[0021] Figure 1c This is a schematic diagram of another step in the manufacturing process of capacitors in the prior art;

[0022] Figure 1d This is a schematic diagram of another step in the manufacturing process of capacitors in the prior art;

[0023] Figure 1e This is a schematic diagram of another step in the manufacturing process of capacitors in the prior art;

[0024] Figure 2a This is a schematic diagram of the structure of a semiconductor device provided in an embodiment of the present invention;

[0025] Figure 2b for Figure 2a A schematic diagram of a semiconductor device as seen from a top view is provided in the image.

[0026] Figure 3 This is a schematic diagram of a step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0027] Figure 4a This is a schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0028] Figure 4b for Figure 4a A schematic diagram of a semiconductor device as seen from a top view is provided in the image.

[0029] Figure 5 This is a schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0030] Figure 6 This is a schematic diagram of another step in a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0031] Figures 1a-1e Figure labels in the diagram:

[0032] 1-Substrate 2-Etching barrier layer 3-Sacrificial film layer

[0033] 4-Capacitor hole; 5-Lower electrode material layer; 6-Lower electrode

[0034] Figures 2a to 6Figure labels in the diagram:

[0035] 10-Substrate 11-Landing Pad 12-Isolation Section 20-Sacrificial Film Layer

[0036] 30 - Capacitor hole; 40 - Lower electrode; 41 - Lower electrode material layer

[0037] 51-First etch barrier layer 52-Second etch barrier layer Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0039] To facilitate understanding of the semiconductor device provided in the embodiments of the present invention, the application scenario of the semiconductor device provided in the embodiments of the present invention will be described first. This semiconductor device is applied in a memory with capacitors. The semiconductor device will then be described in detail with reference to the accompanying drawings.

[0040] refer to Figure 2a and Figure 2b The semiconductor device provided in this embodiment of the invention includes a sacrificial film layer 20 stacked on top of a substrate 10, and a capacitor hole 30 extending downward through the sacrificial film layer 20. A landing pad 11 is formed in the substrate 10, and the capacitor hole 30 communicates with the landing pad 11. The semiconductor device also includes a lower electrode 40, which includes a portion formed within the capacitor hole 30 and in contact with the landing pad 11, and a portion extending upward along the sidewall of the capacitor hole 30 and exposed outside the capacitor hole 30.

[0041] In the above scheme, by retaining a portion of the sacrificial film layer 20, the lower electrode 40 consists of a portion within the capacitor aperture 30 and a portion extending upwards along the sidewall of the capacitor aperture 30 and exposed outside the capacitor aperture 30. Since the sacrificial film layer 20 is partially retained, it surrounds the lower portion of the lower electrode 40, providing support and preventing tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 also prevents bending and deformation, thereby preventing capacitor collapse. In application, because the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 provides support, the capacitor structure is relatively robust, allowing for a suitable increase in the aspect ratio of the stacked capacitor to increase capacitance and improve storage performance. The following section, in conjunction with the accompanying drawings, provides a detailed description of the configuration of each of the above structures.

[0042] The substrate 10 can be a structure comprising a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, etc. The substrate 10 can also be a stacked structure in which a partial semiconductor structure has already been formed. For example, see reference... Figure 2a The substrate 10 may include at least a semiconductor substrate, a transistor, a bit line structure, a memory contact, an insulating portion, a landing pad 11, and an isolation portion 12. The transistor may be formed on the semiconductor substrate of the semiconductor device. The bit line structure may be formed above the transistor. The memory contact and the insulating portion are formed between adjacent bit line structures. The memory contact contacts the source or drain region of the transistor. The insulating portion isolates two adjacent memory contacts. Simultaneously, each landing pad 11 is formed on its corresponding memory contact. The landing pad 11 is electrically connected to the source or drain region of the transistor through the memory contact. The isolation portion 12 is formed on the bit line structure and the insulating portion, and the isolation portion 12 isolates two adjacent landing pads 11.

[0043] Continue to refer to Figure 2a A sacrificial film layer 20 is stacked on top of the substrate 10. A capacitor hole 30 extends from top to bottom through the sacrificial film layer 20 and communicates with the landing pad 11. A lower electrode 40 is formed within the capacitor hole 30. The lower electrode 40 mainly comprises two parts: one part is formed within the capacitor hole 30 and contacts the landing pad 11, and the other part extends upward along the sidewall of the capacitor hole 30 and is exposed outside the capacitor hole 30. The shape of the lower electrode 40 can be cylindrical. The bottom wall of the lower electrode 40 contacts the landing pad 11, and a portion of the sidewall of the lower electrode 40 contacts the sidewall of the capacitor hole 30 and is partially exposed outside the capacitor hole 30.

[0044] Existing methods for manufacturing capacitors include: Figures 1a-1e As shown, for reference Figure 1aFirst, an etching barrier layer 2 and a sacrificial film layer 3 are deposited on substrate 1; then, referencing Figure 1b Etching the sacrificial film layer 3 and the barrier layer 2 forms the capacitor hole 4; then, referencing Figure 1c Electrode material layer 5 is deposited on the sacrificial film layer 3, the inner wall and bottom wall of the capacitor hole 4; then, referring to Figure 1d Remove the lower electrode material layer 5 outside the capacitor hole 4 to form the lower electrode 6; then, refer to Figure 1e The sacrificial film layer 3 is removed; subsequently, a dielectric layer and an upper electrode are deposited on the lower electrode 6 to form a capacitor.

[0045] By using existing technologies Figure 1e The semiconductor device shown is related to the present invention. Figure 2a As can be seen from the comparison of the semiconductor devices shown, the sacrificial film layer 20 in the scheme disclosed in this invention surrounds the lower electrode 40 on the outer wall of the portion of the capacitor hole 30, providing support for the lower electrode 40 and preventing it from tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 also prevents the lower electrode 40 from bending and deforming, thereby preventing the capacitor from collapsing. In application, because the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 supports the lower electrode 40, the capacitor structure is relatively robust, allowing for a suitable increase in the aspect ratio of the stacked capacitor to increase the capacitance and improve storage performance.

[0046] like Figure 2a and Figure 2b As shown, a first etch barrier layer 51 can be stacked on the sacrificial film layer 20. In this case, the capacitor hole 30 passes through the first etch barrier layer 51 and the sacrificial film layer 20 sequentially from top to bottom and connects to the landing pad 11. By stacking the first etch barrier layer 51 on the sacrificial film layer 20, it is possible to remove part of the sacrificial film layer 20 during manufacturing, leaving part of it intact, forming the lower electrode 40 composed of the inner and outer parts of the capacitor hole 30. This also prevents subsequent etching or cleaning operations from affecting the substrate 10, ensuring the quality of the substrate 10. It should be understood that the first etch barrier layer 51 may not be provided on the sacrificial film layer 20. When determining the material of the first etch barrier layer 51, the material can be SiN, SiBN, or SiCN to improve the blocking effect during etching.

[0047] Continue to refer to Figure 2aAlternatively, a second etch barrier layer 52 can be stacked between the sacrificial film layer 20 and the substrate 10, and the capacitor via 30 passes through the first etch barrier layer 51, the sacrificial film layer 20, and the second etch barrier layer 52 sequentially from top to bottom before connecting to the landing pad 11. In this case, the sacrificial film layer 20 is not directly disposed on the substrate 10; the sacrificial film layer 20 and the substrate 10 are separated by the second etch barrier layer 52. By stacking the second etch barrier layer 52 between the sacrificial film layer 20 and the substrate 10, subsequent etching or cleaning operations can be prevented from affecting the substrate 10, ensuring the quality of the substrate 10. When determining the material of the second etch barrier layer 52, the material of the second etch barrier layer 52 can be SiN, SiBN, or SiCN to improve the blocking effect during etching. It should be noted that the sacrificial film layer 20 can also be in direct contact with the substrate 10, i.e., without an etch barrier layer separating the sacrificial film layer 20 and the substrate 10.

[0048] When further forming the dielectric layer and the upper electrode on the lower electrode 40, the upper electrode and the dielectric layer insulating and isolating the lower electrode 40 from the upper electrode can be formed on the bottom wall, inner side wall, and side wall exposed outside the capacitor hole 30 of the lower electrode 40, thereby completing the manufacture of the capacitor. That is, the portion of the lower electrode 40 located in the capacitor hole 30 has the dielectric layer and the upper electrode formed only on the inner side wall and the bottom wall, while the portion of the lower electrode 40 exposed outside the capacitor hole 30 has the dielectric layer and the upper electrode formed not only on the inner side wall but also on the outer side wall. By providing capacitor structures on both the inner and outer sides of the lower electrode 40, the capacitance of the capacitor is increased, and the storage effect is improved. It should be understood that the manner in which the dielectric layer and the upper electrode are formed is not limited to the above-described manner; other methods can also be used. For example, the dielectric layer and the upper electrode can be formed only on the inner side wall and the bottom wall of the lower electrode 40, and no dielectric layer and the upper electrode can be formed on the outer side wall of the lower electrode 40.

[0049] When determining the heights of the two main parts of the lower electrode 40, reference is made to... Figure 2aWe can assume that the height of the portion of the lower electrode 40 located within the capacitor hole 30 is h1, that is, the vertical distance between the surface of the lower electrode 40 in contact with the landing pad 11 and the cross-section of the lower electrode 40 in contact with the upper edge of the capacitor hole 30 is h1. The height of the portion of the lower electrode 40 exposed outside the capacitor hole 30 is h2, that is, the vertical distance between the cross-section of the lower electrode 40 in contact with the upper edge of the capacitor hole 30 and the surface of the uppermost edge of the lower electrode 40 is h2. We can set h1 and h2 to satisfy (h1+h2)×50%≤h1≤(h1+h2)×70%, that is, the height h1 of the portion of the lower electrode 40 located within the capacitor hole 30 accounts for 50% to 70% of the total height of the lower electrode 40. Specifically, h1 can be set to any value between 50% and 70% of the total height of the lower electrode 40, such as h1 = (h1+h2)×50%, h1 = (h1+h2)×55%, h1 = (h1+h2)×60%, h1 = (h1+h2)×65%, h1 = (h1+h2)×70%. When the relationship between the heights of the two parts of the lower electrode 40 satisfies the above relationship, the sacrificial film layer 20 can surround the outer wall of the lower electrode 40 at a suitable height, supporting the lower electrode 40 and ensuring the supporting effect of the remaining portion of the sacrificial film layer 20 on the lower electrode 40. At the same time, the height of the portion of the lower electrode 40 exposed outside the capacitor hole 30 is made more suitable. Since the portion of the lower electrode 40 exposed outside the capacitor hole 30 can be evenly provided with upper electrodes on the inner and outer walls of the lower electrode 40, the surface area of ​​the lower electrode 40 relative to the upper electrode position is increased, thereby increasing the capacitance of the capacitor.

[0050] When determining the type of semiconductor device, it can be a dynamic random access memory (DRAM) to prevent capacitor collapse caused by tilting or bending of the lower electrode 40. The semiconductor device can also be a static random-access memory (SRAM), flash memory, or other memory that uses capacitors as storage cells.

[0051] By retaining a portion of the sacrificial film layer 20, the lower electrode 40 consists of a portion within the capacitor aperture 30 and a portion extending upwards along the sidewall of the capacitor aperture 30 and exposed outside the capacitor aperture 30. Since the sacrificial film layer 20 is partially retained, it surrounds the lower portion of the lower electrode 40, providing support and preventing tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 also prevents bending and deformation, thereby preventing capacitor collapse. In application, because the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 provides support, the capacitor structure is more robust, allowing for a more appropriate increase in the aspect ratio of the stacked capacitor to increase capacitance and improve storage performance.

[0052] In addition, embodiments of the present invention also provide a method for manufacturing a semiconductor device, see reference. Figures 2a to 6 The manufacturing method includes:

[0053] Step 1: Provide a substrate 10, and form a landing pad 11 in the substrate 10;

[0054] Step 2: A sacrificial film layer 20 covering the substrate 10 is formed on top of the substrate 10;

[0055] Step 3: Etch the sacrificial film layer 20 from top to bottom to form a capacitor hole 30 that communicates with the landing pad 11;

[0056] Step 4: Form the lower electrode 40 within the capacitor hole 30, which contacts the landing pad 11;

[0057] Step 5: Remove part of the sacrificial film layer 20 so that the lower electrode 40 is partially located inside the capacitor hole 30 and partially exposed outside the capacitor hole 30.

[0058] In the above scheme, by retaining a portion of the sacrificial film layer 20, the lower electrode 40 consists of a portion within the capacitor aperture 30 and a portion extending upwards along the sidewall of the capacitor aperture 30 and exposed outside the capacitor aperture 30. Since the sacrificial film layer 20 is partially retained, it surrounds the lower portion of the lower electrode 40, providing support and preventing tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 also prevents bending and deformation, thereby preventing capacitor collapse. In application, because the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 provides support, the capacitor structure is relatively robust, allowing for a suitable increase in the aspect ratio of the stacked capacitor to increase capacitance and improve storage performance. Each step described above will be explained in detail below with reference to the accompanying drawings.

[0059] First, refer to Figure 3A substrate 10 is provided in which landing pads 11 are formed. The substrate 10 can be a structure comprising a single semiconductor material, such as a monocrystalline silicon substrate 10, a polycrystalline silicon substrate 10, etc. The substrate 10 can also be a multilayer structure in which partial semiconductor structures have already been formed. For example, see reference... Figure 3 The substrate 10 may include at least a semiconductor substrate, a transistor, a bit line structure, a memory contact, an insulating portion, a landing pad 11, and an isolation portion 12. The transistor may be formed on the semiconductor substrate of the semiconductor device. The bit line structure may be formed above the transistor. The memory contact and the insulating portion are formed between adjacent bit line structures. The memory contact contacts the source or drain region of the transistor. The insulating portion isolates two adjacent memory contacts. Simultaneously, each landing pad 11 is formed on its corresponding memory contact. The landing pad 11 is electrically connected to the source or drain region of the transistor through the memory contact. The isolation portion 12 is formed on the bit line structure and the insulating portion, and the isolation portion 12 isolates two adjacent landing pads 11.

[0060] Next, continue to refer to Figure 3 A sacrificial film layer 20 is formed over the substrate 10, covering the substrate 10. The sacrificial film layer 20 can be formed by deposition. (See reference...) Figure 3 A first etching barrier layer 51 can be formed inside the sacrificial film layer 20 to facilitate the removal of part of the sacrificial film layer 20 and the retention of part of the sacrificial film layer 20 in subsequent processes.

[0061] Before forming the sacrificial film layer 20 covering the substrate 10, a second etch barrier layer 52 covering the substrate 10 can be formed on the substrate 10. In this case, the sacrificial film layer 20 is not directly disposed on the substrate 10; the sacrificial film layer 20 and the substrate 10 are separated by the second etch barrier layer 52. By stacking the second etch barrier layer 52 between the sacrificial film layer 20 and the substrate 10, subsequent etching or cleaning operations can be prevented from affecting the substrate 10, ensuring the quality of the substrate 10. When determining the material of the second etch barrier layer 52, SiN, SiBN, or SiCN can be selected to improve the blocking effect during etching. It should be noted that the sacrificial film layer 20 can also be in direct contact with the substrate 10, i.e., without an etch barrier layer separating the sacrificial film layer 20 and the substrate 10.

[0062] Next, refer to Figure 4a and Figure 4bThe sacrificial film layer 20 is etched from top to bottom to form a capacitor hole 30 communicating with the landing pad 11. If a second etch barrier layer 52 is provided between the sacrificial film layer 20 and the landing pad 11, the second etch barrier layer 52 also needs to be etched to make the capacitor hole 30 communicate with the landing pad 11. If a first etch barrier layer 51 is formed within the sacrificial film layer 20, the first etch barrier layer 51 also needs to be etched to form a capacitor hole 30 that runs vertically through the entire structure.

[0063] Next, refer to Figure 5 and Figure 6 A lower electrode 40 is formed within the capacitor hole 30, contacting the landing pad 11. For details, refer to... Figure 5 Electrode material layer 41 can be deposited first on the bottom and inner wall of the sacrificial film layer 20 and the capacitor hole 30. (Reference) Figure 6 Then, the portion of the lower electrode material layer 41 located outside the capacitor hole 30 is removed to form the lower electrode 40. Plasma etching or wet etching can be used to remove the portion of the lower electrode material layer 41 located outside the capacitor hole 30.

[0064] Next, refer to Figure 2a and Figure 2b A portion of the sacrificial film layer 20 is removed, so that the lower electrode 40 is partially located inside the capacitor hole 30 and partially exposed outside the capacitor hole 30. When a first etch barrier layer 51 is formed inside the sacrificial film layer 20, the portion of the sacrificial film layer 20 above the first etch barrier layer 51 can be removed, while the portion of the sacrificial film layer 20 below the first etch barrier layer 51 is retained, so that the lower electrode 40 is partially located inside the capacitor hole 30 and partially exposed outside the capacitor hole 30. When determining the material of the first etch barrier layer 51, the material of the first etch barrier layer 51 can be SiN, SiBN, or SiCN to improve the blocking effect during etching. Plasma etching or wet etching can be used to etch the portion of the sacrificial film layer 20 above the first etch barrier layer 51, so that the lower electrode 40 is partially located inside the capacitor hole 30 and partially exposed outside the capacitor hole 30. This improves the removal effect of the portion of the sacrificial film layer 20 above the first etch barrier layer 51. By setting a first etch barrier layer 51, a portion of the sacrificial film layer 20 can be removed and a portion of the sacrificial film layer 20 can be retained during the manufacturing process, forming a lower electrode 40 consisting of two parts: the inside and outside of the capacitor hole 30. Simultaneously, after removing the sacrificial film layer 20 located on the first etch barrier layer 51, the first etch barrier layer 51 can also prevent subsequent etching or cleaning operations from affecting the substrate 10, ensuring the quality of the substrate 10. It should be understood that the first etch barrier layer 51 can also be omitted from the sacrificial film layer 20, and a portion of the sacrificial film layer 20 can be etched away using existing processes, retaining a portion of the sacrificial film layer 20.

[0065] By retaining a portion of the sacrificial film layer 20, the lower electrode 40 consists of a portion within the capacitor aperture 30 and a portion extending upwards along the sidewall of the capacitor aperture 30 and exposed outside the capacitor aperture 30. Since the sacrificial film layer 20 is partially retained, it surrounds the lower portion of the lower electrode 40, providing support and preventing tilting. In subsequent processes, when depositing the dielectric layer and the upper electrode on the lower electrode 40, the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 also prevents bending and deformation, thereby preventing capacitor collapse. In application, because the sacrificial film layer 20 surrounding the lower portion of the lower electrode 40 provides support, the capacitor structure is more robust, allowing for a more appropriate increase in the aspect ratio of the stacked capacitor to increase capacitance and improve storage performance.

[0066] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A semiconductor device, characterized in that, include: A landing pad is formed in a substrate, the substrate further including an isolation portion, a storage contact portion and a transistor, the landing pad is formed on the storage contact portion, the landing pad is electrically connected to the source region or drain region of the transistor through the storage contact portion, and the isolation portion is used to isolate two adjacent landing pads; A sacrificial film layer stacked on top of the substrate; A capacitor hole that penetrates the sacrificial film layer from top to bottom and connects to the landing pad; The lower electrode includes a portion formed within the capacitor aperture and in contact with the landing pad, and a portion extending upward along the sidewall of the capacitor aperture and exposed outside the capacitor aperture. The lower electrode is cylindrical in shape. The bottom wall of the lower electrode contacts the landing pad. A portion of the sidewall of the lower electrode contacts the wall of the capacitor aperture and is partially exposed outside the capacitor aperture. The diameter of the landing pad is larger than the diameter of the lower electrode. An upper electrode and a dielectric layer that insulates and isolates the lower electrode from the upper electrode are formed on the bottom wall, inner side wall, and outer side wall of the portion exposed outside the capacitor hole of the lower electrode.

2. The semiconductor device as claimed in claim 1, characterized in that, A first etching barrier layer is stacked on the sacrificial film layer; The capacitor hole passes through the first etch barrier layer and the sacrificial film layer from top to bottom and then connects to the landing pad.

3. The semiconductor device as described in claim 2, characterized in that, A second etch barrier layer is also stacked between the sacrificial film layer and the substrate, and the capacitor hole passes through the first etch barrier layer, the sacrificial film layer and the second etch barrier layer from top to bottom and communicates with the landing pad.

4. The semiconductor device as described in claim 3, characterized in that, The materials of the first etch barrier layer and the second etch barrier layer are SiN, SiBN or SiCN.

5. The semiconductor device as claimed in claim 1, characterized in that, The height of the portion of the lower electrode located inside the capacitor hole is h1, and the height of the portion of the lower electrode exposed outside the capacitor hole is h2. Among them, (h1+h2)×50%≤h1≤(h1+h2)×70%.

6. The semiconductor device as claimed in claim 1, characterized in that, The semiconductor device is a dynamic random access memory.

7. A method for manufacturing a semiconductor device, characterized in that, include: A substrate is provided in which landing pads are formed. The substrate also includes an isolation portion, a storage contact portion, and a transistor. The landing pads are formed on the storage contact portion and are electrically connected to the source or drain region of the transistor through the storage contact portion. The isolation portion is used to isolate two adjacent landing pads. A sacrificial film layer is formed over the substrate to cover the substrate; The sacrificial film layer is etched from top to bottom to form a capacitor via communicating with the landing pad; A lower electrode is formed within the capacitor hole to contact the landing pad; A portion of the sacrificial film layer is removed, so that the lower electrode is partially located inside the capacitor aperture and partially exposed outside the capacitor aperture; the lower electrode is cylindrical in shape; the bottom wall of the lower electrode contacts the landing pad; a portion of the side wall of the lower electrode contacts the hole wall of the capacitor aperture and partially exposed outside the capacitor aperture; the diameter of the landing pad is larger than the diameter of the lower electrode. An upper electrode and a dielectric layer that insulates and isolates the lower electrode from the upper electrode are formed on the bottom wall, inner side wall, and outer side wall of the portion exposed outside the capacitor hole of the lower electrode.

8. The manufacturing method as described in claim 7, characterized in that, A first etch barrier layer is formed inside the sacrificial film layer, and the capacitor hole penetrates from top to bottom through the sacrificial film layer and the first etch barrier layer and communicates with the landing pad. The removal of a portion of the sacrificial film layer, so that the lower electrode portion is located inside the capacitor hole and partially exposed outside the capacitor hole, specifically involves: Remove the portion of the sacrificial film layer located above the first etching barrier layer, so that the lower electrode portion is located inside the capacitor hole and partially exposed outside the capacitor hole.

9. The manufacturing method as described in claim 8, characterized in that, The step of removing the portion of the sacrificial film layer located above the first etch barrier layer, so that the lower electrode portion is located inside the capacitor hole and partially exposed outside the capacitor hole, specifically involves: The portion of the sacrificial film layer located above the first etching barrier layer is etched using plasma etching or wet etching, so that the lower electrode portion is located inside the capacitor hole and partially exposed outside the capacitor hole.

10. The manufacturing method as described in claim 8, characterized in that, Before forming a sacrificial film layer covering the substrate above the substrate, the manufacturing method further includes: forming a second etch barrier layer covering the substrate on the substrate; The specific steps of etching the sacrificial film layer from top to bottom to form a capacitor hole communicating with the landing pad are as follows: The sacrificial film layer, the first etch barrier layer, and the second etch barrier layer are etched from top to bottom to form a capacitor via that communicates with the landing pad.

11. The manufacturing method as described in claim 7, characterized in that, The lower electrode formed within the capacitor hole that contacts the landing pad includes: A lower electrode material layer is deposited on the sacrificial film layer and the bottom and inner wall of the capacitor hole; The portion of the lower electrode material layer located outside the capacitor hole is removed by plasma etching or wet etching to form the lower electrode.

Images