Display substrate, preparation method thereof and display device

Abstract

A display substrate includes a substrate, a circuit structure layer disposed on the substrate, a plurality of ultrasonic sensing elements, and a plurality of micro light emitting elements. The plurality of ultrasonic sensing elements are disposed on a side of the circuit structure layer distal from the substrate, and the plurality of ultrasonic sensing elements are electrically connected to the circuit structure layer. The plurality of micro light emitting elements are disposed on the side of the circuit structure layer distal from the substrate, and the plurality of micro light emitting elements are electrically connected to the circuit structure layer. A footprint of the plurality of ultrasonic sensing elements on the substrate does not overlap a footprint of the plurality of micro light emitting elements on the substrate.

Description

Technical Field

[0001] This article relates to, but is not limited to, the field of display technology, and in particular to a display substrate and its preparation method, and a display device. Background Technology

[0002] With the development of electronic devices and the increasing awareness of personal information protection among users, more and more electronic devices are equipped with functions such as fingerprint recognition for unlocking the screen or making online payments. Currently, fingerprint recognition is mostly achieved through fingerprint sensors, with commonly used sensors including ultrasonic fingerprint sensors. For electronic devices based on Organic Light Emitting Diode (OLED) display panels, ultrasonic fingerprint sensors are often attached to the underside of the display. However, this structure increases the thickness of the display module, hindering the pursuit of thinner and lighter electronic devices. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, a method for preparing the same, and a display device.

[0005] In one aspect, embodiments of this disclosure provide a display substrate, including: a substrate, a circuit structure layer disposed on the substrate, a plurality of ultrasonic sensing elements, and a plurality of micro-light-emitting elements. The plurality of ultrasonic sensing elements are disposed on the side of the circuit structure layer away from the substrate and are electrically connected to the circuit structure layer. The plurality of micro-light-emitting elements are disposed on the side of the circuit structure layer away from the substrate and are electrically connected to the circuit structure layer. The orthographic projections of the plurality of ultrasonic sensing elements on the substrate and the orthographic projections of the plurality of micro-light-emitting elements on the substrate do not overlap.

[0006] In some exemplary embodiments, the display substrate further includes a transparent organic insulating layer disposed on the side of the plurality of micro-light-emitting elements away from the substrate, the transparent organic insulating layer covering the plurality of micro-light-emitting elements. Each of the plurality of ultrasonic sensing elements includes a piezoelectric functional layer. The transparent organic insulating layer is in direct contact with the piezoelectric functional layers of the plurality of ultrasonic sensing elements, and the orthographic projection of the transparent organic insulating layer on the substrate does not overlap with the orthographic projection of the piezoelectric functional layers of the plurality of ultrasonic sensing elements on the substrate.

[0007] In some exemplary embodiments, at least one of the plurality of ultrasonic sensing elements further includes a transmitting electrode and a receiving electrode. The transmitting electrode is located on the side of the piezoelectric functional layer away from the substrate; the receiving electrode is located on the side of the piezoelectric functional layer closer to the substrate, and the receiving electrode is electrically connected to the circuit structure layer.

[0008] In some exemplary embodiments, the transmitting electrode is in direct contact with the piezoelectric functional layer, and an insulating layer is disposed between the receiving electrode and the piezoelectric functional layer.

[0009] In some exemplary embodiments, the circuit structure layer includes: a plurality of first light-emitting driving circuits and a plurality of ultrasonic detection circuits; the plurality of ultrasonic detection circuits are connected one-to-one with the plurality of ultrasonic sensing elements; the plurality of first light-emitting driving circuits are connected one-to-one with the plurality of micro-light-emitting elements. Alternatively, the circuit structure layer includes: a plurality of second light-emitting driving circuits with ultrasonic detection function, the plurality of second light-emitting driving circuits being connected one-to-one with the plurality of ultrasonic sensing elements, and the plurality of second light-emitting driving circuits being connected one-to-one with the plurality of micro-light-emitting elements.

[0010] In some exemplary embodiments, the circuit structure layer further includes: multiple common electrode lines. At least one of the multiple micro-light-emitting elements includes: a light-emitting portion, a first electrode and a second electrode connected to the light-emitting portion. The first electrode is electrically connected to a corresponding first light-emitting driving circuit or a second light-emitting driving circuit, and the second electrode is electrically connected to the common electrode lines.

[0011] In some exemplary embodiments, the display substrate further includes a plurality of first connecting electrodes and a plurality of second connecting electrodes. The first electrode of the at least one micro-light-emitting element is electrically connected to a corresponding first light-emitting driving circuit or a second light-emitting driving circuit through the first connecting electrode, and the second electrode of the at least one micro-light-emitting element is electrically connected to the common electrode line through the second connecting electrode.

[0012] In some exemplary embodiments, the plurality of first connecting electrodes and the plurality of second connecting electrodes are in the same layer as the receiving electrode of the at least one ultrasonic sensing element.

[0013] In some exemplary embodiments, the substrate includes a display area and an ultrasonic sensing area located on one side of the display area; the plurality of ultrasonic sensing elements are located in the ultrasonic sensing area, and the plurality of micro-light-emitting elements are located in the display area. Alternatively, the substrate includes a display area, and the plurality of ultrasonic sensing elements and the plurality of micro-light-emitting elements are regularly arranged in the display area.

[0014] In some exemplary embodiments, the substrate further includes: a bonding region located on one side of the display area; the bonding region includes: a plurality of bonding electrodes; the plurality of bonding electrodes and the circuit structure layer are located on the same side of the substrate, or the plurality of bonding electrodes and the circuit structure layer are located on different sides of the substrate.

[0015] In some exemplary embodiments, the plurality of bonding electrodes and the circuit structure layer are located on different sides of the substrate, and the bonding region further includes a fan-out lead layer, which is located on the same side of the substrate as the circuit structure layer. The fan-out lead layer includes a plurality of fan-out leads, at least one of which is connected to at least one bonding electrode through a via penetrating the substrate.

[0016] In some exemplary embodiments, the circuit structure layer includes: an active layer, a first gate metal layer, a second gate metal layer, and a source / drain metal layer sequentially disposed on the substrate; a first gate insulating layer is disposed between the active layer and the first gate metal layer, a second gate insulating layer is disposed between the first gate metal layer and the second gate metal layer, and an interlayer insulating layer is disposed between the second gate metal layer and the source / drain metal layer.

[0017] In some exemplary embodiments, the plurality of bonded electrodes and the circuit structure layer are located on the same side of the substrate, and the plurality of bonded electrodes and the source / drain metal layer are of the same layer structure.

[0018] On the other hand, embodiments of this disclosure provide a display device including a display substrate as described above.

[0019] On the other hand, this disclosure provides a method for fabricating a display substrate, comprising: forming a circuit structure layer on a substrate; and forming a plurality of micro-light-emitting elements and a plurality of ultrasonic sensing elements on a side of the circuit structure layer away from the substrate. The plurality of micro-light-emitting elements are electrically connected to the circuit structure layer, and the plurality of ultrasonic sensing elements are electrically connected to the circuit structure layer. The orthographic projections of the plurality of ultrasonic sensing elements on the substrate do not overlap with the orthographic projections of the plurality of micro-light-emitting elements on the substrate.

[0020] In some exemplary embodiments, the method for fabricating the display substrate further includes: forming a transparent organic insulating layer covering the plurality of micro-light-emitting elements on the side of the plurality of micro-light-emitting elements away from the substrate. Each of the plurality of ultrasonic sensing elements includes a piezoelectric functional layer; the transparent organic insulating layer is in direct contact with the piezoelectric functional layer of the ultrasonic sensing element, and the orthographic projection of the transparent organic insulating layer on the substrate does not overlap with the orthographic projection of the piezoelectric functional layer of the plurality of ultrasonic sensing elements on the substrate.

[0021] In some exemplary embodiments, forming a plurality of micro-light-emitting elements and a plurality of ultrasonic sensing elements on the side of the circuit structure layer away from the substrate includes: forming a plurality of first connecting electrodes, a plurality of second connecting electrodes, and receiving electrodes for a plurality of ultrasonic sensing elements on the side of the circuit structure layer away from the substrate; forming a plurality of micro-light-emitting elements on the side of the plurality of first connecting electrodes and the plurality of second connecting electrodes away from the substrate using a transfer process; forming a piezoelectric functional layer for the plurality of ultrasonic sensing elements on the side of the receiving electrodes for the plurality of ultrasonic sensing elements away from the substrate; and forming emitting electrodes for the plurality of ultrasonic sensing elements on the side of the piezoelectric functional layer away from the substrate. The plurality of first connecting electrodes, the plurality of second connecting electrodes, and the receiving electrodes are connected to the circuit structure layer. At least one of the plurality of micro-light-emitting elements has its first electrode electrically connected to a first connecting electrode, and at least one of the plurality of micro-light-emitting elements has its second electrode electrically connected to a second connecting electrode.

[0022] In some exemplary embodiments, a piezoelectric functional layer of the plurality of ultrasonic sensing elements is formed on the side of the plurality of ultrasonic sensing elements away from the substrate, including: performing self-aligned polarization treatment on the piezoelectric functional layer using the transparent organic insulating layer; or, performing polarization treatment on the piezoelectric functional layer using a mask and the transparent organic insulating layer.

[0023] In some exemplary embodiments, the method for fabricating the display substrate further includes: forming a plurality of bonding electrodes on a separation layer; forming a substrate on the side of the plurality of bonding electrodes away from the separation layer; and forming a fan-out lead layer on the substrate. The fan-out lead layer includes a plurality of fan-out leads, at least one of the plurality of fan-out leads being connected to at least one bonding electrode through a via penetrating the substrate.

[0024] In some exemplary embodiments, forming a circuit structure layer on the substrate includes: sequentially forming an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, and a source / drain metal layer on the substrate.

[0025] After reading and understanding the accompanying diagrams and detailed descriptions, other aspects can be understood. Attached Figure Description

[0026] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shape and size of one or more components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0027] Figure 1This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0028] Figure 2 for Figure 1 A cross-sectional view along the PP direction;

[0029] Figure 3 This is an equivalent circuit diagram of a first light-emitting driving circuit according to at least one embodiment of the present disclosure;

[0030] Figure 4 for Figure 3 The timing diagram of the first light-emitting driving circuit is provided.

[0031] Figure 5 This is an equivalent circuit diagram of an ultrasonic detection circuit according to at least one embodiment of the present disclosure;

[0032] Figure 6 for Figure 5 The timing diagram of the provided ultrasonic testing circuit;

[0033] Figure 7A This is a schematic diagram of a display substrate after forming a bonding electrode pattern in at least one embodiment of the present disclosure;

[0034] Figure 7B This is a schematic diagram of a display substrate after a substrate pattern has been formed in at least one embodiment of the present disclosure;

[0035] Figure 7C This is a schematic diagram of a display substrate after a passivation layer pattern has been formed in at least one embodiment of this disclosure;

[0036] Figure 7D This is a schematic diagram of a display substrate after the fan-out lead layer pattern has been formed in at least one embodiment of the present disclosure;

[0037] Figure 7E This is a schematic diagram of a display substrate after an active layer pattern has been formed in at least one embodiment of this disclosure;

[0038] Figure 7F This is a schematic diagram of a display substrate after the first gate metal layer pattern has been formed in at least one embodiment of the present disclosure;

[0039] Figure 7G This is a schematic diagram of a display substrate after the second gate metal layer pattern has been formed in at least one embodiment of the present disclosure;

[0040] Figure 7H This is a schematic diagram of a display substrate after the fifth insulating layer pattern has been formed in at least one embodiment of the present disclosure;

[0041] Figure 7I This is a schematic diagram of a display substrate after the source / drain metal layer pattern has been formed in at least one embodiment of the present disclosure;

[0042] Figure 7J This is a schematic diagram of a display substrate after the sixth insulating layer pattern has been formed in at least one embodiment of the present disclosure;

[0043] Figure 7K This is a schematic diagram of a display substrate after the patterns of the receiving electrode, the first connecting electrode, and the second connecting electrode are formed in at least one embodiment of the present disclosure;

[0044] Figure 7L This is a schematic diagram of a display substrate after the micro-light-emitting elements have been formed in at least one embodiment of this disclosure;

[0045] Figure 7M This is a schematic diagram of a display substrate after a transparent organic insulating layer pattern has been formed in at least one embodiment of the present disclosure;

[0046] Figure 7N This is a schematic diagram of a display substrate after the piezoelectric functional layer pattern has been formed in at least one embodiment of the present disclosure;

[0047] Figure 7O This is a schematic diagram of a display substrate after the emission electrode layer pattern has been formed in at least one embodiment of the present disclosure;

[0048] Figure 7P This is a schematic diagram of a display substrate after the cover plate has been formed in at least one embodiment of the present disclosure;

[0049] Figure 8 for Figure 1 Another cross-sectional view along the PP direction;

[0050] Figure 9A This is a schematic diagram of a display substrate after an active layer pattern has been formed in at least one embodiment of this disclosure;

[0051] Figure 9B This is a schematic diagram of a display substrate after the first gate metal layer pattern has been formed in at least one embodiment of the present disclosure;

[0052] Figure 9C This is a schematic diagram of a display substrate after the second gate metal layer pattern has been formed in at least one embodiment of the present disclosure;

[0053] Figure 9D This is a schematic diagram of a display substrate after the fifth insulating layer pattern has been formed in at least one embodiment of the present disclosure;

[0054] Figure 9E This is a schematic diagram of a display substrate after the source / drain metal layer pattern has been formed in at least one embodiment of the present disclosure;

[0055] Figure 9F This is a schematic diagram of a display substrate after the sixth insulating layer pattern has been formed in at least one embodiment of the present disclosure;

[0056] Figure 9G This is a schematic diagram of a display substrate after the patterns of the receiving electrode, the first connecting electrode, and the second connecting electrode are formed in at least one embodiment of the present disclosure;

[0057] Figure 9H This is a schematic diagram of a display substrate after the micro-light-emitting elements have been formed in at least one embodiment of this disclosure;

[0058] Figure 9I This is a schematic diagram of a display substrate after a transparent organic insulating layer pattern has been formed in at least one embodiment of the present disclosure;

[0059] Figure 9J This is a schematic diagram of a display substrate after the piezoelectric functional layer pattern has been formed in at least one embodiment of the present disclosure;

[0060] Figure 9K This is a schematic diagram of polarization treatment of the piezoelectric functional layer in at least one embodiment of the present disclosure;

[0061] Figure 9L This is a schematic diagram of a display substrate after the emission electrode layer pattern has been formed in at least one embodiment of the present disclosure;

[0062] Figure 9M This is a schematic diagram of a display substrate after the cover plate has been formed in at least one embodiment of the present disclosure;

[0063] Figure 10 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure;

[0064] Figure 11 for Figure 10 A cross-sectional view along the QQ direction;

[0065] Figure 12 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Detailed Implementation

[0066] To make the objectives, technical solutions, and advantages of this disclosure clearer, the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The implementation can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be transformed into one or more forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0067] In the accompanying drawings, the size of one or more constituent elements, the thickness of layers, or areas are sometimes exaggerated for clarity. Therefore, this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the various components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0068] The ordinal numbers such as "first," "second," and "third" in this disclosure are used to avoid confusion among the constituent elements, not to limit the quantity. The term "multiple" in this disclosure refers to two or more quantities.

[0069] In this disclosure, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification of the specification, and does not imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately changed depending on the direction in which the constituent elements are described. Therefore, the description is not limited to the terms used in the specification and may be appropriately replaced as appropriate.

[0070] In this disclosure, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linkage" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection or an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the meaning of these terms in this disclosure as appropriate.

[0071] In this disclosure, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In this disclosure, the channel region refers to the region through which current primarily flows.

[0072] In this disclosure, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this disclosure, the "source electrode" and the "drain electrode" can be interchanged.

[0073] In this disclosure, "electrical connection" includes the situation where constituent elements are connected together by a component having a certain electrical function. There are no particular limitations on the "component having a certain electrical function," as long as it enables the transmission and reception of electrical signals between the connected constituent elements. Examples of "component having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components having one or more functions.

[0074] In this disclosure, "parallel" refers to a state in which the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore can include a state in which the angle is greater than or equal to -5° and less than 5°. Furthermore, "perpendicular" refers to a state in which the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore can include a state in which the angle is greater than or equal to 85° and less than 95°.

[0075] In this disclosure, the terms "film" and "layer" can be interchanged. For example, sometimes "conductive layer" can be replaced with "conductive film". Similarly, sometimes "insulating film" can be replaced with "insulating layer".

[0076] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0077] At least one embodiment of this disclosure provides a display substrate, including: a substrate, a circuit structure layer disposed on the substrate, a plurality of ultrasonic sensing elements, and a plurality of micro-light-emitting elements. The plurality of ultrasonic sensing elements are disposed on the side of the circuit structure layer away from the substrate and are electrically connected to the circuit structure layer. The plurality of micro-light-emitting elements are disposed on the side of the circuit structure layer away from the substrate and are electrically connected to the circuit structure layer. The orthographic projections of the plurality of ultrasonic sensing elements on the substrate and the orthographic projections of the plurality of micro-light-emitting elements on the substrate do not overlap.

[0078] In some examples, the micro-light-emitting element can be a micro-LED (Micro-LED) or a mini-LED.

[0079] This embodiment can integrate an ultrasonic sensing element and its corresponding circuit structure within a display substrate utilizing micro-light-emitting elements, which helps to reduce the module thickness. Moreover, the ultrasonic sensing element is close to the ultrasonic detection interface, so that the ultrasonic signal can be detected by the ultrasonic sensing element without passing through the circuit structure, which can reduce the loss of ultrasonic signal, improve the signal-to-noise ratio, and enhance the quality of ultrasonic detection.

[0080] In some exemplary embodiments, the display substrate further includes a transparent organic insulating layer disposed on the side of the plurality of micro-light-emitting elements away from the substrate. The transparent organic insulating layer covers the plurality of micro-light-emitting elements. Each of the plurality of ultrasonic sensing elements includes a piezoelectric functional layer. The transparent organic insulating layer is in direct contact with the piezoelectric functional layers of the plurality of ultrasonic sensing elements, and the orthographic projection of the transparent organic insulating layer on the substrate does not overlap with the orthographic projection of the piezoelectric functional layers of the plurality of ultrasonic sensing elements on the substrate. In this exemplary embodiment, by providing a transparent organic insulating layer to cover the plurality of micro-light-emitting elements, the micro-light-emitting elements can be encapsulated and protected without reducing light transmittance, thus ensuring display performance. Moreover, during the polarization process of the piezoelectric functional layer of the ultrasonic sensing elements, the transparent organic insulating layer can protect the transistors within the circuit structure layer from damage or breakdown by the polarization electric field.

[0081] In some exemplary embodiments, at least one of the multiple ultrasonic sensing elements further includes a transmitting electrode and a receiving electrode. The transmitting electrode is located on the side of the piezoelectric functional layer away from the substrate; the receiving electrode is located on the side of the piezoelectric functional layer closer to the substrate, and the receiving electrode is electrically connected to the circuit structure layer. In this exemplary embodiment, using the same piezoelectric functional layer to achieve both the transmission and reception of ultrasonic signals simplifies the structure.

[0082] In some exemplary embodiments, the transmitting electrode is in direct contact with the piezoelectric functional layer, and an insulating layer is provided between the receiving electrode and the piezoelectric functional layer.

[0083] In some exemplary embodiments, the circuit structure layer includes: a plurality of first light-emitting driving circuits and a plurality of ultrasonic detection circuits; the plurality of ultrasonic detection circuits are connected one-to-one with a plurality of ultrasonic sensing elements; and the plurality of first light-emitting driving circuits are connected one-to-one with a plurality of micro-light-emitting elements. Alternatively, the circuit structure layer includes: a plurality of second light-emitting driving circuits with ultrasonic detection function, the plurality of second light-emitting driving circuits being connected one-to-one with a plurality of ultrasonic sensing elements, and the plurality of second light-emitting driving circuits being connected one-to-one with a plurality of micro-light-emitting elements. However, this embodiment is not limited thereto.

[0084] In some exemplary embodiments, the circuit structure layer further includes multiple common electrode lines. At least one of the multiple micro-light-emitting elements includes a light-emitting portion, a first electrode connected to the light-emitting portion, and a second electrode. The first electrode is electrically connected to a corresponding first light-emitting driving circuit or a second light-emitting driving circuit, and the second electrode is electrically connected to the common electrode lines. In some examples, the first electrode can be an anode, and the second electrode can be a cathode. However, this embodiment is not limited to this.

[0085] In some exemplary embodiments, the display substrate may further include: a plurality of first connecting electrodes and a plurality of second connecting electrodes. The first electrode of at least one micro-light-emitting element is electrically connected to a corresponding first light-emitting driving circuit or a second light-emitting driving circuit via the first connecting electrode, and the second electrode of at least one micro-light-emitting element is electrically connected to a common electrode line via the second connecting electrode. However, this embodiment is not limited thereto. In some examples, the first electrode of at least one micro-light-emitting element may be directly electrically connected to the corresponding first light-emitting driving circuit or the second light-emitting driving circuit, and the second electrode of at least one micro-light-emitting element may be directly electrically connected to the common electrode line.

[0086] In some exemplary embodiments, the plurality of first connecting electrodes and the plurality of second connecting electrodes and the receiving electrode of at least one ultrasonic sensing element may be in the same layer. However, this embodiment is not limited to this.

[0087] In some exemplary embodiments, the substrate includes a display area and an ultrasonic sensing area located on one side of the display area; multiple ultrasonic sensing elements are located in the ultrasonic sensing area, and multiple micro-light-emitting elements are located in the display area. Alternatively, the substrate includes a display area, and multiple ultrasonic sensing elements and multiple micro-light-emitting elements are regularly arranged in the display area. In some examples, multiple ultrasonic sensing elements can be disposed in a separate ultrasonic sensing area, where fingerprint recognition is implemented, and display function is implemented in the display area. In some examples, multiple ultrasonic sensing elements can correspond one-to-one with multiple micro-light-emitting elements, and all are disposed in the display area, integrating display and fingerprint recognition functions in the display area. However, this embodiment is not limited to these embodiments.

[0088] In some exemplary embodiments, the substrate may further include a bonding region located on one side of the display area. The bonding region includes a plurality of bonding electrodes. The plurality of bonding electrodes and the circuit structure layer are located on the same side of the substrate, or the plurality of bonding electrodes and the circuit structure layer are located on different sides of the substrate. In some examples, the circuit structure layer is located on the front side of the substrate, and the plurality of bonding electrodes are located on the back side of the substrate; or, both the circuit structure layer and the plurality of bonding electrodes are located on the front side of the substrate. However, this embodiment is not limited thereto.

[0089] In some exemplary embodiments, multiple bonding electrodes and circuit structure layers are located on different sides of the substrate. The bonding region may further include a fan-out lead layer, which is located on the same side of the substrate as the circuit structure layer. The fan-out lead layer includes multiple fan-out leads, at least one of which is connected to at least one bonding electrode through a via penetrating the substrate.

[0090] In some exemplary embodiments, the circuit structure layer includes: an active layer, a first gate metal layer, a second gate metal layer, and a source / drain metal layer sequentially disposed on a substrate. A first gate insulating layer is disposed between the active layer and the first gate metal layer, a second gate insulating layer is disposed between the first gate metal layer and the second gate metal layer, and an interlayer insulating layer is disposed between the second gate metal layer and the source / drain metal layer.

[0091] In some exemplary embodiments, multiple bonding electrodes are located on the same side of the substrate as the circuit structure layer, and the multiple bonding electrodes and the source / drain metal layers are in the same layer. However, this embodiment is not limited to this.

[0092] Figure 1 This is a schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 1 As shown, the display substrate of this exemplary embodiment includes: a display area 100, a peripheral area 200 surrounding the display area 100, an ultrasonic sensing area 300 within the peripheral area 200 and located on one side of the display area 100, and a bonding area 400 located on the side of the ultrasonic sensing area 300 away from the display area 100. A plurality of display units are disposed in the display area 100 in a regular arrangement. At least one display unit includes: a micro-light-emitting element and a light-emitting driving circuit configured to drive the micro-light-emitting element to emit light. In some examples, the micro-light-emitting element may be a Micro-LED or a Mini-LED. A plurality of ultrasonic sensing units are disposed in the ultrasonic sensing area 300 in a regular arrangement. At least one ultrasonic sensing unit includes: an ultrasonic sensing element configured to transmit and receive ultrasonic signals, and an ultrasonic detection circuit configured to detect ultrasonic signals. The peripheral area 200 is provided with a control circuit for driving the display units to emit light. The bonding area 400 is provided with a plurality of bonding electrodes bonded to an external circuit board (e.g., a flexible printed circuit board (FPC)). In some examples, the circuit board is provided with processing circuitry that can be configured to provide an ultrasonic control signal (e.g., a high-frequency electrical signal or an alternating current signal) to the ultrasonic sensing element so that the ultrasonic sensing element emits an ultrasonic signal; and is also configured to receive fingerprint electrical signals acquired by the ultrasonic detection circuitry for fingerprint identification.

[0093] Figure 2 for Figure 1 A cross-sectional view of the PP section. (See diagram below.) Figure 2 As shown, in a plane perpendicular to the display substrate, the display area 100 of the display substrate includes: a substrate 10, a passivation layer 42, a first insulating layer 11, a second insulating layer 12, and a circuit structure layer sequentially disposed on the substrate 10, and a plurality of micro-light-emitting elements disposed on the circuit structure layer. Figure 2The diagram only shows one micro-light-emitting element 31), a transparent organic insulating layer 18 covering multiple micro-light-emitting elements, an adhesive layer 51 covering the transparent organic insulating layer 18, and a cover plate 52. The circuit structure layer of the display area 100 includes multiple first light-emitting driving circuits and multiple common electrode lines (…). Figure 2 Only one common electrode line 26 is shown in the diagram. Multiple first light-emitting driving circuits correspond one-to-one with multiple micro-light-emitting elements. At least one first light-emitting driving circuit may include multiple transistors and at least one storage capacitor. For example, the first light-emitting driving circuit may be designed as 8T2C (i.e., eight thin-film transistors and two capacitors) or 13T1C (i.e., thirteen thin-film transistors and one capacitor). Figure 2 The diagram illustrates a first thin-film transistor 101 and a first storage capacitor 104. The circuit structure layers of the display area 100 may include: an active layer, a third insulating layer 13, a first gate metal layer, a fourth insulating layer 14, a second gate metal layer, a fifth insulating layer 15, and a source / drain metal layer sequentially disposed on a second insulating layer 12. The active layer may include at least a first active layer, the first gate metal layer may include at least a first gate electrode and a first capacitor electrode, the second gate metal layer may include at least a second capacitor electrode, and the source / drain metal layer may include at least a first source electrode, a first drain electrode, and a common electrode line 26. The first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute the first thin-film transistor 101, and the first capacitor electrode and the second capacitor electrode constitute the first storage capacitor 104. The micro-light-emitting element 31 may include: a light-emitting portion, a first electrode connected to the light-emitting portion, and a second electrode. The first electrode is connected to a first end of the light-emitting portion, and the second electrode is connected to a second end of the light-emitting portion. In some examples, the first electrode of the micro-light-emitting element 31 may be an anode, and the second electrode may be a cathode. The display area 100 also includes: a plurality of first connecting electrodes and a plurality of second connecting electrodes (…). Figure 2 The diagram illustrates a first connecting electrode 33 and a second connecting electrode 34. The first electrode of the micro-light-emitting element 31 can be connected to the first drain electrode of the first thin-film transistor 101 through the first connecting electrode 33, and the second electrode of the micro-light-emitting element 31 can be connected to the common electrode line 26 through the second connecting electrode 34.

[0094] In some exemplary implementations, such as Figure 2 As shown, in a plane perpendicular to the display substrate, the ultrasonic sensing region 300 of the display substrate includes: a substrate 10, a passivation layer 42, a first insulating layer 11, a second insulating layer 12, and a circuit structure layer sequentially disposed on the substrate 10, and a plurality of ultrasonic sensing elements disposed on the circuit structure layer. Figure 2The diagram illustrates two ultrasonic sensing elements, an adhesive layer 51 covering multiple ultrasonic sensing elements, and a cover plate 52. The circuit structure layer of the ultrasonic sensing region 300 includes multiple ultrasonic detection circuits, each corresponding one-to-one with a single ultrasonic sensing element. Each ultrasonic detection circuit may include multiple transistors, for example, a 4T (four thin-film transistors) or 5T (five thin-film transistors) design. Figure 2 The diagram illustrates two ultrasonic detection circuits, with only one second thin-film transistor 102 in each circuit. The circuit structure layer of the ultrasonic sensing region 300 may include: an active layer, a third insulating layer 13, a first gate metal layer, a fourth insulating layer 14, a fifth insulating layer 15, and a source / drain metal layer sequentially disposed on the second insulating layer 12. The active layer may include at least a second active layer, the first gate metal layer may include at least a second gate electrode, and the source / drain metal layer may include at least a second source electrode and a second drain electrode. The second active layer, the second gate electrode, the second source electrode, and the second drain electrode constitute the second thin-film transistor 102. The ultrasonic sensing element may include: a receiving electrode 321, a piezoelectric functional layer 322, and a transmitting electrode 323. The receiving electrode 321 and the first connecting electrode 33 and the second connecting electrode 34 of the display region 100 may be in the same layer. The piezoelectric functional layers 322 of multiple ultrasonic sensing elements may be an integral structure, and the transmitting electrodes 323 of multiple ultrasonic sensing elements may be an integral structure; for example, the transmitting electrode 323 may be a sheet electrode. The orthographic projection of the emitting electrode 323 onto the substrate 10 can cover the orthographic projections of multiple receiving electrodes 321 onto the substrate 10, and the orthographic projection of the piezoelectric functional layer 322 onto the substrate 10 can also cover the orthographic projections of multiple receiving electrodes 321 onto the substrate 10. The piezoelectric functional layer 322 can be configured to emit ultrasonic signals and receive ultrasonic signals reflected by a sensing object (e.g., a finger). The receiving electrodes 321 can be disposed on the side of the piezoelectric functional layer 322 closer to the substrate 10, and the emitting electrode 323 can be disposed on the side of the piezoelectric functional layer 322 away from the substrate 10. The emitting electrode 323 is in direct contact with the piezoelectric functional layer 322, and a seventh insulating layer 17 is disposed between the receiving electrode 321 and the piezoelectric functional layer 322. The receiving electrode 321 can be connected to the second drain electrode of the second thin-film transistor 102 of the ultrasonic detection circuit. The emitting electrode 323 can be connected to an ultrasonic control terminal (not shown) to receive ultrasonic control signals provided by the ultrasonic control terminal.

[0095] In this exemplary embodiment, the piezoelectric functional layer 322 can utilize the piezoelectric effect (divided into direct piezoelectric effect and inverse piezoelectric effect) of the piezoelectric material after crystallization and electric field polarization to realize the transmission and reception of ultrasonic signals. In some examples, when the ultrasonic control signal received by the transmitting electrode 323 via the ultrasonic control terminal is an AC voltage, the piezoelectric functional layer 322 can generate ultrasonic signals under the action of the voltage signal provided by the transmitting electrode 323; this process is the inverse piezoelectric effect. When the ultrasonic signal generated by the piezoelectric functional layer 323 encounters a finger, the reflection interface of the ultrasonic signal is different due to the presence of valleys and ridges on the fingerprint surface. Valleys correspond to air interfaces, which have a higher impedance to ultrasonic signals, resulting in less ultrasonic signal passing through the air interface and thus a higher intensity of reflected ultrasonic signals; ridges correspond to solid interfaces, which have a lower impedance to ultrasonic signals, resulting in more ultrasonic signal passing through the solid interface and thus a lower intensity of reflected ultrasonic signals. When the ultrasonic signal reflected from the air interface and the solid interface is received by the piezoelectric functional layer 322, a positive piezoelectric effect is generated in the piezoelectric functional layer 322, resulting in multiple local charge accumulations on the surface of the piezoelectric functional layer 322. The amount of each local charge accumulation is positively correlated with the intensity of the received reflected ultrasonic signal. After the local charge accumulation, a coupling voltage is generated on the receiving electrode 321 through coupling. The receiving electrode 321 is connected to the ultrasonic detection circuit, which transmits the detected fingerprint electrical signal to the processing circuit in the circuit board, thereby processing the fingerprint electrical signal to obtain an image reflecting fingerprint information. In this exemplary embodiment, the same piezoelectric functional layer can be used to realize the transmission and reception of ultrasonic signals. However, this embodiment is not limited to this. In some examples, the ultrasonic sensing element may include an ultrasonic transmitting element and an ultrasonic receiving element, using different piezoelectric functional layers to realize the transmission and reception of ultrasonic signals respectively.

[0096] In some exemplary implementations, such as Figure 2 As shown, in a plane perpendicular to the display substrate, the bonding area 400 of the display substrate includes: a separation layer 40, a plurality of bonding electrodes 41 disposed on the separation layer 40, a substrate 10 covering the separation layer 40, a passivation layer 42 disposed sequentially on the substrate 10, a fan-out lead layer, a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, a sixth insulating layer 16, a seventh insulating layer 17, a transparent organic insulating layer 18, an adhesive layer 51, and a cover plate 52. The fan-out lead layer includes multiple fan-out leads ( Figure 2 Only one fan-out lead 43 is shown in the diagram. The fan-out lead 43 is connected to at least one bonding electrode (e.g., two bonding electrodes 41) through vias on the substrate 10 and passivation layer 42. The bonding region 400 also includes: a plurality of fan-out connection electrodes ( Figure 2Only one fan-out connection electrode 44 is shown in the diagram. The fan-out connection electrode 44 is in the same layer as the source / drain metal layers in the display area 100 and the ultrasonic sensing area 300. The fan-out connection electrode 44 can be connected to the fan-out lead 43 through vias on the fifth insulating layer 15, the fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11. In some examples, multiple bonding electrodes 41 can be configured to provide data and power signals to the first light-emitting driving circuit of the display area 100, provide various voltage signals to the ultrasonic detection circuit of the ultrasonic sensing area 300, provide ultrasonic control signals to the emitting electrode 323 of the ultrasonic sensing area 300, and transmit the fingerprint electrical signal detected by the ultrasonic detection circuit to an external circuit board. However, this embodiment is not limited to this.

[0097] Figure 3 This is an equivalent circuit diagram of a first light-emitting driving circuit according to at least one embodiment of the present disclosure. Figure 4 for Figure 3 The timing diagram of the first light-emitting driving circuit is provided. Figure 3As shown, the first light-emitting driving circuit of this exemplary embodiment may include: a driving transistor Td, first transistors T1 to T7, a first capacitor C1, and a second capacitor C2. The gate electrode of the first transistor T1 is connected to the light-emitting control terminal EM, the first terminal of the first transistor T1 is connected to the first operating voltage terminal VL1, and the second terminal of the first transistor T1 is connected to the first terminal of the driving transistor Td. The gate electrode of the second transistor T2 is connected to the light-emitting control terminal EM, the first terminal of the second transistor T2 is connected to the second terminal of the driving transistor Td, and the second terminal of the second transistor T2 is connected to the first terminal of the fourth transistor T4. The gate electrode of the third transistor T3 is connected to the second scan signal terminal G_B, the first terminal of the third transistor T3 is connected to the second data signal terminal D_B, and the second terminal of the third transistor T3 is connected to the gate electrode of the fourth transistor T4. The second terminal of the fourth transistor T4 is connected to the first electrode of the micro-light-emitting element EL. The gate electrode of the fifth transistor T5 is connected to the first scan signal terminal G_A, the first terminal of the fifth transistor T5 is connected to the first terminal of the driving transistor Td, and the second terminal of the fifth transistor T5 is connected to the first data signal terminal D_A. The gate electrode of the sixth transistor T6 is connected to the scan signal terminal G_A, the first terminal of the sixth transistor T6 is connected to the gate electrode of the driving transistor Td, and the second terminal of the sixth transistor T6 is connected to the second terminal of the driving transistor Td. The gate electrode of the seventh transistor T7 is connected to the reset control signal terminal RS, the first terminal of the seventh transistor T7 is connected to the gate electrode of the driving transistor Td, and the second terminal of the seventh transistor T7 is connected to the reset voltage terminal VINT. The first terminal of the first capacitor C1 is connected to the second terminal of the third transistor T3, and the second terminal of the first capacitor C2 is connected to the first voltage terminal V1. The first terminal of the second capacitor C2 is connected to the gate electrode of the driving transistor Td, and the second terminal of the second capacitor C2 is connected to the second voltage terminal V2. The second terminal of the micro-light-emitting element EL is connected to the second operating voltage terminal VL2.

[0098] The following reference Figure 4 Taking the example where the first transistors T1 to T7 and the driving transistor Td are all P-type transistors, the operation of the first light-emitting driving circuit within one image frame will be described. However, this embodiment is not limited to this. In some examples, the transistors in the first light-emitting driving circuit may all be N-type transistors.

[0099] like Figure 4 As shown, within an image frame, there are multiple scan cycles, and each scan cycle can be divided into three stages: the first stage t11, the second stage t12, and the third stage t13.

[0100] In the first stage (i.e., the reset stage) t11, the reset control signal terminal RS is input at a low level, the seventh transistor T7 is turned on, and the reset voltage provided by the reset voltage terminal VINT is transmitted to the gate electrode of the driving transistor Td through the seventh transistor T7, thereby resetting the gate electrode of the driving transistor Td. The potential of node N1 is the reset potential provided by the reset voltage terminal VINT.

[0101] In the second stage (i.e., the data writing stage) t12, the first scan signal terminal G_A is input with a low level. Under the control of the first scan signal terminal G_A, the fifth transistor T5 and the sixth transistor T6 are turned on. The first data voltage Vdata_A provided by the first data signal terminal D_A is transmitted to the first terminal of the driving transistor Td through the fifth transistor T5. After the sixth transistor T6 is turned on, the gate electrode and the second terminal of the driving transistor Td are electrically connected, thus making the driving transistor Td a diode. At this time, the first data voltage Vdata_A charges the gate electrode of the driving transistor Td until the driving transistor Td is turned off. When the driving transistor Td is turned off, the gate-source voltage Vgs = Vth, that is, Vg - Vs = Vth. At this time, the gate voltage Vg of the driving transistor Td = Vs + Vth = Vdata_A + Vth. The first data voltage Vdata_A is written to the gate electrode of the driving transistor Td. Under the control of the second scan signal terminal G_B, the third transistor T3 is turned on, and the second data voltage Vdata_B provided by the second data signal terminal D_B is transmitted to the gate electrode of the fourth transistor T4 through the third transistor T3. At this time, the fourth transistor T4 is turned on, and the voltage of node N2 is Vdata_B. Under the action of the first capacitor C1 and the second capacitor C2, the potentials of nodes N1 and N2 remain unchanged until the first scan signal terminal G_A and the second scan signal terminal G_B output a low level again.

[0102] In the third stage (i.e., the light-emitting stage) t13, the light-emitting control terminal EM inputs a low level, and the first transistor T1 and the second transistor T2 are turned on. The second data signal terminal D_B outputs a second data voltage with two modes: high level and low level. It can be set that when the gate electrode of the fourth transistor T4 receives a high level, the fourth transistor T4 is turned off, and when it receives a low level, the fourth transistor T4 is turned on. When the second data voltage is low, the fourth transistor T4 is turned on. The current path between the first working voltage terminal VL1 and the second working voltage terminal VL2 is open. The driving current I generated by the driving transistor Td operating in the saturation region is transmitted to the micro-light-emitting element through the current path, and the micro-light-emitting element emits light.

[0103] The aforementioned driving current I = K(Vgs - Vth) 2

[0104] =K(Vg-Vs-Vth)2

[0105] =K(Vdata_A+Vth-VDD-Vth) 2

[0106] =K(Vdata_A-VDD) 2 .

[0107] Where K is a fixed constant related to the process parameters and geometry of the driving transistor.

[0108] Therefore, the driving current I is independent of the threshold voltage of the driving transistor Td. The magnitude of the driving current I will not change due to the drift of the threshold voltage Vth of the driving transistor Td. This can eliminate the influence of the threshold voltage of the driving transistor on the micro light-emitting element EL, thereby improving the uniformity of the display and the luminous efficiency.

[0109] Figure 5 This is an equivalent circuit diagram of an ultrasonic detection circuit according to at least one embodiment of the present disclosure. Figure 6 for Figure 5 The provided timing diagram for the ultrasonic testing circuit is shown. Figure 5 As shown, the ultrasonic detection circuit of this exemplary embodiment may include: a first switching transistor M1, a reset transistor M2, a follower transistor M3, and a second switching transistor M4. The gate electrode of the first switching transistor M1 is connected to the first output control terminal S1, the first electrode of the first switching transistor M1 is connected to the receiving electrode 321 of the ultrasonic sensing element, and the second electrode of the first switching transistor M1 is connected to node G. The gate electrode of the reset transistor M2 is connected to the second output control terminal S2, the first electrode of the reset transistor M2 is connected to the initial voltage terminal V3, and the second electrode of the reset transistor M2 is connected to node G. The gate electrode of the follower transistor M3 is connected to node G, the first electrode of the follower transistor M3 is connected to the third operating voltage terminal V4, and the second electrode of the follower transistor M3 is connected to the first electrode of the second switching transistor M4. The gate electrode of the second switching transistor M4 is connected to the third output control terminal S3, and the second electrode of the second switching transistor M4 is connected to the read signal terminal RL. The transmitting electrode 323 of the ultrasonic sensing element is connected to the ultrasonic control terminal COL.

[0110] The following reference Figure 6 The example described uses P-type transistors as examples where the first switching transistor M1, reset transistor M2, follower transistor M3, and second switching transistor M4 are all P-type transistors. However, this embodiment is not limited to this. In some examples, all transistors in the ultrasonic detection circuit may be N-type transistors.

[0111] like Figure 6As shown, the working process of the ultrasonic detection circuit includes the following stages: ultrasonic emission stage t21, reset stage t22, charge accumulation stage t23, and sampling stage t24.

[0112] During the ultrasonic emission phase t21, the ultrasonic control terminal COL applies an alternating driving voltage to the emitting electrode 321, causing the piezoelectric functional layer 322 to generate ultrasonic waves. The first output control terminal S1, the second output control terminal S2, and the third output control terminal S3 can all be input with a high level, and the first switching transistor M1, the reset transistor M2, and the second switching transistor M4 are all turned off.

[0113] During the reset phase t22, the ultrasonic control terminal COL no longer applies the alternating drive voltage to the transmitting electrode 321. The first output control terminal S1 and the second output control terminal S2 are input with a low level, and the first switching transistor M1 and the reset transistor M2 are turned on. The initialization signal provided by the initial voltage terminal V3 is output to node G through the reset transistor M2 to reset node G, and the initialization signal is output to the receiving electrode 321 of the ultrasonic sensing element through the first switching transistor M1 to reset the receiving electrode 321.

[0114] During the charge accumulation phase t23, the control signal terminal COL provides a constant voltage to the emitting electrode 321. The first output control terminal S1, the second output control terminal S2, and the third output control terminal S3 can all be input with a high level, and the first switching transistor M1, the reset transistor M2, and the second switching transistor M4 are all turned off. During this phase, the ultrasonic signal reaches the fingerprint area and, after reflection, reaches the piezoelectric functional layer 322. The piezoelectric functional layer 322 will generate a positive piezoelectric effect, resulting in multiple localized charge accumulations on its surface.

[0115] During the sampling phase t24, the first output control terminal S1 is input with a low level, and the first switching transistor M1 is turned on. The second output control terminal S2 is input with a high level, and the reset transistor M2 is turned off. The third output control terminal S3 is input with a low level, and the second switching transistor M4 is turned on. The first switching transistor M1 transmits the fingerprint electrical signal collected by the receiving electrode 321 to the gate electrode of the follower transistor M3, so that the follower transistor M3 generates a corresponding current signal, which is then output to the read signal terminal RL through the second switching transistor M4. The read signal terminal RL transmits the voltage signal corresponding to the current signal output by the follower transistor M4 to the processing circuit in the circuit board to obtain an image reflecting the fingerprint information.

[0116] The first light-emitting driving circuit and ultrasonic detection circuit described above are merely examples. This embodiment is not limited thereto.

[0117] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern."

[0118] The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0119] In some exemplary embodiments, the fabrication process of the display substrate may include the following operations, such as Figures 7A to 7P As shown.

[0120] (1) Form a separation layer (DBL, De-Bonding Layer) and a bonding electrode pattern on a glass substrate.

[0121] In some exemplary embodiments, a separation material is coated on a glass substrate 1, and a separation layer 40 pattern is formed using a patterning process; then, a bonding metal thin film is deposited on the separation layer 40, and a plurality of bonding electrode patterns are formed using a patterning process. Figure 7A As shown, a separation layer 40 and a plurality of bonding electrodes 41 are formed in the bonding region 400, with the plurality of bonding electrodes 41 located on the separation layer 40. In some examples, the separation material may be an organic material.

[0122] (2) Prepare a flexible substrate on a glass substrate.

[0123] In some exemplary embodiments, an organic material (e.g., polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film, etc.) is coated onto the glass substrate 1 forming the aforementioned structure, and the substrate 10 is formed by a patterning process. Figure 7BAs shown, a plurality of first bonding vias KA are formed on the substrate 10 of the bonding region 400. The substrate 10 within any of the first bonding vias KA is etched away, exposing the surface of the bonding electrode 41.

[0124] Following this process, both the display area 100 and the ultrasonic sensing area 300 include a flexible substrate 10.

[0125] (3) Prepare a passivation (PVX) layer on the substrate.

[0126] In some exemplary embodiments, a passivation film is deposited on the substrate 10 forming the aforementioned structure, and the passivation film is patterned using a patterning process to form a passivation layer 42. For example... Figure 7C As shown, a plurality of second binding vias KB are formed on the passivation layer 42 of the bonding region 400. The positions of the plurality of second binding vias KB correspond one-to-one with the positions of the plurality of first binding vias KA, and the second binding vias KB are connected to the corresponding first binding vias KA, exposing the surface of the bonding electrode 41.

[0127] Following this process, the display area 100 and the ultrasonic sensing area 300 include a substrate 10 and a passivation layer 42 stacked on the substrate 10.

[0128] (4) Prepare a fan-out lead layer pattern on the substrate.

[0129] In some exemplary embodiments, a fan-out metal thin film is deposited on the substrate 10 forming the aforementioned structure, and the fan-out metal thin film is patterned using a patterning process to form a fan-out lead layer pattern. For example... Figure 7D As shown, a fan-out lead layer is formed in the bonding region 400, and the fan-out lead layer includes multiple fan-out leads ( Figure 7D Only one fan-out lead 43 is shown in the diagram. The fan-out lead 43 is electrically connected to at least one bonding electrode 41 via a second bonding via KB and a first bonding via KA. In this exemplary embodiment, the fan-out lead 43 is connected to two bonding electrodes 41 to ensure signal transmission quality. However, this embodiment is not limited to this.

[0130] After this process, the film structure of the display area 100 and the ultrasonic sensing area 300 remains unchanged.

[0131] (5) Prepare an active layer pattern on the substrate.

[0132] In some exemplary embodiments, a first insulating film, a second insulating film, and an active layer film are sequentially deposited on a substrate 10 forming the aforementioned structure. The active layer film is patterned using a patterning process to form a first insulating layer 11 covering the entire substrate 10, a second insulating layer 12 disposed on the first insulating layer 11, and an active layer pattern disposed on the second insulating layer 12. For example... Figure 7E As shown, an active layer pattern is formed in the display area 100 and the ultrasonic sensing area 300, including at least a first active layer 21A and a second active layer 21B. The first active layer 21A is located in the display area 100, and the second active layer 21B is located in the ultrasonic sensing area 300.

[0133] After this patterning process, the bonding region 400 includes a separation layer 40, a plurality of bonding electrodes 41 disposed on the separation layer 40, a substrate 10, a passivation layer 42, a fan-out lead layer electrically connected to the bonding electrodes 41, a first insulating layer 11 and a second insulating layer 12 covering the fan-out lead layer.

[0134] (6) Prepare a first gate metal layer pattern on the substrate.

[0135] In some exemplary embodiments, a third insulating film and a first metal film are sequentially deposited on a substrate 10 forming the aforementioned structure. The first metal film is patterned using a patterning process to form a third insulating layer 13 covering the active layer pattern, and a first gate metal layer pattern disposed on the third insulating layer 13. For example... Figure 7F As shown, a first gate metal layer pattern is formed in the display area 100 and the ultrasonic sensing area 300, and includes at least a first gate electrode 22A, a second gate electrode 22B, a first capacitor electrode 23A, multiple gate lines (not shown), and multiple gate leads (not shown). The first gate electrode 22A and the first capacitor electrode 23A are located in the display area 100, and the second gate electrode 22B is located in the ultrasonic sensing area 300.

[0136] After this patterning process, the bonding area 400 includes: a separation layer 40, a plurality of bonding electrodes 41 disposed on the separation layer 40, a substrate 10, a first insulating layer 11, a fan-out lead layer electrically connected to the bonding electrodes 41, a first insulating layer 11 covering the fan-out lead layer, a second insulating layer 12 and a third insulating layer 13.

[0137] (7) Prepare a second gate metal layer pattern on the substrate.

[0138] In some exemplary embodiments, a fourth insulating film and a second metal film are sequentially deposited on the substrate 10 forming the aforementioned structure. The second metal film is patterned using a patterning process to form a fourth insulating layer 14 covering the first gate metal layer, and a second gate metal layer pattern disposed on the fourth insulating layer 14. For example... Figure 7GAs shown, a second gate metal layer pattern is formed in the display area 100, including at least a second capacitor electrode 23B, the position of which corresponds to the position of the first capacitor electrode 23A.

[0139] After this patterning process, the bonding area 400 includes: a separation layer 40, a plurality of bonding electrodes 41 disposed on the separation layer 40, a substrate 10, a first insulating layer 11, a fan-out lead layer electrically connected to the bonding electrodes 41, a first insulating layer 11 covering the fan-out lead layer, a second insulating layer 12, a third insulating layer 13 and a fourth insulating layer 14.

[0140] (8) Prepare a fifth insulating layer pattern on the substrate.

[0141] In some exemplary embodiments, a fifth insulating film is deposited on the substrate 10 forming the aforementioned structure, and the fifth insulating film is patterned using a patterning process to form a pattern of the fifth insulating layer 15 covering the second gate metal layer. For example... Figure 7H As shown, the fifth insulating layer 15 has multiple first vias K1, multiple second vias K2, and multiple third vias ( Figure 7H (Only one third via K3 is shown in the diagram). Multiple first vias K1 are formed in the display area 100, with the positions of two first vias K1 corresponding to the two ends of the first active layer 21A, respectively. The fifth insulating layer 15, the fourth insulating layer 14, and the third insulating layer 13 within any first via K1 are etched away, exposing the surface of the first active layer 21A. Multiple second vias K2 are formed in the ultrasonic sensing area 300, with the positions of two second vias K2 corresponding to the two ends of the second active layer 21B, respectively. The fifth insulating layer 15, the fourth insulating layer 14, and the third insulating layer 13 within any second via K2 are etched away, exposing the surface of the second active layer 21B. A third via K3 is formed in the bonding area 400, with the fifth insulating layer 15, the fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12, and the first insulating layer 11 within the third via K3 being etched away, exposing the surface of the fan-out lead 43.

[0142] (9) Prepare source and drain metal layer patterns on the substrate.

[0143] In some exemplary embodiments, a third metal thin film is deposited on the substrate 10 forming the aforementioned structure, and the third metal thin film is patterned using a patterning process to form a source / drain metal layer pattern on the fifth insulating layer 15. For example... Figure 7IAs shown, the source / drain metal layer pattern includes: a first source electrode 24A, a first drain electrode 25A, and a common electrode line 26 formed in the display area 100; a second source electrode 24B and a second drain electrode 25B formed in the ultrasonic sensing area 300; and a fan-out connection electrode 44 formed in the bonding area 400. The first source electrode 24A and the first drain electrode 25A are respectively connected to the first active layer 21A through a first via, and the second source electrode 24B and the second drain electrode 25B are respectively connected to the second active layer 21B through a second via. The fan-out connection electrode 44 is connected to the fan-out lead 43 through a third via.

[0144] In some examples, the source / drain metal layers may further include one or more of the following: polarization lines, power lines (VDD), compensation lines, and auxiliary cathodes. However, this embodiment is not limited to this. In some examples, the polarization lines may be configured to provide a charge discharge path to the display substrate during subsequent polarization processing. The polarization lines may be located at the edge of the display substrate and can be cut off during subsequent display motherboard cutting.

[0145] At this point, the circuit structure layer pattern has been fabricated on the substrate 10, as follows: Figure 7I As shown. In display area 100, a first active layer 21A, a first gate electrode 22A, a first source electrode 24A, and a first drain electrode 25A constitute a first thin-film transistor 101, and a first capacitor electrode 23A and a second capacitor electrode 23B constitute a first storage capacitor 104. In some examples, the first thin-film transistor 101 is, for example, Figure 3 The fourth transistor T4 in the first light-emitting driving circuit shown, and the first storage capacitor 104 are, for example, Figure 3 The first capacitor C1 in the first light-emitting driving circuit shown. In the ultrasonic sensing region 300, the second active layer 21B, the second gate electrode 22B, the second source electrode 24B, and the second drain electrode 25B constitute the second thin-film transistor 102. Figure 7I The illustration uses two second thin-film transistors 102 as an example. In some examples, the second thin-film transistors 102 are, for example, Figure 5 The ultrasonic detection circuit shown contains a first switching transistor M1. However, this embodiment is not limited to this.

[0146] (10) Prepare a sixth insulating layer on the substrate.

[0147] In some exemplary embodiments, a sixth insulating film is deposited on the substrate 10 forming the aforementioned structure, and the sixth insulating film is patterned using a patterning process to form a pattern of a sixth insulating layer 16 covering the source / drain metal layer. For example... Figure 7J As shown, the sixth insulating layer 16 has multiple fourth vias and multiple fifth vias. Figure 7JThe diagram only illustrates one fourth via K4 and one fifth via K5, along with multiple sixth vias K6. The fourth via K4 and the fifth via K5 are formed in the display area 100. The sixth insulating layer 16 within the fourth via K4 is etched away, exposing the surface of the first drain electrode of the first thin-film transistor 101. The sixth insulating layer 16 within the fifth via K5 is etched away, exposing the surface of the common electrode line 26. The sixth via K6 is formed in the ultrasonic sensing area 300, and the sixth insulating layer 16 within the sixth via K6 is etched away, exposing the surface of the second drain electrode of the second thin-film transistor 102.

[0148] After this patterning process, the bonding area 400 includes: a separation layer 40, a plurality of bonding electrodes 41 disposed on the separation layer 40, a substrate 10, a first insulating layer 11, a fan-out lead layer electrically connected to the bonding electrodes 41, a first insulating layer 11 covering the fan-out lead layer, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, and a sixth insulating layer 16.

[0149] (11) A plurality of receiving electrodes, a plurality of first connecting electrodes and a plurality of second connecting electrode patterns are prepared on a substrate.

[0150] In some exemplary embodiments, a fourth metal thin film is deposited on the substrate 10 on which the aforementioned structure is formed, and the fourth metal thin film is patterned by a patterning process to form a plurality of receiving electrodes, a plurality of first connecting electrodes, and a plurality of second connecting electrode patterns. Figure 7K The diagram only shows two receiving electrodes 321, one first connecting electrode 33, and one second connecting electrode 34. Figure 7K As shown, a receiving electrode 321 is formed in the ultrasonic sensing region 300, and the receiving electrode 321 is connected to the second drain electrode of the second thin-film transistor 102 through a sixth via K6. A first connecting electrode 33 and a second connecting electrode 34 are formed in the display region 100. The first connecting electrode 33 is connected to the first drain electrode of the first thin-film transistor 101 through a fourth via K4, and the second connecting electrode 34 is connected to the common electrode line 26 through a fifth via K5.

[0151] After this patterning process, the membrane structure of the bonding region 400 remained unchanged.

[0152] (12) Prepare a seventh insulating layer on the substrate and transfer micro-light-emitting elements.

[0153] In some exemplary embodiments, a seventh insulating film is deposited on the substrate 10 forming the aforementioned structure, and the seventh insulating film is patterned using a patterning process to form a pattern of the seventh insulating layer 17. For example... Figure 7L As shown, the seventh insulating layer 17 forms a plurality of first grooves and a plurality of second grooves in the display area 100. Figure 7L(Only one first groove and one second groove are shown in the diagram). The seventh insulating layer 17 in the first groove is etched away, exposing the surface of the first connecting electrode 33. The seventh insulating layer 17 in the second groove is etched away, exposing the surface of the second connecting electrode 34.

[0154] In some exemplary embodiments, the micro-light-emitting element is a Micro-LED. The micro-light-emitting element 31 includes a first electrode 311, a second electrode 312, and a light-emitting portion 310. The first electrode 311 is connected to a first end of the light-emitting portion 310, and the second electrode 312 is connected to a second end of the light-emitting portion 310. In some examples, the first electrode 311 can be an anode, and the second electrode 312 can be a cathode. However, this embodiment is not limited to this. In some examples, bonding material (e.g., solder paste) is added to the first groove and the second groove respectively in a vacuum environment using a dispensing machine, and the bonding of the micro-light-emitting element is completed using a transfer process. The first electrode 311 of the micro-light-emitting element is bonded to the first connecting electrode 33 through the bonding material in the first groove, and the second electrode 312 is bonded to the second connecting electrode 34 through the bonding material in the second groove. In this way, the first electrode 311 of the micro-light-emitting element is connected to the first drain electrode of the first thin-film transistor 101 through the first connecting electrode 33, and the second electrode 312 is connected to the common electrode line 26 through the second connecting electrode 34.

[0155] After this process, the bonding region 400 includes: a separation layer 40, a plurality of bonding electrodes 41 disposed on the separation layer 40, a substrate 10, a first insulating layer 11, a fan-out lead layer electrically connected to the bonding electrodes 41, a first insulating layer 11 covering the fan-out lead layer, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, a sixth insulating layer 16, and a seventh insulating layer 17.

[0156] (13) Prepare a transparent organic insulating layer on the substrate.

[0157] In some exemplary embodiments, a transparent organic insulating film is coated on the substrate 10 forming the aforementioned structure, and the transparent organic insulating film is patterned using a patterning process to form a patterned transparent organic insulating layer 18. For example... Figure 7M As shown, the transparent organic insulating layer 18 can cover the display area 100 and the bonding area 400, but the transparent organic insulating layer 18 is not provided within the ultrasonic sensing area 300. In some examples, the transparent organic insulating layer 18 can be provided in areas other than the ultrasonic sensing area 300. In some examples, the transparent organic insulating layer 18 can be made of materials such as polyimide (PI), acrylic, or polyethylene terephthalate.

[0158] After this process, the bonding region 400 includes: a separation layer 40, a plurality of bonding electrodes 41 disposed on the separation layer 40, a substrate 10, a first insulating layer 11, a fan-out lead layer electrically connected to the bonding electrodes 41, a first insulating layer 11 covering the fan-out lead layer, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, a sixth insulating layer 16, a seventh insulating layer 17, and a transparent organic insulating layer 18.

[0159] In this exemplary embodiment, covering multiple micro-light-emitting elements with a transparent organic insulating layer can encapsulate and protect the micro-light-emitting elements without reducing the light transmittance of the emitted light from the micro-light-emitting elements (for example, the light transmittance can be greater than 90%), thereby ensuring the display effect.

[0160] (14) Fabricate a piezoelectric functional layer on the substrate.

[0161] In some exemplary embodiments, a piezoelectric material is coated on the substrate 10 forming the aforementioned structure to form a piezoelectric functional layer 322 pattern. For example... Figure 7N As shown, a piezoelectric functional layer 322 is formed in the ultrasonic sensing region 300. The thickness of the piezoelectric functional layer 322 can be approximately equal to the thickness of the transparent organic insulating layer 18. In some examples, the absolute value of the thickness difference between the transparent organic insulating layer 18 and the piezoelectric functional layer 322 can be less than 1 micrometer (μm).

[0162] In some examples, the piezoelectric material may be, for example, polyvinylidene fluoride (PVDF), piezoelectric ceramics, electrets, etc. However, this embodiment is not limited to this.

[0163] In some exemplary embodiments, a self-aligned method is used, with the transparent organic insulating layer 18 serving as a mask, to polarize the piezoelectric functional layer 322 (e.g., by applying a strong DC electric field to the piezoelectric functional layer). During polarization, the charges generated during polarization can be discharged from the display substrate using polarization lines, avoiding any impact on the circuit structure of the display substrate. In this exemplary embodiment, the ultrasonic sensing region 300 is covered by the piezoelectric functional layer 322, and the remaining areas of the display substrate are covered by the transparent organic insulating layer 18. Therefore, during polarization, the piezoelectric functional layer 322 and the transparent organic insulating layer 18 can effectively protect the thin-film transistors in the circuit structure layer from damage or breakdown by the polarization electric field.

[0164] (15) Prepare an emission electrode layer pattern on the substrate.

[0165] In some exemplary embodiments, a fifth metal thin film is deposited on the substrate 10 forming the aforementioned structure, and a pattern for the emitter electrode layer is formed by a patterning process. For example... Figure 7OAs shown, the transmitting electrode layer is formed in the ultrasonic sensing region 300. The transmitting electrode layer includes a sheet-like transmitting electrode 323, which is in direct contact with the piezoelectric functional layer 322.

[0166] (16) Prepare a cover plate on the substrate.

[0167] In some exemplary embodiments, an adhesive layer 51 is formed on the substrate 10 forming the aforementioned structure using an optically clear adhesive (OCA), and a cover plate 52 (e.g., a glass cover plate) is attached to the adhesive layer 51. Figure 7P As shown, the cover plate 52 can cover the display area 100, the ultrasonic sensing area 300, and the bonding area 400.

[0168] After the above-described film structure is prepared, the display substrate can be peeled off from the glass substrate 1 using a peeling process. Then, utilizing the peelable metal properties of the separation layer 40, the separation layer 40 can be peeled off, allowing the bonding electrodes 41 of the display substrate to be bonded to the circuit board from the back side of the display substrate (i.e., the side of the display substrate facing away from the circuit structure layer). In this exemplary embodiment, the circuit board is disposed on the back side of the display substrate, that is, the circuit board is placed outside the ultrasonic wave transmission path. The ultrasonic wave will not pass through the circuit board during transmission, thus avoiding any interference from the circuit board to the ultrasonic wave transmission.

[0169] In some exemplary embodiments, the passivation film, the first insulating film, the second insulating film, the third insulating film, the fourth insulating film, the fifth insulating film, the sixth insulating film, and the seventh insulating film may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, multiple layers, or composite layers. The first insulating layer 11 is called a barrier layer, used to improve the substrate's resistance to water and oxygen; the second insulating layer 12 is called a buffer layer, used to improve the substrate's resistance to water and oxygen; the third insulating layer 13 and the fourth insulating layer 14 are called gate insulator (GI) layers; the fifth insulating layer 15 is called an interlayer dielectric (ILD) layer; and the sixth insulating layer 16 and the seventh insulating layer 17 are called passivation (PVX) layers. The bonding metal film, fan-out metal film, first metal film, second metal film, third metal film, fourth metal film, and fifth metal film can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The active layer film can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. Therefore, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0170] In this exemplary embodiment, the first light-emitting driving circuit and the ultrasonic detection circuit can be integrated in the circuit structure layer. The orthographic projections of the ultrasonic sensing element and the micro-light-emitting element on the substrate do not overlap, which can reduce the thickness of the display substrate. Moreover, the ultrasonic sensing element and the micro-light-emitting element are arranged side by side, so the ultrasonic signal does not need to pass through the circuit structure, which can reduce the loss of ultrasonic signal, thereby improving the signal-to-noise ratio and enhancing the ultrasonic detection effect. Furthermore, the ultrasonic detection circuit and the first light-emitting driving circuit are protected by a piezoelectric functional layer and a transparent organic insulating layer, respectively. During the polarization process of the piezoelectric functional layer of the ultrasonic sensing element, the transistors in the circuit structure layer can be prevented from being damaged or broken down by the polarization electric field.

[0171] The structure of the display substrate and its fabrication process in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased according to actual needs. For example, the first and second connecting electrodes can be omitted, the first electrode of the micro-light-emitting element can be directly connected to the first drain electrode of the first thin-film transistor, and the second electrode of the micro-light-emitting element can be directly connected to the common electrode line. Furthermore, the driving transistor can be a top-gate structure or a bottom-gate structure; it can be a single-gate structure or a dual-gate structure. However, this embodiment is not limited in this respect.

[0172] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0173] Figure 8 for Figure 1 Another cross-sectional view along the PP direction. (See diagram below.) Figure 8 As shown, in a plane perpendicular to the display substrate, the display area 100 of the display substrate includes: a substrate 10, a first insulating layer 11, a second insulating layer 12 and a circuit structure layer sequentially disposed on the substrate 10, and a plurality of micro-light-emitting elements disposed on the circuit structure layer. Figure 8 The diagram only illustrates one micro-light-emitting element 31), a transparent organic insulating layer 18 covering multiple micro-light-emitting elements, an adhesive layer 51 covering the transparent organic insulating layer 18, and a cover plate 52. The circuit structure layer of the display area 100 includes multiple first light-emitting driving circuits and multiple common electrode lines (…). Figure 8 Only one common electrode line 26 is shown in the diagram. Multiple first light-emitting driving circuits correspond one-to-one with multiple micro-light-emitting elements. The first light-emitting driving circuit may include multiple transistors and at least one storage capacitor. For example, the light-emitting driving circuit may be designed as 8T2C (i.e., eight thin-film transistors and two capacitors) or 13T1C (i.e., thirteen thin-film transistors and one capacitor). Figure 8 The illustration uses a first thin-film transistor 101 and a first storage capacitor 104 as an example. The micro-light-emitting element 31 may include: a light-emitting portion, a first electrode connected to the light-emitting portion, and a second electrode. The first electrode is connected to a first end of the light-emitting portion, and the second electrode is connected to a second end of the light-emitting portion. In some examples, the first electrode of the micro-light-emitting element 31 may be an anode, and the second electrode may be a cathode. The display area 100 also includes: a plurality of first connecting electrodes and a plurality of second connecting electrodes (…). Figure 8 (Only one first connecting electrode 33 and one second connecting electrode 34 are shown in the diagram.) The first electrode of the micro-light-emitting element 31 can be connected to the first drain electrode of the first thin-film transistor 101 through the first connecting electrode 33, and the second electrode of the micro-light-emitting element 31 can be connected to the common electrode line 26 through the second connecting electrode 34.

[0174] In some exemplary implementations, such as Figure 8 As shown, in a plane perpendicular to the display substrate, the ultrasonic sensing region 300 of the display substrate includes: a substrate 10, a first insulating layer 11, a second insulating layer 12 and a circuit structure layer sequentially disposed on the substrate 10, and a plurality of ultrasonic sensing elements disposed on the circuit structure layer. Figure 8 The diagram only illustrates two ultrasonic sensing elements, along with an adhesive layer 51 and a cover plate 52 covering multiple ultrasonic sensing elements. The circuit structure layer of the ultrasonic sensing region 300 includes multiple ultrasonic detection circuits, each corresponding one-to-one with a specific ultrasonic sensing element. Each ultrasonic detection circuit may include multiple transistors, for example, a 4T (four thin-film transistors) or 5T (five thin-film transistors) design. Figure 8 The diagram illustrates two ultrasonic detection circuits, with each circuit represented by a second thin-film transistor 102. The circuit structure layers of the ultrasonic sensing region 300 may include: an active layer, a third insulating layer 13, a first gate metal layer, a fourth insulating layer 14, a fifth insulating layer 15, and a source / drain metal layer sequentially disposed on the second insulating layer 12. The ultrasonic sensing element may include: a receiving electrode 321, a piezoelectric functional layer 322, and a transmitting electrode 323. The piezoelectric functional layer 322 may be configured to emit ultrasonic signals and receive ultrasonic signals reflected by a sensing object (e.g., a finger). The receiving electrode 321 may be disposed on the side of the piezoelectric functional layer 322 closest to the substrate 10, and the transmitting electrode 323 may be disposed on the side of the piezoelectric functional layer 322 furthest from the substrate 10. The transmitting electrode 323 is in direct contact with the piezoelectric functional layer 322, and a seventh insulating layer 17 is disposed between the receiving electrode 321 and the piezoelectric functional layer 322. The receiving electrode 321 may be connected to the second drain electrode of the second thin-film transistor 102 of the ultrasonic detection circuit. The transmitting electrode 323 can be connected to the ultrasonic control terminal (not shown) to receive the ultrasonic control signal provided by the ultrasonic control terminal.

[0175] In some exemplary implementations, such as Figure 8 As shown, in a plane perpendicular to the display substrate, the bonding area 400 of the display substrate includes: a substrate 10 and a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, and a plurality of bonding electrodes stacked on the substrate 10. Figure 8Only one bonding electrode 41 is shown in the diagram. Multiple bonding electrodes are disposed on the same side of the substrate 10 along with the circuit structure layer, micro-light-emitting elements, and ultrasonic sensing elements. In some examples, the multiple bonding electrodes may be configured to provide data signals and power signals to the first light-emitting driving circuit of the display area 100 via fan-out leads, provide various voltage signals to the ultrasonic detection circuit of the ultrasonic sensing area 300, provide ultrasonic control signals to the emitting electrode 323 of the ultrasonic sensing area 300, and transmit the fingerprint electrical signal detected by the ultrasonic detection circuit to an external circuit board. However, this embodiment is not limited to this.

[0176] In some exemplary embodiments, the fabrication process of the display substrate may include the following operations, such as Figures 9A to 9M As shown.

[0177] (1) A flexible substrate is prepared on a glass substrate, and an active layer pattern is prepared on the substrate.

[0178] In some exemplary embodiments, an organic material (e.g., polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer film) is coated onto a glass substrate 1, and a substrate 10 is formed by a patterning process, such as... Figure 9A As shown.

[0179] In some exemplary embodiments, a first insulating film, a second insulating film, and an active layer film are sequentially deposited on a substrate 10 forming the aforementioned structure. The active layer film is patterned using a patterning process to form a first insulating layer 11 covering the entire substrate 10, a second insulating layer 12 disposed on the first insulating layer 11, and an active layer pattern disposed on the second insulating layer 12. For example... Figure 9A As shown, an active layer pattern is formed in the display area 100 and the ultrasonic sensing area 300, including at least a first active layer 21A and a second active layer 21B. The first active layer 21A is located in the display area 100, and the second active layer 21B is located in the ultrasonic sensing area 300.

[0180] After this patterning process, the bonding area 400 includes a substrate 10 and a first insulating layer 11 and a second insulating layer 12 sequentially disposed on the substrate 10.

[0181] (2) Prepare the first gate metal layer pattern on the substrate.

[0182] In some exemplary embodiments, a third insulating film and a first metal film are sequentially deposited on a substrate 10 forming the aforementioned structure. The first metal film is patterned using a patterning process to form a third insulating layer 13 covering the active layer pattern, and a first gate metal layer pattern disposed on the third insulating layer 13. For example... Figure 9BAs shown, a first gate metal layer pattern is formed in the display area 100 and the ultrasonic sensing area 300, and includes at least a first gate electrode 22A, a second gate electrode 22B, a third gate electrode 22C, a first capacitor electrode 23A, multiple gate lines (not shown), and multiple gate leads (not shown). The first gate electrode 22A and the first capacitor electrode 23A are located in the display area 100, and the second gate electrode 22B is located in the ultrasonic sensing area 300.

[0183] After this patterning process, the bonding area 400 includes: a substrate 10, and a first insulating layer 11, a second insulating layer 12 and a third insulating layer 13 sequentially disposed on the substrate 10.

[0184] (3) Prepare a second gate metal layer pattern on the substrate.

[0185] In some exemplary embodiments, a fourth insulating film and a second metal film are sequentially deposited on the substrate 10 forming the aforementioned structure. The second metal film is patterned using a patterning process to form a fourth insulating layer 14 covering the first gate metal layer, and a second gate metal layer pattern disposed on the fourth insulating layer 14. For example... Figure 9C As shown, a second gate metal layer pattern is formed in the display area 100, including at least a second capacitor electrode 23B, the position of which corresponds to the position of the first capacitor electrode 23A.

[0186] After this patterning process, the bonding area 400 includes: a substrate 10, and a first insulating layer 11, a second insulating layer 12, a third insulating layer 13 and a fourth insulating layer 14 sequentially disposed on the substrate 10.

[0187] (4) Prepare a fifth insulating layer pattern on the substrate.

[0188] In some exemplary embodiments, a fifth insulating film is deposited on the substrate 10 forming the aforementioned structure, and the fifth insulating film is patterned using a patterning process to form a pattern of the fifth insulating layer 15 covering the second gate metal layer. For example... Figure 9D As shown, a plurality of first vias K1 and a plurality of second vias K2 are formed on the fifth insulating layer 15. The plurality of first vias K1 are formed in the display area 100, with the positions of two first vias K1 corresponding to the two ends of the first active layer 21A, respectively. The fifth insulating layer 15, the fourth insulating layer 14, and the third insulating layer 13 within any first via K1 are etched away, exposing the surface of the first active layer 21A. A plurality of second vias K2 are formed in the ultrasonic sensing area 300, with the positions of two second vias K2 corresponding to the two ends of the second active layer 21B, respectively. The fifth insulating layer 15, the fourth insulating layer 14, and the third insulating layer 13 within any second via K2 are etched away, exposing the surface of the second active layer 21B.

[0189] Following this process, the bonding area 400 includes: a substrate 10, and a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, and a fifth insulating layer 15 sequentially disposed on the substrate 10.

[0190] (5) Fabricate bonding electrode and source / drain metal layer patterns on the substrate.

[0191] In some exemplary embodiments, a third metal thin film is deposited on the substrate 10 forming the aforementioned structure, and the third metal thin film is patterned using a patterning process to form a plurality of bonding electrodes on the fifth insulating layer 15. Figure 9E The diagram only illustrates one bonding electrode 41) and the source / drain metal layer pattern. (See diagram for reference.) Figure 9E As shown, the source / drain metal layer pattern includes at least: a first source electrode 24A, a first drain electrode 25A, and a common electrode line 26 formed in the display area 100, and a second source electrode 24B and a second drain electrode 25B formed in the ultrasonic sensing area 300. A bonding electrode 41 is formed in the bonding area 400. The first source electrode 24A and the first drain electrode 25A are respectively connected to the first active layer 21A through a first via, and the second source electrode 24B and the second drain electrode 25B are respectively connected to the second active layer 21B through a second via.

[0192] In some examples, the source / drain metal layers may further include one or more of the following: polarization lines, power lines (VDD), compensation lines, and auxiliary cathodes. However, this embodiment is not limited to this. In some examples, the polarization lines may be configured to provide a charge discharge path to the display substrate during subsequent polarization processing. The polarization lines may be located at the edge of the display substrate and can be cut off during subsequent display motherboard cutting.

[0193] At this point, the circuit structure layer pattern has been fabricated on the substrate 10, as follows: Figure 9E As shown. In display area 100, a first active layer 21A, a first gate electrode 22A, a first source electrode 24A, and a first drain electrode 25A constitute a first thin-film transistor 101, and a first capacitor electrode 23A and a second capacitor electrode 23B constitute a first storage capacitor 104. In some examples, the first thin-film transistor 101 is, for example, Figure 3 The fourth transistor T4 in the first light-emitting driving circuit shown, and the first storage capacitor 104 are, for example, Figure 3 The first capacitor C1 in the first light-emitting driving circuit shown. In the ultrasonic sensing region 300, the second active layer 21B, the second gate electrode 22B, the second source electrode 24B, and the second drain electrode 25B constitute the second thin-film transistor 102. Figure 9E The illustration uses two second thin-film transistors 102 as an example. In some examples, the second thin-film transistors 102 are, for example, Figure 5The ultrasonic detection circuit shown contains a first switching transistor M1. However, this embodiment is not limited to this.

[0194] (6) Prepare a sixth insulating layer on the substrate.

[0195] In some exemplary embodiments, a sixth insulating film is deposited on the substrate 10 forming the aforementioned structure, and the sixth insulating film is patterned using a patterning process to form a pattern of a sixth insulating layer 16 covering the source / drain metal layer. For example... Figure 9F As shown, a plurality of fourth vias and a plurality of fifth vias are provided on the sixth insulating layer 16 of the display area 100. Figure 9F (Only one fourth via K4 and one fifth via K5 are shown in the diagram). The sixth insulating layer 16 within the fourth via K4 is etched away, exposing the surface of the first drain electrode of the first thin-film transistor 101. The sixth insulating layer 16 within the fifth via K5 is etched away, exposing the thin film of the common electrode line 26. Multiple sixth vias K6 are formed on the sixth insulating layer 16 of the ultrasonic sensing region 300. The sixth insulating layer 16 within the sixth via K6 is etched away, exposing the surface of the second drain electrode of the second thin-film transistor 102. The sixth insulating layer 16 of the bonding region 400 is etched away, exposing the surfaces of the bonding electrode 41 and the fifth insulating layer 15.

[0196] (7) A plurality of receiving electrodes, a plurality of first connecting electrodes and a plurality of second connecting electrode patterns are prepared on the substrate.

[0197] In some exemplary embodiments, a fourth metal thin film is deposited on the substrate 10 on which the aforementioned structure is formed, and the fourth metal thin film is patterned by a patterning process to form a plurality of receiving electrodes, a plurality of first connecting electrodes, and a plurality of second connecting electrode patterns. Figure 9G The diagram only shows two receiving electrodes 321, one first connecting electrode 33, and one second connecting electrode 34. Figure 9G As shown, a receiving electrode 321 is formed in the ultrasonic sensing region 300, and the receiving electrode 321 is connected to the second drain electrode of the second thin-film transistor 102 through a sixth via K6. A first connecting electrode 33 and a second connecting electrode 34 are formed in the display region 100. The first connecting electrode 33 is connected to the first drain electrode of the first thin-film transistor 101 through a fourth via K4, and the second connecting electrode 34 is connected to the common electrode line 26 through a fifth via K5.

[0198] After this patterning process, the membrane structure of the bonding region 400 remained unchanged.

[0199] (8) Prepare a seventh insulating layer on the substrate and transfer micro-light-emitting elements.

[0200] In some exemplary embodiments, a seventh insulating film is deposited on the substrate 10 forming the aforementioned structure, and the seventh insulating film is patterned using a patterning process to form a pattern of the seventh insulating layer 17. For example... Figure 9H As shown, the seventh insulating layer 17 forms a plurality of first grooves and a plurality of second grooves in the display area 100. Figure 9H (Only one first groove and one second groove are shown in the diagram). The seventh insulating layer 17 in the first groove is etched away, exposing the surface of the first connecting electrode 33. The seventh insulating layer 17 in the second groove is etched away, exposing the surface of the second connecting electrode 34.

[0201] In some exemplary embodiments, the micro-light-emitting element is a Micro-LED. The micro-light-emitting element includes a first electrode 311, a second electrode 312, and a light-emitting portion 310. The first electrode 311 is connected to a first end of the light-emitting portion 310, and the second electrode 312 is connected to a second end of the light-emitting portion 310. In some examples, the first electrode 311 can be an anode, and the second electrode 312 can be a cathode. However, this embodiment is not limited to this. In some examples, bonding material (e.g., solder paste) is added to the first and second grooves respectively using a dispensing machine in a vacuum environment, and a transfer process is used to complete the bonding of the micro-light-emitting element. The first electrode 311 of the micro-light-emitting element is bonded to the first connecting electrode 33 through the bonding material in the first groove, and the second electrode 312 is bonded to the second connecting electrode 34 through the bonding material in the second groove. In this way, the first electrode 311 of the micro-light-emitting element is connected to the first drain electrode of the first thin-film transistor 101 through the first connecting electrode 33, and the second electrode 312 is connected to the common electrode line 26 through the second connecting electrode 34.

[0202] After this patterning process, the membrane structure of the bonding region 400 remained unchanged.

[0203] (9) Prepare a transparent organic insulating layer on the substrate.

[0204] In some exemplary embodiments, a transparent organic insulating film is coated on the substrate 10 forming the aforementioned structure, and the transparent organic insulating film is patterned using a patterning process to form a patterned transparent organic insulating layer 18. For example... Figure 9I As shown, the transparent organic insulating layer 18 can cover the display area 100, while the ultrasonic sensing area 300 and the bonding area 400 are not provided with the transparent organic insulating layer 18.

[0205] In some examples, the transparent organic insulating layer 18 can be made of materials such as polyimide (PI), acrylic, or polyethylene terephthalate.

[0206] In this exemplary embodiment, covering multiple micro-light-emitting elements with a transparent organic insulating layer can encapsulate and protect the micro-light-emitting elements without reducing the light transmittance of the emitted light (e.g., the light transmittance can be greater than 90%).

[0207] After this patterning process, the membrane structure of the bonding region 400 remained unchanged.

[0208] (10) Fabricate a piezoelectric functional layer on the substrate.

[0209] In some exemplary embodiments, a piezoelectric material is coated on the substrate 10 forming the aforementioned structure to form a piezoelectric functional layer 322 pattern. For example... Figure 9J As shown, a piezoelectric functional layer 322 is formed in the ultrasonic sensing region 300. The thickness of the piezoelectric functional layer 322 can be approximately equal to the thickness of the transparent organic insulating layer 18. In some examples, the absolute value of the thickness difference between the transparent organic insulating layer 18 and the piezoelectric functional layer 322 can be less than 1 micrometer.

[0210] In some examples, the piezoelectric material may be, for example, polyvinylidene fluoride (PVDF), piezoelectric ceramics, electrets, etc. However, this embodiment is not limited to this.

[0211] In some exemplary implementations, such as Figure 9K As shown, when polarizing the piezoelectric functional layer 322 (e.g., applying a strong DC electric field to the piezoelectric functional layer), an insulating mask 5 is used to shield the bonding area 400, the display area 100 is covered by a transparent organic insulating layer 18, and the ultrasonic sensing area 300 is covered by the piezoelectric functional layer 322. In this way, during the polarization process, the mask 5, the transparent organic insulating layer 18, and the piezoelectric functional layer 322 can be used to protect the circuit structure of the display substrate, preventing the thin-film transistors from being damaged or broken down by the polarization electric field.

[0212] After this process, the film structure of the display area 100 and the bonding area 400 remains unchanged.

[0213] (11) Prepare an emission electrode layer pattern on the substrate.

[0214] In some exemplary embodiments, a fifth metal thin film is deposited on the substrate 10 forming the aforementioned structure, and a pattern for the emitter electrode layer is formed by a patterning process (e.g., by electroplating or silver paste screen printing). Figure 9L As shown, an emission electrode layer is formed in the ultrasonic sensing region 300. The emission electrode layer includes a sheet-like emission electrode 323, which is in direct contact with the piezoelectric functional layer 322. After this process, the film structure of the bonding region 400 remains unchanged.

[0215] (12) Prepare a cover plate on the substrate.

[0216] In some exemplary embodiments, an adhesive layer 51 is formed on the substrate 10 forming the aforementioned structure using an optically clear adhesive (OCA), and a cover plate 52 (e.g., a glass cover plate) is attached to the adhesive layer 51. Figure 9M As shown, cover plate 52 can cover display area 100 and ultrasonic sensing area 300. After this process, the film structure of bonding area 400 remains unchanged.

[0217] After the above-described film structure is prepared, the display substrate is first peeled off from the glass substrate 1 using a peeling process. In this exemplary embodiment, the bonding electrodes and the circuit structure layer are disposed on the same side of the display substrate (e.g., the front side of the display substrate). The bonding electrodes disposed on the front side of the display substrate can be bonded to a flexible circuit board, which can be bent to the back side of the display substrate to avoid affecting the transmission of ultrasonic waves.

[0218] In some exemplary embodiments, the first, second, third, fourth, fifth, sixth, and seventh insulating films may be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be single-layer, multi-layer, or composite layers. The first insulating layer 11 is called a barrier layer, used to improve the substrate's resistance to water and oxygen; the second insulating layer 12 is called a buffer layer, used to improve the substrate's resistance to water and oxygen; the third insulating layer 13 and the fourth insulating layer 14 are called gate insulation (GI) layers; the fifth insulating layer 15 is called an interlayer insulation (ILD) layer; and the sixth insulating layer 16 and the seventh insulating layer 17 are called passivation (PVX) layers. The first, second, third, fourth, and fifth metal thin films can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb). They can be single-layer structures or multi-layer composite structures, such as Mo / Cu / Mo. The active layer thin film can be made of one or more materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0219] In this exemplary embodiment, the first light-emitting driving circuit and the ultrasonic detection circuit can be integrated into the circuit structure layer. The orthographic projections of the ultrasonic sensing element and the micro-light-emitting element on the substrate do not overlap, which can reduce the thickness of the display substrate and facilitate the design of thinner and lighter display products. Moreover, the ultrasonic signal does not need to pass through the circuit structure, which can reduce the loss of ultrasonic signal, thereby improving the signal-to-noise ratio and enhancing the ultrasonic detection effect. Furthermore, during the polarization process of the piezoelectric functional layer, the display area, the ultrasonic sensing area, and the bonding area are protected by a transparent organic insulating layer, a piezoelectric functional layer, and a mask, respectively, which can prevent the transistors in the circuit structure layer from being damaged or broken down by the polarization electric field.

[0220] The structure of the display substrate and its fabrication process in this exemplary embodiment are merely illustrative. In some exemplary embodiments, the corresponding structure and the patterning process can be modified and increased or decreased according to actual needs. For example, the first and second connecting electrodes can be omitted, the first electrode of the micro-light-emitting element can be directly connected to the first drain electrode of the first thin-film transistor, and the second electrode of the micro-light-emitting element can be directly connected to the common electrode line. Furthermore, the driving transistor can be a top-gate structure or a bottom-gate structure; it can be a single-gate structure or a dual-gate structure. However, this embodiment is not limited in this respect.

[0221] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0222] Figure 10 This is another schematic diagram of a display substrate according to at least one embodiment of the present disclosure. Figure 10 As shown, the display substrate of this exemplary embodiment includes: a display area 100, a peripheral area 200 surrounding the display area 100, and a bonding area 400 on the side away from the display area 100. The display area 100 is provided with a plurality of regularly arranged micro-light-emitting elements and a plurality of ultrasonic sensing elements. The plurality of micro-light-emitting elements and the plurality of ultrasonic sensing elements can correspond one-to-one. In some examples, the micro-light-emitting elements can be Micro-LEDs or Mini-LEDs. The bonding area 400 is provided with a plurality of bonding electrodes that are bonded to an external circuit board (e.g., a flexible circuit board).

[0223] Figure 11 for Figure 10 A cross-sectional view along the QQ direction. (See diagram below.) Figure 11 As shown, in a plane perpendicular to the display substrate, the display area 100 of the display substrate includes: a substrate 10, a first insulating layer 11, a second insulating layer 12 and a circuit structure layer sequentially disposed on the substrate 10, and a plurality of micro-light-emitting elements and a plurality of ultrasonic sensing elements disposed on the circuit structure layer. Figure 11The diagram only illustrates one micro-light-emitting element 31 and one ultrasonic sensing element, a transparent organic insulating layer 18 covering multiple micro-light-emitting elements, an adhesive layer 51 covering the transparent organic insulating layer 18, and a cover plate 52. The multiple micro-light-emitting elements and the multiple ultrasonic sensing elements can be arranged in a one-to-one correspondence and adjacent to each other.

[0224] In some exemplary embodiments, the circuit structure layer may include multiple second light-emitting driving circuits with ultrasonic detection functions. These multiple second light-emitting driving circuits are connected one-to-one with multiple ultrasonic sensing elements, and also one-to-one with multiple micro-light-emitting elements. That is, the second light-emitting driving circuit integrates light-emitting driving and ultrasonic detection functions. However, this embodiment is not limited to this. In some examples, the circuit structure layer may include multiple first light-emitting driving circuits and multiple ultrasonic detection circuits, with the multiple first light-emitting driving circuits connected one-to-one with multiple micro-light-emitting elements, and the multiple ultrasonic detection circuits connected one-to-one with multiple ultrasonic sensing elements. That is, the first light-emitting driving circuits implement the light-emitting driving function, and the ultrasonic detection circuits implement the ultrasonic detection function.

[0225] In some exemplary implementations, such as Figure 11 As shown, the circuit structure layer of the display area 100 may include: an active layer, a third insulating layer 13, a first gate metal layer, a fourth insulating layer 14, a second gate metal layer, a fifth insulating layer 15, and a source / drain metal layer sequentially disposed on the second insulating layer 12. The active layer includes at least a first active layer and a second active layer; the first gate metal layer may include at least a first gate electrode, a second gate electrode, and a first capacitor electrode; the second gate metal layer may include at least a second capacitor electrode; the source / drain metal layer may include at least a first source electrode, a first drain electrode, a second source electrode, a second drain electrode, and a common electrode line 26. The first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute a first thin-film transistor 101, and the first capacitor electrode and the second capacitor electrode constitute a first storage capacitor 104. The second active layer, the second gate electrode, the second source electrode, and the second drain electrode constitute a first thin-film transistor 102.

[0226] In some exemplary implementations, such as Figure 11 As shown, in a plane perpendicular to the display substrate, the bonding area 400 of the display substrate may include: a substrate 10 and a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a fifth insulating layer 15, and a plurality of bonding electrodes stacked on the substrate 10. Figure 11 Only one bonding electrode 41 is illustrated in this example. In this exemplary embodiment, multiple bonding electrodes and the circuit structure layer are located on the same side of the substrate 10. However, this embodiment is not limited to this. In some examples, the bonding electrodes may be disposed on different sides of the substrate from the circuit structure layer; for example, the bonding electrodes may be disposed on the back side of the substrate.

[0227] In some exemplary implementations, such as Figure 11 As shown, the micro-light-emitting element 31 may include: a light-emitting portion, a first electrode connected to the light-emitting portion, and a second electrode. The first electrode is connected to a first end of the light-emitting portion, and the second electrode is connected to a second end of the light-emitting portion. In some examples, the first electrode of the micro-light-emitting element 31 may be an anode, and the second electrode may be a cathode. The first electrode of the micro-light-emitting element 31 may be connected to the first drain electrode of the first thin-film transistor 101 via a first connecting electrode 33, and the second electrode of the micro-light-emitting element 31 may be connected to the common electrode line 26 via a second connecting electrode 34. The ultrasonic sensing element may include: a receiving electrode 321, a piezoelectric functional layer 322, and a transmitting electrode 323. The receiving electrode 321 and the first connecting electrode 33 and the second connecting electrode 34 of the display area 100 may be of the same layer structure. The receiving electrode 321 is located on the side of the piezoelectric functional layer 322 closer to the substrate 10, and the transmitting electrode 323 is located on the side of the piezoelectric functional layer 322 away from the substrate 10. The transmitting electrode 323 is in direct contact with the piezoelectric functional layer 322, and a seventh insulating layer 17 is disposed between the receiving electrode 321 and the piezoelectric functional layer 322.

[0228] Other structures in this embodiment can be referred to the description of the above embodiments, and will not be repeated here.

[0229] The structure (or method) shown in this embodiment can be appropriately combined with the structure (or method) shown in other embodiments.

[0230] At least one embodiment of this disclosure also provides a method for fabricating a display substrate, comprising: forming a circuit structure layer on a substrate; and forming a plurality of micro-light-emitting elements and a plurality of ultrasonic sensing elements on the side of the circuit structure layer away from the substrate. The plurality of micro-light-emitting elements are electrically connected to the circuit structure layer, and the plurality of ultrasonic sensing elements are electrically connected to the circuit structure layer. The orthographic projections of the plurality of ultrasonic sensing elements on the substrate do not overlap with the orthographic projections of the plurality of micro-light-emitting elements on the substrate.

[0231] In some exemplary embodiments, the above-described fabrication method further includes forming a transparent organic insulating layer covering the multiple micro-light-emitting elements on the side away from the substrate. Each of the multiple ultrasonic sensing elements includes a piezoelectric functional layer. The transparent organic insulating layer is in direct contact with the piezoelectric functional layer of the ultrasonic sensing element, and the orthographic projection of the transparent organic insulating layer onto the substrate does not overlap with the orthographic projection of the piezoelectric functional layer of the multiple ultrasonic sensing elements onto the substrate.

[0232] In some exemplary embodiments, a plurality of micro-light-emitting elements are formed on the side of the circuit structure layer away from the substrate, including: forming a plurality of first connecting electrodes, a plurality of second connecting electrodes, and receiving electrodes of a plurality of ultrasonic sensing elements on the side of the circuit structure layer away from the substrate; forming a plurality of micro-light-emitting elements on the side of the plurality of first connecting electrodes and second connecting electrodes away from the substrate using a transfer process; forming a piezoelectric functional layer of ultrasonic sensing elements on the side of the plurality of receiving electrodes away from the substrate; and forming emitting electrodes of a plurality of ultrasonic sensing elements on the side of the piezoelectric functional layer away from the substrate. The plurality of first connecting electrodes, the plurality of second connecting electrodes, and the receiving electrodes are connected to the circuit structure layer. At least one micro-light-emitting element has a first electrode electrically connected to a first connecting electrode and a second electrode electrically connected to a second connecting electrode.

[0233] In some exemplary embodiments, a piezoelectric functional layer of multiple ultrasonic sensing elements is formed on the side of the receiving electrodes of multiple ultrasonic sensing elements away from the substrate, including: performing self-aligned polarization treatment on the piezoelectric functional layer using a transparent organic insulating layer; or, performing polarization treatment on the piezoelectric functional layer using a mask and a transparent organic insulating layer.

[0234] In some exemplary embodiments, the above-described fabrication method further includes: forming a plurality of bonding electrodes on a separation layer; forming a substrate on the side of the plurality of bonding electrodes away from the separation layer; and forming a fan-out lead layer on the substrate. The fan-out lead layer includes a plurality of fan-out leads, at least one of which is connected to at least one bonding electrode through a via penetrating the substrate.

[0235] In some exemplary embodiments, forming a circuit structure layer on a substrate includes: sequentially forming an active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, and a source / drain metal layer on the substrate.

[0236] The preparation method of this embodiment can be referred to the description of the foregoing embodiment, and therefore will not be repeated here.

[0237] Figure 12 This is a schematic diagram of a display device according to at least one embodiment of the present disclosure. Figure 12 As shown, this embodiment provides a display device 91, including a display substrate 910. The display substrate 910 is the display substrate provided in the aforementioned embodiment. The display substrate 910 can be a Micro-LED display substrate or a Mini-LED display substrate. The display device 91 can be any product or component with display function and ultrasonic detection function (e.g., fingerprint recognition function), such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator. However, this embodiment is not limited to this.

[0238] The accompanying drawings in this disclosure only illustrate the structures relevant to this disclosure; other structures can be referenced to common designs. Unless otherwise specified, embodiments of this disclosure and features thereof can be combined to obtain new embodiments.

[0239] Those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions disclosed herein without departing from the spirit and scope of the technical solutions disclosed herein, and all such modifications and substitutions should be covered within the scope of the claims of this disclosure.

Claims

1. A display substrate, comprising: Base; A circuit structure layer disposed on the substrate; Multiple ultrasonic sensing elements are disposed on the side of the circuit structure layer away from the substrate, and the multiple ultrasonic sensing elements are electrically connected to the circuit structure layer; Multiple micro-light-emitting elements are disposed on the side of the circuit structure layer away from the substrate, and the multiple micro-light-emitting elements are electrically connected to the circuit structure layer; The orthographic projections of the plurality of ultrasonic sensing elements on the substrate and the orthographic projections of the plurality of micro-luminescent elements on the substrate do not overlap; The display substrate further includes: a transparent organic insulating layer disposed on the side of the plurality of micro-light-emitting elements away from the substrate, the transparent organic insulating layer covering the plurality of micro-light-emitting elements; Each of the multiple ultrasonic sensing elements includes: a piezoelectric functional layer; The transparent organic insulating layer is in direct contact with the piezoelectric functional layer of the plurality of ultrasonic sensing elements, and the orthographic projection of the transparent organic insulating layer on the substrate does not overlap with the orthographic projection of the piezoelectric functional layer of the plurality of ultrasonic sensing elements on the substrate; the absolute value of the thickness difference between the transparent organic insulating layer and the piezoelectric functional layer is less than 1 micrometer.

2. The display substrate according to claim 1, wherein, At least one of the plurality of ultrasonic sensing elements further includes: a transmitting electrode and a receiving electrode; the transmitting electrode is located on the side of the piezoelectric functional layer away from the substrate; the receiving electrode is located on the side of the piezoelectric functional layer close to the substrate, and the receiving electrode is electrically connected to the circuit structure layer.

3. The display substrate according to claim 2, wherein, The transmitting electrode is in direct contact with the piezoelectric functional layer, and an insulating layer is provided between the receiving electrode and the piezoelectric functional layer.

4. The display substrate according to any one of claims 1 to 3, wherein, The circuit structure layer includes: multiple first light-emitting driving circuits and multiple ultrasonic detection circuits; the multiple ultrasonic detection circuits are connected to the multiple ultrasonic sensing elements in a one-to-one correspondence; the multiple first light-emitting driving circuits are connected to the multiple micro light-emitting elements in a one-to-one correspondence. Alternatively, the circuit structure layer includes: a plurality of second light-emitting driving circuits with ultrasonic detection function, wherein the plurality of second light-emitting driving circuits are connected one-to-one with the plurality of ultrasonic sensing elements, and the plurality of second light-emitting driving circuits are connected one-to-one with the plurality of micro-light-emitting elements.

5. The display substrate according to claim 4, wherein, The circuit structure layer also includes: multiple common electrode lines; At least one of the plurality of micro-light-emitting elements includes: a light-emitting part, a first electrode and a second electrode connected to the light-emitting part; the first electrode is electrically connected to a corresponding first light-emitting driving circuit or a second light-emitting driving circuit, and the second electrode is electrically connected to the common electrode line.

6. The display substrate according to claim 5, further comprising: The at least one micro-light-emitting element has multiple first connecting electrodes and multiple second connecting electrodes. The first electrode of the at least one micro-light-emitting element is electrically connected to the corresponding first light-emitting driving circuit or second light-emitting driving circuit through the first connecting electrode, and the second electrode of the at least one micro-light-emitting element is electrically connected to the common electrode line through the second connecting electrode.

7. The display substrate according to claim 6, wherein, The plurality of first connecting electrodes and the plurality of second connecting electrodes are in the same layer as the receiving electrode of the at least one ultrasonic sensing element.

8. The display substrate according to claim 1, wherein, The substrate includes a display area and an ultrasonic sensing area located on one side of the display area; the plurality of ultrasonic sensing elements are located in the ultrasonic sensing area, and the plurality of micro-light-emitting elements are located in the display area; Alternatively, the substrate may include a display area, in which the plurality of ultrasonic sensing elements and the plurality of micro-light-emitting elements are regularly arranged.

9. The display substrate according to claim 8, wherein, The substrate further includes: a bonding region located on one side of the display area; the bonding region includes: a plurality of bonding electrodes; the plurality of bonding electrodes and the circuit structure layer are located on the same side of the substrate, or the plurality of bonding electrodes and the circuit structure layer are located on different sides of the substrate.

10. The display substrate according to claim 9, wherein, The plurality of bonding electrodes and the circuit structure layer are located on different sides of the substrate. The bonding region further includes a fan-out lead layer, which is located on the same side of the substrate as the circuit structure layer. The fan-out lead layer includes a plurality of fan-out leads, at least one of which is connected to at least one bonding electrode through a via penetrating the substrate.

11. The display substrate according to claim 9, wherein, The circuit structure layer includes: an active layer, a first gate metal layer, a second gate metal layer, and a source / drain metal layer sequentially disposed on the substrate; a first gate insulating layer is disposed between the active layer and the first gate metal layer, a second gate insulating layer is disposed between the first gate metal layer and the second gate metal layer, and an interlayer insulating layer is disposed between the second gate metal layer and the source / drain metal layer.

12. The display substrate according to claim 11, wherein, The plurality of bonded electrodes and the circuit structure layer are located on the same side of the substrate, and the plurality of bonded electrodes and the source / drain metal layer are of the same layer structure.

13. A display device, comprising: The display substrate as described in any one of claims 1 to 12.

14. A method for preparing a display substrate, comprising: A circuit structure layer is formed on the substrate; Multiple micro-light-emitting elements and multiple ultrasonic sensing elements are formed on the side of the circuit structure layer away from the substrate; wherein, the multiple micro-light-emitting elements are electrically connected to the circuit structure layer, the multiple ultrasonic sensing elements are electrically connected to the circuit structure layer, and the orthographic projections of the multiple ultrasonic sensing elements on the substrate and the orthographic projections of the multiple micro-light-emitting elements on the substrate do not overlap. The preparation method further includes: forming a transparent organic insulating layer covering the plurality of micro-light-emitting elements on the side of the plurality of micro-light-emitting elements away from the substrate; The plurality of ultrasonic sensing elements each include a piezoelectric functional layer; the transparent organic insulating layer is in direct contact with the piezoelectric functional layer of the ultrasonic sensing element, and the orthographic projection of the transparent organic insulating layer on the substrate does not overlap with the orthographic projection of the piezoelectric functional layer of the plurality of ultrasonic sensing elements on the substrate; the absolute value of the thickness difference between the transparent organic insulating layer and the piezoelectric functional layer is less than 1 micrometer.

15. The preparation method according to claim 14, wherein, The circuit structure layer comprises a plurality of micro-light-emitting elements and a plurality of ultrasonic sensing elements formed on the side away from the substrate, including: A plurality of first connecting electrodes, a plurality of second connecting electrodes, and a plurality of receiving electrodes for an ultrasonic sensing element are formed on the side of the circuit structure layer away from the substrate, and the plurality of first connecting electrodes, the plurality of second connecting electrodes, and the receiving electrodes are connected to the circuit structure layer. Multiple micro-light-emitting elements are formed on the side of the plurality of first connecting electrodes and the plurality of second connecting electrodes away from the substrate by a transfer process; the first electrode of at least one of the plurality of micro-light-emitting elements is electrically connected to the first connecting electrode, and the second electrode of at least one of the plurality of micro-light-emitting elements is electrically connected to the second connecting electrode. A piezoelectric functional layer of the plurality of ultrasonic sensing elements is formed on the side of the receiving electrodes of the plurality of ultrasonic sensing elements away from the substrate; The emitting electrodes of the plurality of ultrasonic sensing elements are formed on the side of the piezoelectric functional layer away from the substrate.

16. The preparation method according to claim 15, wherein, A piezoelectric functional layer of the plurality of ultrasonic sensing elements is formed on the side of the receiving electrodes of the plurality of ultrasonic sensing elements away from the substrate, including: The piezoelectric functional layer is subjected to self-aligned polarization treatment using the transparent organic insulating layer; or, The piezoelectric functional layer is polarized using a photomask and the transparent organic insulating layer.

17. The preparation method according to claim 14, further comprising: Multiple bonding electrodes are formed on the separation layer; A substrate is formed on the side of the plurality of bonded electrodes away from the separation layer; A fan-out lead layer is formed on the substrate, the fan-out lead layer including a plurality of fan-out leads, at least one of the plurality of fan-out leads being connected to at least one bonding electrode through a via penetrating the substrate.

18. The preparation method according to claim 14, wherein, The process of forming a circuit structure layer on the substrate includes: An active layer, a first gate insulating layer, a first gate metal layer, a second gate insulating layer, a second gate metal layer, an interlayer insulating layer, and a source / drain metal layer are sequentially formed on the substrate.

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