Display module and display device

Abstract

The present invention provides a display module and a display device, belonging to the field of display technology. The display module of the present invention includes a display panel and a light control panel arranged in a stacked manner; the light control panel has a dimming area and a peripheral area surrounding the dimming area; the light control panel includes: a first substrate and a second substrate arranged opposite to each other, and a first liquid crystal layer arranged between the first substrate and the second substrate; wherein, the first substrate includes: a first base, signal transmission lines, arranged on a side of the first base close to the first liquid crystal layer and located in the peripheral area; the second substrate includes: a second base, a first black matrix layer, arranged on a side of the second base close to the first liquid crystal layer and located in the dimming area and the peripheral area; wherein, the first black matrix layer has a slot located in the peripheral area, and at least part of the position of the slot is located on a side of the projection of the signal transmission line on the first base close to the dimming area in the projection of the first base.

Description

Technical Field

[0001] The present invention belongs to the field of display technology, and particularly relates to a display module and a display device. Background Art

[0002] With the continuous development of display technology by users, currently, the industry can adopt a variety of technologies to improve the contrast of the display screen, and the dual-cell regional brightness adjustment technology is one of them. Currently, a display device adopting the dual-cell regional brightness adjustment technology generally includes a light control panel and a display panel. The light control panel is a black-and-white display to control the display brightness of different regions, and the display panel is a normal display. By adopting the dual-cell regional brightness adjustment technology, the contrast of the display screen can be increased from the original 1000 to more than 100,000. Therefore, the contrast of the display screen can be significantly improved, thereby improving the display effect and enhancing the user experience. Summary of the Invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art, and provides a display module and a display device.

[0004] In a first aspect, an embodiment of the present disclosure provides a display module, which includes a display panel and a light control panel arranged in a stacked manner; the light control panel has a dimming area and a peripheral area surrounding the dimming area; the light control panel includes: a first substrate and a second substrate arranged opposite to each other, and a first liquid crystal layer disposed between the first substrate and the second substrate; wherein,

[0005] The first substrate includes:

[0006] A first base,

[0007] A signal transmission line, disposed on a side of the first base close to the first liquid crystal layer and located in the peripheral area;

[0008] The second substrate includes:

[0009] A second base,

[0010] A first black matrix layer, disposed on a side of the second base close to the first liquid crystal layer and located in the dimming area and the peripheral area; wherein,

[0011] The first black matrix layer has a slot located in the peripheral area, and at least a part of the position of the slot is located on a side of the projection of the signal transmission line on the first base close to the dimming area in the projection of the first base.

[0012] Wherein, the slot includes a continuous pattern surrounding the dimming area.

[0013] Wherein, the number of the slots is at least one, and the signal transmission line is disposed around the dimming area.

[0014] The dimming area includes a first side and a second side oppositely disposed along a first direction, and a third side and a fourth side oppositely disposed along a second direction.

[0015] Each of the slots includes a first slot portion and a second slot portion oppositely disposed along the first direction, and a third slot portion and a fourth slot portion oppositely disposed along the second direction.

[0016] For the slot closest to the dimming area, the distance between the first slot portion and the first side of the dimming area is equal to the distance between the second slot portion and the second side of the dimming area, and the distance is d1.

[0017] For the slot closest to the dimming area, the closest distance between the first slot portion and the signal transmission line is equal to the closest distance between the second slot portion and the signal transmission line, and the distance is d2.

[0018] For the slot closest to the dimming area, the distance between the third slot portion and the third side of the dimming area is equal to the distance between the fourth slot portion and the fourth side of the dimming area, and the distance is d3.

[0019] For the slot closest to the dimming area, the closest distance between the third slot portion and the signal transmission line is equal to the closest distance between the fourth slot portion and the signal transmission line, and the distance is d4.

[0020] d1:d2 = kd3:d4, 0.8 < k < 1.2.

[0021] Wherein, the range of d1:d2 is 4:1 to 6:1.

[0022] Wherein, the first substrate further includes a signal connection line disposed on the first base; the signal connection line includes a first sub-signal line and a second sub-signal line which are electrically connected and located in different layers; the connection position of the first sub-signal line and the second sub-signal line is located in the peripheral area; the slot is formed with a protrusion at the connection position corresponding to the first sub-signal line and the second sub-signal line, so that the positive projection of the slot and the connection position of the first sub-signal line and the second sub-signal line on the first base has no overlap.

[0023] Wherein, the first sub-signal line includes a first common electrode line, and the second sub-signal line includes a first common voltage introduction line; one end of the first common voltage introduction line is connected to the first common electrode line, and the other end is connected to a first common electrode.

[0024] The orthographic projection of the protrusion on the first substrate overlaps with the orthographic projection of the first common electrode line on the first substrate.

[0025] Wherein, the signal transmission line includes a first common electrode line.

[0026] Wherein, the first substrate further includes:

[0027] A plurality of dimming units and a plurality of redundant dimming units, disposed on a side of the first substrate close to the first liquid crystal layer, and the plurality of dimming units are located in the dimming area, and the plurality of redundant dimming units are located in the peripheral area; each of the plurality of dimming units and the plurality of redundant dimming units includes a first thin film transistor, a dimming electrode, and a first common electrode disposed on the first substrate;

[0028] The dimming electrode of the redundant dimming unit is electrically connected to the first common electrode.

[0029] Wherein, the orthographic projection of the slotted opening on the first substrate overlaps with the orthographic projection of the redundant dimming unit on the first substrate.

[0030] Wherein, the plurality of dimming units and the plurality of redundant dimming units are arranged side by side in a second direction to form a plurality of first dimming unit groups, and the dimming units and the redundant dimming units in each of the plurality of first dimming unit groups are arranged in a first direction; the plurality of dimming units and the plurality of redundant dimming units are arranged side by side in a first direction to form a plurality of second dimming unit groups, and the dimming units and the redundant dimming units in each of the plurality of second dimming unit groups are arranged in a second direction; the gates of the first thin film transistors of the dimming units and the redundant dimming units located in the same first dimming unit group are connected to the same first gate line; the dimming units and the redundant dimming units located in the same second dimming unit group are provided with data voltages by two first data lines, and the sources of the adjacent first thin film transistors are connected to different first data lines;

[0031] The first substrate further includes:

[0032] A first transparent conductive layer, disposed on a side of the first substrate close to the first liquid crystal layer, and the first transparent conductive layer includes the dimming electrode; the dimming electrode includes a plurality of first opening portions arranged side by side in the second direction, and each of the plurality of first opening portions extends in the first direction;

[0033] The first metal conductive layer is disposed on a side of the first substrate close to the first liquid crystal layer. The first metal conductive layer includes a plurality of first gate lines arranged side by side in the second direction, the gates of the respective first thin film transistors, and the common electrode line. Each of the plurality of first gate lines extends in the first direction, and the orthographic projection of the first gate line and the gate of the first thin film transistor on the first substrate falls within the orthographic projection of the first opening on the first substrate.

[0034] The first gate insulating layer is disposed on a side of the first metal conductive layer away from the first substrate.

[0035] The active semiconductor layer is disposed on a side of the first gate insulating layer away from the first metal conductive layer. The active semiconductor layer includes the active layers of the respective first thin film transistors.

[0036] The second metal conductive layer is disposed on a side of the active semiconductor layer away from the first gate insulating layer. The second metal conductive layer includes a plurality of first data lines arranged side by side in the first direction, and the sources and drains of the respective first thin film transistors. The source and drain of the first thin film transistor are respectively connected to the active layer. Each of the plurality of first data lines extends in the second direction.

[0037] The first interlayer insulating layer is disposed on a side of the second metal conductive layer away from the first interlayer insulating layer. The first substrate further includes a first connection via, a second connection via that penetrate the first interlayer insulating layer and the first gate insulating layer, and a third connection via that penetrates the first interlayer insulating layer.

[0038] The second transparent conductive layer is disposed on a side of the first interlayer insulating layer away from the second metal conductive layer. The second transparent conductive layer includes the first common electrodes of the respective dimming units and the redundant dimming units, and the first connection electrodes. The first connection electrode electrically connects the drain of the first thin film transistor and the dimming electrode through the first connection via and the third connection via. The first common electrode is electrically connected to the common electrode line through the second connection via.

[0039] Wherein, the first black matrix layer includes a first light-shielding portion located in the dimming region and a second light-shielding portion located in the peripheral region.

[0040] The first light-shielding portion includes a plurality of sub-light-shielding portions arranged side by side in the second direction. Each of the plurality of sub-light-shielding portions extends in the first direction. The orthographic projection of one sub-light-shielding portion on the first substrate covers the orthographic projection of one first gate line on the first substrate.

[0041] Among them, the dimming electrode further includes a plurality of second opening portions arranged side by side along the first direction, each of the plurality of second opening portions extending along the second direction; and the positive projection of the first data line on the first substrate falls within the positive projection of the second opening portion on the first substrate.

[0042] Among them, the second transparent conductive layer further includes a plurality of third opening portions formed on the dimming electrode and arranged side by side along the second direction; each of the plurality of third opening portions extends along the first direction, one of the third opening portions is correspondingly arranged with one of the first gate line portions, and their positive projections on the first substrate at least partially overlap.

[0043] Among them, the first transparent conductive layer further includes a plurality of first connection portions arranged at intervals, the first connection portions are electrically connected to the dimming electrodes in the redundant dimming units, and are directly lapped with the first common electrode line.

[0044] Among them, the first substrate further includes a gate driving circuit disposed on the first substrate and located in the peripheral area, and a plurality of gate signal introduction lines, detection signal lines, and compensation signal lines connected to the gate driving circuit; one of the gate signal introduction lines is connected to one of the first gate lines; the detection signal line is connected to one of the first gate lines;

[0045] The first metal conductive layer further includes the detection signal line and the compensation signal line;

[0046] The second metal conductive layer further includes the plurality of gate signal introduction lines.

[0047] Among them, a second connection portion is connected to the end of the first gate line, and a third connection portion is connected to the end of the gate signal introduction line; the second transparent conductive layer further includes a second connection electrode; the first substrate further includes a fourth connection via hole penetrating through the first gate insulating layer and the first interlayer insulating layer, and a fifth connection via hole penetrating through the first interlayer insulating layer; the second connection electrode electrically connects the second connection portion and the third connection portion through the fourth connection via hole and the fifth connection via hole.

[0048] Among them, the first metal conductive layer further includes redundant gate lines extending along the first direction, and the redundant gate lines are connected to the first common electrode line; at least one group in the first dimming unit group only includes the redundant dimming units, and the first gate line connected to the gate of the first thin film transistor in the first dimming unit group is connected to the first common electrode line.

[0049] Among them, the width of the slot is greater than or equal to 18 μm.

[0050] Wherein, the display panel includes a third substrate and a fourth substrate which are oppositely arranged, and a second liquid crystal layer disposed between the third substrate and the fourth substrate; the third substrate is located on a side of the second substrate away from the first liquid crystal layer; the display panel has a display area and a non-display area surrounding the display area;

[0051] A positive projection of the display area on the first substrate is located within a positive projection of the light control area on the first substrate.

[0052] In a second aspect, an embodiment of the present disclosure provides a display device, which includes any one of the above-mentioned display modules. Description of the Drawings

[0053] Figure 1 It is a schematic diagram of an exemplary dual liquid crystal cell display module.

[0054] Figure 2 It is Figure 1 A schematic layout diagram of the light control units of the light control panel in the shown display module.

[0055] Figure 3 It is Figure 1 A cross-sectional view of the light control area of the light control panel in the shown display module.

[0056] Figure 4 It is Figure 1 A cross-sectional view of the peripheral area of the light control panel in the shown display module.

[0057] Figure 5 It is Figure 1 A cross-sectional view of the display area of the display panel in the shown display module.

[0058] Figure 6 It is Figure 1 A cross-sectional view of the non-display area of the display panel in the shown display module.

[0059] Figure 7 It is Figure 1 A schematic diagram of the first black matrix layer of the light control panel in the shown display module.

[0060] Figure 8 It is a schematic diagram of a first black matrix layer of the light control panel in the display module of the embodiment of the present disclosure.

[0061] Figure 9 It is a schematic diagram of another first black matrix layer of the light control panel in the display module of the embodiment of the present disclosure.

[0062] Figure 10 It is a layout diagram of the display module of the embodiment of the present disclosure.

[0063] Figure 11Schematic diagram of the display module according to an embodiment of the present disclosure.

[0064] Figure 12 Schematic diagram of the first transparent conductive layer in the display module according to an embodiment of the present disclosure.

[0065] Figure 13 Schematic diagram of the first metal conductive layer in the display module according to an embodiment of the present disclosure.

[0066] Figure 14 Schematic diagram of the active semiconductor layer in the display module according to an embodiment of the present disclosure.

[0067] Figure 15 Schematic diagram of the second metal conductive layer in the display module according to an embodiment of the present disclosure.

[0068] Figure 16 Schematic diagram of the via distribution in the interlayer insulating layer of the display module according to an embodiment of the present disclosure.

[0069] Figure 17 Schematic diagram of the second transparent conductive layer in the display module according to an embodiment of the present disclosure.

[0070] Figure 18 Schematic diagram of the connection between the first common electrode and the first common electrode line in the display module according to an embodiment of the present disclosure.

[0071] Figure 19 Schematic diagram of the connection between the second connection portion and the third connection portion in the display module according to an embodiment of the present disclosure.

[0072] Figure 20 Schematic diagram of another first black matrix layer of the light control panel in the display module according to an embodiment of the present disclosure. Detailed implementation manners

[0073] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners.

[0074] Unless otherwise defined, technical terms or scientific terms used in this disclosure shall have the ordinary meanings as understood by those of ordinary skill in the art to which this disclosure pertains. The terms "first", "second" and similar words used in this disclosure do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a", "an" or "the" do not denote a quantity limitation, but mean that there is at least one. Words such as "comprising" or "including" mean that the elements or objects appearing before this word cover the elements or objects listed after this word and their equivalents, without excluding other elements or objects. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Upper", "lower", "left", "right", etc. are only used to indicate relative positional relationships, and when the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0075] Figure 1 A schematic diagram of an exemplary dual liquid crystal cell display module, as Figure 1 shown, the display module includes a light control panel 100 and a display panel 200 arranged in a stacked manner. The light control panel 100 is used to control the light transmittance of the light emitted by the backlight; the display panel 200 is used for displaying images.

[0076] Figure 2 is Figure 1 a schematic diagram of the arrangement of the dimming units of the light control panel in the shown display module; Figure 3 is Figure 1 a cross-sectional view of the dimming area of the light control panel in the shown display module; Figure 4 is Figure 1 a cross-sectional view of the peripheral area of the light control panel in the shown display module. As Figures 2 - 4 shown, the light control panel 100 has a dimming area Q11 and a peripheral area Q12 surrounding the dimming area Q11; there are dimming components in the dimming area Q11, and signal transmission lines for providing signals to the dimming components are provided in the peripheral area Q12; in the following description, taking the signal transmission line as the first common electrode line 20 as an example, of course, it should be understood that the signal transmission line is not limited to the first common electrode line 20, and it may also include ground wires, etc. Therefore, the signal transmission line being the first common wire 20 does not constitute a limitation on the protection scope of the embodiments of this disclosure.

[0077] Specifically, the light control panel 100 includes a first substrate and a second substrate disposed opposite to each other, and a first liquid crystal layer 30 disposed between the first substrate and the second substrate. A first lower polarizer (not shown in the figure) is disposed on a side of the first substrate facing away from the first liquid crystal layer. Among them, the first substrate includes a first base 11, a plurality of dimming units 01 disposed on the first base 11 and located in the dimming area Q11, a plurality of redundant dimming units (not shown in the figure) disposed on the first base 11 and located in the peripheral area Q11, and a first common electrode line 20. The redundant dimming units are disposed on a side of the first common electrode line 20 close to the dimming area Q11. The structures of the dimming units 01 and the redundant dimming units may be the same, and the redundant dimming units can repair the dimming units 01 when the dimming units Q11 are defective. Each dimming unit 01 and redundant dimming unit may include a first thin film transistor T1, a dimming electrode 010, and a first common electrode 020. The second substrate includes a second base 21 and a first black matrix layer BM1 disposed on the second base 21. The first black matrix layer BM1 has a plurality of first hollow portions located in the dimming area Q11, and one first hollow portion corresponds to one dimming electrode 010. For example, the first hollow portions and the dimming electrodes 010 are arranged in one-to-one correspondence, and the first hollow portions and the dimming electrodes 010 are completely overlapped in the orthographic projection on the first base 11.

[0078] Continue to refer to Figure 3, in the first substrate, a dimming electrode 010 and a first common electrode 020 are sequentially disposed on a first substrate 11. The dimming electrode 010 may adopt a plate-shaped electrode, while the first common electrode 020 adopts a slit electrode. Since the light control panel 100 is used to adjust the light transmittance of the backlight, the light control panel 100 is transmissive. Therefore, the dimming electrode 010 and the first common electrode 020 are made of a transparent conductive material, such as indium tin oxide (ITO). Additionally, since the first common electrodes 020 of each dimming unit 01 and the redundant dimming unit can be applied with the same voltage during operation, each first common electrode 020 may be an integrally formed structure. The first thin film transistor T1 is a bottom-gate thin film transistor, and its gate electrode adopts a metal conductive material. Since the patterning process (wet etching) of the gate electrode is different from the patterning process (dry etching) of the dimming electrode 010, the gate electrodes of each first thin film transistor T1 can be directly formed on the layer where the dimming electrode 010 is located. The first common electrode line 20 may be disposed on the same layer as the gate electrodes of each first thin film transistor T1 and use the same material, that is, the first common electrode line 20 is formed simultaneously when forming the gate electrodes of each first thin film transistor T1. A first gate insulating layer 12 is formed on the layer where the gate electrodes of each first thin film transistor T1 are located. The active layer of each first thin film transistor T1 is formed on the first gate insulating layer 12. Respective source and drain electrodes are formed on the active layer of each first thin film transistor T1. A first interlayer insulating layer 13 is formed on the source and drain electrodes of each first thin film transistor T1, and the first common electrode 020 is formed on the first interlayer insulating layer 13. At this time, a first connection electrode 14 may be formed on the layer where the first common electrode 020 is located, and the first common electrode 020 and the first connection electrode 14 are made of the same material, that is, the two can be formed in a single patterning process. A first connection via penetrating the first gate insulating layer 12 and the first interlayer insulating layer 13, and a third connection via penetrating the first interlayer insulating layer 13 are also formed in the first substrate. The first connection electrode 14 can electrically connect the drain electrode of the first thin film transistor T1 and the dimming electrode 010 through the first connection via and the second connection via. It should be noted that the first connection via and the third connection via can be formed in a single patterning process, and they can be not only independently disposed but also interconnected. Additionally, a second connection via penetrating the first gate insulating layer 12 and the first interlayer insulating layer 13 is further included in the first substrate, and the first common electrode 020 and the first common electrode line 20 are electrically connected through the second connection via.

[0079] For example: Continuing to refer to Figure 2, the dimming units 01 and redundant dimming units in the first substrate can be arranged in an array, forming a plurality of first dimming unit groups 10a arranged side by side in the second direction. The dimming units 01 and redundant dimming units in each first dimming unit group 10a are arranged in the first direction. At the same time, a plurality of second dimming unit groups 10b arranged side by side in the first direction are also formed. The dimming units 01 and redundant dimming units in each second dimming unit group 10b are arranged in the second direction. It should be noted that the first direction and the second direction intersect. For example, the included angle between the two is 90°, that is, one of the first direction and the second direction is the row direction X, and the other is the column direction Y. In the embodiment of the present disclosure, the first direction is taken as the row direction X and the second direction is taken as the column direction Y as an example for description. In addition, in the following description, the example that the dimming units 01 and redundant dimming units in the first substrate can be arranged in an array is used for illustration.

[0080] Figure 5 is Figure 1 a cross-sectional view of the display area of the display panel in the display module shown; Figure 6 is Figure 1 a cross-sectional view of the non-display area of the display panel in the display module shown; as Figure 5 , 6As shown, the display panel 200 has a display area and a non-display area surrounding the display area; the display panel 200 includes: a third substrate and a fourth substrate disposed opposite to each other, and a second liquid crystal layer 50 disposed between the third substrate and the fourth substrate. A second lower polarizer (not shown in the figure) is formed on the side of the third substrate facing away from the second liquid crystal layer 50, and a first upper polarizer (not shown in the figure) is formed on the side of the fourth substrate facing away from the liquid crystal layer. Specifically, the third substrate includes a third base 31, and a plurality of sub-pixels disposed on the third base 31 and located in the display area; each sub-pixel includes a pixel electrode 030, a second thin film transistor T2, and a second common electrode 040. A second common electrode line 40 and redundant sub-pixels (not shown in the figure) are disposed on the third base 31 and located in the non-display area. The pixel electrode 030 in each sub-pixel is electrically connected to the drain of the second thin film transistor T2 through a connection electrode 34. The redundant sub-pixels are located on the side of the second common electrode line 40 close to the display area, and the redundant sub-pixels have the same structure as the sub-pixels, and are used to repair the sub-pixels when problems occur in the sub-pixels. The fourth substrate includes a fourth base 41, a second black matrix layer BM2 disposed on the fourth base 41, and a color filter layer 42; wherein, the color filter layer 42 includes color filters of different colors, for example: a red filter R, a green filter G, and a blue filter B, and the color filters are arranged in one-to-one correspondence with the sub-pixels and the redundant sub-pixels. The second black matrix layer BM2 is formed with a second hollow portion at a position corresponding to the color filter. In addition, one sub-pixel in the display panel 200 can be arranged in one-to-one correspondence with one dimming unit 01 in the light control panel 100, and one redundant sub-pixel is arranged in one-to-one correspondence with one redundant dimming unit. Of course, it can also be that a plurality of sub-pixels arranged in an array in the display panel 200 are arranged in one-to-one correspondence with one dimming unit 01 in the light control panel 100, and correspondingly, a plurality of redundant sub-pixels arranged in an array are arranged in one-to-one correspondence with one redundant dimming unit.

[0081] It should be noted that, with reference to FIGS. 5 and 6, in the embodiments of the present disclosure, the second thin film transistor T2 is taken as an example of a bottom-gate thin film transistor for illustration. Of course, the second thin film transistor T2 can also be a top-gate thin film transistor, which is not limited in the embodiments of the present disclosure. Among them, a second gate insulating layer 32 is disposed between the gate and the active layer of the second thin film transistor T2, and a second interlayer insulating layer 33 is disposed between the pixel electrode and the source and drain of the second thin film transistor T2. In addition, the difference between the display panel 200 and the light control panel 100 is only that the display panel has a color filter layer 42 and a first upper polarizer, and the rest of the structures are substantially the same except for the naming differences. Therefore, the structure of the display panel 200 will not be described in detail herein.

[0082] Specifically, when a voltage is applied to the first common electrode 020 and the light-dimming electrode 010 on the first substrate to form an electric field therebetween, the deflection angle of the liquid crystal molecules in the first liquid crystal layer 300 is controlled, and further the light transmittance of the light emitted by the backlight is controlled.

[0083] Continue to refer to Figure 4 and 6 , since the light control panel 100 has one less color filter layer 42 than the display panel 200, the distance between the first black matrix layer BM1 and the first common electrode line 20 in the peripheral area Q12 of the light control panel 100 is greater than the distance between the second black matrix layer BM2 and the second common electrode line 40 in the non-display area of the display panel 200. Figure 7 is Figure 1 a schematic diagram of the first black matrix layer of the light control panel in the display module shown; as Figure 7 shown, the first black matrix layer BM1 is in a continuous pattern at the position corresponding to the peripheral area Q12 to avoid light leakage in the peripheral area Q12 of the light control panel 100. The inventor found that since the distance between the first black matrix layer BM1 and the first common electrode line 20 in the peripheral area Q12 of the light control panel is relatively close, and the first black matrix layer BM1 at this position is in a continuous pattern, the charge on the first common electrode line 20 is easily coupled to the first black matrix layer BM1 and conducted to the light-dimming area Q11, resulting in abnormal deflection of the liquid crystal molecules in the light-dimming area Q11, and further resulting in the problem of edge bright lines when the display module is turned off.

[0084] In view of the above problems, the following technical solutions are provided in the embodiments of the present disclosure. It should be noted that in the following description, the first common electrode line 20 is taken as an example of the signal transmission line for description.

[0085] In a first aspect, an embodiment of the present disclosure provides a display module, which includes a light control panel 100 and a display panel 200 arranged in a stacked manner; wherein, the light control panel 100 and the display panel 200 are respectively substantially the same as the light control panel 100 and the display panel 200 in the display module in the above Figure 1 , the difference being the structure of the first black matrix layer BM1 in the second substrate of the light control panel 100. Figure 8 is a schematic diagram of a first black matrix layer of the light control panel in the display module of the embodiment of the present disclosure, as Figure 8As shown, a slot 300 is formed in the peripheral area Q12 of the first black matrix layer BM1, and at least part of the slot 300 is projected onto the first substrate 11 on the side of the projection of the first common electrode line 20 on the first substrate 11 close to the dimming area Q11. With such a setting, through the slot 300 on the first black matrix layer BM1, the charge coupled from the first common electrode line 20 to the first black matrix layer BM1 can be prevented from being conducted to the dimming area Q11 of the second substrate, thereby avoiding the charge coupled from the first common electrode line 20 to the first black matrix layer BM1 from affecting the electric field of the dimming area Q11, and further avoiding the problem of bright lines during shutdown when the device is turned off.

[0086] In some embodiments, with continued reference to Figure 8 , the slot 300 on the first black matrix layer BM1 is a continuous pattern surrounding the dimming area Q11. That is to say, through the slot 300, the part of the first black matrix layer BM1 corresponding to the first common electrode line 20 can be separated from the part corresponding to the dimming area Q11, which is equivalent to forming an isolation zone between the first common electrode line 20 and the dimming area Q11, thereby effectively preventing the charge coupled from the first common electrode line 20 to the first black matrix layer BM1 from being conducted to the dimming area Q11 of the second substrate.

[0087] As Figure 8 shown, if the dimming area Q11 is rectangular, the slot 300 is then a rectangular ring pattern at this time. Of course, if the dimming area Q11 is circular, the slot 300 can also be a circular ring pattern at this time. In the embodiments of the present disclosure, the shape of the slot 300 is not specifically limited.

[0088] In some embodiments, the number of slots 300 on the first black matrix layer BM1 can be multiple, such as 2, 3 or even more. Figure 9 Another schematic diagram of the first black matrix layer of the light control panel in the display module according to the embodiment of the present disclosure; as Figure 9 shown, in the embodiment of the present disclosure, the number of slots 300 on the first black matrix layer BM1 is 2, namely the first slot 301 and the second slot 302; among them, the second slot 302 is closer to the dimming area Q11 than the first slot 301. The first common electrode line 20 is arranged surrounding the dimming area Q11, and at this time both the first slot 301 and the second slot 302 are arranged surrounding the dimming area Q11. Taking the dimming area Q11 as a rectangle as an example. The dimming area Q11 includes a first side a and a second side b oppositely arranged along the row direction X, and a third side c and a fourth side d oppositely arranged along the column direction Y. Both the first slot 301 and the second slot 302 include a first slot part 300a and a second slot part 300b oppositely arranged along the row direction X, and a third slot part 300c and a fourth slot part 300d oppositely arranged along the column direction Y. Figure 10 The layout of the display module according to the embodiment of the present disclosure; asFigure 10 As shown, the distance between the first groove portion 300a of the second slot 302 and the first side a of the dimming area Q11 is equal to the distance between the second groove portion 300b of the second slot 302 and the second side a of the dimming area Q11, and both are d1; the minimum distance between the first groove portion 300a of the second slot 302 and the first common electrode line 20 is equal to the minimum distance between the second groove portion 300a of the second slot 302 and the first common electrode line 20, and both are d2; the distance between the third groove portion 300c of the second slot 302 and the third side c of the dimming area Q11 is equal to the distance between the fourth groove portion 300d of the second slot 302 and the fourth side d of the dimming area Q11, and both are d3; the minimum distance between the third groove portion 300c of the second slot 302 and the first common electrode line 20 is equal to the minimum distance between the fourth groove portion 300d of the second slot 302 and the first common electrode line 20, and both are d4. In the embodiments of the present disclosure, d1:d2 = kd3:d4, where 0.8 < k < 1.2. Preferably, k = 1. Such a setting is to ensure that the slots on the first black matrix layer BM1 have substantially the same or the same ability to isolate the charges coupled from the first common electrode line 20 to the first black matrix layer BM1 in the row direction X and the column direction Y of the dimming area Q11. In this way, even if there are charges coupled from the first common electrode line 20 to the first black matrix layer BM1 entering the dimming area, the influence on the row direction X and the column direction Y of the dimming area is the same, and it is possible to avoid the influence of a certain area of the dimming area being prominent and causing display abnormalities of the display panel 200. In some embodiments,

[0089] It should be noted here that the above description takes the number of slots 300 being 2 as an example. However, in actual products, the number of slots 300 depends on factors such as the width of the first common electrode line 20 in the peripheral region Q12 and the size of the display module. Of course, the number of slots 300 can also be 1. In the embodiments of the present disclosure, when the number of slots 300 is multiple, the following conditions only need to be met. For the slot 300 closest to the dimming region Q11, the distance between its first slot portion 300a and the first side a of the dimming region Q11 is equal to the distance between its second slot portion 300d and the second side b of the dimming region Q11, and the distance is d1; for the slot closest to the dimming region Q11, the minimum distance between its first slot portion 300a and the first common electrode line 20 is equal to the minimum distance between its second slot portion 300b and the first common electrode line 20, and the distance is d2; for the slot 300 closest to the dimming region Q11, the distance between its third slot portion 300c and the third side c of the dimming region Q11 is equal to the distance between its fourth slot portion 300d and the fourth side d of the dimming region Q11, and the distance is d3; for the slot 300 closest to the dimming region Q11, the minimum distance between its third slot portion 300c and the first common electrode line 20 is equal to the minimum distance between its fourth slot portion 300d and the first common electrode line 20, and the distance is d4; d1:d2 = kd3:d4, where 0.8 < k < 1.2.

[0090] For example: d1:d2 = d3:d4, and the ratio range is 4:1 to 6:1. Preferably, d1:d2 = d3:d4 = 5:1. Of course, the ratio of d1:d2 (or d3:d4) can be specifically set according to the size of the display module.

[0091] In some embodiments, when the number of slots 300 is multiple and the multiple slots 300 are arranged around the dimming region Q11. Taking a rectangular display module as an example, the spacing between two adjacent slots 300 in the row direction X is approximately 140 μm, and the spacing in the column direction Y is approximately 210 μm.

[0092] In some embodiments, a first alignment layer is provided on one side of the first common electrode 020 of the first substrate 11 of the light control panel 100 close to the first liquid crystal layer 300, and a second alignment layer is provided on one side of the first black matrix layer BM1 of the second substrate 21 close to the first liquid crystal layer 300. Grooves are formed on the first alignment layer and the second alignment layer by a rubbing process so that the liquid crystal molecules of the first liquid crystal layer 30 have an initial arrangement direction. A signal connection line is also provided on the first substrate 11 of the light control panel 100 to supply an external signal to a light modulating device in the light modulating unit 01. In order to facilitate the routing of the signal connection line, the signal connection line can be formed by electrically connecting sub-signal lines located in different layers. In the embodiments of the present disclosure, an example is given in which the signal connection line is formed by electrically connecting a first sub-signal line and a second sub-signal line located in different layers. For example, the first sub-signal connection line is provided on the same layer as the gate of the first thin film transistor T1 and has the same material, and the second sub-signal line is provided on the same layer as the source and drain of the first thin film transistor T1 and has the same material. That is, the first sub-signal line and the gate of the first thin film transistor T1 are fabricated in one patterning process, and the second sub-signal line and the source and drain of the first thin film transistor T1 are fabricated in one patterning process. In this case, the first sub-signal line and the second sub-signal line need to be electrically connected through a via hole penetrating the first gate insulating layer. Among them, the connection position of the first sub-signal line and the second sub-signal line for signal connection is located in the peripheral region Q12. Since the first sub-signal line and the second sub-signal line are located in different layers, the connection position between the two needs to be overlapped by two-layer structures to achieve electrical connection. In this way, the thickness of the connection position between the first sub-signal line and the second sub-signal line is different from that of other positions, resulting in abnormal grooves formed by rubbing the first alignment layer at this position compared with other positions. Therefore, the arrangement of the liquid crystal molecules in this area is abnormal, so the first black matrix layer BM1 needs to block this part. Therefore, in the embodiments of the present disclosure, the slot 300 needs to bypass the connection position of the first sub-signal line and the second sub-signal line, that is, as Figure 10 shown, the slot 300 forms a protrusion 310 at the connection position corresponding to the first sub-signal line and the second sub-signal line so that the orthographic projection of the slot 300 on the first substrate 11 at the connection position of the first sub-signal line and the second sub-signal line has no overlap.

[0093] In one example, the signal connection line is configured to provide a common voltage signal to the first common electrode 020. At this time, the first sub-signal line of the signal connection line can be the first common electrode line 20, and the second sub-signal line can be the first common voltage introduction line; one end of the first common voltage introduction line is connected to the first common electrode line 20, and the other end is connected to the first common electrode 020; at this time, the positive projection of the protruding portion 310 of the slot 300 on the first substrate 11 overlaps with the positive projection of the first common electrode line 20 on the first substrate 11. That is to say, the protruding portion 310 protrudes toward the side away from the dimming area Q11. Hereinafter, an example in which the first sub-signal line is the first common electrode line 20 and the second sub-signal line is the first common voltage introduction line will be described. In some embodiments, the positive projection of the slot 300 on the first substrate 11 overlaps with the positive projection of the redundant dimming unit on the first substrate 11. For example: the redundant dimming unit is located on the side of the first common electrode line 20 close to the dimming area Q11 and is adjacent to the first common electrode line 20. In the embodiments of the present disclosure, the positive projection of the slot 300 on the first substrate 11 overlaps with the positive projection of the redundant dimming unit on the first substrate 11, that is to say, the distance between the position of the slot 300 and the first common electrode line 20 is relatively close, so as to effectively prevent the charge coupled to the first black matrix layer BM1 by the first common electrode line 20 from being conducted to the dimming area.

[0094] In some embodiments, the width of the slot on the first black matrix layer BM1 is greater than or equal to 18 μm. Of course, the width of the slot 300 can be specifically set according to factors such as the signal lines on the first substrate 11, the dimming unit 01, and the position of the redundant dimming unit.

[0095] In some embodiments, the width of the display area of the display panel 200 in the display module is smaller than the width of the light control panel 100 to avoid deviation in the alignment accuracy between the display panel 200 and the light control panel 100, which affects the normal display of the display panel 200. Figure 11 Schematic diagram of the display module according to the embodiments of the present disclosure, as Figure 11 shown, the display panel 200 has a display area and a non-display area surrounding the display area; the positive projection of the display area on the first substrate 11 is located within the positive projection of the dimming area Q11 on the first substrate 11. That is to say, there is a certain fitting tolerance (△Xmax) between the display area of the display panel 200 and the dimming area Q11 of the light control panel 100.

[0096] To more clearly illustrate the structure of the light control panel 100 in the embodiments of the present disclosure, the following specifically describes each layer structure on the first substrate in the light control panel 100. Among them, a rectangular display module is taken as an example of the display module. At this time, the dimming area Q11 is rectangular, and the peripheral area Q12 is a rectangular ring. The dimming unit 01 is located in the dimming area Q11, and the redundant dimming unit is located in the peripheral area Q12. A plurality of dimming units 01 and a plurality of redundant dimming units are arranged side by side in the column direction Y to form a plurality of first dimming unit groups 10a, and the dimming units 01 and redundant dimming units in each of the plurality of first dimming unit groups 10a are arranged in the row direction X; a plurality of dimming units 01 and a plurality of redundant dimming units are arranged side by side in the row direction X to form a plurality of second dimming unit groups 10b, and the dimming units 01 and redundant dimming units in each of the plurality of second dimming unit groups 10b are arranged in the column direction Y; the gates of the first thin film transistors T1 of the dimming units and redundant dimming units located in the same first dimming unit group 10a are connected to the same first gate line; the dimming units 01 and redundant dimming units located in the same second dimming unit group 10b are provided with data voltage signals by two first data lines, and the sources of the adjacent first thin film transistors T1 are connected to different first data lines, and the first common electrodes 20 of the dimming units 01 and redundant dimming units located in the same second dimming unit group 10b are connected to the same first common voltage introduction line.

[0097] In one example, the first substrate includes a first substrate 11, and a first transparent conductive layer, a first metal conductive layer, a first gate insulating layer 12, an active semiconductor layer, a second metal conductive layer, a first interlayer insulating layer 13, and a second transparent conductive layer that are sequentially disposed on the first substrate 11. Among them, for example: the first transparent conductive layer may include, for example: a dimming electrode 010; the first metal conductive layer may include a first common electrode line 20, a first gate line, and the gates of each first thin film transistor T1; the active semiconductor layer includes the active layers of each first thin film transistor T1; the second metal conductive layer may include the sources and drains of each first thin film transistor T1 and a first data line; the second transparent conductive layer may include a first common electrode 020. The following specifically describes each film layer of the first transparent conductive layer, the first metal conductive layer, the first gate insulating layer 12, the active semiconductor layer, the second metal conductive layer, the first interlayer insulating layer 13, and the second transparent conductive layer.

[0098] For example: Figure 12 Schematic diagram of the first transparent conductive layer in the display module of the embodiments of the present disclosure; as Figure 12As shown, the first transparent conductive layer 1 is disposed on the first substrate 11. The first transparent conductive layer 1 includes a dimming electrode 010, and the dimming electrode 010 is located at partial positions of the dimming region Q11 and the peripheral region Q12. The dimming electrode 010 has a plurality of first openings 011 arranged side by side in the column direction Y, and a plurality of second openings 012 arranged side by side in the row direction X. Each of the plurality of first openings 011 extends in the row direction X, and each of the plurality of second openings 012 extends in the column direction Y. The shape of the first opening 011 may be Figure 12 the serrated shape shown in Figure 12 . Of course, it may be other shapes such as a straight line shape. In the embodiments of the present disclosure, the shape of the first opening 011 is not specifically limited. Among them, the reason for providing the first opening 011 on the dimming electrode 010 is to prevent the first gate line from being electrically connected to the dimming electrode 010 when the first gate line is formed subsequently. The reason for providing the second opening 012 on the dimming electrode 010 is to prevent the first data line formed subsequently from overlapping with the first common electrode 010 in the orthographic projection on the first substrate 11 to form an overlapping capacitance, so as to affect the signal written on the first data line. It should be noted here that the dimming electrodes 010 in each redundant dimming unit may be connected together, and the dimming electrodes 010 in each redundant dimming unit and the dimming electrode 010 in the dimming unit 01 are disconnected, and the dimming electrodes 010 in each dimming unit 01 are also disconnected.

[0099] Continue to refer to Figure 12 , the first transparent conductive layer 1 further includes a plurality of first connection portions 013 which are spaced apart and disposed in the peripheral region Q12. The first connection portion 013 is used to realize the electrical connection between the dimming electrode 010 in the redundant dimming unit and the first common electrode line 20 formed subsequently. Among them, the dimming electrode 010 and the first connection portion 013 in the redundant dimming unit may be an integrally formed structure. The shape of the first connection portion 013 may be Figure 12 the rectangular shape shown in Figure 12 . Of course, it may also be other shapes such as a circular shape, which is not limited herein.

[0100] For example: Figure 13 is a schematic diagram of the first metal conductive layer in the display module according to the embodiments of the present disclosure; as Figure 13As shown, the first metal conductive layer 2 is formed on the first transparent conductive layer 1. The first metal conductive layer 2 includes a plurality of first gate lines 201 arranged side by side in the column direction Y. Each of the plurality of first gate lines 201 extends in the row direction X, and the first gate lines 201 are arranged in one-to-one correspondence with the first openings 011. Moreover, the orthographic projection of the first gate lines 201 on the first substrate 11 falls within the orthographic projection of the first openings 011 on the first substrate 11. The first metal conductive layer 2 further includes the gates 202 of the respective first thin film transistors T1, and the gates 202 of the first thin film transistors T1 are connected to the first gate lines 201, and the two can be an integral structure. The first metal conductive layer 2 further includes a first common electrode line 20 located in the peripheral region Q12. The first common electrode line 20 can be directly overlapped with the first connection portion 013 in the first transparent conductive layer 1 to achieve the electrical connection between the first common electrode 010 and the first common electrode line 20.

[0101] Continue to refer to Figure 13 , a second connection portion 205 is connected to the end of the first gate line 201. The second connection portion 205 can be an integrally formed structure with the first gate line 201 and is used to electrically connect the subsequently formed gate signal introduction line to the first gate line 201.

[0102] Continue to refer to Figure 13 , the first metal conductive layer 2 further includes redundant gate lines 206; when only redundant dimming units are included in the first dimming unit group 10a, the gates 202 of the first thin film transistors T1 in the redundant dimming units are connected to the redundant gate lines 206. Since the redundant dimming units do not need to work during display, the redundant gate lines 206 and the first common electrode line 20 can be connected into an integral structure.

[0103] It should be noted that there is a bonding area on one side of the peripheral region Q12. Connection pads are provided in this area for bonding with external circuits, such as COF, FPC, and PCB; at the same time, the connection pads also need to be electrically connected to each signal introduction line (fan-out line) to provide signals for each signal line on the first substrate. Of course, a gate driving circuit (such as Gate On Array; GOA) and other structures are also provided on the first substrate. Continue to refer to Figure 13 , the first substrate further includes a detection signal line 204 and a compensation signal line 203 that are provided on the first substrate 11 and are located in the peripheral region Q12; the compensation signal line 203 and the detection signal line 204 are sequentially arranged on the side of the first common electrode line 20 away from the dimming region Q11. Among them, the detection signal line 204 is electrically connected to one of the first gate lines 201 closest to the bonding area and is used to detect the gate signal. The compensation signal line 203 is used to compensate the signals input to the dimming unit 01.

[0104] For example, a first gate insulating layer 12 is formed on the first metal conductive layer 2 to insulate from the subsequent formed active semiconductor layer 3. Figure 14 is a schematic diagram of the active semiconductor layer in the display module according to an embodiment of the present disclosure; as Figure 14 shown, the active semiconductor layer 3 includes the active layers 301 of the first thin film transistors T1, and the orthographic projection of the active layer 301 of each first thin film transistor T1 on the first substrate 11 at least partially overlaps with the orthographic projection of its gate 202 on the first substrate 11 to achieve the switching characteristics of the first thin film transistor T1. In addition, the active semiconductor layer can be made of amorphous silicon, polysilicon, oxide semiconductor materials, etc.

[0105] For example: Figure 15 is a schematic diagram of the second metal conductive layer in the display module according to an embodiment of the present disclosure; as Figure 15 shown, the second metal conductive layer 4 is formed on the active semiconductor layer 3. The second conductive metal layer 4 includes the source electrodes 402 and drain electrodes 403 of the first thin film transistors T1. The source electrodes 402 and drain electrodes 403 of each first thin film transistor T1 overlap with the orthographic projection of its active layer on the first substrate 11 to achieve the electrical connection between the source electrodes 402 and drain electrodes 403 of each first thin film transistor T1 and its active layer 301. The second metal conductive layer 4 further includes a plurality of first data lines 401 arranged side by side in the row direction X. Each of the plurality of first data lines 401 extends in the column direction Y, and the first data lines 401 are arranged in one-to-one correspondence with the second openings 012 on the first common electrode 010, and the orthographic projection of each first data line 401 on the first substrate 11 falls within the orthographic projection of the corresponding second opening 012 on the first common electrode 010 on the first substrate. The second metal conductive layer 4 further includes a plurality of first common voltage introduction lines 406 arranged side by side in the row direction X. Each first common voltage introduction line 406 extends in the column direction Y. The first common voltage introduction line 406 can be connected to the first common electrode line 20 through the subsequently formed third connection electrode. Of course, each first common voltage introduction line 406 is also connected to the first common electrode 020 formed subsequently in the same column. In one example, the first data lines 401 and the first common voltage introduction lines 406 in the second metal conductive layer 4 are alternately arranged in the row direction X to make the wiring on the display substrate more uniform, which helps to improve the light emission uniformity of the light control panel 100.

[0106] Continue to refer to Figure 15, a gate signal introduction line 404 located in the peripheral area Q12 is further provided on the second metal conductive layer 4. One gate signal introduction line 404 is connected to one first gate line 201, and each gate signal introduction line 404 is also electrically connected to the gate driving circuit. Specifically, an end of the gate signal introduction line 404 is connected with a third connection part 405. The third connection part 405 and the gate signal introduction line 404 can be an integrally formed structure. The third connection part 405 is electrically connected to the second connection part 205 to realize the electrical connection between the gate signal introduction line 404 and the first gate line 201.

[0107] In addition, as Figure 15 shown, all the first dimming unit groups 10a located in the peripheral area Q12 are redundant dimming units. In this area, the first gate lines 301 (for example, Figure 13 the first first gate line 301 shown) connected to the redundant dimming units in the same first dimming unit group 10a are connected to the first common electrode line 20. The reason why the first gate line 301 is connected to the first common electrode line 20 is that when the display module is normally displaying, the redundant dimming units do not need to work.

[0108] For example: a first interlayer insulating layer 13 is formed on the second metal conductive layer 4 to insulate the second metal conductive layer 4 from the subsequently formed second transparent conductive layer 5. Figure 16 is a schematic diagram of the via distribution in the interlayer insulating layer in the display module of the present disclosure embodiment; as Figure 16 shown, after the first interlayer insulating layer 13 is formed, the first gate insulating layer 12 and the first interlayer insulating layer 13 are etched to form a first connection via 131, a second connection via 132, a fourth connection via 134, and a third connection via 133 and a fifth connection via 135 penetrating the first interlayer insulating layer. Among them, the first connection via 131 and the third connection via 133 are used to electrically connect the subsequently formed first connection electrode 14 to connect the dimming electrode 010 to the drain 403 of the first thin film transistor T1; the second connection via is used to electrically connect the subsequently formed first common electrode 020 to the first common electrode line 20. The fourth connection via 134 and the fifth connection via 135 are used to electrically connect the second connection part 205 and the third connection part 405 through the subsequently formed second connection electrode to realize the electrical connection between the first gate line 201 and the gate signal introduction line 401.

[0109] Continue to refer to Figure 16 , since the widths of the two relatively arranged parts of the first common electrode line 20 in the row direction X are greater than the widths of the two relatively arranged parts in the column direction Y, the second connection vias 132 at the positions of the two relatively arranged parts of the first common electrode line 20 in the row direction X can be arranged in an array to enable the reliable connection between the subsequently formed first common electrode 020 and the first common electrode line 20.

[0110] In addition, at this time, the first substrate further includes a sixth connection via 136 penetrating through the first gate insulating layer 12 and the first interlayer insulating layer 13 and a seventh connection via 137 penetrating through the first interlayer insulating layer 13. The sixth connection via 136 and the seventh connection via 137 are used to electrically connect the first common electrode line 20 and the first common voltage introduction line 406 through a third connection electrode formed in the second transparent conductive layer subsequently (that is, Figure 10 the position corresponding to the protrusion 310 in

[0111] For example: Figure 17 is a schematic diagram of the second transparent conductive layer in the display module according to an embodiment of the present disclosure. As Figure 17 shown, the second transparent conductive layer 5 is formed on the interlayer insulating layer 13. The second transparent conductive layer 5 includes first common electrodes 020 of each dimming unit 01 and each redundant dimming unit, a first connection electrode 14, and a second connection electrode 502. A plurality of third openings 501 arranged side by side along the column direction Y are formed on the first common electrode 020, and each third opening 501 extends along the row direction X. The third opening 501 is correspondingly arranged with the first gate line 201, and the orthographic projection of the first gate line 201 on the first substrate 11 falls within the orthographic projection of the third opening 501 on the first substrate 11 to avoid forming a coupling capacitance between the first gate line 201 and the first common electrode 020.

[0112] Referring to Figure 4 , the first connection electrode 14 electrically connects the dimming electrode 010 to the drain 403 of the first thin film transistor T1 through the first connection via 131 and the third connection via 133. Figure 18 is a connection schematic diagram of the first common electrode and the first common electrode line in the display module according to an embodiment of the present disclosure. As Figure 18 shown, the first common electrode 020 is electrically connected to the first common electrode line 20 through the second connection via 132. Generally, the width of the second connection portion 205 is greater than the width of the first gate line 201. The fourth connection via 134 and the fifth connection via 135 at each position of the second connection portion 205 can be multiple, and the multiple fourth connection vias 134 and fifth connection vias 135 can be arranged in an array to achieve a reliable connection between the gate signal introduction line 404 and the second connection portion 205. Figure 19 is a connection schematic diagram of the second connection portion and the third connection portion in the display module according to an embodiment of the present disclosure. As Figure 19As shown, the second connection electrode 502 electrically connects the second connection portion 205 and the third connection portion 405 through the fourth connection via 134 and the fifth connection via 135, so as to realize the electrical connection between the first gate line 201 and the gate signal introduction line 401. Of course, the second transparent conductive layer 5 further includes a third connection electrode, and the third connection electrode electrically connects the first common electrode line 20 and the first common voltage introduction line 406 through the sixth connection via 136 and the seventh connection via 137.

[0113] Here, it should be noted that the positive projection of the first common electrode 020 in the second transparent conductive layer 5 on the first substrate 11 covers the positive projection of the first data line 401 on the first substrate 11. Since the voltage input to the first common electrode 020 during operation is a constant voltage, by covering the first data line 401, it is equivalent to a shielding electrode of the first data line 401, which can effectively avoid the problem of light leakage caused by the ineffective deflection of liquid crystal molecules at the position of the first data line 401.

[0114] So far, the introduction of each film layer on the first substrate is completed.

[0115] For the above first substrate, a first black matrix layer BM1 corresponding to the first substrate is given; since in the above first substrate, the first common electrode 020 in the second transparent conductive layer 5 is equivalent to a shielding electrode of the first data line 401, a light shielding portion may not be provided at the position of the first data line 401 for light shielding. Figure 20 It is a schematic diagram of another first black matrix layer of the light control panel in the display module of the embodiment of the present disclosure; as Figure 20 shown, the first black matrix layer BM1 includes a first light shielding portion BM11 located in the dimming area Q11 and a second light shielding portion BM12 located in the peripheral area Q12; the first light shielding portion BM11 includes a plurality of sub-light shielding portions BM111 arranged side by side along the column direction Y, and each sub-light shielding portion BM111 extends along the row direction X; and the positive projection of a sub-light shielding portion BM111 on the first substrate 11 covers the positive projection of a first gate line 301 on the first substrate 11, and is used for shielding light at the position corresponding to the first gate line 201. In one example, if the first gate line 201 is in a zigzag shape, such as a sawtooth shape, an S-shaped wave, etc., the sub-light shielding portion also presents the same shape at this time. For the second light shielding portion BM112 in the peripheral area Q12 of the first black matrix layer BM1, an annular slot 300 is provided thereon, and except for the position of the slot 300, other positions of the second light shielding portion BM12 are light-impermeable.

[0116] In a second aspect, the embodiment of the present disclosure provides a display device, including the above display module. Of course, it may also include structures such as a backlight source.

[0117] It should be noted that the display device provided in this embodiment can be: any product or component with a display function, such as a flexible wearable device, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, etc. Other essential components of the display device should be understood by those of ordinary skill in the art and will not be elaborated here, nor should they be regarded as a limitation to the present invention.

[0118] It can be understood that the above embodiments are merely exemplary embodiments adopted to illustrate the principle of the present invention. However, the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also regarded as the protection scope of the present invention.

Claims

1. A display module, which comprises a display panel and a light control panel arranged in a stacked manner; The light control panel has a dimming area and a peripheral area surrounding the dimming area; the light control panel includes: A first substrate and a second substrate disposed opposite to each other, and a first liquid crystal layer disposed between the first substrate and the second substrate; wherein, the first substrate includes: A first base A signal transmission line disposed on a side of the first base close to the first liquid crystal layer and located in the peripheral area; The second substrate includes: A second base A first black matrix layer disposed on a side of the second base close to the first liquid crystal layer and located in the dimming area and the peripheral area; wherein, The first black matrix layer has a slot located in the peripheral area, and at least a part of the position of the slot is projected onto the first base on a side of the projection of the signal transmission line on the first base close to the dimming area; The first substrate further includes a signal connection line disposed on the first base; the signal connection line includes a first sub-signal line and a second sub-signal line that are electrically connected and located in different layers; a connection position of the first sub-signal line and the second sub-signal line is located in the peripheral area; a protrusion is formed at a position of the slot corresponding to the connection position of the first sub-signal line and the second sub-signal line.

2. The display module according to claim 1, wherein The slot includes a continuous pattern surrounding the dimming area.

3. The display module according to claim 2, wherein, The number of the slots is at least one, and the signal transmission line is disposed surrounding the dimming area. The dimming area includes a first side and a second side disposed opposite to each other in a first direction, and a third side and a fourth side disposed opposite to each other in a second direction; Each of the slots includes a first slot portion and a second slot portion disposed opposite to each other in the first direction, and a third slot portion and a fourth slot portion disposed opposite to each other in the second direction; For the slot closest to the dimming area, a distance between the first slot portion and the first side of the dimming area is equal to a distance between the second slot portion and the second side of the dimming area, and the distance is d1; For the slot closest to the dimming area, a closest distance between the first slot portion and the signal transmission line is equal to a closest distance between the second slot portion and the signal transmission line, and the distance is d2; For the slot closest to the dimming area, a distance between the third slot portion and the third side of the dimming area is equal to a distance between the fourth slot portion and the fourth side of the dimming area, and the distance is d3; For the slot closest to the dimming area, a closest distance between the third slot portion and the signal transmission line is equal to a closest distance between the fourth slot portion and the signal transmission line, and the distance is d4; Wherein, d1:d2 = kd3:d4, 0.8 < k < 1.

2.

4. The display module according to claim 3, wherein, The range of d1:d2 is 4:1 to 6:

1.

5. The display module according to claim 1, wherein, The first sub-signal line includes a first common electrode line, and the second sub-signal line includes a first common voltage introduction line; One end of the first common voltage introduction line is connected to the first common electrode line, and the other end is connected to a first common electrode; A projection of the protrusion on the first base overlaps with a projection of the first common electrode line on the first base.

6. The display module according to claim 1, wherein, The signal transmission line includes a first common electrode line.

7. The display module according to claim 6, wherein The first substrate further includes: A plurality of dimming units and a plurality of redundant dimming units are disposed on a side of the first substrate close to the first liquid crystal layer, and the plurality of dimming units are located in the dimming area, and the plurality of redundant dimming units are located in the peripheral area; each of the plurality of dimming units and the plurality of redundant dimming units includes a first thin film transistor, a dimming electrode, and a first common electrode disposed on the first substrate; The dimming electrode of the redundant dimming unit is electrically connected to the first common electrode.

8. The display module according to claim 7, wherein, An orthographic projection of the slotted portion on the first substrate overlaps an orthographic projection of the redundant dimming unit on the first substrate.

9. The display module according to claim 7, wherein, The plurality of dimming units and the plurality of redundant dimming units are arranged side by side in a second direction to form a plurality of first dimming unit groups, and the dimming units and the redundant dimming units in each of the plurality of first dimming unit groups are arranged in a first direction; the plurality of dimming units and the plurality of redundant dimming units are arranged side by side in a first direction to form a plurality of second dimming unit groups, and the dimming units and the redundant dimming units in each of the plurality of second dimming unit groups are arranged in a second direction; gates of the first thin film transistors of the dimming units and the redundant dimming units located in the same first dimming unit group are connected to the same first gate line; the dimming units and the redundant dimming units located in the same second dimming unit group are provided with data voltages by two first data lines, and sources of the adjacent first thin film transistors are connected to different first data lines; The first substrate further includes: A first transparent conductive layer is disposed on a side of the first substrate close to the first liquid crystal layer, and the first transparent conductive layer includes the dimming electrode; the dimming electrode includes a plurality of first openings arranged side by side in the second direction, and each of the plurality of first openings extends in the first direction; A first metal conductive layer is disposed on a side of the first substrate close to the first liquid crystal layer, and the first metal conductive layer includes a plurality of first gate lines arranged side by side in the second direction, gates of the first thin film transistors, and a common electrode line, and each of the plurality of first gate lines extends in the first direction, and an orthographic projection of the first gate line and the gate of the first thin film transistor on the first substrate falls within an orthographic projection of the first opening on the first substrate; A first gate insulating layer is disposed on a side of the first metal conductive layer facing away from the first substrate; An active semiconductor layer is disposed on a side of the first gate insulating layer facing away from the first metal conductive layer; the active semiconductor layer includes active layers of the first thin film transistors; A second metal conductive layer is disposed on a side of the active semiconductor layer facing away from the first gate insulating layer, and the second metal conductive layer includes a plurality of first data lines arranged side by side in the first direction, and sources and drains of the first thin film transistors, and the sources and drains of the first thin film transistors are respectively connected to the active layer; each of the plurality of first data lines extends in the second direction; The first interlayer insulating layer is disposed on a side of the second metal conductive layer facing away from the first interlayer insulating layer, and the first substrate further includes a first connection via hole, a second connection via hole penetrating through the first interlayer insulating layer and the first gate insulating layer, and a third connection via hole penetrating through the first interlayer insulating layer; The second transparent conductive layer is disposed on a side of the first interlayer insulating layer facing away from the second metal conductive layer. The second transparent conductive layer includes first common electrodes of the respective dimming units and the respective redundant dimming units, and a first connection electrode; the first connection electrode electrically connects the drain electrode of the first thin film transistor and the dimming electrode through the first connection via hole and the third connection via hole; the first common electrode is electrically connected to the first common electrode line through the second connection via hole.

10. The display module according to claim 9, wherein, The first black matrix layer includes a first light-shielding portion located in the dimming area and a second light-shielding portion located in the peripheral area; The first light-shielding portion includes a plurality of sub-light-shielding portions arranged side by side in the second direction, and each of the plurality of sub-light-shielding portions extends in the first direction; and a positive projection of one of the sub-light-shielding portions on the first substrate covers a positive projection of one of the first gate lines on the first substrate.

11. The display module according to claim 9, wherein, The dimming electrode further includes: a plurality of second opening portions arranged side by side in the first direction, and each of the plurality of second opening portions extends in the second direction; and a positive projection of the first data line on the first substrate falls within a positive projection of the second opening portion on the first substrate.

12. The display module according to claim 9, wherein, The second transparent conductive layer further includes a plurality of third opening portions formed on the first common electrode and arranged side by side in the second direction; each of the plurality of third opening portions extends in the first direction, one of the third opening portions is correspondingly arranged with one of the first gate lines, and their positive projections on the first substrate at least partially overlap.

13. The display module according to claim 9, wherein, The first transparent conductive layer further includes a plurality of first connection portions arranged at intervals, and the first connection portions are electrically connected to the dimming electrodes in the redundant dimming units and are directly overlapped with the first common electrode line.

14. The display module according to claim 9, wherein, The first substrate further includes a gate driving circuit disposed on the first substrate and located in the peripheral area, and a plurality of gate signal introduction lines, detection signal lines, and compensation signal lines connected to the gate driving circuit; one of the gate signal introduction lines is connected to one of the first gate lines; the detection signal line is connected to one of the first gate lines; The first metal conductive layer further includes the detection signal line and the compensation signal line; The second metal conductive layer further includes the plurality of gate signal introduction lines.

15. The display module according to claim 14, wherein, A second connection portion is connected to an end of the first gate line, and a third connection portion is connected to an end of the gate signal introduction line; the second transparent conductive layer further includes a second connection electrode; the first substrate further includes a fourth connection via hole penetrating through the first gate insulating layer and the first interlayer insulating layer, and a fifth connection via hole penetrating through the first interlayer insulating layer; the second connection electrode electrically connects the second connection portion and the third connection portion through the fourth connection via hole and the fifth connection via hole.

16. The display module according to claim 9, wherein, The first metal conductive layer further includes redundant gate lines extending in a first direction, and the redundant gate lines are connected to the first common electrode line; at least one group in the first dimming unit group only includes the redundant dimming units, and the gates of the first thin film transistors in the first dimming unit group are connected to the redundant gate lines.

17. The display module according to any one of claims 1-16, wherein, The width of the slot is greater than or equal to 18 μm.

18. The display module according to any one of claims 1-16, wherein, The display panel includes a third substrate and a fourth substrate disposed opposite to each other, and a second liquid crystal layer disposed between the third substrate and the fourth substrate; the third substrate is located on a side of the second substrate away from the first liquid crystal layer; the display panel has a display area and a non-display area surrounding the display area; The orthographic projection of the display area on the first substrate is located within the orthographic projection of the dimming area on the first substrate.

19. A display device, which includes the display module according to any one of claims 1-18.

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