NUMA-aware parallel computing method and system for arm architecture

Abstract

The application discloses a kind of NUMA perception parallel computing method and system for ARM architecture, the method includes: obtaining computing task and carrying out type division to computing task, obtain the computing task after division;Determine execution space size and select execution strategy;According to NUMA architecture information, divide execution space, and distribute the execution subspace after division to CPU core;Execute computing task and reduce to computing result, obtain final result.The system includes: type division module, setting module, distribution module and reduction module.The application is reasonably distributed to the CPU core of different NUMA node by the pre-allocation of execution space and the redistribution strategy of computing resource, and performance can be effectively improved.The application is a kind of NUMA perception parallel computing method and system for ARM architecture, and can be widely applied in computer parallel computing field.

Description

Technical Field

[0001] This invention relates to the field of parallel computing in computers, and more particularly to a NUMA-aware parallel computing method and system for ARM architecture. Background Technology

[0002] The ARM architecture is a processor architecture that uses a unique ARM instruction set system and is developed for different application scenarios. Unlike the Complex Instruction Set Computing (CISC) architecture of x86, the ARM architecture is a Reduced Instruction Set Computing (RISC) architecture, which reduces a large number of infrequently used instructions, thus reducing chip complexity. It employs a Load / Store instruction architecture, where only load and store instructions can access memory, while other data processing instructions operate only on registers. Therefore, ARM architecture processors are characterized by low power consumption, low cost, and high performance.

[0003] In recent years, the growth in the number of transistors integrated on a single chip has gradually approached its limit. To pursue continuous improvements in processor performance, processor design has shifted from increasing clock frequency to increasing the number of processor cores, leading to the emergence of multi-core processors. Currently, most multi-core processors adopt NUMA (Non-Uniform Memory Access) architecture. Unlike traditional uniform memory access architectures, memory in NUMA architectures is physically distributed. Different CPU cores belong to different NUMA nodes, and each NUMA node has its own integrated memory controller. Processors access the memory of their own NUMA node faster than they access the memory of other NUMA nodes. Parallel programs often contain numerous parallel computing tasks. These tasks may be independent, with the results of each task unaffected by others. However, in some scenarios, parallel tasks may have dependencies, involving data exchange between threads. Because processors exhibit performance differences when accessing memory across different NUMA nodes, handling dependent parallel computing tasks with numerous cross-NUMA node memory accesses significantly increases performance overhead. Summary of the Invention

[0004] To address the aforementioned technical problems, the present invention aims to provide a NUMA-aware parallel computing method and system for ARM architecture, employing different parallel data processing procedures depending on the type of computing task.

[0005] The first technical solution adopted in this invention is: a NUMA-aware parallel computing method for ARM architecture, comprising the following steps:

[0006] Obtain the computing tasks and classify them into different types to obtain the classified computing tasks;

[0007] Determine the size of the execution space and select the execution strategy;

[0008] The execution space is divided according to the NUMA architecture information, and the divided execution subspaces are allocated to the CPU cores;

[0009] Perform the computation task and reduce the computation results to obtain the final result.

[0010] Preferably, the task type of the partitioned computational task is a parallel for loop, and the execution strategy includes a one-dimensional space execution strategy, a multi-dimensional space execution strategy, and a group execution strategy.

[0011] Preferably, the step of dividing the execution space according to the NUMA architecture information and allocating the divided execution subspaces to CPU cores specifically includes:

[0012] Obtain the NUMA architecture information of the current device;

[0013] The NUMA architecture information includes the number of NUMA nodes and the number of CPU cores contained in each NUMA node;

[0014] The allocation coefficients are calculated based on the device's NUMA architecture information;

[0015] Based on the allocation coefficient, the number of sub-execution spaces is allocated to each NUMA node in a sequential manner.

[0016] Preferably, the step of performing the computation task and reducing the computation results to obtain the final result specifically includes:

[0017] Computational tasks are performed based on execution sub-intervals;

[0018] Within the execution sub-interval, a serial reduction mode is used to output the reduction result of each computation task and save it to the corresponding memory address space, thus completing the reduction between CPU cores within the NUMA node;

[0019] The results between NUMA nodes are reduced to obtain the final result.

[0020] Preferably, a one-dimensional execution strategy is selected, wherein the division of the execution space based on NUMA architecture information specifically includes:

[0021] Based on the number of available CPU cores in the device, the linear execution interval is evenly divided to obtain the divided execution sub-intervals;

[0022] The lengths of the divided execution sub-intervals are equal.

[0023] Preferably, a multi-dimensional execution strategy is selected, wherein the division of the execution space based on NUMA architecture information specifically includes:

[0024] The execution space dimensions, except for the last one, are grouped according to a preset unit length, and the last space dimension is not divided.

[0025] The groups of each execution space dimension are combined to obtain the partitioned execution subspace.

[0026] Preferably, the selection of a group execution strategy, specifically the division of the execution space based on NUMA architecture information, includes:

[0027] Group the CPU cores to get the number of groups;

[0028] The execution subspace is obtained by dividing the first dimension according to the number of groups and the second dimension according to the number of cores in each group.

[0029] The second technical solution adopted in this invention is: a NUMA-aware parallel computing system for ARM architecture, comprising:

[0030] The type partitioning module is used to acquire computing tasks and partition them into types to obtain the partitioned computing tasks;

[0031] The configuration module is used to determine the size of the execution space and select the execution strategy;

[0032] The allocation module is used to divide the execution space according to the NUMA architecture information and allocate the divided execution subspace to the CPU cores;

[0033] The reduction module is used to perform computation tasks and reduce the computation results to obtain the final result.

[0034] The beneficial effects of the method and system of the present invention are as follows: The present invention rationally allocates parallel task threads to the CPU cores of different NUMA nodes through the pre-allocation of execution space and the reallocation strategy of computing resources, which effectively improves the utilization of computing resources. In addition, the performance is further improved through various calculation result reduction schemes designed for NUMA architecture. Attached Figure Description

[0035] Figure 1 This is a flowchart of the steps of a NUMA-aware parallel computing method for ARM architecture according to the present invention.

[0036] Figure 2 This is a block diagram of a NUMA-aware parallel computing system for ARM architecture according to the present invention. Detailed Implementation

[0037] The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. The step numbers in the following embodiments are only for ease of explanation and do not limit the order of the steps. The execution order of each step in the embodiments can be adapted according to the understanding of those skilled in the art. Specific Implementation Example 1:

[0039] This invention provides a NUMA-aware parallel computing method for ARM architecture, the method comprising the following steps:

[0040] S1. Obtain computing tasks and classify them into different types to obtain the divided computing tasks, wherein the divided computing tasks are parallel for loops;

[0041] Specifically, this paper implements parallel for loops with different execution strategies for various computing scenarios. It focuses on pure computational parallel computing tasks, where each task is independent and has no data dependencies. The actual computational tasks are encapsulated as functors for execution by the actual CPU core threads. The actual execution flow of the parallel for loop varies depending on the execution strategy.

[0042] S2. Determine the execution space size and select the execution strategy;

[0043] The execution strategies include one-dimensional space execution strategy, multi-dimensional space execution strategy, and group execution strategy. The actual execution flow of the parallel for loop differs depending on the execution strategy, and the specific implementation scheme is as follows:

[0044] For a one-dimensional execution strategy, the linear execution interval is first uniformly divided based on the number of available CPU cores on the device, with each sub-interval having an equal length. Each sub-interval is assigned to one available CPU core, and the length of the sub-interval is equal to the number of computational tasks to be executed.

[0045] For multi-dimensional execution strategies, the default execution space partitioning grouped all execution space dimensions except the last one into groups of two units in length, leaving the last dimension unpartitioned. Each group of execution space dimensions is then combined, with each combination containing a subspace partition of all dimensions. Each combination of execution subspaces is assigned to an available CPU core. Custom partitioning schemes are also provided, allowing users to specify the partitioning unit for each space dimension, enabling flexible execution space partitioning.

[0046] The grouped execution strategy, oriented towards two-dimensional nested for loops, is primarily designed for specific computational scenarios such as matrix calculations. The execution space is partitioned as follows: first, the number of available CPU cores is grouped, and the first dimension is divided based on the number of groups. Then, the second dimension is divided based on the number of CPU cores within each group, with each core allocated to a two-dimensional sub-execution space.

[0047] S3. Divide the execution space according to the NUMA architecture information and allocate the divided execution subspace to the CPU core;

[0048] S4. Perform the calculation task. Specific Implementation Example 2:

[0050] S1. Obtain computing tasks and classify the computing tasks by type to obtain the divided computing tasks, wherein the divided computing tasks are parallel reduce;

[0051] Specifically, this operation targets computational scenarios that require summing the results of multiple computational tasks. The data types of these results include scalars, vectors, and multidimensional arrays. Unlike parallel for loops, this operation involves data communication between CPU cores.

[0052] S2. Determine the execution space size and select the execution strategy;

[0053] Specifically, for parallel reduce operations employing one-dimensional and multi-dimensional execution strategies, the execution space is pre-divided according to the method described in Specific Implementation Example 1.

[0054] S3. Divide the execution space according to the NUMA architecture information and allocate the divided execution subspace to the CPU core;

[0055] Specifically, after space pre-partitioning, the NUMA architecture information of the current device is obtained, including the number of NUMA nodes and the number of CPU cores in each NUMA node. An allocation coefficient X is calculated based on this information, and then, in a sequential allocation manner, each NUMA node is allocated a sub-execution space number X times its number of cores. This reduces the dispersion of data across NUMA nodes, thereby reducing the number of memory accesses across NUMA nodes during reduction operations and improving parallel performance.

[0056] S4. Perform the calculation task and reduce the calculation results to obtain the final result.

[0057] Specifically, in actual execution, a block reduction pattern is adopted. First, reduction is performed among the CPU cores within each NUMA node, and the reduction result of each NUMA node is saved to its local memory space. Then, a second reduction is performed on the reduction results of all NUMA nodes to obtain the final result. The reduction within each NUMA node adopts a tree-structured reduction pattern. Specific Implementation Example 3:

[0059] S1. Obtain computing tasks and classify them into different types to obtain the divided computing tasks, wherein the divided computing tasks are parallel scans;

[0060] Specifically, the parallel scan operation is only designed for computational scenarios in a one-dimensional execution space. It sorts all computational tasks within the execution interval, and the final result of each task is obtained by reducing the results of all tasks preceding it. Essentially, it is equivalent to recursively performing data reduction operations.

[0061] S2. Determine the execution space size and select the execution strategy;

[0062] Specifically, for a one-dimensional execution space strategy, the execution space is pre-divided in the manner described above.

[0063] S3. Divide the execution space according to the NUMA architecture information and allocate the divided execution subspace to the CPU core;

[0064] Specifically, when reallocating computing resources, the NUMA architecture information is obtained in the parallel reduce operation mentioned above, the number of execution sub-intervals allocated to each NUMA node is calculated, and the execution sub-intervals are mapped to the CPU cores of the NUMA node for computation in a sequential manner.

[0065] Each execution sub-interval is executed by a CPU core thread. Each index within the interval represents a computation task, and the interval length represents the total number of computation tasks executed. First, a memory space is allocated for each core thread to store the computation results of each thread. The size of the space is determined by the data type of the computation results and the length of the execution sub-interval.

[0066] S4. Perform the calculation task and reduce the calculation results to obtain the final result.

[0067] S4.1 Execute computation tasks based on execution sub-intervals;

[0068] S4.2. For the execution sub-interval, use serial reduction mode to output the reduction result of each calculation task and save it to the corresponding memory address space to complete the reduction between CPU cores within the NUMA node.

[0069] S4.3. Reduce the results between NUMA nodes to obtain the final result.

[0070] Specifically, within each execution sub-interval, a serial reduction mode is used to obtain the reduction result of each computation task and save it to the corresponding memory address space. Between different execution sub-intervals on the same CPU core, a serial reduction mode is used; the results of all computation tasks within the sub-interval with the largest index are reduced to the reduction result of the computation task with the largest index in the immediately preceding sub-interval. Overall, a block reduction mode is still used, first reducing between CPU cores within a NUMA node, and then reducing results between NUMA nodes. The difference between this operation and the parallel reduce operation is that a reduction operation is performed for each computation task.

[0071] This invention provides a scalable, performance-portable parallel computing library that is adaptive to the characteristics of different ARM architectures. Analyzing the characteristics of ARM architecture and the features of NUMA architecture in multi-core processors, a scalable and performance-portable parallel computing library is provided. This includes parallel for loops, parallel reduce operations, and parallel scan operations. Furthermore, different execution strategies are designed for different computing scenarios: one-dimensional space execution strategy, multi-dimensional space execution strategy, and group execution strategy, which can reasonably allocate computing resources according to different NUMA architectures to achieve performance optimization.

[0072] like Figure 2 As shown, a NUMA-aware parallel computing system for ARM architecture includes:

[0073] The type partitioning module is used to acquire computing tasks and partition them into types to obtain the partitioned computing tasks;

[0074] The configuration module is used to determine the size of the execution space and select the execution strategy;

[0075] The allocation module is used to divide the execution space according to the NUMA architecture information and allocate the divided execution subspace to the CPU cores;

[0076] The reduction module is used to perform computation tasks and reduce the computation results to obtain the final result.

[0077] The content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0078] A NUMA-aware parallel computing device for ARM architecture:

[0079] At least one processor;

[0080] At least one memory for storing at least one program;

[0081] When the at least one program is executed by the at least one processor, the at least one processor implements a NUMA-aware parallel computing method for ARM architecture as described above.

[0082] The content of the above method embodiments is applicable to the device embodiments. The specific functions implemented by the device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0083] A storage medium storing processor-executable instructions, characterized in that: the processor-executable instructions, when executed by a processor, are used to implement a NUMA-aware parallel computing method for ARM architecture as described above.

[0084] The content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0085] The above is a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the embodiments described. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of this application.

Claims

1. A NUMA-aware parallel computing method for ARM architecture, characterized in that, Includes the following steps: Obtain the computing tasks and classify them into different types to obtain the classified computing tasks; Determine the size of the execution space and select the execution strategy; The execution space is divided according to the NUMA architecture information, and the divided execution subspaces are allocated to the CPU cores; Perform the computation task and reduce the computation results to obtain the final result; The execution strategies include one-dimensional space execution strategies, multi-dimensional space execution strategies, and grouped execution strategies. The step of dividing the execution space according to the NUMA architecture information and allocating the divided execution subspaces to CPU cores specifically includes: Obtain the NUMA architecture information of the current device; The NUMA architecture information includes the number of NUMA nodes and the number of CPU cores contained in each NUMA node; The allocation coefficients are calculated based on the device's NUMA architecture information; Based on the allocation coefficient, the number of sub-execution spaces is allocated to each NUMA node in a sequential manner. Selecting a one-dimensional execution strategy, specifically the division of the execution space based on NUMA architecture information, includes: Based on the number of available CPU cores in the device, the linear execution interval is evenly divided to obtain the divided execution sub-intervals; The lengths of the divided execution sub-intervals are equal.

2. The NUMA-aware parallel computing method for ARM architecture according to claim 1, characterized in that, The step of performing the computation task and reducing the computation results to obtain the final result specifically includes: Computational tasks are performed based on execution sub-intervals; Within the execution sub-interval, a serial reduction mode is used to output the reduction result of each computation task and save it to the corresponding memory address space, thus completing the reduction between CPU cores within the NUMA node; The results between NUMA nodes are reduced to obtain the final result.

3. The NUMA-aware parallel computing method for ARM architecture according to claim 1, characterized in that, Selecting a multi-dimensional execution strategy, specifically the division of the execution space based on NUMA architecture information, includes: The execution space dimensions, except for the last one, are grouped according to a preset unit length, and the last space dimension is not divided. The groups of each execution space dimension are combined to obtain the partitioned execution subspace.

4. The NUMA-aware parallel computing method for ARM architecture according to claim 1, characterized in that, Selecting a grouping execution strategy, specifically the division of the execution space based on NUMA architecture information, includes: Group the CPU cores to get the number of groups; The execution subspace is obtained by dividing the first dimension according to the number of groups and the second dimension according to the number of cores in each group.

5. A NUMA-aware parallel computing system for ARM architecture, characterized in that, For performing the NUMA-aware parallel computing method for ARM architecture as described in claim 1, comprising: The type partitioning module is used to acquire computing tasks and partition them into types to obtain the partitioned computing tasks; The configuration module is used to determine the size of the execution space and select the execution strategy; The allocation module is used to divide the execution space according to the NUMA architecture information and allocate the divided execution subspace to the CPU cores; The reduction module is used to perform computation tasks and reduce the computation results to obtain the final result.

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