Controller and memory system and data processing system comprising the controller

Abstract

A controller and a memory system including the same are disclosed. The memory system can include a memory device adapted to store data and valid information of the data, and a controller adapted to allocate a logical address to write data requested by a host based on the valid information, and to notify the host of the allocated logical address.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2020-0159859, filed on November 25, 2020, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The various embodiments of this disclosure generally relate to a controller. More specifically, the embodiments relate to a controller that allocates data addresses based on file system information and a system including the controller. Background Technology

[0004] Recently, the paradigm of computing environments has shifted towards ubiquitous computing, making computer systems accessible virtually anytime, anywhere. Consequently, the use of portable electronic devices such as mobile phones, digital cameras, and laptops is rapidly increasing. These portable electronic devices typically use or include memory systems that use or embed at least one memory device, i.e., data storage devices. Data storage devices can serve as either primary or secondary storage devices for portable electronic devices.

[0005] Unlike hard drives, data storage devices using non-volatile semiconductor memory offer advantages such as superior stability and durability due to the absence of mechanical drive components (e.g., robotic arms), high data access speeds, and low power consumption. In the context of memory systems with these advantages, data storage devices include Universal Serial Bus (USB) memory devices, memory cards with various interfaces, solid-state drives (SSDs), and more. Summary of the Invention

[0006] Various embodiments of this disclosure relate to a controller and its operating method, which can allocate data addresses based on data file system information and valid information and notify the host of the allocated addresses, thereby optimizing system storage space and reducing redundant operations.

[0007] According to embodiments of this disclosure, a memory system may include: a memory device adapted to store data and valid information of the data; and a controller adapted to assign a logical address to write data requested by a host based on the valid information, and to notify the host of the assigned logical address.

[0008] According to embodiments of the present disclosure, a controller may include: a memory adapted to store disk information representing a plurality of region identifiers identifying a plurality of data regions and a plurality of logical addresses corresponding to each of the plurality of region identifiers; and a control component adapted to assign corresponding logical addresses to the data to be written based on the region identifiers of the data to be written and the disk information.

[0009] According to an embodiment of the disclosure, a data processing system can include a memory system; and a host adapted to provide disk information to the memory system, wherein the memory system includes a memory device adapted to store data requested by the host; a memory adapted to store disk information and valid information of the data; and a control component adapted to assign a corresponding logical address to the data based on the disk information and the valid information.

[0010] According to an embodiment of the disclosure, a data processing system can include a host; and a memory system including a memory device including a plurality of regions coupled to the host and configured to: receive and store disk information from the host, the disk information including identification information of the plurality of regions and logical block addresses (LBAs) of each region; perform one or more operations on one or more regions among the plurality of regions; update, in response to the one or more operations, whether one or more logical block addresses among the logical block addresses are associated with valid data or invalid data; receive write data from the host; assign a logical block address among the logical block addresses associated with the invalid data to the write data; perform a write operation on the memory device associated with the write data; and transmit information indicating completion of the write operation and the assigned logical block address to the host. BRIEF DESCRIPTION OF DRAWINGS

[0011] Figure 1 is a block diagram illustrating a data processing system including a memory system according to an embodiment of the disclosure.

[0012] Figure 2 is a block diagram illustrating Figure 1 the memory system.

[0013] Figure 3 is a diagram illustrating disk information provided from a host to a memory system according to an embodiment of the disclosure.

[0014] Figure 4 is a diagram illustrating disk information and valid information stored in a memory system according to an embodiment of the disclosure.

[0015] Figure 5 is a diagram illustrating an operation of a controller according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0016] Various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings, in order to describe the present disclosure in detail and enable a person of ordinary skill in the art to which the present disclosure pertains to easily implement the technical spirit of the present disclosure. However, the present disclosure is not limited to the embodiments disclosed below, but can be implemented in various other forms. The disclosed embodiments are provided in order to make the present disclosure complete and enable a person skilled in the art to practice the present invention.

[0017] Figure 1 is a block diagram illustrating a data processing system 100 including a memory system according to an embodiment of the present disclosure. Referring to Figure 1 , the data processing system 100 can include a host 110 and a memory system 120.

[0018] For example, the host 110 can include any one of various portable (i.e., wireless) electronic devices such as a mobile phone, an MP3 player, and a laptop computer, or any one of various non-portable (i.e., wired) electronic devices such as a desktop computer, a game console, a television (TV), and a projector.

[0019] The host 120 further includes at least one operating system (OS) that can generally manage and control functions and operations performed in the host 110. The OS can provide interoperability between the host 110 interfaced with the memory system 120 and a user who needs and uses the memory system 120. The OS can support functions and operations corresponding to a user request. By way of example and not limitation, the OS can be classified into a general-purpose operating system and a mobile operating system according to mobility of the host 110. The general-purpose operating system can be classified into a personal operating system and an enterprise operating system according to system requirements or a user's environment. The personal operating system including Windows and Chrome can be used to support services for general purposes. The enterprise operating system including Windows Server, Linux, Unix, etc. can be used to obtain and support high performance. Further, the mobile operating system can include Android, iOS, Windows Mobile, etc. The mobile operating system can be used to support services or functions for mobility (e.g., power saving functions). The host 110 can include a plurality of operating systems. The host 110 can run a plurality of operating systems interlocked with the memory system 120 corresponding to a user's request. The host 110 can transmit a plurality of commands corresponding to a user's request to the memory system 120, thereby performing operations corresponding to the commands within the memory system 120.

[0020] According to an embodiment, the host 110 can include an application program, a file system, a device driver, a memory, and a disk information management module 130.

[0021] An application can request a write operation or a read operation from a file system. The file system can manage data stored in the memory system 120 in units of files. The host 110 can include a plurality of file systems. A device driver can transmit a write request or a read request to the memory system 120 to process the write operation or the read operation. The memory can be used to temporarily store data in the host 110.

[0022] The disk information management module 130 can manage disk information about disks managed in the host 110. The host 110 according to an embodiment can provide the memory system 120 with disk information managed by the disk information management module 130. The disk information management module 130 can manage disk information according to partition information or file system information, and transmit the disk information to the memory system 120. The following refers to the disk information management module 130 as a disk information management module 130. Figure 3 and Figure 4 The structure of the disk information is described in more detail.

[0023] The memory system 120 can operate or perform a specific function or operation in response to a request from the host 110, and, in particular, can store data to be accessed by the host 110. The memory system 120 can serve as a main memory system or an auxiliary memory system of the host 110. The memory system 120 can be implemented with any one of various types of storage devices that can be electrically coupled with the host 110 according to a protocol of a host interface. Non-limiting examples of suitable storage devices include a solid state drive (SSD), a multimedia card (MMC), an embedded MMC (eMMC), a reduced size MMC (RS-MMC), a micro- MMC, a secure digital (SD) card, a mini-SD, a micro-SD, a universal serial bus (USB) storage device, a universal flash storage (UFS) device, a compact flash (CF) card, a smart media (SM) card, a memory stick, or the like.

[0024] The memory system 120 can be configured as a part of, for example, a computer, an ultra mobile personal computer (UMPC), a workstation, a netbook, a personal digital assistant (PDA), a portable computer, a network tablet, a tablet computer, a wireless phone, a mobile phone, a smart phone, an electronic book, a portable multimedia player (PMP), a portable game machine, a navigation system, a black box, a digital camera, a digital multimedia broadcasting (DMB) player, a three-dimensional (3D) television, a smart television, a digital audio recorder, a digital audio player, a digital picture recorder, a digital picture player, a digital video recorder, a digital video player, a storage device configured for a data center, a device capable of transmitting and receiving information in a wireless environment, one of various electronic devices configured for a home network, one of various electronic devices configured for a computer network, one of various electronic devices configured for a telematics network, a radio frequency identification (RFID) device, or one of various components configured for a computing system.

[0025] The storage device of the memory system 120 can be implemented with a volatile memory device such as dynamic random access memory (DRAM) and static RAM (SRAM) and / or a non-volatile memory device such as read only memory (ROM), mask ROM (MROM), programmable ROM (PROM), erasable programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), ferroelectric RAM (FRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), resistive RAM (RRAM or ReRAM), and flash memory.

[0026] Referring to Figure 1 , the memory system 120 can include a controller 140 and a memory device 150. The controller 140 can process data accessed by the host 110, and the memory device 150 can store data processed by the controller 140.

[0027] The controller 140 can control the memory device 150 in response to a request of the host 110. For example, the controller 140 can store data provided by the host 110 in the memory device 150, and provide data read from the memory device 150 to the host 110. To this end, the controller 140 can control a write operation, a read operation, a program operation, an erase operation, and a background operation of the memory device 150.

[0028] Figure 2 is a block diagram illustrating Figure 1 the memory system 120 shown in FIG. 1.

[0029] Referring to Figure 2The controller 140 can include a host interface 210, a memory interface 220, a processor 230, and a memory 240. All components 210, 220, 230, and 240 included in the controller 140 can share signals transmitted inside the controller 140 through an internal bus.

[0030] The host interface 210 can interface the host 110 and the memory system 120 in response to a protocol of the host 110. The host interface 210 can perform an operation of exchanging commands and data transmitted between the host 110 and the memory system 120.

[0031] The host interface 210 can process commands and data provided from the host 110 and can communicate with the host 110 through at least one of various interface protocols such as a universal serial bus (USB), a multimedia card (MMC), a peripheral component interconnect express (PCI-e or PCIe), a small computer system interface (SCSI), a serial attached SCSI (SAS), a serial advanced technology attachment (SATA), a parallel advanced technology attachment (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), and an electronic integrated drive (IDE). According to an embodiment, the host interface 210 is a component for exchanging data with the host 110, which can be implemented through firmware called a host interface layer (HIL).

[0032] The memory interface 220 can serve as an interface for handling commands and data transferred between the controller 140 and the memory device 150 to allow the controller 140 to control the memory device 150 in response to a request transferred from the host 110. In the case when the memory device 150 is a flash memory, and particularly when the memory device 150 is a NAND flash memory, the memory interface 220 can generate a control signal of the memory device 150 under the control of the processor 230 and can process data input into or output from the memory device 150. The memory interface 220 can provide an interface for handling commands and data between the controller 140 and the memory device 150, for example, operations of a NAND flash interface, particularly, operations between the controller 140 and the memory device 150. According to an embodiment, the memory interface 220 can be implemented through firmware called a flash interface layer (FIL) as a component for exchanging data with the memory device 150.

[0033] The processor 230 can be implemented with a microprocessor or a central processing unit (CPU). The memory system 120 can include one or more processors 230. The processor 230 can control overall operations of the memory system 120. As an example and not a limitation, the processor 230 can control a program operation or a read operation of the memory device 150 in response to a write request or a read request input from the host 110. According to an embodiment, the processor 230 can use or run firmware to control overall operations of the memory system 120. Herein, the firmware can be referred to as a flash translation layer (FTL). The FTL can perform operations as an interface between the host 110 and the memory device 150. The host 110 can transmit a request for a write operation and a read operation to the memory device 150 through the FTL.

[0034] For example, when performing an operation requested from the host 110 in the memory device 150, the controller 140 uses a processor 230 implemented with a microprocessor or a central processing unit (CPU) or the like. The processor 230 interfaced with the memory device 150 can handle instructions or commands corresponding to input commands from the host 110. The controller 140 can perform foreground operations, which are operation of commands, corresponding to commands input from the host 110, such as a program operation corresponding to a write command, a read operation corresponding to a read command, an erase / trash operation corresponding to an erase / trash command, and a parameter setting operation corresponding to a set parameter command or a set feature command.

[0035] For another example, the controller 140 can perform background operations on the memory device 150 through the processor 230. As an example and not a limitation, the background operations of the memory device 150 include a garbage collection (GC) operation, a wear leveling (WL) operation, a mapping clean operation, and a bad block management operation of checking or searching bad blocks.

[0036] The garbage collection operation can include an operation of copying and processing data stored in one random memory block among the memory blocks MEMORY BLOCK<0,1,2,...> of the memory device 150 to another random memory block. The wear leveling operation can include an operation of exchanging and processing stored data between the memory blocks MEMORY BLOCK<0,1,2,...> of the memory device 150. The mapping clean operation can include an operation of storing mapping data stored in the controller 140 in the memory blocks MEMORY BLOCK<0,1,2,...> of the memory device 150. The bad block management operation can include an operation of checking and processing bad blocks among the memory blocks MEMORY BLOCK<0,1,2,...> of the memory device 150.

[0037] The controller 140 can generate and manage log data by the processor 230 in response to an operation of accessing the memory blocks MEMORY BLOCK<0,1,2,...> of the memory device 150. The operation of accessing the memory blocks MEMORY BLOCK<0,1,2,...> of the memory device 150 can include a foreground operation or a background operation performed on the memory blocks MEMORY BLOCK<0,1,2,...> of the memory device 150.

[0038] The memory 240, which is a working memory of the memory system 120 and the controller 140, can store data for driving the memory system 120 and the controller 140. More specifically, when the controller 140 controls the memory device 150 in response to a request of the host 110, the memory 240 can store firmware driven by the processor 230 and data, e.g., metadata, for driving the firmware.

[0039] In addition, the memory 240, which is a buffer memory of the memory system 120 and the controller 140, can temporarily store write data transmitted from the host 110 to the memory device 150 and read data transmitted from the memory device 150 to the host 110. The memory 240 can include a program memory, a data memory, a write buffer / cache, a read buffer / cache, a data buffer / cache, and a mapping buffer / cache for storing the write data and the read data.

[0040] The memory 240 can be implemented with a volatile memory. The memory 240 can be implemented with a static random access memory (SRAM), a dynamic random access memory (DRAM), or both.

[0041] Although Figure 2 Although it is illustrated that the memory 240 is included in the controller 140, the present disclosure is not limited thereto. The memory 240 can be included outside the controller 140, and the controller 140 can input and output data to and from the memory 240 through a separate memory interface (not shown).

[0042] The memory device 150 can serve as a storage medium of the memory system 120.

[0043] The memory device 150 can be a non-volatile memory device, and can retain data stored therein even if power is not supplied. The memory device 150 can store data provided from the host 110 through a write operation, while providing data stored therein to the host 110 through a read operation.

[0044] In an embodiment of the disclosure, the memory device 150 is implemented as a non-volatile memory, for example, a flash memory such as a NAND flash memory, a NOR flash memory, or the like. Alternatively, the memory device 150 can be implemented by at least one of a phase change random access memory (PCRAM), a ferroelectric random access memory (FRAM), and a spin injection magnetic memory or a spin transfer torque magnetic random access memory (STT-MRAM).

[0045] The memory device 150 can include a plurality of memory blocks MEMORY BLOCK<0, 1, 2, …>. Each of the memory blocks MEMORY BLOCK<0, 1, 2, …> included in the memory device 150 can include a plurality of pages P<0, 1, 2, 3, 4, …>. Further, although not specifically shown in the drawings, each of the pages P<0, 1, 2, 3, 4, …> can include a plurality of memory cells.

[0046] Each of the memory blocks MEMORY BLOCK<0, 1, 2, …> included in the memory device 150 can be classified as a single-level cell (SLC) memory block and a multi-level cell (MLC) memory block according to the number of bits that can be stored or represented in a single memory cell included therein.

[0047] The memory device 150 can include a plurality of memory blocks. The plurality of memory blocks can be any one of different types of memory blocks such as a single-level cell (SLC) memory block, a multi-level cell (MLC) memory block, and the like, according to the number of bits that can be stored or represented in a single memory cell. Here, the SLC memory block includes a plurality of pages implemented by memory cells each storing one bit of data. The SLC memory block can have a higher data I / O operation performance and a higher endurance. The MLC memory block includes a plurality of pages implemented by memory cells each storing a plurality of bits (e.g., two or more bits) of data. The MLC memory block can have a greater storage capacity for the same space compared to the SLC memory block. The MLC memory block can be highly integrated in terms of storage capacity. In an embodiment, the memory device 150 can be implemented with MLC memory blocks such as an MLC memory block, a triple-level cell (TLC) memory block, a quad-level cell (QLC) memory block, and combinations thereof. The MLC memory block can include a plurality of pages implemented by memory cells each capable of storing 2 bits of data. The triple-level cell (TLC) memory block can include a plurality of pages implemented by memory cells each capable of storing 3 bits of data. The quad-level cell (QLC) memory block can include a plurality of pages implemented by memory cells each capable of storing 4 bits of data. In another embodiment, the memory device 150 can be implemented with blocks including a plurality of pages implemented by memory cells each capable of storing 5 bits or more of data.

[0048] As described above, the disk information managed by the disk information management module 130 of the host 110 can be provided to the memory system 120. The controller 140 can store the disk information transmitted by the host 110 in the memory device 150. During a write operation, the controller 140 can allocate logical addresses to write data based on the disk information, and notify the host 110 of the allocated logical addresses.

[0049] Specifically, the processor 230 of the controller 140, which serves as a control component (hereinafter, referred to as a control component 230) that controls the overall operation of the memory system 120, can store the disk information in the memory 240. The control component 230 can allocate logical addresses to write data based on the disk information stored in the memory 240. In addition, the disk information stored in the memory 240 can be backed up to the memory device 150 by the control component 230.

[0050] The disk information provided by the host 110 and the structure of data stored in the memory system 120 are described in detail below.

[0051] Figure 3 The format of the disk information provided from the host 110 to the memory system 120 according to an embodiment of the disclosure is illustrated. However, the disclosure is not limited thereto, and the host 110 can provide the memory system 120 with disk information in various formats.

[0052] In Figure 3 In the illustrated example, the host 110 can transmit the disk information to the memory system 120 together with a command CMD indicating the provision of the information. In some embodiments, the disk information can include the number of data regions DI No., and the first and last logical addresses DIA LBA(S) and DIB LBA(S) and DIA LBA(E) and DIB LBA(E) corresponding to each of the data regions. That is, the first and last logical addresses DIA LBA(S) and DIA LBA(E) are for a data region A, and the first and last logical addresses DIB LBA(S) and DIB LBA(E) are for a data region B.

[0053] The number of data regions DI No. of the disk information indicates the number of a plurality of data regions distinguished from each other. That is, the host 110 can distinguish a plurality of data regions according to the number of disk partitions, the type of disk partitions (e.g., an exchange partition and a file system partition), the name of a file system, and the type of data (e.g., metadata and general data) managed by the file system.

[0054] The plurality of data areas distinguished as above can be identified by area identifiers DI, and correspond to logical addresses LBAs that do not overlap with each other. As an example, Figure 3 The number of data areas DI No. is shown to be 2, and thus the data areas are identified by area identifiers DI "A" and "B". The two data areas can correspond to logical addresses LBAs "0 to 100" and "101 to 2000", respectively.

[0055] As Figure 3 indicated, when the number of data areas DI No. is provided by the host 110 as disk information, the storage system 120 can sequentially assign the area identifiers DI "A" and "B" to respective data areas corresponding to the number of data areas DI No., and identify the data areas. However, the present disclosure is not limited thereto. The area identifiers DI can be directly provided by the host 110 as disk information instead of the number of data areas DI No., and managed by the storage system 120.

[0056] Figure 4 is a diagram showing disk information and valid information stored in the storage system 120 according to an embodiment of the present disclosure.

[0057] Referring to Figure 4 , when the disk information is received together with a command CMD instructing to provide the information from the host 110, the control component 230 of the controller 140 can store or update the received disk information in or to the storage 240. The disk information stored in the storage 240 can represent a plurality of area identifiers DI for identifying a plurality of data areas, and a plurality of logical addresses LBAs corresponding to the plurality of area identifiers DI, respectively. According to Figure 3 the example shown, when the number of data areas DI No. is 2, and the disk information corresponding to logical addresses LBAs "0 to 100" and "101 to 2000" is received, the control component 230 can update and manage the disk information such that the area identifier DI "A" corresponds to the data area of which the logical address LBA is "0 to 100", and the area identifier DI "B" corresponds to the data area of which the logical address LBA is "101 to 2000".

[0058] In addition, the control component 230 can store valid information VALID in the memory 240, the valid information VALID indicating whether data corresponding to a logical address LBA is valid. The valid information VALID can indicate whether data corresponding to a logical address LBA is stored in the memory device 150. For example, when data corresponding to a logical address LBA "0" is stored in the first page P<0> of the memory device 150, the control component 230 can set valid information VALID of the logical address LBA "0" to a logical level "1". On the other hand, valid information VALID of a logical address LBA (e.g., a logical address LBA "100") for which data is not stored in the memory device 150 can correspond to a logical level "0".

[0059] According to the present embodiment, the controller 140 can transmit valid information VALID to the host 110. When a request for valid information VALID is received from the host 110, the controller 140 can transmit valid information VALID to the host 110 and can back up the transmitted valid information VALID to a memory of the host 110.

[0060] During a data invalidation operation, the controller 140 can invalidate or delete data stored in the memory device 150. For example, when a trim command is received from the host 110, the controller 140 can delete data corresponding to a logical address LBA received from the memory device 150 together with the trim command. To this end, the controller 140 can invalidate valid information VALID corresponding to the received logical address LBA, i.e., update the valid information VALID to a logical level "0". In the illustrated example, when a logical address LBA "101" is received together with the trim command during the data invalidation operation, the control component 230 can update valid information VALID of the logical address LBA "101" to a logical level "0". Figure 4 In the illustrated example, when a logical address LBA "101" is received together with the trim command during the data invalidation operation, the control component 230 can update valid information VALID of the logical address LBA "101" to a logical level "0".

[0061] Figure 5 is a diagram illustrating an operation of the controller 140 according to an embodiment of the present disclosure. As an example, Figure 5 a write operation of data corresponding to a region identification DI "A" is illustrated.

[0062] According to an embodiment, during a write operation, a region identification DI "A" corresponding to write data can be transmitted from the host 110 to the memory system 120 along with the write data. For example, the host 110 can transmit the region identification DI "A" to the memory system 120 at the same time as transmitting a write command indicating the write operation. Based on the transmitted region identification DI "A" and the disk information, the controller 140 of the memory system 120 can allocate logical addresses LBAs to the write data, and notify the host 110 of the allocated logical addresses LBAs.

[0063] As described in the example shown in Figure 5 When the region identification DI "A" is received, the control component 230 of the controller 140 can check logical addresses LBAs "0 to 100" corresponding to the region identification DI "A" based on the disk information stored in the memory 240. In addition, the control component 230 can allocate a logical address LBA "2" among the checked logical addresses LBAs "0 to 100" for which corresponding data is invalid (i.e., the logical level of the valid information VALID is "0") to the received write data based on the valid information VALID. As an example, Figure 5 Logical addresses LBAs "2" and "3" for which the logical level of the valid information VALID is "0" are sequentially allocated to the write data, and the smaller logical address LBA "2" is allocated to the write data, as shown by way of example. However, the present disclosure is not limited thereto, and any one of the logical addresses LBAs "2" and "3" for which the logical level of the valid information VALID is "0" can be randomly allocated to the write data.

[0064] After the write operation, the controller 140 can transmit information indicating whether the write operation is completely performed to the host 110. In some embodiments, the controller 140 can transmit the logical address LBA "2" allocated (designated) to the write data to the host 110 along with the information indicating whether the write operation is completely performed.

[0065] According to the present embodiment, the controller 140 can replace and perform an operation for operating a file system performed by the host 110 by using information managed for a background operation of the memory device 140. For example, data stored in the memory device 140 can be invalidated by a trim operation, and the controller 140 can manage the invalidated data or valid data using a bitmap table to perform a background operation, such as a garbage collection operation. The controller 140 can allocate an invalidated (i.e., available) logical address to data requested to the host 110 using the bitmap table, and notify the host 110 of the allocated logical address. Accordingly, the host 110 can not need to separately manage logical addresses, and can request a write operation without logical addresses. Accordingly, the overhead and storage space of the host 110 can be reduced.

[0066] According to embodiments of the present disclosure, the controller can replace and perform operations for operating a file system, which are performed by the host, by using information managed for a background operation of the memory device together with file system information. Accordingly, the overhead of the host can be reduced and the space used in the system can be optimized. In addition, based on improved performance by configuration of a circuit implemented in the memory device in a hardware manner, the controller can perform operations for operating a file system.

[0067] The methods, processes and / or operations described herein can be executed by code or instructions to be executed by a computer, processor, controller, or other signal processing apparatus. The computer, processor, controller, or other signal processing apparatus can be those described herein or others besides those described herein. Since the algorithms forming the basis of the methods (or the operations of the computer, processor, controller, or other signal processing apparatus) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing apparatus into a special purpose processor for executing the methods herein.

[0068] When implemented at least partly in software, the controllers, processors, devices, modules, units, multiplexers, generators, logic, managers, interfaces, decoders, drivers, and other signal generation and processing features can include, among other things, memories or other storage devices for storing code or instructions to be executed by, for example, computers, processors, microprocessors, controllers, or other signal processing apparatus. The computers, processors, microprocessors, controllers, or other signal processing apparatus can be those described herein or others besides those described herein. Since the algorithms forming the basis of the methods (or the operations of the computer, processor, microprocessor, controller, or other signal processing apparatus) are described in detail, the code or instructions for implementing the operations of the method embodiments can transform the computer, processor, controller, or other signal processing apparatus into a special purpose processor for executing the methods described herein.

[0069] While the present disclosure has been described with reference to various embodiments, it should be understood that the disclosed embodiments are for purposes of illustration and are not limiting, for example, although the disclosed embodiments describe a controller managing bad blocks of a memory device, a plurality of memory blocks can be designated as bad blocks by control logic included in the memory device. Further, those skilled in the art will appreciate that various adaptations and modifications of the embodiments described can be practiced within the scope of the present disclosure. While embodiments of the disclosed technology have been described with reference to particular details of certain embodiments thereof, it is not intended that such details should limit the scope of the present disclosure, which should only be limited by the claims and equivalents thereof.

Claims

1.A memory system comprising: a memory device storing data and valid information of the data; and a controller, when receiving a write command including a region identification corresponding to write data requested by a host from the host, allocating a logical address to the write data based on the valid information, and notifying the host of the allocated logical address, wherein the write command does not include a logical address corresponding to the write data, wherein the allocated logical address by the controller includes a logical address corresponding to invalid data or a logical address of non-stored data. 2.The memory system of claim 1, wherein the memory device stores disk information indicating a plurality of region identifications identifying a plurality of data regions and a plurality of logical addresses corresponding to each of the plurality of region identifications. 3.The memory system of claim 1, wherein the controller transmits the allocated logical address to the host together with information indicating whether a write operation corresponding to the write command is completely performed. 4.The memory system of claim 1, wherein the valid information indicates whether data corresponding to a plurality of logical addresses is valid. 5.The memory system of claim 4, wherein the controller checks a logical address corresponding to a region identification transmitted by the host based on disk information, and allocates a logical address corresponding to invalid data among the checked logical addresses to the write data based on the valid information. 6.The memory system of claim 4, wherein the controller transmits the valid information to the host according to a request of the host. 7.The memory system of claim 4, wherein the controller receives a logical address from the host during a data invalidation operation, and invalidates valid information corresponding to the received logical address during the data invalidation operation. 8.The memory system of claim 2, wherein a number of the plurality of data regions and a first logical address and a last logical address corresponding to each of the plurality of data regions are received from the host as the disk information. 9.The memory system of claim 2, wherein the plurality of data regions are distinguished according to partition information or file system information. 10.A controller comprising: a memory storing disk information indicating a plurality of region identifications identifying a plurality of data regions and a plurality of logical addresses corresponding to each of the plurality of region identifications; and a control component, when receiving a write command including a region identification corresponding to write data from a host, allocating a logical address of non-valid data to the write data based on the region identification of the write data and the disk information, wherein the write command does not include a logical address corresponding to the write data, wherein the allocated logical address by the control component includes a logical address corresponding to invalid data or a logical address of non-stored data. ​ ​ 11.The controller of claim 10, wherein the control component transfers the allocated logical address to the host along with information indicating whether a write operation corresponding to the write command is completely performed. 12.The controller of claim 10, wherein the memory stores valid information indicating whether data corresponding to the plurality of logical addresses is valid. 13.The controller of claim 12, wherein the control component checks logical addresses corresponding to region identifiers of the write data based on the disk information, and allocates, based on the valid information, logical addresses corresponding to invalid data among the checked logical addresses to the write data. 14.The controller of claim 12, wherein the control component transfers the valid information to the host according to a request of the host. 15.The controller of claim 12, wherein the control component invalidates valid information corresponding to a received logical address in response to the received logical address being received during a data invalidation operation. 16.The controller of claim 10, wherein the number of the plurality of data regions and a first logical address and a last logical address corresponding to each of the plurality of data regions are received from the host as the disk information. 17.The controller of claim 10, wherein the plurality of data regions are distinguished according to partition information or file system information. 18.A data processing system comprising: a memory system; and a host providing disk information to the memory system, wherein the memory system comprises: a memory device storing data requested by the host; a memory storing the disk information and valid information of the data; and a control component allocating logical addresses to write data based on the disk information and the valid information when a write command including region identifiers corresponding to write data is received from the host, wherein the write command does not include logical addresses corresponding to the write data, wherein allocated logical addresses by the memory system include logical addresses corresponding to invalid data or logical addresses of non-stored data. 19.The data processing system of claim 18, wherein the host comprises a disk information management module managing the disk information according to partition information or file system information, and transferring the disk information to the memory system. ​

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