Display device and method for manufacturing the same

Abstract

A display device and a method of manufacturing the display device are disclosed. The display device includes a substrate and pixels. The substrate includes a non-display area and a display area including a pixel area, and the pixels are disposed in each pixel area. The pixel may include a first area to a third area separated from each other in one direction, a first sub-electrode and a second sub-electrode disposed in each of the first area to the third area and spaced apart from each other, a plurality of light-emitting elements disposed in each of the first area to the third area and disposed between the first sub-electrode and the second sub-electrode, a bridging pattern disposed in each of the first area and the third area under the first sub-electrode and the second sub-electrode of the corresponding area with an insulating layer disposed therebetween, a first contact electrode disposed on the first sub-electrode of the corresponding area in each of the first area to the third area, and a second contact electrode disposed on the second sub-electrode of the corresponding area in each of the first area to the third area.

Description

Technical Field

[0001] Various embodiments of the present disclosure relate to a display device and a method of manufacturing the display device. Background Art

[0002] With the increasing interest in information display and the increasing demand for using portable information media, the demand for display devices has increased significantly, and their commercialization is underway. Summary of the Invention

[0003] Technical Problem

[0004] Various embodiments of the present disclosure relate to a display device having enhanced reliability and a method of manufacturing the display device.

[0005] Technical Solution

[0006] A display device according to an embodiment of the present disclosure may include: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas; and pixels disposed in each of the pixel areas. The pixels may include: a first area to a third area separated from each other in one direction; a first sub-electrode and a second sub-electrode disposed in each of the first area to the third area and spaced apart from each other; a plurality of light-emitting elements disposed in each of the first area to the third area and disposed between the first sub-electrode and the second sub-electrode; a bridging pattern disposed in each of the first area to the third area under the first sub-electrode and the second sub-electrode of the corresponding area, and an insulating layer interposed between the bridging pattern and the first sub-electrode and the second sub-electrode of the corresponding area; a first contact electrode disposed on the first sub-electrode of the corresponding area in each of the first area to the third area; and a second contact electrode disposed on the second sub-electrode of the corresponding area in each of the first area to the third area.

[0007] In an embodiment of the present disclosure, the bridging pattern of the first area and the first contact electrode of the second area may be electrically connected to each other.

[0008] In an embodiment of the present disclosure, in each of the first area to the third area, one of the first sub-electrode and the second sub-electrode may have a circular shape, and the other of the first sub-electrode and the second sub-electrode may have a shape surrounding the one sub-electrode.

[0009] In an embodiment of the present disclosure, the light-emitting element may include: a first light-emitting element disposed between a first sub-electrode and a second sub-electrode in a first region; a second light-emitting element disposed between the first sub-electrode and the second sub-electrode in a second region; and a third light-emitting element disposed between the first sub-electrode and the second sub-electrode in a third region. Each of the first to third light-emitting elements may be disposed between the one sub-electrode and the other sub-electrode in the circumferential direction of the one sub-electrode in the corresponding region.

[0010] In an embodiment of the present disclosure, in a plan view, the bridging pattern in the first region, the bridging pattern in the second region, and the bridging pattern in the third region may be spaced apart from each other.

[0011] In an embodiment of the present disclosure, at least a part of the bridging pattern in the first region may extend to the second region. At least a part of the bridging pattern in the second region may extend to the third region.

[0012] In an embodiment of the present disclosure, the insulating layer may include a plurality of contact holes formed to expose a part of the bridging pattern in each of the first to third regions. The display device may further include a first intermediate electrode disposed in at least one of the contact holes formed in a region between the first region and the second region among the plurality of contact holes, and electrically connecting the bridging pattern in the first region to the first contact electrode in the second region.

[0013] In an embodiment of the present disclosure, the first intermediate electrode may be integral with the first contact electrode in the second region.

[0014] In an embodiment of the present disclosure, the display device may further include a second intermediate electrode disposed in at least one of the contact holes formed in a region between the second region and the third region among the plurality of contact holes, and electrically connecting the bridging pattern in the second region to the first contact electrode in the third region. Here, the second intermediate electrode may be integral with the first contact electrode in the third region.

[0015] In an embodiment of the present disclosure, the bridging pattern in the first region may be electrically connected to each of the first intermediate electrode and the second sub-electrode in the first region. The bridging pattern in the second region may be electrically connected to each of the first intermediate electrode, the second intermediate electrode, and the second sub-electrode in the second region. The bridging pattern in the third region may be electrically connected to each of the second intermediate electrode and the second sub-electrode in the third region.

[0016] In an embodiment of the present disclosure, a first light-emitting element connected in parallel between a first sub-electrode and a second sub-electrode in a first region may form a first group, a second light-emitting element connected in parallel between the first sub-electrode and the second sub-electrode in a second region may form a second group, and a third light-emitting element connected in parallel between the first sub-electrode and the second sub-electrode in a third region may form a third group. The first group and the second group may be electrically connected through a first intermediate electrode and a bridging pattern in the first region, and the second group and the third group may be electrically connected through a second intermediate electrode and a bridging pattern in the second region.

[0017] In an embodiment of the present disclosure, the display device may further include: a conductive pattern disposed on the bridging pattern in each of the first region to the third region and electrically connected to the bridging pattern; a first auxiliary electrode disposed between the first intermediate electrode and the bridging pattern in the region between the first region and the second region; and a second auxiliary electrode disposed between the second intermediate electrode and the bridging pattern in the region between the second region and the third region.

[0018] In an embodiment of the present disclosure, the conductive pattern in the first region may be disposed between the second sub-electrode in the first region and the bridging pattern in the first region. The conductive pattern in the second region may be disposed between the second sub-electrode in the second region and the bridging pattern in the second region. The conductive pattern in the third region may be disposed between the second sub-electrode in the third region and the bridging pattern in the third region.

[0019] In an embodiment of the present disclosure, the conductive patterns in each of the first region to the third region, the first auxiliary electrode, and the second auxiliary electrode may be disposed on the same layer.

[0020] A display device according to an embodiment of the present disclosure may include: a substrate including a display region and a non-display region, the display region including a plurality of pixel regions; and pixels disposed in each of the plurality of pixel regions. The pixel may include: a first region to a third region separated from each other in one direction; a first sub-electrode and a second sub-electrode disposed in each of the first region to the third region and spaced apart from each other; a plurality of light-emitting elements disposed in each of the first region to the third region and disposed between the first sub-electrode and the second sub-electrode; a first bridging pattern extending from the first region to the second region and disposed under the second sub-electrode in each of the first region and the second region; a second bridging pattern disposed in the third region and disposed under the second sub-electrode in the third region; and a connection line disposed between the first sub-electrode in the second region and the first sub-electrode in the third region and electrically connecting the first sub-electrode in the second region to the first sub-electrode in the third region.

[0021] In an embodiment of the present disclosure, the connection line may be integral with one of the first sub-electrodes of the second region and the first sub-electrode of the third region.

[0022] In an embodiment of the present disclosure, in each of the first region to the third region, one of the first sub-electrode and the second sub-electrode may have a circular shape, and the other of the first sub-electrode and the second sub-electrode may have a shape surrounding the one sub-electrode.

[0023] In an embodiment of the present disclosure, the light-emitting element may include a first light-emitting element disposed between the first sub-electrode and the second sub-electrode in the first region, a second light-emitting element disposed between the first sub-electrode and the second sub-electrode in the second region, and a third light-emitting element disposed between the first sub-electrode and the second sub-electrode in the third region. Each of the first light-emitting element to the third light-emitting element may be disposed between the one sub-electrode and the other sub-electrode in the circumferential direction of the one sub-electrode in the corresponding region.

[0024] In an embodiment of the present disclosure, the first light-emitting element connected in parallel between the first sub-electrode and the second sub-electrode in the first region may form a first group, the second light-emitting element connected in parallel between the first sub-electrode and the second sub-electrode in the second region may form a second group, and the third light-emitting element connected in parallel between the first sub-electrode and the second sub-electrode in the third region may form a third group. Here, the first group and the second group may be electrically connected to each other through a first bridging pattern, and the second group and the third group may be electrically connected to each other through a connection line.

[0025] The display device described above may be manufactured by a method including disposing pixels in a pixel region, where the pixel region includes a first region to a third region separated from each other in one direction. Here, disposing the pixels may include forming a pixel circuit layer and forming a display element layer.

[0026] In an embodiment of the present disclosure, forming the pixel circuit layer may include: forming at least one transistor and a bridging pattern corresponding to each of the first region to the third region on a substrate; and forming an insulating layer on the transistor and the bridging pattern.

[0027] In an embodiment of the present disclosure, forming a display element layer may include: forming a second sub-electrode corresponding to each of a first region to a third region and having a circular shape, and a first sub-electrode having a shape surrounding a periphery of the second sub-electrode on an insulating layer; providing a plurality of light-emitting elements to each of the first region to the third region, and aligning the plurality of light-emitting elements between the first sub-electrode and the second sub-electrode; and forming a contact electrode on each of the first sub-electrode and the second sub-electrode, forming a first intermediate electrode integrated with the contact electrode on the first sub-electrode in the second region, and forming a second intermediate electrode integrated with the contact electrode on the first sub-electrode in the third region.

[0028] In an embodiment of the present disclosure, a bridging pattern in the first region and a contact electrode on the first sub-electrode in the second region may be electrically connected to each other through the first intermediate electrode.

[0029] In an embodiment of the present disclosure, a bridging pattern in the second region and a contact electrode on the first sub-electrode in the third region may be electrically connected to each other through the second intermediate electrode.

[0030] Advantageous Effects

[0031] In a display device and a method of manufacturing a display device according to an embodiment of the present disclosure, light-emitting elements distributed to each of a plurality of sub-emission regions forming each pixel may be connected in a series / parallel combination structure, so that the light output efficiency of the light-emitting elements can be improved, and the light output distribution of the light-emitting elements in the sub-emission regions may be uniform. Description of the Drawings

[0032] Figure 1a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0033] Figure 1b shows Figure 1a a cross-sectional view of the light-emitting element.

[0034] Figure 2a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0035] Figure 2b shows Figure 2a a cross-sectional view of the light-emitting element.

[0036] Figure 3a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0037] Figure 3b shows Figure 3a a cross-sectional view of the light-emitting element.

[0038] Figure 4ais a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0039] Figure 4b shows Figure 4a a cross-sectional view of the light-emitting element.

[0040] Figure 5 shows a display device according to an embodiment of the present disclosure, and in particular, is a schematic plan view of a display device using any one of the light-emitting elements shown in Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b as a light source.

[0041] Figures 6a to 6e shows Figure 5 a schematic diagram of an equivalent circuit of various embodiments showing the electrical connection relationships of the components included in the pixel shown in

[0042] Figures 7a to 7c shows Figure 5 a schematic diagram of an equivalent circuit of different embodiments showing the electrical connection relationships of the components included in the pixel shown in

[0043] Figure 8 schematically shows Figure 5 a plan view of the pixel in the pixel shown in

[0044] Figure 9 is a cross-sectional view taken along the line I-I' of Figure 8 .

[0045] Figure 10 is a cross-sectional view taken along the line II-II' of Figure 8 .

[0046] Figure 11 shows a display device including first to third conductive patterns connected to first to third bridging patterns shown in Figure 9 , and is a cross-sectional view corresponding to the line I-I' of Figure 8 .

[0047] Figure 12 is a plan view showing the drive current flowing through a pixel according to an embodiment of the present disclosure, and for example, shows the flow of the drive current flowing through the pixel of Figure 8 .

[0048] Figure 13 is a schematic plan view showing another example of a pixel according to an embodiment of the present disclosure.

[0049] Figure 14 is a cross-sectional view taken along line III-III’ of Figure 13 .

[0050] Figure 15 is a cross-sectional view taken along line IV-IV’ of Figure 13 .

[0051] Figure 16 shows another embodiment of the first embankment shown in Figure 15 , and is a cross-sectional view corresponding to line IV-IV’ of Figure 13 .

[0052] Figure 17 shows another embodiment of the display element layer shown in Figure 15 , and is a cross-sectional view corresponding to line IV-IV’ of Figure 13 .

[0053] Figures 18a to 18f is a schematic plan view showing in sequence the method of manufacturing the pixel shown in Figure 13 .

[0054] Figures 19a to 19h is a cross-sectional view showing in sequence the method of manufacturing the pixel shown in Figure 14 .

[0055] Figure 20 is a schematic plan view showing another example of a pixel according to an embodiment of the present disclosure.

[0056] Figure 21 is a cross-sectional view taken along line V-V’ of Figure 20 .

[0057] Figure 22 is a schematic plan view showing another example of a pixel according to an embodiment of the present disclosure. Detailed Embodiments

[0058] Since the present disclosure allows for various variations and numerous embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. However, this is not intended to limit the present disclosure to a particular practice mode, and it should be understood that all changes, equivalents, and substitutions that do not depart from the technical scope of the present disclosure are included in the present disclosure.

[0059] Throughout this disclosure, in the various figures and embodiments of this disclosure, the same reference numerals always denote the same components. For clarity of illustration, the dimensions of the elements in the figures may be exaggerated. It should be understood that although terms such as "first", "second" etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element. Similarly, the second element may also be referred to as the first element. In this disclosure, the singular form is also intended to include the plural form, unless the context clearly indicates otherwise.

[0060] It should also be understood that when used in this specification, the terms "comprise", "include", "have", etc. specify the presence of the stated features, wholes, steps, operations, elements, components, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or combinations thereof. Further, in the case where a first component such as a layer, film, region, or plate is disposed on a second component, it can be not only that the first component is directly on the second component, but also that a third component is interposed therebetween. In addition, in the case where a first component such as a layer, film, region, or plate is formed on a second component, the direction of forming the first component is not limited to the upward direction and can include a lateral direction or a downward direction. Conversely, in the case where a first component such as a layer, film, region, or plate is formed under a second component, it can be not only that the first component is directly under the second component, but also that a third component is interposed therebetween.

[0061] Embodiments of the present disclosure and the required details are described with reference to the accompanying drawings in order to describe the present disclosure in detail so that those of ordinary skill in the art to which the present disclosure pertains can easily practice the present disclosure. In addition, the singular form can include the plural form as long as it is not specifically mentioned in the sentence.

[0062] Figure 1a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 1b shows Figure 1a a cross-sectional view of the light-emitting element. Figure 2a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 2b shows Figure 2a a cross-sectional view of the light-emitting element. Figure 3a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 3b shows Figure 3a a cross-sectional view of the light-emitting element. Figure 4ais a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure. Figure 4b shows Figure 4a a cross-sectional view of the light-emitting element.

[0063] For explanatory purposes, reference will be made to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b to describe a light-emitting element LD manufactured by an etching method, and then reference will be made to Figure 4a and Figure 4b to describe a light-emitting element LD manufactured by a growth method. In an embodiment of the present disclosure, the type and / or shape of the light-emitting element LD are not limited to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b shown in the embodiments.

[0064] Referring to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b , the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as an emission stack formed by continuously stacking the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0065] In an embodiment of the present disclosure, the light-emitting element LD may extend in one direction. If the direction in which the light-emitting element LD extends is defined as the longitudinal direction, the light-emitting element LD may have one end and the other end in the extending direction. Any one of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at one end of the light-emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be provided at the other end thereof.

[0066] The light-emitting element LD can have various shapes. For example, the light-emitting element LD can have a rod-shaped or bar-shaped form extending in the longitudinal direction (i.e., having an aspect ratio greater than 1). In an embodiment of the present disclosure, the length L of the light-emitting element LD in the longitudinal direction can be greater than its diameter (D, or the width of the cross-section). The light-emitting element LD can include a light-emitting diode manufactured to have a small size (e.g., having a length L and / or a diameter D corresponding to the micron or nanometer level). In various embodiments of the present disclosure, the shape of the light-emitting element LD can be changed to meet the requirements (or design conditions) of an illumination device or a self-emitting display device.

[0067] The first semiconductor layer 11 can include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 can include an n-type semiconductor layer including any one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and doped with a first conductive dopant such as Si, Ge, or Sn. However, the material of the first semiconductor layer 11 is not limited thereto, and various other materials can be used to form the first semiconductor layer 11.

[0068] The active layer 12 can be disposed on the first semiconductor layer 11 and have a single quantum well structure or a multi-quantum well structure. The position of the active layer 12 can be changed in various ways according to the type of the light-emitting element LD. The active layer 12 can emit light having a wavelength of 400 nm to 900 nm and uses a double heterostructure. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant can be formed on and / or under the active layer 12. For example, the cladding layer can be formed of an AlGaN layer or an InAlGaN layer. In an embodiment, materials such as AlGaN or InAlGaN can be used to form the active layer 12, and various other materials can be used to form the active layer 12.

[0069] If an electric field of a predetermined voltage or higher voltage is applied to opposite ends of the light-emitting element LD, the light-emitting element LD emits light through the coupling of electron-hole pairs in the active layer 12. Since the light emission of the light-emitting element LD can be controlled based on the foregoing principle, the light-emitting element LD can be used as a light source for various light-emitting devices (including pixels of a display device).

[0070] The second semiconductor layer 13 may be disposed on the active layer 12 and include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include a p-type semiconductor layer including any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN and doped with a second conductive dopant such as Mg. However, the material for forming the second semiconductor layer 13 is not limited thereto, and the second semiconductor layer 13 may be formed of various other materials.

[0071] In an embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) in the longitudinal direction of the light-emitting element LD. For example, the width (or thickness) of the first semiconductor layer 11 in the longitudinal direction of the light-emitting element LD may be greater than the width (or thickness) of the second semiconductor layer 13 in the longitudinal direction of the light-emitting element LD. Therefore, as Figures 1a to 3b shown, the active layer 12 of the light-emitting element LD may be disposed at a position closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0072] In an embodiment of the present disclosure, in addition to the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light-emitting element LD may further include an additional electrode 15 disposed on the second semiconductor layer 13. In an embodiment, as Figure 3a and Figure 3b shown, the light-emitting element LD may further include an additional electrode 16 disposed on one end of the first semiconductor layer 11.

[0073] Although each of the additional electrodes 15 and 16 may be an ohmic contact electrode, the present disclosure is not limited thereto, and it may be a Schottky contact electrode according to an embodiment. In addition, each of the additional electrodes 15 and 16 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, and ITO may be used alone or in combination. However, the present disclosure is not limited thereto.

[0074] The materials included in each of the additional electrodes 15 and 16 may be the same as or different from each other. The additional electrodes 15 and 16 may be transparent or translucent. Therefore, the light generated from the light-emitting element LD may pass through the additional electrodes 15 and 16 and then be emitted to the outside of the light-emitting element LD. In some embodiments, in the case where the light generated from the light-emitting element LD is emitted to the outside of the light-emitting element LD through a region portion other than the opposite ends of the light-emitting element LD rather than passing through the additional electrodes 15 and 16, the additional electrodes 15 and 16 may include an opaque metal.

[0075] In an embodiment of the present disclosure, the light-emitting element LD may further include an insulating layer 14. However, in some embodiments, the insulating layer 14 may be omitted, or the insulating layer 14 may be provided to cover only some of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0076] The insulating layer 14 can prevent the active layer 12 from short-circuiting due to contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, due to the insulating layer 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, and thus the lifespan and efficiency of the light-emitting element LD can be improved. When a plurality of light-emitting elements LD are arranged in close contact with each other, the insulating layer 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD. Whether the insulating layer 14 is provided or not is not limited as long as the active layer 12 can be prevented from short-circuiting with an external conductive material.

[0077] As Figure 1a and Figure 1b shown, the insulating layer 14 may be provided in a shape surrounding the outer peripheral surface of the emission stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15. For the sake of explanation, Figure 1a a part of the insulating layer 14 has been removed is shown. The first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15 included in the light-emitting element LD may be surrounded by the insulating layer 14.

[0078] Although the insulating layer 14 has been described as surrounding the entire outer peripheral surface of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15 in the above embodiment, the present disclosure is not limited thereto.

[0079] In some embodiments, as Figure 2a and Figure 2b shown, the insulating layer 14 may surround the respective outer peripheral surfaces of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and may not surround the entire outer peripheral surface of the additional electrode 15 provided on the second semiconductor layer 13, or may surround only a part of the outer peripheral surface of the additional electrode 15 and not surround the other part of the outer peripheral surface of the additional electrode 15. Here, the insulating layer 14 may allow at least the opposite ends of the light-emitting element LD to be exposed to the outside. For example, the insulating layer 14 may allow not only the additional electrode 15 provided at one end of the second semiconductor layer 13 to be exposed to the outside, but also one end of the first semiconductor layer 11 to be exposed to the outside. In an embodiment, as Figure 3a and Figure 3bAs shown, when additional electrodes 15 and 16 are provided at corresponding opposite ends of the light-emitting element LD, the insulating layer 14 may allow at least a region portion of each of the additional electrodes 15 and 16 to be exposed to the outside. As another example, in an embodiment, the insulating layer 14 may not be provided.

[0080] In an embodiment of the present disclosure, the insulating layer 14 may include a transparent insulating material. For example, the insulating layer 14 may include at least one insulating material selected from the group consisting of SiO2, Si3N4, Al2O3, and TiO2, but the present disclosure is not limited thereto. In other words, various materials having insulating properties may be used.

[0081] If the insulating layer 14 is provided on the surface of the light-emitting element LD, a short circuit between the active layer 12 and a first electrode and / or a second electrode (not shown in the drawings) can be prevented. In addition, due to the insulating layer 14, the occurrence of defects on the surface of the light-emitting element LD can be minimized, whereby the lifetime and efficiency of the light-emitting element LD can be improved. In a case where a plurality of light-emitting elements LD are arranged in close contact with each other, the insulating layer 14 can prevent an undesired short circuit from occurring between the light-emitting elements LD.

[0082] The light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, the light-emitting element LD can be surface-treated such that when a plurality of light-emitting elements LD are mixed with a fluid solution (or solvent) and then provided to each emission region (for example, the emission region of each pixel or the emission region of each sub-pixel), the light-emitting elements LD can be uniformly distributed in the solution instead of being unevenly aggregated.

[0083] A light-emitting device including the light-emitting element LD described above can be used not only in a display device but also in various devices that require a light source. For example, in a case where a plurality of light-emitting elements LD are provided in the emission region of each pixel of a display panel, the light-emitting element LD can be used as a light source for the pixel. However, the application field of the light-emitting element LD is not limited to the examples described above. For example, the light-emitting element LD can also be used in other types of devices that require a light source (such as lighting devices).

[0084] Next, reference will be made to Figure 4a and Figure 4b to describe the light-emitting element LD manufactured by a growth method.

[0085] The following description of the light-emitting element LD manufactured by a growth method will focus on differences from the above-described embodiment, and components of the light-emitting element LD that are not separately explained in the following description may be consistent with the components of the foregoing embodiment. The same reference numerals will be used to denote the same components, and similar reference numerals will be used to denote similar components.

[0086] Reference Figure 4a and Figure 4b According to an embodiment of the present disclosure, the light emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. In some embodiments, the light emitting element LD may include an emission pattern 10 having a core-shell structure. The emission pattern 10 may include a first semiconductor layer 11 disposed in a central portion of the light emitting element LD, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0087] The light emitting element LD may be formed in a shape of a multi-pyramid extending in one direction. For example, the light emitting element LD may have a hexagonal pyramid shape. If the direction in which the light emitting element LD extends is defined as the longitudinal direction, the light emitting element LD may have one end (or lower end) and the other end (or upper end) in the longitudinal direction. A part of any one of the first semiconductor layer 11 and the second semiconductor layer 13 on one end (or lower end) of the light emitting element LD may be exposed to the outside. A part of the other of the first semiconductor layer 11 and the second semiconductor layer 13 on the other end (or upper end) of the light emitting element LD may be exposed to the outside. For example, a part of the first semiconductor layer 11 on one end (or lower end) of the light emitting element LD may be exposed, and a part of the second semiconductor layer 13 on the other end (or upper end) of the light emitting element LD may be exposed. In an embodiment, in the case where the light emitting element LD includes the additional electrode 15, a part of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 on the other end (or upper end) of the light emitting element LD may be exposed.

[0088] In an embodiment of the present disclosure, the first semiconductor layer 11 may be disposed in the core (i.e., the central (or middle) portion) of the light emitting element LD. The light emitting element LD may have a shape corresponding to the shape of the first semiconductor layer 11. For example, if the first semiconductor layer 11 has a hexagonal pyramid shape, the light emitting element LD and the emission pattern 10 may each also have a hexagonal pyramid shape.

[0089] The active layer 12 may be disposed and / or formed to surround an outer peripheral surface of the first semiconductor layer 11 in the longitudinal direction of the light emitting element LD. Specifically, the active layer 12 may be disposed and / or formed to surround a region portion of the first semiconductor layer 11 except for the lower end of the opposite ends of the first semiconductor layer 11 in the longitudinal direction of the light emitting element LD.

[0090] The second semiconductor layer 13 may be provided and / or formed to surround the active layer 12 in the longitudinal direction of the light-emitting element LD, and may include a semiconductor layer having a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0091] In an embodiment of the present disclosure, the light-emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode or a Schottky contact electrode electrically connected to the second semiconductor layer 13, but the present disclosure is not limited thereto.

[0092] As described above, the light-emitting element LD may have a hexagonal pyramid shape with opposite ends protruding outward, and may be implemented as an emission pattern 10 having a core-shell structure, which includes a first semiconductor layer 11 provided in its central portion, an active layer 12 surrounding the first semiconductor layer 11, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 may be provided at one end (or the lower end) of the light-emitting element LD having a hexagonal pyramid shape, and the additional electrode 15 may be provided at the other end (or the upper end) of the light-emitting element LD.

[0093] In an embodiment, the light-emitting element LD may further include an insulating layer 14 provided on the outer peripheral surface of the emission pattern 10 having a core-shell structure. The insulating layer 14 may include a transparent insulating material.

[0094] Figure 5 A display device according to an embodiment of the present disclosure is shown, and in particular, is a schematic plan view of a display device using any one of the light-emitting elements shown in Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a and Figure 4b as a light source.

[0095] For the sake of explanation, Figure 5 the structure of the display device is schematically shown focusing on the display area DA where an image is displayed. In some embodiments, although not shown in the drawings, at least one driving circuit (e.g., a scan driver and a data driver) and / or a plurality of lines may also be provided in the display device.

[0096] Referring to Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a, Figure 4b and Figure 5 , a display device according to an embodiment of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB, a driver (not shown) disposed on the substrate SUB and configured to drive the pixels PXL, and a line assembly (not shown) connecting the pixels PXL to the driver, and each of the pixels PXL includes at least one light-emitting element LD.

[0097] According to the method of driving the light-emitting element LD, the display device may be classified into a passive matrix type display device and an active matrix type display device. For example, in the case where the display device is of the active matrix type, each of the pixels PXL may include a driving transistor that controls the amount of current supplied to the light-emitting element LD and a switching transistor that transmits a data signal to the driving transistor.

[0098] Recently, considering resolution, contrast, and operating speed, an active matrix type display device capable of selectively turning on each pixel PXL has become mainstream. However, the present disclosure is not limited thereto. For example, a passive matrix type display device in which the pixels PXL can be turned on in groups may also employ components (e.g., a first electrode and a second electrode) for driving the light-emitting element LD.

[0099] The substrate SUB may include a display area DA and a non-display area NDA.

[0100] In an embodiment, the display area DA may be disposed in a central portion of the display device, and the non-display area NDA may be disposed in a peripheral portion of the display device so as to surround the display area DA. The positions of the display area DA and the non-display area NDA are not limited thereto, and their positions may be changed.

[0101] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which some of the driver for driving the pixels PXL and the line assembly for connecting the pixels PXL to the driver are disposed.

[0102] The display area DA may have various shapes. For example, the display area DA may be set to a closed polygon shape including linear sides. As another example, the display area DA may be set to a circular and / or elliptical shape including curved sides. As still another example, the display area DA may be set to various shapes such as a semi-circular shape and a semi-elliptical shape including linear sides and curved sides.

[0103] The non-display area NDA may be disposed on at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the periphery (or edge) of the display area DA.

[0104] The substrate SUB may include a transparent insulating material that allows light transmission.

[0105] The substrate SUB may be a rigid substrate. For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0106] The substrate SUB may be a flexible substrate. Here, the flexible substrate may be a film substrate or a plastic substrate including a polymer organic material. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0107] However, the material constituting the substrate SUB may be changed and may include, for example, fiber-reinforced plastic (FRP).

[0108] A portion of the substrate SUB may be set as a display area DA where pixels PXL are provided, and the remaining portion of the substrate SUB may be set as a non-display area NDA. For example, the substrate SUB may include a display area DA and a non-display area NDA provided around the display area DA, and the display area DA includes a plurality of pixel areas where corresponding pixels PXL are formed.

[0109] The pixels PXL may be provided in the display area DA on the substrate SUB. In an embodiment of the present disclosure, the pixels PXL may be arranged in a stripe or PenTile arrangement structure in the display area DA, but the present disclosure is not limited thereto.

[0110] Each of the pixels PXL may include at least one light-emitting element LD configured to be driven in response to a corresponding scan signal and a corresponding data signal. The light-emitting element LD may have a small size corresponding to the micron or nanometer scale and may be connected in parallel with the light-emitting element LD provided adjacent thereto, but the present disclosure is not limited thereto. The light-emitting element LD may form a light source for each pixel PXL.

[0111] Each of the pixels PXL may include at least one light source driven by a predetermined signal (e.g., a scan signal and a data signal) and / or a predetermined power supply (e.g., a first driving power supply and a second driving power supply). For example, each of the pixels PXL may include Figures 1a to 4b the light-emitting element LD shown in each of the embodiments of, for example, at least one ultra-small light-emitting element LD having a small size corresponding to the nanometer or micron scale. However, in the embodiments of the present disclosure, the type of the light-emitting element LD that can be used as a light source for each of the pixels PXL is not limited thereto.

[0112] In an embodiment of the present disclosure, the color, type, and / or number of the pixels PXL are not particularly limited. For example, the color of the light emitted from each pixel PXL can be changed in various ways.

[0113] The driver can provide a predetermined signal and a predetermined power voltage to each of the pixels PXL through a line assembly, and thus control the operation of the pixels PXL. For the sake of explanation, in Figure 5 the line assembly is omitted.

[0114] The driver may include: a scan driver configured to provide a scan signal to the pixels PXL through scan lines; an emission driver configured to provide an emission control signal to the pixels PXL through emission control lines; a data driver configured to provide a data signal to the pixels PXL through data lines; and a timing controller. The timing controller can control the scan driver, the emission driver, and the data driver.

[0115] Figures 6a to 6e is a diagram showing Figure 5 equivalent circuits of various embodiments of the electrical connection relationships of the components included in the pixels shown in

[0116] For example, Figures 6a to 6e shows different embodiments of the electrical connection relationships of the components included in the pixel PXL that can be adopted in an active display device. However, the types of the components included in the pixel PXL to which the embodiments of the present disclosure can be applied are not limited thereto.

[0117] As Figures 6a to 6e shown, not only Figure 5 the components included in each of the pixels PXL shown in Figures 6a to 6e but also the regions where the components are provided are included in the definition of the term "pixel PXL". In an embodiment, Figure 5 each pixel PXL shown in

[0118] can be any one of the pixels PXL provided in the display device of Figures 1a to 4b , Figure 5 and Figures 6a to 6e The pixels (PXL, hereinafter referred to as "pixels") can each include an emission unit EMU configured to generate light having a luminance corresponding to a data signal. The pixel PXL may also selectively include a pixel circuit 144 configured to drive the emission unit EMU.

[0119] In an embodiment, the emission unit EMU may include a plurality of light-emitting elements LD connected in parallel between a first power line PL1 to which a first driving power supply VDD is applied and a second power line PL2 to which a second driving power supply VSS is applied. For example, the emission unit EMU may include a first electrode EL1 (or “first alignment electrode”) connected to the first driving power supply VDD via a pixel circuit 144 and the first power line PL1, a second electrode EL2 (or “second alignment electrode”) connected to the second driving power supply VSS via the second power line PL2, and a plurality of light-emitting elements LD connected in parallel to each other in the same direction between the first electrode EL1 and the second electrode EL2. In an embodiment of the present disclosure, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

[0120] In an embodiment of the present disclosure, each of the light-emitting elements LD included in the emission unit EMU may include a first end connected to the first driving power supply VDD through the first electrode EL1 and a second end connected to the second driving power supply VSS through the second electrode EL2. The first driving power supply VDD and the second driving power supply VSS may have different potentials. For example, the first driving power supply VDD may be set as a high-potential power supply, and the second driving power supply VSS may be set as a low-potential power supply. Here, the potential difference between the first driving power supply VDD and the second driving power supply VSS may be set to be equal to or greater than the value of the threshold voltage of the light-emitting element LD during the light-emitting period of the pixel PXL.

[0121] As described above, the light-emitting elements LD connected in parallel to each other in the same direction (e.g., in the forward direction) between the first electrode EL1 and the second electrode EL2 may form corresponding effective light sources, where voltages having different potentials are respectively supplied to the first electrode EL1 and the second electrode EL2. The effective light sources may jointly form the emission unit EMU of the pixel PXL.

[0122] The light-emitting elements LD of the emission unit EMU may emit light having a brightness corresponding to the driving current supplied thereto through the pixel circuit 144. For example, during each frame period, the pixel circuit 144 may supply a driving current corresponding to the gray-scale value of the corresponding frame data to the emission unit EMU. The driving current supplied to the emission unit EMU may be divided and flow into the light-emitting elements LD connected to each other in the same direction. Therefore, each of the light-emitting elements LD may emit light having a brightness corresponding to the current applied thereto, such that the emission unit EMU may emit light having a brightness corresponding to the driving current.

[0123] Although Figures 6a to 6eAn embodiment is shown in which the light-emitting elements LD are connected to each other in the same direction between the first driving power supply VDD and the second driving power supply VSS, but the present disclosure is not limited thereto. In the embodiment, in addition to the light-emitting elements LD forming the corresponding effective light sources, the emission unit EMU may further include at least one ineffective light source. For example, as Figure 6d and Figure 6e shown, at least one reverse light-emitting element LDr may also be connected between the first electrode EL1 and the second electrode EL2 of the emission unit EMU. The reverse light-emitting element LDr may be connected in parallel with the light-emitting elements LD forming the effective light sources between the first electrode EL1 and the second electrode EL2. Here, the reverse light-emitting element LDr may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to that of the light-emitting element LD. Even when a predetermined driving voltage (e.g., a driving voltage in the forward direction) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element LDr remains disabled. Therefore, current substantially does not flow through the reverse light-emitting element LDr.

[0124] The pixel circuit 144 may be connected to the scan line (e.g., the i-th scan line Si) and the data line (e.g., the j-th data line Dj) corresponding to the pixel PXL. For example, if the pixel PXL is disposed in the i-th row (where i is a positive integer) and the j-th column (where j is a positive integer) of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. In the embodiment, as Figure 6a and Figure 6b shown, the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst. The structure of the pixel circuit 144 is not limited to the embodiment shown in Figure 6a and Figure 6b shown.

[0125] First, referring to Figure 6a , the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0126] The first terminal of the second transistor (T2; switching transistor) may be connected to the data line (e.g., the j-th data line Dj), and its second terminal may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 are different terminals, and for example, if the first terminal is the source electrode and the second terminal is the drain electrode. The gate electrode of the second transistor T2 may be connected to the scan line (e.g., the i-th scan line Si).

[0127] When a scan signal that provides a voltage (e.g., a low-level voltage) capable of turning on the second transistor T2 is supplied from a scan line (e.g., the i-th scan line Si), the second transistor T2 turns on to electrically connect the data line (e.g., the j-th data line Dj) to the first node N1. Here, a data signal corresponding to a corresponding frame is supplied to the data line (e.g., the j-th data line Dj), and thus, the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 can charge the storage capacitor Cst.

[0128] The first terminal of the first transistor (T1; driving transistor) may be connected to the first driving power supply VDD, and its second terminal may be electrically connected to the first electrode EL1 of the light-emitting element LD. The gate electrode of the first transistor T1 may be connected to the first node N1. Therefore, the first transistor T1 can control the amount of driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0129] One electrode of the storage capacitor Cst may be connected to the first driving power supply VDD, and its other electrode may be connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to the data signal supplied to the first node N1 and holds the charged voltage until a data signal of a subsequent frame is supplied thereto.

[0130] Figure 6a and Figure 6b Each shows a pixel circuit 144 including a second transistor T2 configured to transmit a data signal to a pixel PXL, a storage capacitor Cst configured to store the data signal, and a first transistor T1 configured to supply a driving current corresponding to the data signal to the light-emitting element LD.

[0131] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 can be changed in various ways. For example, the pixel circuit 144 may further include at least one transistor element (such as a transistor element configured to compensate for the threshold voltage of the first transistor T1, a transistor element configured to initialize the first node N1, and / or a transistor element configured to control the light-emitting time of the light-emitting element LD) or other circuit elements (such as a boosting capacitor for increasing the voltage of the first node N1).

[0132] In addition, although Figure 6a it is shown that the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are formed of P-type transistors, the present disclosure is not limited thereto. In other words, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0133] Reference Figures 1a to 4b 、 Figure 5 andFigure 6b , according to an embodiment of the present disclosure, the first transistor T1 and the second transistor T2 may be formed of N-type transistors. Except for some changes in the connection positions of components due to the change in the type of transistors, Figure 6b the configuration and operation of the pixel circuit 144 shown in Figure 6a are similar to the configuration and operation of the pixel circuit 144 of

[0134] In an embodiment of the present disclosure, Figure 6b the pixel circuit 144 shown in Figure 6b may include a storage capacitor Cst and a first transistor T1 and a second transistor T2 formed of N-type transistors. In the case where the first transistor T1 and the second transistor T2 are formed of N-type transistors, the emission unit EMU may be connected between the first driving power supply VDD and the pixel circuit 144 to ensure the stabilization of the storage capacitor Cst, and the storage capacitor Cst is configured to be charged with a voltage corresponding to the data signal provided to the first node N1. Here, the present disclosure is not limited thereto. In an embodiment, Figure 6a the emission unit EMU shown in Figure 6a and Figure 6b may be connected between the pixel circuit 144 and the second driving power supply VSS. In an embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figure 6a and Figure 6b the embodiments shown in Figure 6c and Figure 6d For example, the pixel circuit 144 may be configured in the same manner as the pixel circuit 144 of the embodiments shown in Figure 6c and Figure 6d

[0135] As shown in Figure 6c and Figure 6d , the pixel circuit 144 may be connected to the scan line (e.g., the i-th scan line Si) and the data line (e.g., the j-th data line Dj) of the pixel PXL. For example, if the pixel PXL is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0136] In an embodiment, the pixel circuit 144 may also be connected to at least another scan line. For example, the pixel PXL disposed in the i-th row of the display area DA may also be connected to the (i - 1)-th scan line Si-1 and / or the (i + 1)-th scan line Si+1. In an embodiment, the pixel circuit 144 may be connected not only to the first driving power supply VDD and the second driving power supply VSS, but also to a third power supply. For example, the pixel circuit 144 may also be connected to the initialization power supply Vint.

[0137] The pixel circuit 144 may include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0138] One electrode (e.g., the source electrode) of the first transistor (T1; driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and its other electrode (e.g., the drain electrode) can be connected to one end of the light-emitting element LD via the sixth transistor T6. The gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 can control the driving current flowing through the light-emitting element LD between the first driving power supply VDD and the second driving power supply VSS in response to the voltage of the first node N1.

[0139] The second transistor (T2; switching transistor) can be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. The gate electrode of the second transistor T2 can be connected to the i-th scan line Si connected to the pixel PXL. When a scan signal having a gate conduction voltage (e.g., a low-level voltage) is provided from the i-th scan line Si, the second transistor T2 can be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, if the second transistor T2 is turned on, the data signal provided from the j-th data line Dj can be transmitted to the first transistor T1.

[0140] The third transistor T3 can be connected between the drain electrode of the first transistor T1 and the first node N1. The gate electrode of the third transistor T3 can be connected to the i-th scan line Si. When a scan signal having a gate conduction voltage is provided from the i-th scan line Si, the third transistor T3 can be turned on to electrically connect the drain electrode of the first transistor T1 to the first node N1.

[0141] The fourth transistor T4 can be connected between the first node N1 and the initialization power line IPL to which the initialization power supply Vint is to be applied. The gate electrode of the fourth transistor T4 can be connected to the previous scan line, e.g., the (i - 1)-th scan line Si-1. When a scan signal having a gate conduction voltage is provided to the (i - 1)-th scan line Si-1, the fourth transistor T4 can be turned on so that the voltage of the initialization power supply Vint can be transmitted to the first node N1. Here, the initialization power supply Vint can have a voltage equal to or less than the minimum voltage of the data signal.

[0142] The fifth transistor T5 can be connected between the first driving power supply VDD and the first transistor T1. The gate electrode of the fifth transistor T5 can be connected to the corresponding emission control line, e.g., the i-th emission control line Ei. The fifth transistor T5 can be turned off when an emission control signal having a gate cut-off voltage is provided to the i-th emission control line Ei, and can be turned on in other cases.

[0143] The sixth transistor T6 may be connected between the first transistor T1 and the first end of the light-emitting element LD (which is connected to the second node N2 connected to the seventh transistor T7). The gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate cut-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0144] The seventh transistor T7 may be connected between the initialization power line IPL and the first end of the light-emitting element LD. The gate electrode of the seventh transistor T7 may be connected to any one of the scan lines in the subsequent group, for example, connected to the (i + 1)-th scan line Si+1. When a scan signal having a gate conduction voltage is supplied to the (i + 1)-th scan line Si+1, the seventh transistor T7 may be turned on, so that the voltage of the initialization power supply Vint may be supplied to the first end of the light-emitting element LD.

[0145] The storage capacitor Cst may be connected between the first driving power supply VDD and the first node N1. The storage capacitor Cst may store a voltage corresponding to both the data signal applied to the first node N1 and the threshold voltage of the first transistor T1 during each frame period.

[0146] Although it is shown in Figure 6c and Figure 6d that the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit 144 are formed of P-type transistors, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an N-type transistor.

[0147] In an embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to the Figures 6a to 6d embodiment shown in Figure 6e . For example, the pixel circuit 144 may be configured in the same manner as the pixel circuit 144 in the

[0148] As shown in Figure 6e , the pixel circuit 144 may also be connected to a control line (e.g., the i-th control line CLi) and a sensing line (e.g., the j-th sensing line SENj). For example, the pixel circuit 144 of the pixel PXL provided in the i-th row and the j-th column of the display area DA may be connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA. In addition to the Figure 6a and Figure 6b shown first transistor T1 and second transistor T2, the pixel circuit 144 described above may further include a third transistor T3.

[0149] The third transistor T3 is connected between the first transistor T1 and a sensing line (e.g., the j-th sensing line SENj). For example, one electrode of the third transistor T3 may be connected to a terminal (e.g., a source electrode) of the first transistor T1 connected to the first electrode EL1, and the other electrode of the third transistor T3 may be connected to the sensing line (e.g., the j-th sensing line SENj). In the case where the sensing line (e.g., the j-th sensing line SENj) is omitted, this other electrode of the third transistor T3 may be connected to a data line (e.g., the j-th data line Dj). The capacitor C OLED may be electrically connected between the first electrode EL1 and the second electrode EL2.

[0150] In an embodiment, the gate electrode of the third transistor T3 is connected to a control line (e.g., the i-th control line CLi). In the case where the control line (e.g., the i-th control line CLi) is omitted, the gate electrode of the third transistor T3 may be connected to a scan line (e.g., the i-th scan line Si). The third transistor T3 may be turned on by a control signal having a gate turn-on voltage (e.g., a high-level voltage) and is supplied to the control line (e.g., the i-th control line CLi) during a predetermined sensing period, so that the sensing line (e.g., the j-th sensing line SENj) and the second transistor T2 can be electrically connected to each other.

[0151] In an embodiment, the sensing period may be a period in which characteristic information (e.g., the threshold voltage of the first transistor T1, etc.) of each of the pixels PXL provided in the display area DA is extracted. During the above sensing period, the first transistor T1 may be turned on by supplying a predetermined reference voltage capable of turning on the first transistor T1 to the first node N1 via the data line (e.g., the j-th data line Dj) and the second transistor T2 or connecting each pixel PXL to a current source, etc. In addition, the third transistor T3 may be turned on by supplying a control signal having a gate turn-on voltage to the third transistor T3, so that the first transistor T1 can be connected to the sensing line (e.g., the j-th sensing line SENj). Therefore, the characteristic information of each pixel PXL (including the threshold voltage of the first transistor T1, etc.) can be extracted through the sensing line (e.g., the j-th sensing line SENj). The extracted characteristic information may be used to convert image data to compensate for the characteristic deviation between the pixels PXL.

[0152] Although Figure 6e an embodiment in which all of the first transistor T1 to the third transistor T3 are N-type transistors is shown, the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 may be changed to a P-type transistor. In addition, although Figure 6eAn embodiment is shown in which the emission unit EMU is connected between the pixel circuit 144 and the second driving power supply VSS. However, the emission unit EMU can be connected between the first driving power supply VDD and the pixel circuit 144.

[0153] Although Figures 6a to 6e an embodiment is shown in which all the light-emitting elements LD of each emission unit EMU are connected in parallel with each other, the present disclosure is not limited thereto. In an embodiment, the emission unit EMU may include at least one series group including a plurality of light-emitting elements LD connected in parallel with each other. In other words, the emission unit EMU may be formed of a series / parallel combination structure. The foregoing configuration will be described below with reference to Figures 7a to 7c describe the foregoing configuration.

[0154] The structure of the pixel PXL that can be applied to the present disclosure is not limited to Figures 6a to 6e the embodiment shown in, and the corresponding pixel PXL may have various structures. In an embodiment of the present disclosure, each pixel PXL may be configured in a passive light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and the opposite ends of the light-emitting elements LD included in the emission unit EMU may be directly connected to a predetermined control line, scan lines Si-1, Si, and Si+1, a data line (e.g., the j-th data line Dj), a first power line PL1 to which the first driving power supply VDD is to be applied, and / or a second power line PL2 to which the second driving power supply VSS is to be applied.

[0155] Figures 7a to 7c is a diagram showing an equivalent circuit of different embodiments of the electrical connection relationship of the components included in one pixel shown in Figure 5 As shown in Figures 7a to 7c each emission unit EMU of each pixel PXL may be configured to include a plurality of series groups connected continuously to each other. In the following description of the embodiment of Figures 7a to 7c the detailed explanation of the components similar or identical to those of the embodiment of Figures 6a to 6e will be omitted (e.g., the detailed explanation of the pixel circuit 144 will be omitted) to avoid redundant explanation.

[0156] First, with reference to Figure 7a, the emitting unit EMU may include a plurality of light-emitting elements LD connected in series with each other. For example, the emitting unit EMU may include a first light-emitting element LD1, a second light-emitting element LD2, a third light-emitting element LD3, and a fourth light-emitting element LD4 connected in series in a forward direction between a first driving power supply VDD and a second driving power supply VSS, and thus form an effective light source. In the following embodiments, the term "one light-emitting element LD" or "a plurality of light-emitting elements LD" will be used to arbitrarily specify one light-emitting element among the first light-emitting element LD1 to the fourth light-emitting element LD4, or to collectively specify the first light-emitting element LD1 to the fourth light-emitting element LD4.

[0157] One end of the first light-emitting element LD1 (e.g., the second semiconductor layer) may be connected to the first driving power supply VDD through the first electrode EL1, and the other end of the first light-emitting element LD1 (e.g., the first semiconductor layer) may be connected to one end of the second light-emitting element LD2 (e.g., the second semiconductor layer) through the first intermediate electrode CTE1 connected between the first series group and the second series group.

[0158] One end of the second light-emitting element LD2 may be connected to the first intermediate electrode CTE1, and the other end of the second light-emitting element LD2 (e.g., the first semiconductor layer) may be connected to one end of the third light-emitting element LD3 (e.g., the second semiconductor layer) through the second intermediate electrode CTE2 connected between the second series group and the third series group.

[0159] One end of the third light-emitting element LD3 may be connected to the second intermediate electrode CTE2, and the other end of the third light-emitting element LD3 (e.g., the first semiconductor layer) may be connected to one end of the fourth light-emitting element LD4 (e.g., the second semiconductor layer) through the third intermediate electrode CTE3 connected between the third series group and the fourth series group.

[0160] One end of the fourth light-emitting element LD4 may be connected to the third intermediate electrode CTE3, and the other end of the fourth light-emitting element LD4 (e.g., the first semiconductor layer) may be connected to the second driving power supply VSS through the second electrode EL2.

[0161] As described above, the first light-emitting element LD1 to the fourth light-emitting element LD4 may be connected in series between the first electrode EL1 and the second electrode EL2 of the emitting unit EMU of the pixel PXL.

[0162] In the case of the emission unit EMU having a structure in which the light-emitting elements LD are connected in series with each other, compared with the case of the emission unit EMU having a structure in which the light-emitting elements LD are connected in parallel with each other, the voltage applied between the first electrode EL1 and the second electrode EL2 can be increased, and the amount of drive current flowing through the emission unit EMU can be reduced. Therefore, in the case where the emission unit EMU of each pixel PXL has a series structure, the power consumption of the display device can be reduced.

[0163] In an embodiment, at least one series group may be provided in a form including a plurality of light-emitting elements LD connected in parallel with each other. In this case, the emission unit EMU of each pixel PXL may be formed of a series / parallel combination structure. For example, the emission unit EMU may be configured as shown in Figure 7b and Figure 7c as shown.

[0164] Next, referring to Figure 7b and Figure 7c , the emission unit EMU of the pixel PXL may include a plurality of series groups connected continuously between the first drive power source VDD and the second drive power source VSS. Each of the series groups may include one or more light-emitting elements LD connected in a forward direction between two sub-electrodes of the corresponding series group.

[0165] The emission unit EMU may include a first series group SET1 to a third series group SET3 connected continuously between the first drive power source VDD and the second drive power source VSS.

[0166] The first series group SET1 may include at least one first light-emitting element LD1 connected between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1. For example, the first series group SET1 may include a 1-1 sub-electrode SEL1_1 connected to the first drive power source VDD via the pixel circuit 144, a 2-1 sub-electrode SEL2_1 connected to the second drive power source VSS, and a plurality of first light-emitting elements LD1 connected between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1. One end (e.g., the second semiconductor layer) of each first light-emitting element LD1 may be electrically connected to the 1-1 sub-electrode SEL1_1 of the first series group SET1, and the other end (e.g., the first semiconductor layer) may be electrically connected to the 2-1 sub-electrode SEL2_1 of the first series group SET1. The first light-emitting elements LD1 may be connected in parallel between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1 of the first series group SET1, and are connected between the first drive power source VDD and the second drive power source VSS in the same direction (e.g., in a forward direction) through the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1. In an embodiment, asFigure 7c As shown, at least a reverse light-emitting element LDr may be connected between the first sub-electrode SEL1_1 and the second sub-electrode SEL2_1. The reverse light-emitting element LDr and the first light-emitting element LD1 forming an effective light source may be connected in parallel between the first sub-electrode SEL1_1 and the second sub-electrode SEL2_1. The reverse light-emitting element LDr may be connected between the first sub-electrode SEL1_1 and the second sub-electrode SEL2_1 in a direction opposite to that of the first light-emitting element LD1. For example, the first semiconductor layer of the reverse light-emitting element LDr may be electrically connected to the first sub-electrode SEL1_1, and its second semiconductor layer may be electrically connected to the second sub-electrode SEL2_1. Even when a predetermined driving voltage (e.g., a forward driving voltage) is applied between the first sub-electrode SEL1_1 and the second sub-electrode SEL2_1, the reverse light-emitting element LDr remains disabled. Therefore, current substantially does not flow through the reverse light-emitting element LDr.

[0167] The second series group SET2 may include at least one second light-emitting element LD2 connected between the first sub-electrode SEL1_2 and the second sub-electrode SEL2_2. For example, the second series group SET2 may include the first sub-electrode SEL1_2 connected to the first driving power supply VDD via the pixel circuit 144 and the first series group SET1, the second sub-electrode SEL2_2 connected to the second driving power supply VSS, and a plurality of second light-emitting elements LD2 connected between the first sub-electrode SEL1_2 and the second sub-electrode SEL2_2. One end (e.g., the second semiconductor layer) of each second light-emitting element LD2 may be electrically connected to the first sub-electrode SEL1_2 of the second series group SET2, and the other end (e.g., the first semiconductor layer) may be electrically connected to the second sub-electrode SEL2_2 of the second series group SET2. The second light-emitting elements LD2 may be connected in parallel between the first sub-electrode SEL1_2 and the second sub-electrode SEL2_2 of the second series group SET2, and are connected between the first driving power supply VDD and the second driving power supply VSS in the same direction (e.g., in the forward direction) through the first sub-electrode SEL1_2 and the second sub-electrode SEL2_2. In an embodiment, as Figure 7cAs shown, at least one reverse light-emitting element LDr may also be connected between the first-second sub-electrode SEL1_2 and the second-second sub-electrode SEL2_2. The reverse light-emitting element LDr and the second light-emitting element LD2 forming an effective light source may be connected in parallel between the first-second sub-electrode SEL1_2 and the second-second sub-electrode SEL2_2. The reverse light-emitting element LDr may be connected between the first-second sub-electrode SEL1_2 and the second-second sub-electrode SEL2_2 in a direction opposite to that of the second light-emitting element LD2. For example, the first semiconductor layer of the reverse light-emitting element LDr may be connected to the first-second sub-electrode SEL1_2, and its second semiconductor layer may be connected to the second-second sub-electrode SEL2_2.

[0168] The third series group SET3 may include at least one third light-emitting element LD3 connected between the first-third sub-electrode SEL1_3 and the second-third sub-electrode SEL2_3. For example, the third series group SET3 may include a first-third sub-electrode SEL1_3 connected to the first driving power supply VDD via the pixel circuit 144 and a previous series group (e.g., the first series group SET1 and the second series group SET2), a second-third sub-electrode SEL2_3 connected to the second driving power supply VSS, and a plurality of third light-emitting elements LD3 connected between the first-third sub-electrode SEL1_3 and the second-third sub-electrode SEL2_3. One end (e.g., the second semiconductor layer) of each third light-emitting element LD3 may be electrically connected to the first-third sub-electrode SEL1_3 of the third series group SET3, and its other end (e.g., the first semiconductor layer) may be electrically connected to the second-third sub-electrode SEL2_3 of the third series group SET3. The third light-emitting elements LD3 may be connected in parallel between the first-third sub-electrode SEL1_3 and the second-third sub-electrode SEL2_3 of the third series group SET3, and are connected between the first driving power supply VDD and the second driving power supply VSS in the same direction (e.g., in the forward direction) through the first-third sub-electrode SEL1_3 and the second-third sub-electrode SEL2_3. In an embodiment, as Figure 7c As shown, at least a reverse light-emitting element LDr may also be connected between the first-third sub-electrode SEL1_3 and the second-third sub-electrode SEL2_3. The reverse light-emitting element LDr and the third light-emitting element LD3 forming an effective light source may be connected in parallel between the first-third sub-electrode SEL1_3 and the second-third sub-electrode SEL2_3. The reverse light-emitting element LDr may be connected between the first-third sub-electrode SEL1_3 and the second-third sub-electrode SEL2_3 in a direction opposite to that of the third light-emitting element LD3. For example, the first semiconductor layer of the reverse light-emitting element LDr may be connected to the first-third sub-electrode SEL1_3, and its second semiconductor layer may be connected to the second-third sub-electrode SEL2_3.

[0169] In the foregoing embodiment, the 1-1 sub-electrode SEL1_1 of the first series group SET1 may be the anode electrode of the emission unit EMU of each pixel PXL. The 2-3 sub-electrode SEL2_3 of the third series group SET3 may be the cathode electrode of the emission unit EMU.

[0170] In addition, the emission unit EMU may include a plurality of intermediate electrodes configured to electrically connect consecutive series groups of the first series group SET1 to the third series group SET3. For example, the emission unit EMU may include a first intermediate electrode CTE1 disposed between the first series group SET1 and the second series group SET2 and a second intermediate electrode CTE2 disposed between the second series group SET2 and the third series group SET3.

[0171] The first series group SET1 and the second series group SET2 may be electrically connected to each other through the first intermediate electrode CTE1. For example, the 2-1 sub-electrode SEL2_1 of the first series group SET1 may be connected to the first intermediate electrode CTE1, and the 1-2 sub-electrode SEL1_2 of the second series group SET2 may be connected to the first intermediate electrode CTE1. The second series group SET2 and the third series group SET3 may be connected to each other through the second intermediate electrode CTE2. For example, the 2-2 sub-electrode SEL2_2 of the second series group SET2 may be connected to the second intermediate electrode CTE2, and the 1-3 sub-electrode SEL1_3 of the third series group SET3 may be connected to the second intermediate electrode CTE2.

[0172] As described above, in the emission unit EMU of the pixel PXL including the light-emitting elements LD connected to each other in a series or parallel combination structure, the drive current / voltage conditions can be easily adjusted in response to the specifications of the product to which the emission unit EMU is applied.

[0173] Specifically, in the emission unit EMU of the pixel PXL including light-emitting elements LD connected to each other in a series / parallel combination structure, its drive current can be reduced compared to the drive current of the emission unit EMU including light-emitting elements LD connected in parallel to each other. In addition, in the emission unit EMU of the pixel PXL including light-emitting elements LD connected to each other in a series / parallel combination structure, the drive voltage applied to the opposite ends of the emission unit EMU can be reduced compared to the drive voltage of the emission unit EMU including all light-emitting elements LD connected in series to each other. In the case where all the light-emitting elements LD are only connected in series, if at least one of the light-emitting elements LD connected in series does not face completely in the forward direction (or includes a reverse light-emitting element LDr), a dark spot defect may occur in the case where the path along which the drive current can flow in the pixel PXL is blocked. On the other hand, in the case where the light-emitting elements LD are connected to each other in a series / parallel combination structure, even if some of the light-emitting elements LD in each series group are not correctly connected in the forward direction (or include a reverse light-emitting element LDr) or defects occur in some of the light-emitting elements LD, the drive current is allowed to flow through the other light-emitting elements LD of the corresponding series group. Therefore, defects in the pixel PXL can be prevented or reduced.

[0174] Figure 8 schematically shows Figure 5 a plan view of one of the pixels shown in Figure 9 is a cross-sectional view taken along Figure 8 line I-I' of Figure 10 is a cross-sectional view taken along Figure 8 line II-II' of Figure 11 shows a display device including first to third conductive patterns connected to first to third bridging patterns shown in Figure 9 and is a cross-sectional view corresponding to line I-I' of Figure 8

[0175] Figure 8 The pixel PXL shown in Figures 6a to 6e and Figures 7a to 7c can be any one of the pixels PXL shown in Figure 8 For example, the pixel PXL shown in Figure 7b and / or Figure 7c the pixel PXL shown in

[0176] For explanatory purposes, the illustration of the transistor connected to the light-emitting element LD and the signal line connected to the transistor is omitted in Figure 8

[0177] Although Figures 8 to 11 ​​Simplified illustration shows the structure of pixel PXL. For example, it shows that each electrode is formed of a single electrode layer and each insulating layer is formed of a single insulating layer, but the present disclosure is not limited thereto.

[0178] In addition, in the description of the embodiments of the present disclosure, "components are disposed and / or formed on the same layer" may mean that the components are formed by the same process, and "components are disposed and / or formed on different layers" may mean that the components are formed by different processes.

[0179] Reference Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c and Figures 8 to 11 According to the embodiments of the present disclosure, a display device may include a substrate SUB, a line component, and a plurality of pixels PXL.

[0180] The substrate SUB may include a transparent insulating material that allows light to pass through. The substrate SUB may be a rigid substrate or a flexible substrate. The material applied to the substrate SUB may be resistant to high processing temperatures (heat resistance) during the process of manufacturing the display device. The substrate SUB may include a display area DA and a non-display area NDA disposed around the display area DA. The display area DA includes at least one pixel area PXA in which the pixels PXL are disposed.

[0181] In an embodiment, the pixels PXL may be arranged in a matrix shape and / or a stripe shape along a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 intersecting the first direction DR1 in the display area DA, but the present disclosure is not limited thereto. In an embodiment, the pixels PXL may be disposed on the substrate SUB in various arrangements in the display area DA.

[0182] The pixel area PXA in which each pixel PXL is disposed may include an emission area EMA that emits light therefrom and a peripheral area surrounding the periphery of the emission area EMA. In the embodiments of the present disclosure, the term "peripheral area" may include a non-emission area from which no light is emitted. In the embodiments of the present disclosure, the pixel area PXA in which each pixel PXL is disposed may include a first area A1, a second area A2, and a third area A3 that are separated from each other in one direction (for example, the second direction DR2). Each of the first area A1, the second area A2, and the third area A3 may include an emission area EMA and a peripheral area surrounding the periphery of the emission area EMA.

[0183] Each pixel PXL may include a substrate SUB, a pixel circuit layer PCL in which a pixel circuit 144 is disposed (or formed), and a display element layer DPL in which at least one light-emitting element LD is disposed. The display element layer DPL may be disposed in an emission region EMA of each of a first region A1, a second region A2, and a third region A3 of a pixel region PXA.

[0184] The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit 144 including at least one transistor T, a driving voltage line DVL, and a passivation layer PSV.

[0185] The buffer layer BFL may prevent impurities from diffusing into the transistor T. The buffer layer BFL may include an inorganic insulating layer formed of an inorganic material. For example, the buffer layer BFL may include silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and at least one of metal oxides (such as, AlO x ). Although the buffer layer BFL may be provided as a single-layer structure, the buffer layer BFL may be provided as a multi-layer structure having two or more layers. In the case where the buffer layer BFL has a multi-layer structure, each layer may be formed of the same material or different materials. Depending on the material or processing conditions of the substrate SUB, the buffer layer BFL may be omitted.

[0186] The transistor T may include a first transistor T1 and a second transistor T2. The first transistor T1 is a driving transistor for controlling the amount of driving current to be supplied to the light-emitting element LD, and the second transistor T2 is a switching transistor. In an embodiment of the present disclosure, the first transistor T1 may be the first transistor T1 of the pixel circuit 144 described with reference to Figure 6a 、 Figure 7b and Figure 7c . The second transistor T2 may be the second transistor T2 of the pixel circuit 144 described with reference to Figure 6a 、 Figure 7b and Figure 7c .

[0187] Each of the first transistor T1 (T) and the second transistor T2 (T) may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be one of a source electrode and a drain electrode, and the second terminal DE may be the other electrode. For example, in the case where the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

[0188] The transistor semiconductor pattern SCL may be disposed and / or formed on the buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact region contacting the first terminal SE and a second contact region contacting the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The transistor semiconductor pattern SCL may be a semiconductor panel formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region may be an intrinsic semiconductor as an undoped semiconductor pattern. Each of the first contact region and the second contact region may be a semiconductor pattern doped with impurities.

[0189] The gate electrode GE may be disposed and / or formed on the transistor semiconductor pattern SCL, and the gate insulating layer GI is interposed between the gate electrode GE and the transistor semiconductor pattern SCL. The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include at least one of silicon nitride (SiN x )), silicon oxide (SiO x ), silicon oxynitride (SiON), and metal oxide (such as, AlO x ). However, the material of the gate insulating layer GI is not limited to the materials of the foregoing embodiments. In an embodiment, the gate insulating layer GI may be formed of an organic insulating layer including an organic material. Although the gate insulating layer GI may be disposed in a single-layer structure, the gate insulating layer GI may be disposed in a multi-layer structure having two or more layers. The first terminal SE and the second terminal DE may contact the first contact region and the second contact region of the transistor semiconductor pattern SCL through corresponding contact holes passing through the first interlayer insulating layer ILD1 and the gate insulating layer GI, respectively. The first interlayer insulating layer ILD1 may be an inorganic insulating layer including an inorganic material. For example, the first interlayer insulating layer ILD1 may include at least one of silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and metal oxide (such as, AlO x ). The first interlayer insulating layer ILD1 and the gate insulating layer GI may have the same material, but the present disclosure is not limited thereto. Although the first interlayer insulating layer ILD1 may be disposed in a single-layer structure, the first interlayer insulating layer ILD1 may be disposed in a multi-layer structure having two or more layers.

[0190] Although in the foregoing embodiments, the first terminal SE and the second terminal DE of each of the first transistor T1 (T) and the second transistor T2 (T) are separate electrodes electrically connected to the transistor semiconductor pattern SCL, the present disclosure is not limited thereto. In an embodiment, the first terminal SE of each of the first transistor T1 (T) and the second transistor T2 (T) may be one of the first contact region and the second contact region that is adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. The second terminal DE of each of the first transistor T1 (T) and the second transistor T2 (T) may be the other of the first contact region and the second contact region that is adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. In this case, the second terminal DE of each of the first transistor T1 (T) and the second transistor T2 (T) may be electrically connected to the light-emitting element LD of the corresponding pixel PXL through a bridging electrode, a contact electrode, or the like.

[0191] In an embodiment of the present disclosure, the transistor T included in the pixel circuit 144 may be formed of an LTPS thin-film transistor, but the present disclosure is not limited thereto. In some embodiments, the transistor T may be formed of an oxide semiconductor thin-film transistor. In addition, the case where the transistor T is a thin-film transistor having a top-gate structure has been shown, but the present disclosure is not limited thereto. In an embodiment, the transistor T may be a thin-film transistor having a bottom-gate structure.

[0192] The drive voltage line DVL may be provided on the gate insulating layer GI, but the present disclosure is not limited thereto. In some embodiments, the drive voltage line DVL may be provided on any one of the insulating layers included in the pixel circuit layer PCL. The voltage of the second drive power source VSS may be applied to the drive voltage line DVL. In an embodiment of the present disclosure, in the pixel PXL shown in Figure 7b and Figure 7c , the drive voltage line DVL may be the second power line PL2 to which the second drive power source VSS is applied.

[0193] The second interlayer insulating layer ILD2 may be provided on the transistor T. The second interlayer insulating layer ILD2 may cover the transistor T. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In an embodiment, the second interlayer insulating layer ILD2 and the first interlayer insulating layer ILD1 may include the same material, but the present disclosure is not limited thereto. Although the second interlayer insulating layer ILD2 may be provided in a single-layer structure, the first interlayer insulating layer ILD1 may be provided in a multi-layer structure having two or more layers.

[0194] The passivation layer PSV may be provided on the second interlayer insulating layer ILD2. The passivation layer PSV may be provided in the form of an organic insulating layer, an inorganic insulating layer, or a structure including an organic insulating layer provided on an inorganic insulating layer. The inorganic insulating layer may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiON), and metal oxide (such as, AlO x ). The organic insulating layer may include an organic insulating material that allows light to pass therethrough. The organic insulating layer may include at least one of, for example, polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0195] Each of the second interlayer insulating layer ILD2 and the passivation layer PSV may include a first contact hole CH1 that exposes a part of the second terminal DE of the first transistor T1 (T).

[0196] The pixel circuit layer PCL may include a first bridging pattern BRP1 provided (or formed) in the first region A1, a second bridging pattern BRP2 provided (or formed) in the second region A2, and a third bridging pattern BRP3 provided (or formed) in the third region A3.

[0197] The first bridging pattern BRP1 may be provided in the first region A1 of each pixel PXL and have a bar shape extending in the second direction DR2. The first bridging pattern BRP1 may extend to the region (or boundary region) between the first region A1 and the second region A2. In an embodiment, the first bridging pattern BRP1 may extend from the first region A1 of the pixel region PXA to a part of the second region A2 of the pixel region PXA. In an embodiment of the present disclosure, the first bridging pattern BRP1, the first terminal SE, and the second terminal DE of the first transistor T1 (T) may be provided on the same layer and may include the same material. For example, the first bridging pattern BRP1 may be provided and / or formed on the first interlayer insulating layer ILD1.

[0198] The first bridging pattern BRP1 can be electrically connected to some components, such as the 2-1st sub-electrode SEL2_1, provided in the first region A1 included in the display element layer DPL, by continuously passing through the second contact hole CH2 of the second interlayer insulating layer ILD2 and the passivation layer PSV. In addition, the first bridging pattern BRP1 can be electrically connected to some components, such as the first intermediate electrode CTE1, provided in the region between the first region A1 and the second region A2 included in the display element layer DPL, by continuously passing through the third contact hole CH3 of the second interlayer insulating layer ILD2 and the passivation layer PSV. The connection relationship among the first bridging pattern BRP1, the 2-1st sub-electrode SEL2_1, and the first intermediate electrode CTE1 will be described below.

[0199] The second bridging pattern BRP2 can be provided in the second region A2 of each pixel PXL and has a shape extending in the second direction DR2 and bent in the first direction DR1, but the shape of the second bridging pattern BRP2 is not limited thereto. The second bridging pattern BRP2 can extend to the region (or boundary region) between the second region A2 and the third region A3. In an embodiment, the second bridging pattern BRP2 can extend from the second region A2 of the pixel region PXA to a part of the third region A3 of the pixel region PXA. In an embodiment of the present disclosure, the second bridging pattern BRP2 and the first bridging pattern BRP1 can be provided on the same layer and can include the same material. For example, the second bridging pattern BRP2 can be provided and / or formed on the first interlayer insulating layer ILD1.

[0200] The second bridging pattern BRP2 can be electrically connected to the 2-2nd sub-electrode SEL2_2 provided in the second region A2 included in the display element layer DPL by continuously passing through the fifth contact hole CH5 of the second interlayer insulating layer ILD2 and the passivation layer PSV. In addition, the second bridging pattern BRP2 can be electrically connected to some components, such as the second intermediate electrode CTE2, provided in the region between the second region A2 and the third region A3 included in the display element layer DPL, by continuously passing through the sixth contact hole CH6 of the second interlayer insulating layer ILD2 and the passivation layer PSV. The connection relationship among the second bridging pattern BRP2, the 2-2nd sub-electrode SEL2_2, and the second intermediate electrode CTE2 will be described below.

[0201] The third bridging pattern BRP3 can be disposed in the third region A3 of the pixel region PXA and has a shape that extends in the second direction DR2 and is curved in the first direction DR1. However, the shape of the third bridging pattern BRP3 is not limited to the foregoing embodiment. The third bridging pattern BRP3 can extend from the emission region EMA of the third region A3 to the peripheral region formed around the emission region EMA. The third bridging pattern BRP3 can be electrically connected to the 2-3 sub-electrode SEL2_3 disposed in the third region A3 included in the display element layer DPL through the seventh contact hole CH7 that continuously passes through the second interlayer insulating layer ILD2 and the passivation layer PSV. In addition, the third bridging pattern BRP3 can be electrically connected to the driving voltage line DVL(PL2) through the eighth contact hole CH8 that passes through the first interlayer insulating layer ILD1. Since the third bridging pattern BRP3 is electrically connected to the driving voltage line DVL(PL2), the voltage of the second driving power supply VSS applied to the driving voltage line DVL(PL2) can be transmitted to the third bridging pattern BRP3. The connection relationship among the third bridging pattern BRP3, the 2-3 sub-electrode SEL2_3, and the driving voltage line DVL(PL2) will be described below.

[0202] In an embodiment of the present disclosure, the first bridging pattern BRP1, the second bridging pattern BRP2, and the third bridging pattern BRP3 can be disposed at positions spaced apart from each other in corresponding respective regions. For example, the first bridging pattern BRP1 can be spaced apart from the second bridging pattern BRP2 by a predetermined distance therebetween. The second bridging pattern BRP2 can be spaced apart from the third bridging pattern BRP3 by a predetermined distance therebetween.

[0203] In an embodiment, as Figure 11 shown, the pixel circuit layer PCL of each pixel PXL can further include a first conductive pattern CP1, a second conductive pattern CP2, and a third conductive pattern CP3, and a first auxiliary electrode AUX1 and a second auxiliary electrode AUX2 disposed between the second interlayer insulating layer ILD2 and the passivation layer PSV.

[0204] The first conductive pattern CP1 can be disposed between the first bridging pattern BRP1 and the 2-1st sub-electrode SEL2_1 in the first region A1. For example, the first conductive pattern CP1 can be disposed and / or formed on the first bridging pattern BRP1, and the second interlayer insulating layer ILD2 is interposed between the first conductive pattern CP1 and the first bridging pattern BRP1. In other words, the first conductive pattern CP1 can be disposed on the second interlayer insulating layer ILD2 and overlap with the first bridging pattern BRP1. The first conductive pattern CP1 can be electrically connected to the first bridging pattern BRP1 through a second contact hole CH2 that penetrates the second interlayer insulating layer ILD2. The first conductive pattern CP1 can be electrically connected to the 2-1st sub-electrode SEL2_1 through a second contact hole CH2 that penetrates the passivation layer PSV. The first bridging pattern BRP1, the first conductive pattern CP1, and the 2-1st sub-electrode SEL2_1 can be electrically connected to each other. In an embodiment of the present disclosure, the second contact hole CH2 of the second interlayer insulating layer ILD2 and the second contact hole CH2 of the passivation layer PSV can be located in the first region A1 and correspond to each other.

[0205] In the case where the first bridging pattern BRP1 is electrically connected to the first conductive pattern CP1 disposed thereon, the line resistance of the first bridging pattern BRP1 can be reduced, so that distortion of the signal transmitted to the first bridging pattern BRP1 can be prevented.

[0206] The second conductive pattern CP2 can be disposed between the second bridging pattern BRP2 and the 2-2nd sub-electrode SEL2_2 in the second region A2. For example, the second conductive pattern CP2 can be disposed and / or formed on the second bridging pattern BRP2, and the second interlayer insulating layer ILD2 is interposed between the second conductive pattern CP2 and the second bridging pattern BRP2. In other words, the second conductive pattern CP2 can be disposed on the second interlayer insulating layer ILD2 and overlap with the second bridging pattern BRP2. The second conductive pattern CP2 can be electrically connected to the second bridging pattern BRP2 through a fifth contact hole CH5 that penetrates the second interlayer insulating layer ILD2. The second conductive pattern CP2 can be electrically connected to the 2-2nd sub-electrode SEL2_2 through a fifth contact hole CH5 that penetrates the passivation layer PSV. The second bridging pattern BRP2, the second conductive pattern CP2, and the 2-2nd sub-electrode SEL2_2 can be electrically connected to each other. In an embodiment of the present disclosure, the fifth contact hole CH5 of the second interlayer insulating layer ILD2 and the fifth contact hole CH5 of the passivation layer PSV can be located in the second region A2 and correspond to each other.

[0207] In the case where the second bridging pattern BRP2 is electrically connected to the second conductive pattern CP2 disposed thereon, the line resistance of the second bridging pattern BRP2 can be reduced, so that distortion of the signal transmitted to the second bridging pattern BRP2 can be prevented.

[0208] The third conductive pattern CP3 may be disposed between the third bridging pattern BRP3 and the 2-3rd sub-electrode SEL2_3 in the third region A3. For example, the third conductive pattern CP3 may be disposed and / or formed on the third bridging pattern BRP3, and the second interlayer insulating layer ILD2 is interposed between the third conductive pattern CP3 and the third bridging pattern BRP3. In other words, the third conductive pattern CP3 may be disposed on the second interlayer insulating layer ILD2 and overlap with the third bridging pattern BRP3. The third conductive pattern CP3 may be electrically connected to the third bridging pattern BRP3 through a seventh contact hole CH7 passing through the second interlayer insulating layer ILD2. The third conductive pattern CP3 may be electrically connected to the 2-3rd sub-electrode SEL2_3 through a seventh contact hole CH7 passing through the passivation layer PSV. The third bridging pattern BRP3, the third conductive pattern CP3, and the 2-3rd sub-electrode SEL2_3 may be electrically connected to each other. In an embodiment of the present disclosure, the seventh contact hole CH7 of the second interlayer insulating layer ILD2 and the seventh contact hole CH7 of the passivation layer PSV may be located in the third region A3 and correspond to each other.

[0209] In the case where the third bridging pattern BRP3 is electrically connected to the third conductive pattern CP3 disposed thereon, the line resistance of the third bridging pattern BRP3 can be reduced, so that distortion of the signal transmitted to the third bridging pattern BRP3 can be prevented.

[0210] The first auxiliary electrode AUX1 may be disposed on the second interlayer insulating layer ILD2 and correspond to the region between the first region A1 and the second region A2. The first auxiliary electrode AUX1 may be electrically connected to at least a part of the first bridging pattern BRP1 extending from the first region A1 to the second region A2 through a third contact hole CH3 passing through the second interlayer insulating layer ILD2. The first auxiliary electrode AUX1 may be electrically connected to the first intermediate electrode CTE1 through a third contact hole CH3 passing through the passivation layer PSV. In an embodiment of the present disclosure, the third contact hole CH3 of the second interlayer insulating layer ILD2 and the third contact hole CH3 of the passivation layer PSV may be located in the region between the first region A1 and the second region A2 and correspond to each other.

[0211] The second auxiliary electrode AUX2 may be disposed on the second interlayer insulating layer ILD2 and correspond to the region between the second region A2 and the third region A3. The second auxiliary electrode AUX2 may be electrically connected through a sixth contact hole CH6 passing through the second interlayer insulating layer ILD2 to a second bridging pattern BRP2 extending at least partially from the second region A2 to the third region A3. The second auxiliary electrode AUX2 may be electrically connected through a sixth contact hole CH6 passing through the passivation layer PSV to the second intermediate electrode CTE2. The sixth contact hole CH6 of the second interlayer insulating layer ILD2 and the sixth contact hole CH6 of the passivation layer PSV may be located in the region between the second region A2 and the third region A3 and correspond to each other.

[0212] The first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3, and the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may be disposed on the same layer and include the same material. The first conductive pattern CP1, the second conductive pattern CP2, and the third conductive pattern CP3, and the first auxiliary electrode AUX1 and the second auxiliary electrode AUX2 may be disposed on the second interlayer insulating layer ILD2 and spaced apart from each other at a constant distance. In a cross-sectional view, the first auxiliary electrode AUX1 may be disposed between the first conductive pattern CP1 and the second conductive pattern CP2, and the second auxiliary electrode AUX2 may be disposed between the second conductive pattern CP2 and the third conductive pattern CP3.

[0213] Hereinafter, the display element layer DPL will be described.

[0214] The display element layer DPL of each pixel PXL may include a first electrode EL1 and a second electrode EL2, a first connection pattern CNP1 and a second connection pattern CNP2, a contact electrode CNE, a first intermediate electrode CTE1 and a second intermediate electrode CTE2, and a light-emitting element LD disposed in the emission region EMA. In addition, the display element layer DPL of each pixel PXL may include a bank BNK disposed in the peripheral region.

[0215] The bank BNK can surround at least one side of the emission area EMA of each pixel PXL. The bank BNK can be a structure configured to define (or divide) the respective emission areas EMA of each pixel PXL and the neighboring pixels PXL, and can be, for example, a pixel defining layer. The bank BNK can include at least one light-blocking material and / or reflective material to prevent light leakage defects where light (or light rays) leak between each pixel PXL and the neighboring pixels PXL. In an embodiment, a reflective material layer can be formed on the bank BNK to further improve the efficiency of the light emitted from each pixel PXL. The bank BNK can be provided and / or formed on the passivation layer PSV, but the present disclosure is not limited thereto. In an embodiment, the bank BNK can be provided and / or formed on any one of the insulating layers included in the display element layer DPL.

[0216] The first electrode EL1 and the second electrode EL2 can be spaced apart from each other. The first electrode EL1 can include a 1-1 sub-electrode SEL1_1 disposed in a first region A1, a 1-2 sub-electrode SEL1_2 disposed in a second region A2, and a 1-3 sub-electrode SEL1_3 disposed in a third region A3. In a plan view, the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3 can be spaced apart from each other. The second electrode EL2 can include a 2-1 sub-electrode SEL2_1 disposed in the first region A1, a 2-2 sub-electrode SEL2_2 disposed in the second region A2, and a 2-3 sub-electrode SEL2_3 disposed in the third region A3. In a plan view, the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 can be spaced apart from each other.

[0217] In a plan view, the 2-1 sub-electrode SEL2_1 can be disposed in the central portion of the first region A1 and have a circular shape. The 1-1 sub-electrode SEL1_1 can have a shape surrounding the periphery of the 2-1 sub-electrode SEL2_1 in the circumferential direction. The 2-1 sub-electrode SEL2_1 can be disposed in an isolated circular island shape surrounded by the 1-1 sub-electrode SEL1_1, but the present disclosure is not limited thereto. The 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1 can be disposed on the passivation layer PSV and spaced apart from each other by a predetermined distance.

[0218] In a plan view, the second sub-electrode SEL2_2 can be disposed in a central portion of the second region A2 and has a circular shape. The first sub-electrode SEL1_2 can have a shape surrounding the periphery of the second sub-electrode SEL2_2 in a circumferential direction. The second sub-electrode SEL2_2 can be disposed in an isolated circular island shape surrounded by the first sub-electrode SEL1_2, but the present disclosure is not limited thereto. The first sub-electrode SEL1_2 and the second sub-electrode SEL2_2 can be disposed on the passivation layer PSV and spaced apart from each other by a predetermined distance.

[0219] In a plan view, the second sub-electrode SEL2_3 can be disposed in a central portion of the third region A3 and has a circular shape. The first sub-electrode SEL1_3 can have a shape surrounding the periphery of the second sub-electrode SEL2_3 in a circumferential direction. The second sub-electrode SEL2_3 can be disposed in an isolated circular island shape surrounded by the first sub-electrode SEL1_3, but the present disclosure is not limited thereto. The first sub-electrode SEL1_3 and the second sub-electrode SEL2_3 can be disposed on the passivation layer PSV and spaced apart from each other by a predetermined distance.

[0220] In an embodiment of the present disclosure, the distance between the first sub-electrode SEL1_1 and the second sub-electrode SEL2_1, the distance between the first sub-electrode SEL1_2 and the second sub-electrode SEL2_2, and the distance between the first sub-electrode SEL1_3 and the second sub-electrode SEL2_3 can be the same as each other. Accordingly, the light-emitting elements LD can be more regularly aligned in the first region A1, the second region A2, and the third region A3. However, the present disclosure is not limited thereto. In an embodiment, the distance between the first sub-electrode SEL1_1 and the second sub-electrode SEL2_1, the distance between the first sub-electrode SEL1_2 and the second sub-electrode SEL2_2, and the distance between the first sub-electrode SEL1_3 and the second sub-electrode SEL2_3 can be different from each other.

[0221] Each of the first sub-electrode SEL1_1, the first sub-electrode SEL1_2, the first sub-electrode SEL1_3, the second sub-electrode SEL2_1, the second sub-electrode SEL2_2, and the second sub-electrode SEL2_3 can be formed of a material having a predetermined reflectivity to allow light emitted from each of the light-emitting elements LD disposed in the corresponding region to travel in an image display direction of the display device.

[0222] Each of the first - 1 sub - electrodes SEL1_1, the first - 2 sub - electrodes SEL1_2, and the first - 3 sub - electrodes SEL1_3, and the second - 1 sub - electrodes SEL2_1, the second - 2 sub - electrodes SEL2_2, and the second - 3 sub - electrodes SEL2_3 can be formed of a conductive material having a predetermined reflectivity. The conductive material can include an opaque metal having an advantage of reflecting light emitted from the light - emitting element LD in the image display direction of the display device. The opaque metal can include metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and their alloys. In an embodiment, each of the first - 1 sub - electrodes SEL1_1, the first - 2 sub - electrodes SEL1_2, and the first - 3 sub - electrodes SEL1_3, and the second - 1 sub - electrodes SEL2_1, the second - 2 sub - electrodes SEL2_2, and the second - 3 sub - electrodes SEL2_3 can include a transparent conductive material. The transparent conductive material can include a conductive oxide (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium tin zinc oxide (ITZO)) or a conductive polymer (such as PEDOT). In the case where each of the first - 1 sub - electrodes SEL1_1, the first - 2 sub - electrodes SEL1_2, and the first - 3 sub - electrodes SEL1_3, and the second - 1 sub - electrodes SEL2_1, the second - 2 sub - electrodes SEL2_2, and the second - 3 sub - electrodes SEL2_3 includes a transparent conductive material, a separate additional conductive layer made of an opaque metal can be included for reflecting light emitted from the light - emitting element LD in the image display direction of the display device. However, the material of each of the first - 1 sub - electrodes SEL1_1, the first - 2 sub - electrodes SEL1_2, and the first - 3 sub - electrodes SEL1_3, and the second - 1 sub - electrodes SEL2_1, the second - 2 sub - electrodes SEL2_2, and the second - 3 sub - electrodes SEL2_3 is not limited to the foregoing materials.

[0223] In addition, each of the first 1-1 sub-electrode SEL1_1, the first 1-2 sub-electrode SEL1_2, and the first 1-3 sub-electrode SEL1_3, and the second 2-1 sub-electrode SEL2_1, the second 2-2 sub-electrode SEL2_2, and the second 2-3 sub-electrode SEL2_3 may be provided as a single layer and / or formed of a single layer, but the present disclosure is not limited thereto. In an embodiment, each of the first 1-1 sub-electrode SEL1_1, the first 1-2 sub-electrode SEL1_2, and the first 1-3 sub-electrode SEL1_3, and the second 2-1 sub-electrode SEL2_1, the second 2-2 sub-electrode SEL2_2, and the second 2-3 sub-electrode SEL2_3 may be provided as a multi-layer structure and / or formed of a multi-layer structure by stacking two or more materials among metals, alloys, conductive oxides, and conductive polymers. Each of the first 1-1 sub-electrode SEL1_1, the first 1-2 sub-electrode SEL1_2, and the first 1-3 sub-electrode SEL1_3, and the second 2-1 sub-electrode SEL2_1, the second 2-2 sub-electrode SEL2_2, and the second 2-3 sub-electrode SEL2_3 may have a multi-layer structure including at least two layers to minimize distortion caused by signal delay in the case where a signal (or voltage) is transmitted to opposite ends of each of the light-emitting elements LD. For example, each of the first 1-1 sub-electrode SEL1_1, the first 1-2 sub-electrode SEL1_2, and the first 1-3 sub-electrode SEL1_3, and the second 2-1 sub-electrode SEL2_1, the second 2-2 sub-electrode SEL2_2, and the second 2-3 sub-electrode SEL2_3 may have a multi-layer structure in which layers are stacked in the order of ITO / Ag / ITO.

[0224] As described above, since each of the first 1-1 sub-electrode SEL1_1, the first 1-2 sub-electrode SEL1_2, and the first 1-3 sub-electrode SEL1_3, and the second 2-1 sub-electrode SEL2_1, the second 2-2 sub-electrode SEL2_2, and the second 2-3 sub-electrode SEL2_3 is formed of a conductive material having a predetermined reflectance, light emitted from each of the light-emitting elements LD can be reflected by each of the first 1-1 sub-electrode SEL1_1, the first 1-2 sub-electrode SEL1_2, and the first 1-3 sub-electrode SEL1_3, and the second 2-1 sub-electrode SEL2_1, the second 2-2 sub-electrode SEL2_2, and the second 2-3 sub-electrode SEL2_3 and travel in the image display direction of the display device.

[0225] In the first region A1 of each pixel PXL, the 2-1 sub-electrode SEL2_1 and the 1-1 sub-electrode SEL1_1 surrounding the periphery of the 2-1 sub-electrode SEL2_1, together with a plurality of light-emitting elements LD connected in parallel between the 2-1 sub-electrode SEL2_1 and the 1-1 sub-electrode SEL1_1, can form a first series group SET1. In the second region A2 of each pixel PXL, the 2-2 sub-electrode SEL2_2 and the 1-2 sub-electrode SEL1_2 surrounding the periphery of the 2-2 sub-electrode SEL2_2, together with a plurality of light-emitting elements LD connected in parallel between the 2-2 sub-electrode SEL2_2 and the 1-2 sub-electrode SEL1_2, can form a second series group SET2. In the third region A3 of each pixel PXL, the 2-3 sub-electrode SEL2_3 and the 1-3 sub-electrode SEL1_3 surrounding the periphery of the 2-3 sub-electrode SEL2_3, together with a plurality of light-emitting elements LD connected in parallel between the 2-3 sub-electrode SEL2_3 and the 1-3 sub-electrode SEL1_3, can form a third series group SET3.

[0226] In an embodiment of the present disclosure, the first series group SET1 to the third series group SET3 are disposed in the emission region EMA of each pixel PXL. The first series group SET1 to the third series group SET3 can form the emission portion EMU of the pixel PXL.

[0227] The 1-1 sub-electrode SEL1_1 included in the first series group SET1 of each pixel PXL can be the anode electrode of the emission portion EMU of the pixel PXL. The 2-3 sub-electrode SEL2_3 included in the third series group SET3 can be the cathode electrode of the emission portion EMU.

[0228] In an embodiment of the present disclosure, the 1-1 sub-electrode SEL1_1 of each pixel PXL can be electrically connected to the pixel circuit 144 included in the pixel circuit layer PCL of the pixel PXL through the first contact hole CH1. For example, the 1-1 sub-electrode SEL1_1 can be electrically connected to the first transistor T1(T) of the pixel circuit 144 through the first contact hole CH1.

[0229] In the foregoing embodiments, each of the light-emitting elements LD may be formed of a material having an inorganic crystal structure and having an ultra-small size, for example, in the nanometer to micrometer range. For example, each of the light-emitting elements LD may be an ultra-small light-emitting element manufactured by an etching method or an ultra-small light-emitting element manufactured by a growth method. The type, size, shape, etc. of the light-emitting element LD may be changed in various ways. Although two to several tens of light-emitting elements LD may be aligned and / or arranged in the emission area EMA of each pixel PXL, the number of the light-emitting elements LD is not limited thereto. In the embodiment, the number of the light-emitting elements LD aligned and / or arranged in the emission area EMA of each pixel PXL may be changed in various ways.

[0230] In the first region A1, the light-emitting elements LD may be aligned along the periphery of the second first sub-electrode SEL2_1. For example, the light-emitting elements LD may be radially aligned around the second first sub-electrode SEL2_1 having a circular shape between the first first sub-electrode SEL1_1 and the second first sub-electrode SEL2_1. In the second region A2, the light-emitting elements LD may be aligned along the periphery of the second second sub-electrode SEL2_2. For example, the light-emitting elements LD may be radially aligned around the second second sub-electrode SEL2_2 having a circular shape between the first second sub-electrode SEL1_2 and the second second sub-electrode SEL2_2. In the third region A3, the light-emitting elements LD may be aligned along the periphery of the second third sub-electrode SEL2_3. For example, the light-emitting elements LD may be radially aligned around the second third sub-electrode SEL2_3 having a circular shape between the first third sub-electrode SEL1_3 and the second third sub-electrode SEL2_3.

[0231] In the embodiment, at least one reverse light-emitting element LDr connected in the reverse direction may be provided between two adjacent sub-electrodes in each series group, or at least one defective light-emitting element (for example, an invalid light source) not connected to the two sub-electrodes may be provided between two adjacent sub-electrodes in each series group.

[0232] The light-emitting elements LD may be diffused in a solution and supplied to the emission area EMA of the pixel PXL.

[0233] In an embodiment of the present disclosure, the light-emitting element LD can be provided to the emission region EMA of each pixel PXL by an inkjet printing method, a slit coating method, or various other methods. For example, the light-emitting element LD can be mixed with a volatile solvent and then provided to the emission region EMA of each pixel PXL by an inkjet printing method or a slit coating method. Here, when a corresponding alignment signal (or alignment voltage) is provided to the first electrode EL1 and the second electrode EL2 disposed in the emission region EMA of each pixel PXL, an electric field can be formed between the first electrode EL1 and the second electrode EL2, so that the light-emitting element LD can be aligned between the first electrode EL1 and the second electrode EL2. After the light-emitting element LD is aligned, the solvent can be removed by a volatilization method or other methods. In this way, the light-emitting element LD can be disposed between the first electrode EL1 and the second electrode EL2.

[0234] Before the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3 included in the first electrode EL1 can be electrically connected and / or physically connected to each other. In addition, the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 included in the second electrode EL2 can be electrically connected to each other through the first bridging pattern BRP1, the second bridging pattern BRP2, the third bridging pattern BRP3, the first connection pattern CNP1, and the second connection pattern CNP2. The following will refer to Figure 18c Describe the arrangement relationship of the 1-1 sub-electrode SEL1_1 to the 1-3 sub-electrode SEL1_3 and the 2-1 sub-electrode SEL2_1 to the 2-3 sub-electrode SEL2_3 before the light-emitting element LD is aligned.

[0235] After the light-emitting element LD is aligned in the emission region EMA of each of the first region A1, the second region A2, and the third region A3, the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3 can be separated from each other and located on the same column and spaced apart from each other. By removing or disconnecting a part of the first electrode EL1 after the light-emitting element LD is aligned, the first electrode EL1 can be provided in a form including the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3 that are disposed on the same column and spaced apart from each other.

[0236] As described above, when the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the first electrode EL1 and the second electrode EL2 can be used as alignment electrodes (or alignment lines) for aligning the light-emitting element LD. For example, the first electrode EL1 can be a first alignment electrode to which a first alignment signal (or a first alignment voltage) is to be applied, and the second electrode EL2 can be a second alignment electrode to which a second alignment signal (or a second alignment voltage) is to be applied. In other words, each of the 1-1 sub-electrodes SEL1_1, the 1-2 sub-electrodes SEL1_2, and the 1-3 sub-electrodes SEL1_3 can be a first alignment electrode, and each of the 2-1 sub-electrodes SEL2_1, the 2-2 sub-electrodes SEL2_2, and the 2-3 sub-electrodes SEL2_3 can be a second alignment electrode. The first alignment signal and the second alignment signal can have different voltage levels. If corresponding alignment signals are provided to the first electrode EL1 and the second electrode EL2, each electric field can be formed between the first electrode EL1 and the second electrode EL2. In other words, each electric field can be formed between the 1-1 sub-electrodes SEL1_1 and the 2-1 sub-electrodes SEL2_1, between the 2-1 sub-electrodes SEL2_1 and the 2-2 sub-electrodes SEL2_2, and between the 1-3 sub-electrodes SEL1_3 and the 2-3 sub-electrodes SEL2_3. The light-emitting element LD can be aligned in the emission region EMA of the pixel PXL by the electric field formed between two adjacent sub-electrodes.

[0237] After the light-emitting element LD is aligned in the emission region EMA of each of the first region A1, the second region A2, and the third region A3 of each pixel PXL, the 1-1 sub-electrodes SEL1_1, the 1-2 sub-electrodes SEL1_2, and the 1-3 sub-electrodes SEL1_3, and the 2-1 sub-electrodes SEL2_1, the 2-2 sub-electrodes SEL2_2, and the 2-3 sub-electrodes SEL2_3 can be used as drive electrodes configured to drive the light-emitting element LD.

[0238] In an embodiment of the present disclosure, at the step of aligning the light-emitting element LD in the emission region EMA of each pixel PXL, the light-emitting element LD provided to the emission region EMA can be controlled to be relatively biased and aligned by controlling the alignment signals (or alignment voltages) respectively applied to the first electrode EL1 and the second electrode EL2 or by forming a magnetic field. For example, at the alignment step of the light-emitting element LD, when adjusting the waveform of the alignment signal or forming a magnetic field in the emission region EMA, the number of light-emitting elements LD oriented in the forward direction such that one of the opposite ends EP1 and EP2 of each of the light-emitting elements LD faces the first alignment electrode and the other of the opposite ends EP1 and EP2 faces the second alignment electrode can be controlled to be greater than the number of reverse light-emitting elements LDr oriented in the opposite direction.

[0239] Each of the light-emitting elements LD may include a light-emitting element manufactured by an etching method or a core-shell light-emitting element manufactured by a growth method. When each of the light-emitting elements LD is a light-emitting element manufactured by an etching method, each light-emitting element LD may include an emission stack (or stack pattern) formed by continuously stacking a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an additional electrode 15 in the longitudinal direction of each light-emitting element LD. When each of the light-emitting elements LD is a light-emitting element having a core-shell structure and manufactured by a growth method, each light-emitting element LD may include an emission pattern 10 having a first semiconductor layer 11 provided in the central portion of the light-emitting element LD, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0240] Each of the light-emitting elements LD may include a first end EP1 and a second end EP2. The first end EP1 is electrically connected to one of two adjacent sub-electrodes in each of a first region A1, a second region A2, and a third region A3, and the second end EP2 is electrically connected to the other of the two adjacent sub-electrodes. In an embodiment of the present disclosure, the first end EP1 of each light-emitting element LD may be the first semiconductor layer 11 including an n-type semiconductor layer, and its second end EP2 may be the second semiconductor layer 13 including a p-type semiconductor layer. In other words, in the emission region EMA of the pixel PXL, each light-emitting element LD may be connected in a forward direction between two adjacent sub-electrodes in the first direction DR1. As described above, the light-emitting elements LD connected in a forward direction between two adjacent sub-electrodes may form an effective light source for each of the first series group SET1 to the third series group SET3.

[0241] The first end EP1 of each of the light-emitting elements LD may be directly connected to one of two adjacent sub-electrodes in the first direction DR1, or may be connected to the one sub-electrode through a contact electrode CNE. In addition, the second end EP2 of each of the light-emitting elements LD may be directly connected to the other of the two adjacent sub-electrodes, or may be connected to the other sub-electrode through a contact electrode CNE.

[0242] The light-emitting element LD can be disposed between two adjacent sub-electrodes on the passivation layer PSV in each of the first region A1, the second region A2, and the third region A3. Here, in order to stably support the light-emitting element LD, an insulating pattern INSP can be disposed between the passivation layer PSV and each light-emitting element LD. The insulating pattern INSP can be formed as an inorganic insulating layer including an inorganic material or formed as an organic insulating layer including an organic material. The insulating pattern INSP can be disposed on the passivation layer PSV to fill the space between the passivation layer PSV and each light-emitting element LD. The insulating pattern INSP can stably support the light-emitting element LD such that the light-emitting element LD aligned between two adjacent sub-electrodes can be prevented from being removed from the alignment position. The insulating pattern INSP and two adjacent sub-electrodes (e.g., the 1-1st sub-electrode SEL1_1 and the 2-1st sub-electrode SEL2_1) can have the same height, but the present disclosure is not limited thereto. In an embodiment, the insulating pattern INSP, the 1-1st sub-electrode SEL1_1, and the 2-1st sub-electrode SEL2_1 can have different heights. In addition, the insulating pattern INSP can be omitted according to the processing conditions of the display element layer DPL.

[0243] The light-emitting element LD of each pixel PXL can include a first light-emitting element LD1(LD) included in the first series group SET1, a second light-emitting element LD2(LD) included in the second series group SET2, and a third light-emitting element LD3(LD) included in the third series group SET3. In an embodiment, the light-emitting element LD of each pixel PXL can include at least one reverse light-emitting element LDr connected between two adjacent sub-electrodes in a direction opposite to the forward direction (e.g., the reverse direction).

[0244] Contact electrodes CNE can be respectively disposed on the 1-1st sub-electrode SEL1_1, the 1-2nd sub-electrode SEL1_2, and the 1-3rd sub-electrode SEL1_3, and the 2-1st sub-electrode SEL2_1, the 2-2nd sub-electrode SEL2_2, and the 2-3rd sub-electrode SEL2_3.

[0245] Each contact electrode CNE can be formed of various transparent conductive materials. For example, the contact electrode CNE can include at least one of various conductive materials (e.g., ITO, IZO, and ITZO), and can be substantially transparent or translucent to meet a predetermined transmittance. However, the material of the contact electrode CNE is not limited to the materials of the foregoing embodiments. In some embodiments, the contact electrode CNE can be formed of various opaque conductive materials. In an embodiment of the present disclosure, the contact electrode CNE can include a first contact electrode CNE1 disposed on the 1-1 sub-electrode SEL1_1, a second contact electrode CNE2 disposed on the 2-1 sub-electrode SEL2_1, a third contact electrode CNE3 disposed on the 1-2 sub-electrode SEL1_2, a fourth contact electrode CNE4 disposed on the 2-2 sub-electrode SEL2_2, a fifth contact electrode CNE5 disposed on the 1-3 sub-electrode SEL1_3, and a sixth contact electrode CNE6 disposed on the 2-3 sub-electrode SEL2_3.

[0246] The first contact electrode CNE1 can connect one of the opposite ends EP1 and EP2 of each of the first light-emitting elements LD1 (LD) to the 1-1 sub-electrode SEL1_1 in the first region A1 of each pixel PXL. In a plan view, the first contact electrode CNE1 can overlap both one end of each of the first light-emitting elements LD1 (LD) and the 1-1 sub-electrode SEL1_1.

[0247] The second contact electrode CNE2 can connect the other of the opposite ends EP1 and EP2 of each of the first light-emitting elements LD1 (LD) to the 2-1 sub-electrode SEL2_1 in the first region A1. In a plan view, the second contact electrode CNE2 can overlap both the other end of each of the first light-emitting elements LD1 (LD) and the 2-1 sub-electrode SEL2_1.

[0248] The third contact electrode CNE3 can connect one of the opposite ends EP1 and EP2 of each of the second light-emitting elements LD2 (LD) to the 1-2 sub-electrode SEL1_2 in the second region A2 of each pixel PXL. In a plan view, the third contact electrode CNE3 can overlap one end of each of the second light-emitting elements LD2 (LD) and the 1-2 sub-electrode SEL1_2. In an embodiment of the present disclosure, the third contact electrode CNE3 can extend from the second region A2 to at least a part of the first region A1.

[0249] The fourth contact electrode CNE4 can connect the other ends of the relative ends EP1 and EP2 of each of the 2-2 sub-electrodes SEL2_2 to the second light-emitting element LD2 (LD) in the second region A2. In a plan view, the fourth contact electrode CNE4 can overlap both the other end of each of the second light-emitting elements LD2 (LD) and the 2-2 sub-electrodes SEL2_2.

[0250] The fifth contact electrode CNE5 can connect one of the relative ends EP1 and EP2 of each of the 1-3 sub-electrodes SEL1_3 to the third light-emitting element LD3 (LD) in the third region A3 of each pixel PXL. In a plan view, the fifth contact electrode CNE5 can overlap both one end of each of the third light-emitting elements LD3 (LD) and the 1-3 sub-electrodes SEL1_3. In an embodiment of the present disclosure, the fifth contact electrode CNE5 can extend from the third region A3 to at least a part of the second region A2.

[0251] The sixth contact electrode CNE6 can connect the other ends of the relative ends EP1 and EP2 of each of the 2-3 sub-electrodes SEL2_3 to the third light-emitting element LD3 (LD) in the third region A3. In a plan view, the sixth contact electrode CNE6 can overlap both the other end of each of the third light-emitting elements LD3 (LD) and the 2-3 sub-electrodes SEL2_3.

[0252] The first bridging pattern BRP1 provided in the first region A1 can be electrically connected and / or physically connected to the third contact electrode CNE3 provided in the second region A2 through the first intermediate electrode CTE1.

[0253] The first intermediate electrode CTE1 can be provided in the region between the first region A1 and the second region A2 and is integral with the third contact electrode CNE3. When the first intermediate electrode CTE1 is integral with the third contact electrode CNE3, the first intermediate electrode CTE1 can be considered as a part of the third contact electrode CNE3. For example, in a plan view, the part of the third contact electrode CNE3 extending (or protruding) from the second region A2 to at least a part of the first region A1 can be the first intermediate electrode CTE1. Since the first intermediate electrode CTE1 is a part of the third contact electrode CNE3, the first intermediate electrode CTE1 and the third contact electrode CNE3 can include the same material.

[0254] In a plan view, the first intermediate electrode CTE1 may overlap with a first bridging pattern BRP1 provided in a first region A1. In addition, the first intermediate electrode CTE1 may overlap with a part of a first connection pattern CNP1 provided in a region between the first region A1 and a second region A2. The first intermediate electrode CTE1 may be electrically connected and / or physically connected to the first bridging pattern BRP1 through a third contact hole CH3. Here, a part of the first connection pattern CNP1 may be provided between the first intermediate electrode CTE1 and the first bridging pattern BRP1.

[0255] As described above, since the first bridging pattern BRP1, the first intermediate electrode CTE1, and the third contact electrode CNE3 are connected to each other, a first series group SET1 and a second series group SET2 included in an emission unit EMU of each pixel PXL may be electrically connected and / or physically connected to each other.

[0256] A second bridging pattern BRP2 provided in the second region A2 may be electrically connected and / or physically connected to a fifth contact electrode CNE5 provided in a third region A3 through a second intermediate electrode CTE2.

[0257] The second intermediate electrode CTE2 may be provided in a region between the second region A2 and the third region A3 and may be integral with the fifth contact electrode CNE5. When the second intermediate electrode CTE2 is integral with the fifth contact electrode CNE5, the second intermediate electrode CTE2 may be regarded as a part of the fifth contact electrode CNE5. For example, in a plan view, a part of the fifth contact electrode CNE5 extending (or protruding) from the third region A3 to at least a part of the second region A2 may be the second intermediate electrode CTE2. Since the second intermediate electrode CTE2 is a part of the fifth contact electrode CNE5, the second intermediate electrode CTE2 and the fifth contact electrode CNE5 may include the same material.

[0258] In a plan view, the second intermediate electrode CTE2 may overlap with a second bridging pattern BRP2 provided in the second region A2. In addition, the second intermediate electrode CTE2 may overlap with a part of a second connection pattern CNP2 provided in a part between the second region A2 and the third region A3. The second intermediate electrode CTE2 may be electrically connected and / or physically connected to the second bridging pattern BRP2 through a sixth contact hole CH6. Here, a part of the second connection pattern CNP2 may be provided between the second intermediate electrode CTE2 and the second bridging pattern BRP2.

[0259] As described above, since the second bridging pattern BRP2, the second intermediate electrode CTE2, and the fifth contact electrode CNE5 are connected to each other, the second series group SET2 and the third series group SET3 included in the emission unit EMU of each pixel PXL can be electrically and / or physically connected to each other.

[0260] The display element layer DPL of each pixel PXL may include a first connection pattern CNP1 disposed in a region between the first region A1 and the second region A2 and a second connection pattern CNP2 disposed in a region between the second region A2 and the third region A3.

[0261] A part of the first connection pattern CNP1 may correspond to the third contact hole CH3 and is disposed between the first bridging pattern BRP1 and the first intermediate electrode CTE1. Further, in a plan view, another part of the first connection pattern CNP1 may overlap with the second bridging pattern BRP2 and is electrically connected to the second bridging pattern BRP2 through the fourth contact hole CH4.

[0262] A part of the second connection pattern CNP2 may correspond to the sixth contact hole CH6 and is disposed between the second bridging pattern BRP2 and the second intermediate electrode CTE2. Further, in a plan view, another part of the second connection pattern CNP2 may overlap with the third bridging pattern BRP3 and is electrically connected to the third bridging pattern BRP3 through the ninth contact hole CH9.

[0263] In an embodiment of the present disclosure, the first connection pattern CNP1 and the second connection pattern CNP2 may be disposed on the same layer and include the same material. For example, the first connection pattern CNP1 and the second connection pattern CNP2, the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3, and the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 may be disposed on the same layer and include the same material.

[0264] Each of the first contact electrode CNE1 to the sixth contact electrode CNE6 may have a circular shape, but the present disclosure is not limited thereto, and for example, it may be changed in various shapes as long as it can reliably electrically and / or physically connect one of the sub-electrodes disposed thereunder to one of the opposite ends EP1 and EP2 of each of the light-emitting elements LD.

[0265] An encapsulation layer ENC may be provided and / or formed on the first contact electrode CNE1 to the sixth contact electrode CNE6. The encapsulation layer ENC may cover the pixel circuit layer PCL and the display element layer DPL provided in each pixel PXL. The encapsulation layer ENC may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the encapsulation layer ENC may have a structure formed by alternately stacking at least one inorganic layer and at least one organic layer.

[0266] According to the foregoing embodiment, the emission region EMA of each pixel PXL is divided into a first region A1, a second region A2, and a third region A3 in the second direction DR2. In each of the first region A1, the second region A2, and the third region A3, two sub-electrodes spaced apart from each other and a light-emitting element LD connected in parallel with each other between the two sub-electrodes may be provided. In an embodiment of the present disclosure, the light-emitting element LD provided in each of the first region A1, the second region A2, and the third region A3 may be provided (or aligned) in different directions in the circumferential direction of one of the two sub-electrodes provided in the corresponding region, and the one sub-electrode has an isolated circular island shape surrounded by the other sub-electrode. In this case, the light-emitting element LD may not be provided (or aligned) in a specific direction in the emission region EMA of each pixel PXL. Therefore, it is possible to prevent the light emitted from each of the light-emitting elements LD from concentrating in a specific direction. Therefore, the amount (or intensity) of light emitted from the emission region EMA of each pixel PXL may be similar to or substantially equal to the amount (or intensity) of light emitted from the emission region EMA of an adjacent pixel PXL. Therefore, the display device according to the embodiment of the present disclosure may have a uniform emission distribution throughout its entire region.

[0267] According to the foregoing embodiments, in each of the first region A1, the second region A2, and the third region A3, two sub-electrodes spaced apart from each other and light-emitting elements LD connected in parallel with each other between the two sub-electrodes can form a series group of the corresponding region. The bridging patterns provided in each of the first region A1, the second region A2, and the third region A3, and the intermediate electrodes provided between two consecutive regions of them and integral with the contact electrodes in one of the two consecutive regions can be used to electrically connect the light-emitting elements LD located in each of the two consecutive regions. In other words, the bridging patterns of each of the first region A1, the second region A2, and the third region A3, and the intermediate electrodes provided between two consecutive regions can be connected to each other such that the first series group SET1 of the first region A1 and the second series group SET2 of the second region A2 can be electrically connected to each other, and the second series group SET2 of the second region A2 and the third series group SET3 of the third region A3 can be electrically connected to each other. In this way, the light-emitting elements LD provided in each of the first region A1, the second region A2, and the third region A3 can be connected in a series / parallel combination structure such that the light-emitting part EMU of each pixel PXL can be formed.

[0268] According to the foregoing embodiments, the light-emitting part EMU has a series / parallel combination structure. Therefore, each pixel PXL can be reliably driven such that the driving current flowing into the display panel of the display device can be reduced, thereby improving the power consumption efficiency.

[0269] In the foregoing embodiments, in the cross-sectional view, the pixel circuit layer PCL included in each pixel PXL is shown as an example provided below the display element layer DPL and overlapping the display element layer DPL. However, the present disclosure is not limited thereto. In an embodiment, the pixel circuit layer PCL included in each pixel PXL may be provided below the display element layer DPL and in a region not overlapping the display element layer DPL.

[0270] Figure 12 is a plan view showing the driving current flowing through a pixel according to an embodiment of the present disclosure, and shows, for example, the flow of the driving current flowing through Figure 8 the pixel. As Figure 12 shown, in the case of driving the pixel PXL to emit light in response to a data signal having a predetermined gray-scale value, the flow of the driving current flowing through Figure 8 the pixel PXL is shown by a dotted arrow.

[0271] Refer to Figures 1a to 5 、 Figure 7b 、 Figure 7c and Figures 8 to 12, when a driving current flows from a first power line PL1 to a driving voltage line DVL (PL2) through a first transistor T1 (T) (e.g., a driving transistor provided in a pixel circuit layer PCL included in each pixel PXL), the driving current can be introduced into an emission part EMU of each pixel PXL through a first contact hole CH1. For example, the driving current flows through the first contact hole CH1 to a 1-1st sub-electrode SEL1_1 of a first series group SET1, and the driving current flows to a 2-1st sub-electrode SEL2_1 via a first light-emitting element LD1 (LD) of the first series group SET1. Therefore, each of the first light-emitting elements LD1 (LD) can emit light with a brightness corresponding to the current assigned thereto.

[0272] The driving current flowing through the 2-1st sub-electrode SEL2_1 of the first series group SET1 can be introduced into a 1-2nd sub-electrode SEL1_2 of a second series group SET2 via a first bridging pattern BRP1 electrically connected to the 2-1st sub-electrode SEL2_1 through a second contact hole CH2, a first intermediate electrode CTE1 electrically connected to the first bridging pattern BRP1 through a third contact hole CH3, and a fifth contact electrode CNE5 electrically connected to the first intermediate electrode CTE1. The driving current can flow to a 2-2nd sub-electrode SEL2_2 of the second series group SET2 via a second light-emitting element LD2 (LD) connected in a forward direction between the 1-2nd sub-electrode SEL1_2 and the 2-2nd sub-electrode SEL2_2 of the second series group SET2. Therefore, each of the second light-emitting elements LD2 (LD) can emit light with a brightness corresponding to the current assigned thereto.

[0273] The driving current flowing through the 2-2nd sub-electrode SEL2_2 of the second series group SET2 can be introduced into a 1-3rd sub-electrode SEL1_3 of a third series group SET3 via a second bridging pattern BRP2 electrically connected to the 2-2nd sub-electrode SEL2_2 through a fifth contact hole CH5, a second intermediate electrode CTE2 electrically connected to the second bridging pattern BRP2 through a sixth contact hole CH6, and a fifth contact electrode CNE5 electrically connected to the second intermediate electrode CTE2. The driving current can flow to a 2-3rd sub-electrode SEL2_3 of the third series group SET3 via a third light-emitting element LD3 (LD) connected in a forward direction between the 1-3rd sub-electrode SEL1_3 and the 2-3rd sub-electrode SEL2_3 of the third series group SET3. Therefore, each of the third light-emitting elements LD3 (LD) can emit light with a brightness corresponding to the current assigned thereto.

[0274] In this way, the drive current of each pixel PXL can continuously flow through the first light-emitting element LD1 (LD) of the first series group SET1, the second light-emitting element LD2 (LD) of the second series group SET2, and the third light-emitting element LD3 (LD) of the third series group SET3. Therefore, each pixel PXL can emit light having a brightness corresponding to the data signal provided thereto during each frame period.

[0275] Figure 13 is a schematic plan view showing another example of a pixel according to an embodiment of the present disclosure. Figure 14 is along Figure 13 is a cross-sectional view taken along line III-III'. Figure 15 is along Figure 13 is a cross-sectional view taken along line IV-IV'. Figure 16 shows Figure 15 another embodiment of the first bank shown in, and is a cross-sectional view corresponding to Figure 13 line IV-IV'. Figure 17 shows Figure 15 another embodiment of the display element layer shown in, and is a cross-sectional view corresponding to Figure 13 line IV-IV'.

[0276] As shown in Figures 13 to 17 the detailed description of configurations similar or identical to those of the embodiment of Figure 8 will be omitted.

[0277] Referring to Figures 1a to 5 , Figure 7b , Figure 7c and Figures 13 to 17 , each pixel PXL may include an emission area EMA and a peripheral area surrounding the emission area EMA. The pixel area PXA in which each pixel PXL is provided may include a first area A1, a second area A2, and a third area A3 that are separated from each other in the second direction DR2. Each pixel PXL may include a pixel circuit layer PCL and a display element layer DPL.

[0278] The pixel circuit layer PCL may include at least one transistor T, a first bridging pattern BRP1 provided in the first area A1, a second bridging pattern BRP2 provided in the second area A2, and a third bridging pattern BRP3 provided in the third area A3.

[0279] The display element layer DPL may include a first bank BNK1, a first electrode EL1, and a second electrode EL2, a light-emitting element LD, a contact electrode CNE, a first intermediate electrode CTE1, and a second intermediate electrode CTE2 disposed in the emission area EMA of each pixel PXL, and a second bank BNK2 disposed in the peripheral area of each pixel PXL.

[0280] The first bank BNK1 may be a support component that supports each of the sub-electrodes disposed in the emission area EMA, allowing the light emitted from the light-emitting element LD to travel more reliably in the image display direction of the display device. For example, the first bank BNK1 may be disposed in the emission area EMA of the first area A1, the emission area EMA of the second area A2, and the emission area EMA of the third area A3.

[0281] The first bank BNK1 may be disposed and / or formed between the passivation layer PSV and the sub-electrode in the emission area EMA of each of the first area A1, the second area A2, and the third area A3. For example, in the emission area EMA of the first area A1, the first bank BNK1 may be disposed and / or formed between the 1-1 sub-electrode SEL1_1 and the passivation layer PSV and between the 2-1 sub-electrode SEL2_1 and the passivation layer PSV, respectively. In the emission area EMA of the second area A2, the first bank BNK1 may be disposed and / or formed between the 1-2 sub-electrode SEL1_2 and the passivation layer PSV and between the 2-2 sub-electrode SEL2_2 and the passivation layer PSV, respectively. In the emission area EMA of the third area A3, the first bank BNK1 may be disposed and / or formed between the 1-3 sub-electrode SEL1_3 and the passivation layer PSV and between the 2-3 sub-electrode SEL2_3 and the passivation layer PSV, respectively.

[0282] Each first bank BNK1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In an embodiment, the first bank BNK1 may include an organic insulating layer having a single-layer structure and / or an inorganic insulating layer having a single-layer structure, but the present disclosure is not limited thereto. In an embodiment, the first bank BNK1 may be provided in the form of a multi-layer structure formed by stacking at least one organic insulating layer and at least one inorganic insulating layer.

[0283] The first bank BNK1 may have a trapezoidal cross-section in which its width decreases upward from one surface of the passivation layer PSV, but the present disclosure is not limited thereto. In an embodiment, as Figure 16As shown, the first bank BNK1 may include a curved surface having a cross-section such as a semi-elliptical shape or a semi-circular shape with its width decreasing upward from one surface of the passivation layer PSV. In a cross-sectional view, the shape of the first bank BNK1 is not limited to the foregoing examples and may be changed in various ways within a range that can improve the efficiency of light emitted from each of the light-emitting elements LD. The first banks BNK1 adjacent to each other may be provided on the same plane as the passivation layer PSV and have the same height.

[0284] As described above, each of the first sub-electrodes SEL1_1, SEL1_2, and SEL1_3 and the second sub-electrodes SEL2_1, SEL2_2, and SEL2_3 may be provided and / or formed on the first bank BNK1 and have a surface profile corresponding to the shape of the first bank BNK1. For example, each of the first sub-electrodes SEL1_1, SEL1_2, and SEL1_3 and the second sub-electrodes SEL2_1, SEL2_2, and SEL2_3 may have a protruding portion corresponding to the first bank BNK1 and a planar portion corresponding to the passivation layer PSV. As described above, each of the first sub-electrodes SEL1_1, SEL1_2, and SEL1_3 and the second sub-electrodes SEL2_1, SEL2_2, and SEL2_3 has a surface profile corresponding to the shape of the first bank BNK1 provided thereunder, so that the light emitted from each of the light-emitting elements LD can be reflected by each of the first sub-electrodes SEL1_1, SEL1_2, and SEL1_3 and the second sub-electrodes SEL2_1, SEL2_2, and SEL2_3 and travel more reliably in the image display direction of the display device. Therefore, the efficiency of light emitted from each of the light-emitting elements LD can be further improved.

[0285] In an embodiment of the present disclosure, the first bank BNK1, the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, the 1-3 sub-electrode SEL1_3, the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 can each serve as a reflector that guides the light emitted from the light-emitting element LD disposed in the emission region EMA of each pixel PXL in a desired direction, thereby improving the light efficiency of the display device. In other words, the first bank BNK1, the 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, the 1-3 sub-electrode SEL1_3, the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 can each serve as a reflector that enables the light emitted from the light-emitting element LD to travel in the image display direction of the display device, thereby improving the light-emitting efficiency of the light-emitting element LD.

[0286] The second bank BNK2 can be disposed in the peripheral region of each pixel PXL. The second bank BNK2 and the bank BNK shown in the pixel PXL described above Figure 9 can have the same configuration. Although the second bank BNK2 and the first bank BNK1 can be formed and / or disposed on different layers, the present disclosure is not limited thereto. In an embodiment, the second bank BNK2 and the first bank BNK1 can be formed and / or disposed on the same layer. In an embodiment of the present disclosure, the second bank BNK2 and the first bank BNK1 can be formed on different layers, and the second bank BNK2 can be disposed on the first insulating layer INS1.

[0287] In an embodiment of the present disclosure, the light-emitting element LD can be disposed and / or formed on the first insulating layer INS1 in the emission region EMA of each of the first region A1, the second region A2, and the third region A3.

[0288] The first insulating layer INS1 can be formed and / or disposed under each of the light-emitting elements LD disposed between two adjacent sub-electrodes of the sub-electrodes forming each series group in the emission region EMA of each pixel PXL. The first insulating layer INS1 can fill the space between each of the light-emitting elements LD and the passivation layer PSV to stably support the light-emitting element LD and prevent the light-emitting element LD from being removed from the passivation layer PSV.

[0289] In addition, in the emission area EMA of each pixel PXL, the first insulating layer INS1 may expose a part of each of the sub-electrodes forming each series group, and cover other areas except this part. Here, the contact electrode CNE may be disposed and / or formed in a part of each of the exposed sub-electrodes, so that each of the sub-electrodes and the contact electrode CNE may be electrically connected and / or physically connected to each other.

[0290] The first insulating layer INS1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. Although in an embodiment of the present disclosure, the first insulating layer INS1 may be formed of an inorganic insulating layer that has an advantage in protecting the light-emitting element LD from the influence of the pixel circuit layer PCL of each pixel PXL, the present disclosure is not limited thereto. In an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer that has an advantage in planarizing the support surface of the light-emitting element LD.

[0291] A second insulating layer INS2 may be disposed and / or formed on the light-emitting element LD. The second insulating layer INS2 may be disposed and / or formed on each of the light-emitting elements LD to cover a part of the upper surface of each of the light-emitting elements LD, and expose the opposite ends EP1 and EP2 of each of the light-emitting elements LD to the outside. The second insulating layer INS2 may be formed in an independent pattern in the emission area EMA of each pixel PXL, but the present disclosure is not limited thereto.

[0292] The second insulating layer INS2 may have a single-layer structure or a multi-layer structure, and include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The second insulating layer INS2 may fix each of the light-emitting elements LD aligned in the emission area EMA of each pixel PXL. In an embodiment of the present disclosure, the second insulating layer INS2 may include an inorganic insulating layer that has an advantage in protecting the active layer 12 of each of the light-emitting elements LD from the influence of external oxygen, water, etc. However, the present disclosure is not limited thereto. The second insulating layer INS2 may be formed of an organic insulating layer including an organic material according to the design conditions of the display device to which the light-emitting element LD is applied.

[0293] In an embodiment of the present disclosure, after the light-emitting elements LD are aligned in the emission area EMA of each pixel PXL, the second insulating layer INS2 is formed on the light-emitting elements LD, so that the light-emitting elements LD can be prevented from being removed from the alignment position. As Figure 17As shown, when there is a gap (or space) between the first insulating layer INS1 and the light-emitting element LD before forming the second insulating layer INS2, during the process of forming the second insulating layer INS2, this gap can be filled with the second insulating layer INS2. Therefore, the light-emitting element LD can be supported more stably. Thus, the second insulating layer INS2 can be formed of an organic insulating layer that has an advantage in filling the gap between the first insulating layer INS1 and the light-emitting element LD.

[0294] In an embodiment of the present disclosure, the second insulating layer INS2 can be formed on each of the light-emitting elements LD so that the active layer 12 of each of the light-emitting elements LD can be prevented from contacting an external conductive material. The second insulating layer INS2 can cover only a part of the surface of each of the light-emitting elements LD so that the opposite ends EP1 and EP2 of each of the light-emitting elements LD can be exposed to the outside.

[0295] The contact electrode CNE can be provided and / or formed on the second insulating layer INS2.

[0296] The first contact electrode CNE1 and the second contact electrode CNE2 can be provided and / or formed on the second insulating layer INS2 on the light-emitting element LD disposed in the emission region EMA of the first region A1 (for example, on the first light-emitting element LD1 (LD)). The first contact electrode CNE1 and the second contact electrode CNE2 can be spaced apart from each other at a predetermined distance on the second insulating layer INS2 on the first light-emitting element LD1 (LD), and thus are electrically separated and / or physically separated from each other.

[0297] The third contact electrode CNE3 and the fourth contact electrode CNE4 can be provided and / or formed on the second insulating layer INS2 on the light-emitting element LD disposed in the emission region EMA of the second region A2 (for example, on the second light-emitting element LD2 (LD)). The third contact electrode CNE3 and the fourth contact electrode CNE4 can be spaced apart from each other at a predetermined distance on the second insulating layer INS2 on the second light-emitting element LD2 (LD), and thus are electrically separated and / or physically separated from each other.

[0298] The fifth contact electrode CNE5 and the sixth contact electrode CNE6 can be provided and / or formed on the second insulating layer INS2 on the light-emitting element LD disposed in the emission region EMA of the third region A3 (for example, on the third light-emitting element LD3 (LD)). The fifth contact electrode CNE5 and the sixth contact electrode CNE6 can be spaced apart from each other at a predetermined distance on the second insulating layer INS2 on the third light-emitting element LD3 (LD), and thus are electrically separated and / or physically separated from each other.

[0299] Figures 18a to 18fis a schematic plan view showing a method of manufacturing the Figure 13 pixels shown in Figures 19a to 19h is a cross-sectional view showing a method of manufacturing the Figure 14 pixels shown in

[0300] Hereinafter, with reference to Figures 18a to 18f and Figures 19a to 19h a method of manufacturing the Figure 13 and Figure 14 pixels PXL shown in accordance with an embodiment of the present disclosure will be described.

[0301] Referring to Figures 1a to 5 , Figure 7b , Figure 7c , Figures 13 to 17 , Figure 18a and Figure 19a , a pixel circuit layer PCL of the pixel PXL is formed on a substrate SUB. The pixel region PXA where the pixel PXL is provided may include a first region A1, a second region A2, and a third region A3 that are separated from each other in a second direction DR2. Each of the first region A1, the second region A2, and the third region A3 may include an emission region EMA that emits light therefrom and a peripheral region surrounding the periphery of the emission region EMA.

[0302] The pixel circuit layer PCL may include a pixel circuit 144 (which includes at least one transistor T), a first bridging pattern BRP1, a second bridging pattern BRP2, and a third bridging pattern BRP3, a driving voltage line DVL (PL2), and at least one insulating layer. Here, the at least one insulating layer may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and a passivation layer PSV that are continuously formed on the substrate SUB.

[0303] The first interlayer insulating layer ILD1 may include an eighth contact hole CH8 that exposes a part of the driving voltage line DVL (PL2).

[0304] Each of the second interlayer insulating layer ILD2 and the passivation layer PSV may include a first contact hole CH1, and a second contact hole CH2 and a third contact hole CH3, the first contact hole CH1 exposing a portion of the second terminal DE of the first transistor T1 (T) included in the pixel circuit 144, and the second contact hole CH2 and the third contact hole CH3 each exposing a portion of the first bridge pattern BRP1. In addition, each of the second interlayer insulating layer ILD2 and the passivation layer PSV may include a fourth contact hole CH4, a fifth contact hole CH5, and a sixth contact hole CH6, each exposing a portion of the second bridge pattern BRP2. In addition, each of the second interlayer insulating layer ILD2 and the passivation layer PSV may include a seventh contact hole CH7 and a ninth contact hole CH9, each exposing a portion of the third bridge pattern BRP3.

[0305] Each of the first bridge pattern BRP1, the second bridge pattern BRP2, and the third bridge pattern BRP3 may be formed on the first interlayer insulating layer ILD1. In a plan view, each of the first bridge pattern BRP1, the second bridge pattern BRP2, and the third bridge pattern BRP3 may extend in the second direction DR2 and be spaced apart from each other and electrically and / or physically separated from each other. In an embodiment of the present disclosure, the third bridge pattern BRP3 may be electrically and / or physically connected to the driving voltage line DVL(PL2) through the eighth contact hole CH8.

[0306] refer to Figures 1a to 5 , Figure 7b , Figure 7c , Figures 13 to 17 , Figure 18b , Figure 19a and Figure 19b , a first bank BNK1 is formed on the passivation layer PSV. Each first bank BNK1 may be spaced apart from an adjacent first bank BNK1 by a predetermined distance on the passivation layer PSV. The first bank BNK1 may be formed of an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0307] refer to Figures 1a to 5 , Figure 7b , Figure 7c , Figures 13 to 17 , Figure 18c and Figures 19a to 19c, on a passivation layer PSV on which a first bank BNK1 is formed, a first sub-electrode SEL1_1 to a third sub-electrode SEL1_3, a second sub-electrode SEL2_1 to a third sub-electrode SEL2_3, a first connection line CNL1 and a second connection line CNL2, and a first connection pattern CNP1 and a second connection pattern CNP2 including a conductive material (or substance) having a high reflectivity are formed.

[0308] Each of the first sub-electrode SEL1_1 to the third sub-electrode SEL1_3 and the second sub-electrode SEL2_1 to the third sub-electrode SEL2_3 may be formed on a corresponding first bank BNK1.

[0309] The first sub-electrode SEL1_1 and the second sub-electrode SEL2_1 may be formed in an emission region EMA of a first region A1 of each pixel PXL. The first sub-electrode SEL1_2 and the second sub-electrode SEL2_2 may be formed in an emission region EMA of a second region A2 of the pixel PXL. The first sub-electrode SEL1_3 and the second sub-electrode SEL2_3 may be formed in an emission region EMA of a third region A3 of the pixel PXL.

[0310] In a first region A1 of each pixel PXL, the second sub-electrode SEL2_1 may have an isolated circular island shape, and the first sub-electrode SEL1_1 may have a shape surrounding the periphery of the second sub-electrode SEL2_1. In a second region A2 of each pixel PXL, the second sub-electrode SEL2_2 may have an isolated circular island shape, and the first sub-electrode SEL1_2 may have a shape surrounding the periphery of the second sub-electrode SEL2_2. In a third region A3 of each pixel PXL, the second sub-electrode SEL2_3 may have an isolated circular island shape, and the first sub-electrode SEL1_3 may have a shape surrounding the periphery of the second sub-electrode SEL2_3.

[0311] In an embodiment of the present disclosure, the first sub-electrode SEL1_1 and the first sub-electrode SEL1_2 may be electrically connected and / or physically connected to each other through the first connection line CNL1. The first connection line CNL1 may be integral with the first sub-electrode SEL1_1 or integral with the first sub-electrode SEL1_2. For example, when the first connection line CNL1 is integral with the first sub-electrode SEL1_1, the first connection line CNL1 may be regarded as a part of the first sub-electrode SEL1_1. When the first connection line CNL1 is integral with the first sub-electrode SEL1_2, the first connection line CNL1 may be regarded as a part of the first sub-electrode SEL1_2.

[0312] The first - second sub - electrode SEL1_2 and the first - third sub - electrode SEL1_3 can be electrically connected and / or physically connected to each other through the second connection line CNL2. The second connection line CNL2 can be integral with the first - second sub - electrode SEL1_2 or integral with the first - third sub - electrode SEL1_3. For example, in the case where the second connection line CNL2 is integral with the first - second sub - electrode SEL1_2, the second connection line CNL2 can be regarded as part of the first - second sub - electrode SEL1_2. In the case where the second connection line CNL2 is integral with the first - third sub - electrode SEL1_3, the second connection line CNL2 can be regarded as part of the first - third sub - electrode SEL1_3.

[0313] In an embodiment of the present disclosure, the first - first sub - electrode SEL1_1 in the first region A1 and the first - second sub - electrode SEL1_2 in the second region A2 can be electrically connected and / or physically connected to each other through the first connection line CNL1. The first - second sub - electrode SEL1_2 in the second region A2 and the first - third sub - electrode SEL1_3 in the third region A3 can be electrically connected and / or physically connected to each other through the second connection line CNL2. In other words, the first - first sub - electrode SEL1_1, the first - second sub - electrode SEL1_2, and the first - third sub - electrode SEL1_3 can be electrically connected and / or physically connected to each other through the first connection line CNL1 and the second connection line CNL2.

[0314] In an embodiment of the present disclosure, in a plan view, the second - first sub - electrode SEL2_1 in the first region A1, the second - second sub - electrode SEL2_2 in the second region A2, and the second - third sub - electrode SEL2_3 in the third region A3 can be spaced apart from each other at regular intervals.

[0315] The first connection pattern CNP1 can be formed in a portion between the first region A1 and the second region A2. One end of the first connection pattern CNP1 can be connected to the first bridging pattern BRP1 through the third contact hole CH3, and the other end thereof can be connected to the second bridging pattern BRP2 through the fourth contact hole CH4. The second connection pattern CNP2 can be formed in the region between the second region A2 and the third region A3. One end of the second connection pattern CNP2 can be connected to the second bridging pattern BRP2 through the sixth contact hole CH6, and the other end thereof can be connected to the third bridging pattern BRP3 through the ninth contact hole CH9.

[0316] The 2-1 sub-electrode SEL2_1 of the first region A1 can be electrically and / or physically connected to the first bridging pattern BRP1 through the second contact hole CH2. The 2-2 sub-electrode SEL2_2 of the second region A2 can be electrically and / or physically connected to the second bridging pattern BRP2 through the fifth contact hole CH5. The 2-3 sub-electrode SEL2_3 of the third region A3 can be electrically and / or physically connected to the third bridging pattern BRP3 through the seventh contact hole CH7.

[0317] In an embodiment of the present disclosure, the 2-1 sub-electrode SEL2_1 of the first region A1 can be electrically and / or physically connected to the 2-2 sub-electrode SEL2_2 of the second region A2 through the first bridging pattern BRP1, the first connection pattern CNP1, and the second bridging pattern BRP2. In addition, the 2-2 sub-electrode SEL2_2 of the second region A2 can be electrically and / or physically connected to the 2-3 sub-electrode SEL2_3 of the third region A3 through the second bridging pattern BRP2, the second connection pattern CNP2, and the third bridging pattern BRP3. In other words, the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3 can be electrically and / or physically connected to each other through the first bridging pattern BRP1, the second bridging pattern BRP2, and the third bridging pattern BRP3, as well as the first connection pattern CNP1 and the second connection pattern CNP2.

[0318] The 1-1 sub-electrode SEL1_1 of the first region A1 can be connected to the first transistor T1(T) of the pixel circuit 144 through the first contact hole CH1.

[0319] The 1-1 sub-electrode SEL1_1, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3, the 2-1 sub-electrode SEL2_1, the 2-2 sub-electrode SEL2_2, and the 2-3 sub-electrode SEL2_3, as well as the first connection pattern CNP1 and the second connection pattern CNP2 can be disposed on the same layer, include the same material, and are formed by the same process.

[0320] Reference [[ID=27 、 ​ 、 ​ 、 ​ and ​, an insulating material layer INSM is formed on the passivation layer PSV, and a 1-1st sub-electrode SEL1_1, a 1-2nd sub-electrode SEL1_2, a 1-3rd sub-electrode SEL1_3, a 2-1st sub-electrode SEL2_1, a 2-2nd sub-electrode SEL2_2, a 2-3rd sub-electrode SEL2_3, a first connection pattern CNP1, a second connection pattern CNP2, etc. are formed on the passivation layer PSV. The insulating material layer INSM may include an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0321] Subsequently, a second bank BNK2 is formed in the peripheral area of each of the first area A1, the second area A2, and the third area A3 of each pixel PXL. Here, the second bank BNK2 may be formed on the insulating material layer INSM. The second bank BNK2 may be a pixel defining layer configured to define (or divide) an emission area EMA between each pixel PXL and a pixel PXL adjacent thereto.

[0322] refer to ​ , ​ , ​ , Figures 13 to 17 , Figure 18d and Figures 19a to 19e , a corresponding alignment signal (or alignment voltage) is provided to each of the 1-1st sub-electrode SEL1_1 to the 1-3rd sub-electrode SEL1_3 and the 2-1st sub-electrode SEL2_1 to the 2-3rd sub-electrode SEL2_3, so that an electric field is formed between two adjacent sub-electrodes in each of the first area A1 to the third area A3. The first alignment signal (or the first alignment voltage) may be applied to the 1-1st sub-electrode SEL1_1 to the 1-3rd sub-electrode SEL1_3 connected through the first connection line CNL1 and the second connection line CNL2. The second alignment signal (or the second alignment voltage) may be applied to the 2-1st sub-electrode SEL2_1 to the 2-3rd sub-electrode SEL2_3 connected through the first bridge pattern BRP1 to the third bridge pattern BRP3 and the first connection pattern CNP1 and the second connection pattern CNP2.

[0323] For example, when AC power having a predetermined period or DC power having a predetermined voltage is repeatedly applied several times to each of the 1-1 sub-electrode SEL1_1 to the 1-3 sub-electrode SEL1_3 and the 2-1 sub-electrode SEL2_1 to the 2-3 sub-electrode SEL2_3, an electric field can be formed between two adjacent sub-electrodes in each of the first area A1 to the third area A3, and the electric field corresponds to the difference between the corresponding potentials of the two adjacent sub-electrodes.

[0324] As described above, after an electric field has been formed between two adjacent sub-electrodes in each of the first region A1 to the third region A3, a mixed solution including the light-emitting element LD can be supplied to the emission region EMA of each of the first region A1 to the third region A3 by an inkjet printing method or the like. For example, an inkjet nozzle is provided on the insulating material layer INSM, and a solvent mixed with a plurality of light-emitting elements LD can be supplied to the emission region EMA of each of the first region A1 to the third region A3 of each pixel PXL through the inkjet nozzle. Here, the solvent can be any one of acetone, water, alcohol, and toluene, but the present disclosure is not limited thereto. For example, the solvent can be in the form of an ink or a paste. The method of supplying the light-emitting element LD to the emission region EMA of each of the first region A1 to the third region A3 of each pixel PXL is not limited to the method of the foregoing embodiment. The method of supplying the light-emitting element LD can be changed in various ways.

[0325] After the light-emitting element LD has been supplied to the emission region EMA of each of the first region A1 to the third region A3 of each pixel PXL, the solvent can be removed.

[0326] In the case of supplying the light-emitting element LD to the emission region EMA, self-alignment of the light-emitting element LD can be guided by the respective electric fields formed between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1, between the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2, and between the 1-3 sub-electrode SEL1_3 and the 2-3 sub-electrode SEL2_3. Accordingly, the light-emitting element LD can be aligned between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1, between the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2, and between the 1-3 sub-electrode SEL1_3 and the 2-3 sub-electrode SEL2_3. For example, the first light-emitting element LD1 (LD) can be aligned between the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1. The second light-emitting element LD2 (LD) can be aligned between the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2. The third light-emitting element LD3 (LD) can be aligned between the 1-3 sub-electrode SEL1_3 and the 2-3 sub-electrode SEL2_3. The first light-emitting element LD1 (LD) can be aligned on the insulating material layer INSM in the emission region EMA of the first region A1. The second light-emitting element LD2 (LD) can be aligned on the insulating material layer INSM in the emission region EMA of the second region A2. The third light-emitting element LD3 (LD) can be aligned on the insulating material layer INSM in the emission region EMA of the third region A3.

[0327] In an embodiment, the light-emitting element LD may include at least one reverse light-emitting element LDr that is connected in a direction opposite to the forward direction according to the wavelength of the alignment signal applied to each of two adjacent sub-electrodes in each of the first region A1, the second region A2, and the third region A3.

[0328] As described above, at the step of aligning the light-emitting element LD, for example, by adjusting the alignment signal applied to two adjacent sub-electrodes, the direction and amplitude of the electric field formed between the two adjacent sub-electrodes can be controlled, and the ratio of the number of light-emitting elements LD aligned in the forward direction and the number of light-emitting elements connected in the opposite direction (e.g., the number of reverse light-emitting elements LDr) in the emission region EMA of each of the first region A1, the second region A2, and the third region A3 can be adjusted, or the light-emitting elements LD aligned in the forward direction can be concentratedly arranged at a specific position in the emission region EMA.

[0329] Reference Figures 1a to 5 、 Figure 7b 、 Figure 7c 、 Figures 13 to 17 and Figures 19a to 19f After the light-emitting element LD is aligned in the emission region EMA of each of the first region A1, the second region A2, and the third region A3, a second insulating layer INS2 is formed on each of the light-emitting elements LD. The second insulating layer INS2 may cover at least a part of the upper surface of each of the light-emitting elements LD, so that only the opposite ends EP1 and EP2 of the active layer 12 of each of the light-emitting elements LD can be exposed to the outside.

[0330] The first insulating layer INS1 may be formed by etching the insulating material layer INSM so that a part of each of the first sub-electrode SEL1_1 to the first sub-electrode SEL1_3 and the second sub-electrode SEL2_1 to the second sub-electrode SEL2_3 is exposed by the process of forming the second insulating layer INS2 or an etching process performed before or after that.

[0331] Reference Figures 1a to 5 、 Figure 7b 、 Figure 7c 、 Figures 13 to 17 、 Figure 18e and Figures 19a to 19g The first contact electrode CNE1 to the sixth contact electrode CNE6, the first intermediate electrode CTE1, and the second intermediate electrode CTE2 are formed on the passivation layer PSV on which the second insulating layer INS2 is formed.

[0332] The first contact electrode CNE1 can be directly formed on the 1-1 sub-electrode SEL1_1. The second contact electrode CNE2 can be directly formed on the 2-1 sub-electrode SEL2_1. The third contact electrode CNE3 can be directly formed on the 1-2 sub-electrode SEL1_2. The fourth contact electrode CNE4 can be directly formed on the 2-2 sub-electrode SEL2_2. The fifth contact electrode CNE5 can be directly formed on the 1-3 sub-electrode SEL1_3. The sixth contact electrode CNE6 can be directly formed on the 2-3 sub-electrode SEL2_3.

[0333] The first intermediate electrode CTE1 can be integral with the third contact electrode CNE3 and protrude from the second region A2 to the first region A1. The first intermediate electrode CTE1 can be formed on the first connection pattern CNP1 in the region between the first region A1 and the second region A2.

[0334] The second intermediate electrode CTE2 can be integral with the fifth contact electrode CNE5 and have a shape protruding from the third region A3 to the second region A2. The second intermediate electrode CTE2 can be formed on the second connection pattern CNP2 in the region between the second region A2 and the third region A3.

[0335] Reference Figures 1a to 5 、 Figure 7b 、 Figure 7c 、 Figures 13 to 17 、 Figure 18f and Figures 19a to 19h , By using an etching method using a mask or the like, the process of removing the first connection line CNL1 and the second connection line CNL2 is performed so that two sub-electrodes in each of the first region A1 to the third region A3 provided in each pixel PXL and the light-emitting element LD aligned between the two sub-electrodes can embody a series group. When the first connection line CNL1 and the second connection line CNL2 are removed, the 1-1 sub-electrode SEL1_1 provided in the first region A1, the 1-2 sub-electrode SEL1_2 provided in the second region A2, and the 1-3 sub-electrode SEL1_3 provided in the third region A3 can be spaced apart from each other.

[0336] In addition, during the process of removing the first connection line CNL1 and the second connection line CNL2, a part of each of the first connection pattern CNP1 and the second connection pattern CNP2 can be removed. When a part of the first connection pattern CNP1 is removed, the first bridging pattern BRP1 in the first region A1 and the second bridging pattern BRP2 in the second region A2 can be electrically separated and / or physically separated from each other. When a part of the second connection pattern CNP2 is removed, the second bridging pattern BRP2 in the second region A2 and the third bridging pattern BRP3 in the third region A3 can be electrically separated and / or physically separated from each other.

[0337] In addition, during the process of removing the first connection line CNL1 and the second connection line CNL2, a part of the 1-1 sub-electrode SEL1_1 in the first region A1 and a part of the 1-3 sub-electrode SEL1_3 in the third region A3 can be removed. Thus, each pixel PXL can be driven independently (or separately) from its neighboring pixels PXL.

[0338] Due to the aforementioned process, the 1-1 sub-electrode SEL1_1 and the 2-1 sub-electrode SEL2_1 in the first region A1 and the first light-emitting element LD1 (LD) connected in parallel therebetween can form a first series group SET1, the 1-2 sub-electrode SEL1_2 and the 2-2 sub-electrode SEL2_2 in the second region A2 and the second light-emitting element LD2 (LD) connected in parallel therebetween can form a second series group SET2, and the 1-3 sub-electrode SEL1_3 and the 2-3 sub-electrode SEL2_3 in the third region A3 and the third light-emitting element LD3 (LD) connected in parallel therebetween can form a third series group SET3.

[0339] In an embodiment of the present disclosure, the 1-1 sub-electrode SEL1_1 of the first series group SET1, the 1-2 sub-electrode SEL1_2 of the second series group SET2, and the 1-3 sub-electrode SEL1_3 of the third series group SET3 can form a first electrode EL1 of each pixel PXL. In addition, the 2-1 sub-electrode SEL2_1 of the first series group SET1, the 2-2 sub-electrode SEL2_2 of the second series group SET2, and the 2-3 sub-electrode SEL2_3 of the third series group SET3 can form a second electrode EL2 of each pixel PXL.

[0340] The first series group SET1 can be electrically connected to the pixel circuit 144 and thus electrically connected to the second series group SET2 through the first bridging pattern BRP1 and the first intermediate electrode CTE1. The second series group SET2 can be electrically connected to the third series group SET3 through the second bridging pattern BRP2 and the second intermediate electrode CTE2. The third series group SET3 can be electrically connected to the drive voltage line DVL (PL2) through the third bridging pattern BRP3. Thus, in the case where a drive current flows from the first power line PL1 to the drive voltage line DVL (PL2) through a first transistor T1 (T) (e.g., a drive transistor) included in the pixel circuit 144 of each pixel PXL, the drive current can be introduced into an emission unit EMU of each pixel PXL formed by the first series group SET1 to the third series group SET3.

[0341] Subsequently, an encapsulation layer ENC is formed to cover the first through sixth contact electrodes CNE1 to CNE6. The encapsulation layer ENC may have a structure formed by alternately stacking at least one inorganic layer and at least one organic layer.

[0342] Figure 20 is a schematic plan view showing another example of a pixel according to an embodiment of the present disclosure. Figure 21 is along Figure 20 a cross-sectional view taken along line V-V'.

[0343] To avoid redundant explanations, the description will focus on the differences from the foregoing embodiment Figure 20 and Figure 21 of the pixel PXL. Components not separately explained in the following description of the present embodiment are consistent with the components of the foregoing embodiment. The same reference numerals will be used to denote the same components, and similar reference numerals will be used to denote similar components.

[0344] Refer to Figures 1a to 5 , Figure 7b , Figure 7c , Figure 20 and Figure 21 , where the pixel region PXA in which each pixel PXL is provided (or provided) may include a first region A1, a second region A2, and a third region A3 that are separated from each other in the second direction DR2. Each pixel PXL may include a pixel circuit layer PCL and a display element layer DPL.

[0345] The pixel circuit layer PCL may include at least one transistor T and a first bridging pattern BRP1 and a second bridging pattern BRP2. In an embodiment of the present disclosure, the first bridging pattern BRP1 and the second bridging pattern BRP2 may be disposed on the first interlayer insulating layer ILD1, and the first bridging pattern BRP1 and the second bridging pattern BRP2 and the transistor T may be disposed on the same layer and include the same material. However, the present disclosure is not limited thereto. In an embodiment, the first bridging pattern BRP1 and the second bridging pattern BRP2 and a conductive layer forming at least one of the signal lines included in the pixel circuit layer PCL may be disposed on the same layer.

[0346] The first bridging pattern BRP1 can be set to extend from the first region A1 to the second region A2. In addition, the first bridging pattern BRP1 can be located between the second region A2 and the third region A3. The second bridging pattern BRP2 can be set only in the third region A3. In an embodiment of the present disclosure, before the light-emitting element LD is aligned in each pixel PXL, the first bridging pattern BRP1 and the second bridging pattern BRP2 can form a wire for electrical connection and / or physical connection. The wire can receive a second alignment signal (or a second alignment voltage) through the driving voltage line DVL. After the light-emitting element LD is aligned in each pixel PXL, the wire can be set in a form including the first bridging pattern BRP1 and the second bridging pattern BRP2, and the first bridging pattern BRP1 and the second bridging pattern BRP2 are spaced apart from each other by disconnecting or removing a part of the wire. The first bridging pattern BRP1 and the second bridging pattern BRP2 spaced apart from each other can be electrically separated and / or physically separated from each other after the light-emitting element LD is aligned.

[0347] The 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, at least one first light-emitting element LD1 (LD), and the first contact electrode CNE1 and the second contact electrode CNE2 can be set in the first region A1. The 1-1 sub-electrode SEL1_1, the 2-1 sub-electrode SEL2_1, and the first light-emitting element LD1 (LD) connected in parallel therebetween can form the first series group SET1 of each pixel PXL. In the first region A1, the first end EP1 (e.g., the first semiconductor layer) of the first light-emitting element LD1 (LD) can be electrically connected to the 2-1 sub-electrode SEL2_1, and its second end EP2 (e.g., the second semiconductor layer) can be electrically connected to the 1-1 sub-electrode SEL1_1.

[0348] In an embodiment of the present disclosure, the 1-1 sub-electrode SEL1_1 can be electrically connected to the pixel circuit 144 of each pixel PXL through the first contact hole CH1 passing through the second interlayer insulating layer ILD2 and the passivation layer PSV. The 2-1 sub-electrode SEL2_1 can be electrically connected to one side of the first bridging pattern BRP1 through the second contact hole CH2 passing through the second interlayer insulating layer ILD2 and the passivation layer PSV.

[0349] The first - second sub - electrode SEL1_2, the second - second sub - electrode SEL2_2, at least one second light - emitting element LD2(LD), at least one reverse light - emitting element LDr(LD), and the third contact electrode CNE3 and the fourth contact electrode CNE4 may be disposed in the second region A2. The first - second sub - electrode SEL1_2, the second - second sub - electrode SEL2_2, and the second light - emitting element LD2(LD) and the reverse light - emitting element LDr(LD) connected in parallel therebetween may form a second series group SET2 of each pixel PXL.

[0350] In the second region A2, a first end EP1 (e.g., a first semiconductor layer) of the second light - emitting element LD2(LD) may be electrically connected to the first - second sub - electrode SEL1_2, and a second end EP2 (e.g., a second semiconductor layer) thereof may be electrically connected to the second - second sub - electrode SEL2_2. In the second region A2, a first end EP1 of the reverse light - emitting element LDr(LD) may be electrically connected to the second - second sub - electrode SEL2_2, and a second end EP2 thereof may be electrically connected to the first - second sub - electrode SEL1_2.

[0351] In an embodiment of the present disclosure, the second - second sub - electrode SEL2_2 may be electrically connected to the other side of the first bridging pattern BRP1 through a third contact hole CH3 passing through the second inter - layer insulating layer ILD2 and the passivation layer PSV. Accordingly, the first series group SET1 and the second series group SET2 may be electrically connected to each other through the first bridging pattern BRP1 disposed in a portion between the first region A1 and the second region A2.

[0352] The second bridging pattern BRP2, the first - third sub - electrode SEL1_3, the second - third sub - electrode SEL2_3, at least one third light - emitting element LD3(LD), at least one reverse light - emitting element LDr(LD), and the fifth contact electrode CNE5 and the sixth contact electrode CNE6 may be disposed in the third region A3. The first - third sub - electrode SEL1_3, the second - third sub - electrode SEL2_3, and the third light - emitting element LD3(LD) and the reverse light - emitting element LDr(LD) connected in parallel therebetween may form a third series group SET3 of each pixel PXL.

[0353] The second bridging pattern BRP2 may be electrically connected to the second - third sub - electrode SEL2_3 through a fourth contact hole CH4 passing through the second inter - layer insulating layer ILD2 and the passivation layer PSV, and may be electrically connected to the driving voltage line DVL(PL2) through a fifth contact hole CH5 passing through the first inter - layer insulating layer ILD1.

[0354] In the third region A3, the first end EP1 (e.g., the first semiconductor layer) of the third light-emitting element LD3 (LD) may be electrically connected to the 2-3 sub-electrode SEL2_3, and its second end EP2 (e.g., the second semiconductor layer) may be electrically connected to the 1-3 sub-electrode SEL1_3. In the third region A3, the first end EP1 of the reverse light-emitting element LDr (LD) may be electrically connected to the 1-3 sub-electrode SEL1_3, and its second end EP2 may be electrically connected to the 2-3 sub-electrode SEL2_3.

[0355] The second series group SET2 and the third series group SET3 may be electrically connected to each other through a connection line CNL in a region between the second region A2 and the third region A3.

[0356] In an embodiment of the present disclosure, the connection line CNL may be provided between the 1-2 sub-electrode SEL1_2 and the 1-3 sub-electrode SEL1_3, and electrically connect and / or physically connect the 1-2 sub-electrode SEL1_2 and the 1-3 sub-electrode SEL1_3. In other words, the 1-2 sub-electrode SEL1_2 and the 1-3 sub-electrode SEL1_3 may be electrically connected and / or physically connected to each other through the connection line CNL.

[0357] The connection line CNL may be integral with the 1-2 sub-electrode SEL1_2 and / or the 1-3 sub-electrode SEL1_3. When the connection line CNL is integral with the 1-2 sub-electrode SEL1_2, the connection line CNL may be regarded as a part of the 1-2 sub-electrode SEL1_2. When the connection line CNL is integral with the 1-3 sub-electrode SEL1_3, the connection line CNL may be regarded as a part of the 1-3 sub-electrode SEL1_3. Since the connection line CNL is integral with the 1-2 sub-electrode SEL1_2 and / or the 1-3 sub-electrode SEL1_3, the connection line CNL, the 1-2 sub-electrode SEL1_2, and the 1-3 sub-electrode SEL1_3 may be provided on the same layer and include the same material.

[0358] In an embodiment of the present disclosure, before the light-emitting element LD is aligned in each pixel PXL, the first sub-electrode SEL1_1 and the first sub-electrode SEL1_2 may be electrically connected and / or physically connected, and may be spaced apart from each other after the light-emitting element LD is aligned. For example, before the light-emitting element LD is aligned in each pixel PXL, the first sub-electrode SEL1_1 and the first sub-electrode SEL1_2 may be electrically connected and / or physically connected to each other in a boundary portion between the first region A1 and the second region A2, and after the light-emitting element LD is aligned, they are spaced apart from each other by disconnecting or removing a part of the first sub-electrode SEL1_1 and the first sub-electrode SEL1_2 in the boundary portion. Therefore, after the light-emitting element LD is aligned in each pixel PXL, the first sub-electrode SEL1_1 and the first sub-electrode SEL1_2 may be electrically separated and / or physically separated from each other.

[0359] Before the light-emitting element LD is aligned, the first sub-electrode SEL1_1 and the first sub-electrode SEL1_2 may be electrically connected and / or physically connected to each other, and the first sub-electrode SEL1_2 and the first sub-electrode SEL1_3 may be electrically connected and / or physically connected to each other through a connection line CNL. Therefore, before the light-emitting element LD is aligned, the first sub-electrode SEL1_1, the first sub-electrode SEL1_2, and the first sub-electrode SEL1_3 may be electrically connected and / or physically connected to each other, and a first alignment signal (or a first alignment voltage) may be provided thereto from the pixel circuit 144 through the first contact hole CH1.

[0360] When a driving current flows from the first power line PL1 to the driving voltage line DVL (PL2) through a first transistor T1(T) (for example, a driving transistor) of the pixel circuit 144 included in each pixel PXL having the above configuration, the driving current may be provided to the first sub-electrode SEL1_1 of the first series group SET1 through the first contact hole CH1.

[0361] The driving current provided to the first sub-electrode SEL1_1 flows to the second sub-electrode SEL2_1 through the first light-emitting element LD1(LD) of the first series group SET1. Therefore, the first light-emitting element LD1(LD) may emit light having a brightness corresponding to the current allocated to the first light-emitting element LD1(LD).

[0362] The driving current flowing to the 2-1st sub-electrode SEL2_1 of the first series group SET1 can be introduced into the 2-2nd sub-electrode SEL2_2 of the second series group SET2 via the third contact hole CH3 and the first bridging pattern BRP1 electrically connected to the 2-1st sub-electrode SEL2_1 through the second contact hole CH2. The driving current can flow to the 1-2nd sub-electrode SEL1_2 via the second light-emitting element LD2 (LD) connected between the 2-2nd sub-electrode SEL2_2 and the 1-2nd sub-electrode SEL1_2 of the second series group SET2. Therefore, the second light-emitting element LD2 (LD) can emit light with a brightness corresponding to the current allocated to the second light-emitting element LD2 (LD). Here, since the driving current does not flow to the reverse light-emitting element LDr in the second region A2, the reverse light-emitting element LDr remains disabled. In other words, the reverse light-emitting element LDr in the second region A2 can not emit light.

[0363] The driving current flowing to the 1-2nd sub-electrode SEL1_2 of the second series group SET2 can be introduced into the 1-3rd sub-electrode SEL1_3 of the third series group SET3 via the connection line CNL. The driving current can flow to the 2-3rd sub-electrode SEL2_3 via the third light-emitting element LD3 (LD) connected between the 1-3rd sub-electrode SEL1_3 and the 2-3rd sub-electrode SEL2_3 of the third series group SET3. Therefore, the third light-emitting element LD3 (LD) can emit light with a brightness corresponding to the current allocated to the third light-emitting element LD3 (LD). Here, since the driving current does not flow to the reverse light-emitting element LDr in the third region A3, the reverse light-emitting element LDr remains disabled. In other words, the reverse light-emitting element LDr in the third region A3 can not emit light.

[0364] In this way, the driving current of each pixel PXL can continuously flow through the first light-emitting element LD1 (LD) of the first series group SET1, the second light-emitting element LD2 (LD) of the second series group SET2, and the third light-emitting element LD3 (LD) of the third series group SET3. Therefore, each pixel PXL can emit light with a brightness corresponding to the data signal provided during each frame period.

[0365] Figure 22 is a schematic plan view showing another example of a pixel according to an embodiment of the present disclosure.

[0366] Regarding Figure 22 for the pixel PXL, the detailed description of the configuration similar or identical to that of the Figure 20 and Figure 21 embodiment will be omitted.

[0367] Refer to Figures 1a to 5 、 Figure 7b 、Figure 7c and Figure 22 , wherein the pixel region PXA of each pixel PXL may include a first region A1, a second region A2, a third region A3, a fourth region A4, and a fifth region A5 that are separated from each other in the second direction DR2. Each pixel PXL may include a pixel circuit layer PCL and a display element layer DPL.

[0368] The pixel circuit layer PCL may include at least one transistor T, a first bridging pattern BRP1, a second bridging pattern BRP2, and a third bridging pattern BRP3.

[0369] The first bridging pattern BRP1 may be disposed to extend from the first region A1 to the second region A2. The second bridging pattern BRP2 may be disposed in the third region A3. The third bridging pattern BRP3 may be disposed to extend from the fourth region A4 to the fifth region A5.

[0370] A first sub-electrode SEL1_1, a second sub-electrode SEL2_1, at least one first light-emitting element LD1 (LD), a first contact electrode CNE1, and a second contact electrode CNE2 may be disposed in the first region A1. The first sub-electrode SEL1_1, the second sub-electrode SEL2_1, and the first light-emitting element LD1 (LD) connected in parallel therebetween may form a first series group SET1 of each pixel PXL. In the first region A1, a first end EP1 (e.g., a first semiconductor layer) of each first light-emitting element LD1 (LD) may be electrically connected to the second sub-electrode SEL2_1, and a second end EP2 (e.g., a second semiconductor layer) thereof may be electrically connected to the first sub-electrode SEL1_1.

[0371] The first sub-electrode SEL1_1 may be electrically connected to the pixel circuit 144 of each pixel PXL through a first contact hole CH1. The second sub-electrode SEL2_1 may be electrically connected to one side of the first bridging pattern BRP1 through a second contact hole CH2.

[0372] A first sub-electrode SEL1_2, a second sub-electrode SEL2_2, at least one second light-emitting element LD2 (LD), at least one reverse light-emitting element LDr (LD), a third contact electrode CNE3, and a fourth contact electrode CNE4 may be disposed in the second region A2. The first sub-electrode SEL1_2, the second sub-electrode SEL2_2, the second light-emitting element LD2 (LD), and the reverse light-emitting element LDr (LD) connected in parallel therebetween may form a second series group SET2 of each pixel PXL.

[0373] The first end EP1 of the second light-emitting element LD2 (LD) can be electrically connected to the 1-2nd sub-electrode SEL1_2, and its second end EP2 can be electrically connected to the 2-2nd sub-electrode SEL2_2. The first end EP1 of the reverse light-emitting element LDr (LD) in the second region A2 can be electrically connected to the 2-2nd sub-electrode SEL2_2, and its second end EP2 can be electrically connected to the 1-2nd sub-electrode SEL1_2.

[0374] The 2-2nd sub-electrode SEL2_2 can be electrically connected to the other side of the first bridging pattern BRP1 through the third contact hole CH3. Therefore, the first series group SET1 and the second series group SET2 can be electrically connected to each other through the first bridging pattern BRP1.

[0375] The 1-3rd sub-electrode SEL1_3, the 2-3rd sub-electrode SEL2_3, at least one third light-emitting element LD3 (LD), at least one reverse light-emitting element LDr (LD), and the fifth contact electrode CNE5 and the sixth contact electrode CNE6 can be provided in the third region A3. The 1-3rd sub-electrode SEL1_3 and the 2-3rd sub-electrode SEL2_3, and the third light-emitting element LD3 (LD) and the reverse light-emitting element LDr (LD) connected in parallel therebetween can form the third series group SET3 of each pixel PXL.

[0376] The first end EP1 of the third light-emitting element LD3 (LD) can be electrically connected to the 2-3rd sub-electrode SEL2_3, and its second end EP2 can be electrically connected to the 1-3rd sub-electrode SEL1_3. The first end EP1 of the reverse light-emitting element LDr (LD) in the third region A3 can be electrically connected to the 1-3rd sub-electrode SEL1_3, and its second end EP2 can be electrically connected to the 2-3rd sub-electrode SEL2_3.

[0377] The second series group SET2 and the third series group SET3 can be electrically connected to each other through the first connection line CNL1 provided in the region between the second region A2 and the third region A3.

[0378] The first connection line CNL1 can be provided between the 1-2nd sub-electrode SEL1_2 and the 1-3rd sub-electrode SEL1_3, and electrically connect and / or physically connect the 1-2nd sub-electrode SEL1_2 and the 1-3rd sub-electrode SEL1_3. In other words, the 1-2nd sub-electrode SEL1_2 and the 1-3rd sub-electrode SEL1_3 can be electrically connected and / or physically connected to each other through the first connection line CNL1. The first connection line CNL1 can be integral with the 1-2nd sub-electrode SEL1_2 and / or the 1-3rd sub-electrode SEL1_3.

[0379] The second to third sub-electrode SEL2_3 can be electrically connected to one side of the second bridging pattern BRP2 through the fourth contact hole CH4.

[0380] The first to fourth sub-electrode SEL1_4, the second to fourth sub-electrode SEL2_4, at least one fourth light-emitting element LD4 (LD), at least one reverse light-emitting element LDr (LD), and the seventh contact electrode CNE7 and the eighth contact electrode CNE8 can be disposed in the fourth region A4. The first to fourth sub-electrode SEL1_4 and the second to fourth sub-electrode SEL2_4, and the fourth light-emitting element LD4 (LD) and the reverse light-emitting element LDr (LD) connected in parallel therebetween can form the fourth series group of each pixel PXL.

[0381] The first end EP1 of the fourth light-emitting element LD4 (LD) can be electrically connected to the first to fourth sub-electrode SEL1_4, and its second end EP2 can be electrically connected to the second to fourth sub-electrode SEL2_4. The first end EP1 of the reverse light-emitting element LDr (LD) in the fourth region A4 can be electrically connected to the second to fourth sub-electrode SEL2_4, and its second end EP2 can be electrically connected to the first to fourth sub-electrode SEL1_4.

[0382] In an embodiment of the present disclosure, the seventh contact electrode CNE7 can be disposed on the first to fourth sub-electrode SEL1_4 and the first end EP1 of the fourth light-emitting element LD4 (LD), and thus connect the first to fourth sub-electrode SEL1_4 and the first end EP1 of the fourth light-emitting element LD4 (LD). The seventh contact electrode CNE7 can be disposed in the second end EP2 of the reverse light-emitting element LDr (LD) in the fourth region A4. The eighth contact electrode CNE8 can be disposed on the second to fourth sub-electrode SEL2_4 and the second end EP2 of the fourth light-emitting element LD4 (LD), and thus connect the second to fourth sub-electrode SEL2_4 and the second end EP2 of the fourth light-emitting element LD4 (LD). The eighth contact electrode CNE8 can be disposed in the first end EP1 of the reverse light-emitting element LDr (LD) in the fourth region A4.

[0383] The second to fourth sub-electrode SEL2_4 can be electrically connected to the other side of the second bridging pattern BRP2 through the fifth contact hole CH5. Thus, the third series group SET3 and the fourth series group can be electrically connected to each other through the second bridging pattern BRP2.

[0384] The third bridging pattern BRP3, the first to fifth sub-electrodes SEL1_5, the second to fifth sub-electrodes SEL2_5, at least one fifth light-emitting element LD5 (LD), and the ninth contact electrode CNE9 and the tenth contact electrode CNE10 may be disposed in the fifth region A5. The first to fifth sub-electrodes SEL1_5, the second to fifth sub-electrodes SEL2_5, and the fifth light-emitting element LD5 (LD) connected in parallel therebetween may form a fifth series group of each pixel PXL.

[0385] A first end EP1 of the fifth light-emitting element LD5 (LD) may be electrically connected to the second to fifth sub-electrodes SEL2_5, and a second end EP2 thereof may be electrically connected to the first to fifth sub-electrodes SEL1_5.

[0386] In an embodiment of the present disclosure, the ninth contact electrode CNE9 may be disposed on the first to fifth sub-electrodes SEL1_5 and the second end EP2 of the fifth light-emitting element LD5 (LD), and thus connect the first to fifth sub-electrodes SEL1_5 and the second end EP2 of the fifth light-emitting element LD5 (LD). The tenth contact electrode CNE10 may be disposed on the second to fifth sub-electrodes SEL2_5 and the first end EP1 of the fifth light-emitting element LD5 (LD), and thus connect the second to fifth sub-electrodes SEL2_5 and the first end EP1 of the fifth light-emitting element LD5 (LD).

[0387] The fourth series group and the fifth series group may be electrically connected to each other through a second connection line CNL2 disposed in a region between the fourth region A4 and the fifth region A5.

[0388] The second connection line CNL2 may be disposed between the first to fourth sub-electrodes SEL1_4 and the first to fifth sub-electrodes SEL1_5, and electrically connect and / or physically connect the first to fourth sub-electrodes SEL1_4 and the first to fifth sub-electrodes SEL1_5. In other words, the first to fourth sub-electrodes SEL1_4 and the first to fifth sub-electrodes SEL1_5 may be electrically connected and / or physically connected to each other through the second connection line CNL2.

[0389] The second connection line CNL2 may be integral with the 1st - 4th sub - electrodes SEL1_4 and / or the 1st - 5th sub - electrodes SEL1_5. When the second connection line CNL2 is integral with the 1st - 4th sub - electrodes SEL1_4, the second connection line CNL2 may be regarded as part of the 1st - 4th sub - electrodes SEL1_4. When the second connection line CNL2 is integral with the 1st - 5th sub - electrodes SEL1_5, the second connection line CNL2 may be regarded as part of the 1st - 5th sub - electrodes SEL1_5. Since the second connection line CNL2 is integral with the 1st - 4th sub - electrodes SEL1_4 and / or the 1st - 5th sub - electrodes SEL1_5, the second connection line CNL2, the 1st - 4th sub - electrodes SEL1_4, and the 1st - 5th sub - electrodes SEL1_5 may be disposed on the same layer and have the same material.

[0390] The 2nd - 5th sub - electrodes SEL2_5 may be electrically connected to the third bridging pattern BRP3 through the sixth contact hole CH6. The third bridging pattern BRP3 may be electrically connected to the second power line (refer to Figure 7b and Figure 7c PL2) to which the second driving power supply VSS will be applied.

[0391] When a driving current flows from the first power line PL1 to the second power line (refer to Figure 7b and Figure 7c PL2) through the first transistor T1(T) (e.g., driving transistor T) in the pixel circuit 144 included in each pixel PXL having the above - described configuration, the driving current may be supplied to the 1st - 1st sub - electrode SEL1_1 of the first series group SET1 through the first contact hole CH1.

[0392] The driving current supplied to the 1st - 1st sub - electrode SEL1_1 flows to the 2nd - 1st sub - electrode SEL2_1 via the first light - emitting element LD1(LD) of the first series group SET1. Thus, each of the first light - emitting elements LD1(LD) may emit light with a brightness corresponding to the current allocated thereto.

[0393] The driving current flowing to the 2nd - 1st sub - electrode SEL2_1 of the first series group SET1 may be introduced into the 2nd - 2nd sub - electrode SEL2_2 of the second series group SET2 via the third contact hole CH3 and the first bridging pattern BRP1 electrically connected to the 2nd - 1st sub - electrode SEL2_1 through the second contact hole CH2. The driving current may flow to the 1st - 2nd sub - electrode SEL1_2 via the second light - emitting element LD2(LD) connected between the 2nd - 2nd sub - electrode SEL2_2 and the 1st - 2nd sub - electrode SEL1_2 of the second series group SET2. Thus, the second light - emitting element LD2(LD) may emit light having a brightness corresponding to the current allocated to the second light - emitting element LD2(LD).

[0394] The drive current flowing to the 1-2 sub-electrode SEL1_2 of the second series group SET2 can be introduced into the 1-3 sub-electrode SEL1_3 of the third series group SET3 via the first connection line CNL1. The drive current can flow to the 2-3 sub-electrode SEL2_3 via the third light-emitting element LD3 (LD) connected between the 1-3 sub-electrode SEL1_3 and the 2-3 sub-electrode SEL2_3 of the third series group SET3. Therefore, the third light-emitting element LD3 (LD) can emit light with a brightness corresponding to the current allocated to the third light-emitting element LD3 (LD).

[0395] The drive current flowing to the 2-3 sub-electrode SEL2_3 of the third series group SET3 can be introduced into the 2-4 sub-electrode SEL2_4 of the fourth series group via the fifth contact hole CH5 and the second bridging pattern BRP2 electrically connected to the 2-3 sub-electrode SEL2_3 through the fourth contact hole CH4. The drive current can flow to the 1-4 sub-electrode SEL1_4 via the fourth light-emitting element LD4 (LD) connected between the 2-4 sub-electrode SEL2_4 and the 1-4 sub-electrode SEL1_4 of the fourth series group. Therefore, the fourth light-emitting element LD4 (LD) can emit light with a brightness corresponding to the current allocated to the fourth light-emitting element LD4 (LD).

[0396] The drive current flowing to the 1-4 sub-electrode SEL1_4 of the fourth series group can be introduced into the 1-5 sub-electrode SEL1_5 of the fifth series group via the second connection line CNL2. The drive current can flow to the 2-5 sub-electrode SEL2_5 via the fifth light-emitting element LD5 (LD) connected between the 1-5 sub-electrode SEL1_5 and the 2-5 sub-electrode SEL2_5 of the fifth series group. Therefore, the fifth light-emitting element LD5 (LD) can emit light with a brightness corresponding to the current allocated to the fifth light-emitting element LD5 (LD).

[0397] In this way, the drive current of each pixel PXL can continuously flow through the first light-emitting element LD1 (LD) of the first series group SET1, the second light-emitting element LD2 (LD) of the second series group SET2, the third light-emitting element LD3 (LD) of the third series group SET3, the fourth light-emitting element LD4 (LD) of the fourth series group, and the fifth light-emitting element LD5 (LD) of the fifth series group. Therefore, each pixel PXL can emit light with a brightness corresponding to the data signal provided during each frame period.

[0398] Although various embodiments have been described above, those skilled in the art will understand that various modifications, additions, and substitutions are possible without departing from the scope of the present disclosure.

[0399] Accordingly, the embodiments disclosed in this specification are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure must be defined by the appended claims.

Claims

1. A display device, comprising: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas; and pixels disposed in each of the plurality of pixel areas, wherein each of the pixels includes: a first area, a second area, and a third area separated from each other in one direction; a first sub-electrode and a second sub-electrode disposed in each of the first area, the second area, and the third area and spaced apart from each other; a plurality of light-emitting elements disposed in each of the first area, the second area, and the third area and disposed between the first sub-electrode and the second sub-electrode; a bridging pattern disposed under the first sub-electrode and the second sub-electrode in the corresponding area in each of the first area, the second area, and the third area, and an insulating layer is interposed between the bridging pattern and the first sub-electrode and the second sub-electrode in the corresponding area; a first contact electrode disposed on the first sub-electrode in the corresponding area in each of the first area, the second area, and the third area; and a second contact electrode disposed on the second sub-electrode in the corresponding area in each of the first area, the second area, and the third area, wherein the bridging pattern in the first area and the first contact electrode in the second area are electrically connected to each other, wherein, at least a part of the bridging pattern in the first area extends to the second area, and at least a part of the bridging pattern in the second area extends to the third area.

2. The display device according to claim 1, wherein In each of the first area, the second area, and the third area, one of the first sub-electrode and the second sub-electrode has a circular shape, and the other of the first sub-electrode and the second sub-electrode has a shape surrounding the one sub-electrode.

3. The display device according to claim 2, wherein, The plurality of light-emitting elements includes: a first light-emitting element disposed between the first sub-electrode and the second sub-electrode in the first area; a second light-emitting element disposed between the first sub-electrode and the second sub-electrode in the second area; and a third light-emitting element disposed between the first sub-electrode and the second sub-electrode in the third area, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element are each disposed between the one sub-electrode and the other sub-electrode in the circumferential direction of the one sub-electrode in the corresponding area.

4. The display device according to claim 3, wherein In a plan view, the bridging pattern in the first area, the bridging pattern in the second area, and the bridging pattern in the third area are spaced apart from each other.

5. The display device according to claim 1, wherein The insulating layer includes a plurality of contact holes formed to expose a part of the bridging pattern in each of the first area, the second area, and the third area, The display device further includes a first intermediate electrode disposed in at least one of the plurality of contact holes in a region formed between the first region and the second region, and electrically connecting the bridging pattern in the first region to the first contact electrode in the second region.

6. The display device according to claim 5, wherein, The first intermediate electrode and the first contact electrode in the second region are integral.

7. The display device according to claim 5, further comprising a second intermediate electrode disposed in at least one of the plurality of contact holes in a region formed between the second region and the third region, and electrically connecting the bridging pattern in the second region to the first contact electrode in the third region.

8. The display device according to claim 7, wherein, The second intermediate electrode and the first contact electrode in the third region are integral.

9. The display device according to claim 8, wherein, the bridging pattern in the first region is electrically connected to each of the first intermediate electrode and the second sub-electrode in the first region, the bridging pattern in the second region is electrically connected to each of the first intermediate electrode, the second intermediate electrode, and the second sub-electrode in the second region, and the bridging pattern in the third region is electrically connected to each of the second intermediate electrode and the second sub-electrode in the third region.

10. The display device according to claim 9, Among them, in each of the first region, the second region, and the third region, one of the first sub-electrode and the second sub-electrode has a circular shape, and the other of the first sub-electrode and the second sub-electrode has a shape surrounding the one sub-electrode, wherein the plurality of light-emitting elements includes: a first light-emitting element disposed between the first sub-electrode and the second sub-electrode in the first region; a second light-emitting element disposed between the first sub-electrode and the second sub-electrode in the second region; and a third light-emitting element disposed between the first sub-electrode and the second sub-electrode in the third region, wherein the first light-emitting element, the second light-emitting element, and the third light-emitting element are each disposed between the one sub-electrode and the other sub-electrode in the circumferential direction of the one sub-electrode in the corresponding region, wherein, the first light-emitting elements connected in parallel between the first sub-electrode and the second sub-electrode in the first region form a first group, the second light-emitting elements connected in parallel between the first sub-electrode and the second sub-electrode in the second region form a second group, the third light-emitting elements connected in parallel between the first sub-electrode and the second sub-electrode in the third region form a third group, the first group and the second group are electrically connected through the first intermediate electrode and the bridging pattern in the first region, and the second group and the third group are electrically connected through the second intermediate electrode and the bridging pattern in the second region.

11. The display device according to claim 10, further comprising: A conductive pattern is disposed on the bridging pattern in each of the first region, the second region, and the third region and is electrically connected to the bridging pattern; A first auxiliary electrode is disposed between the first intermediate electrode and the bridging pattern in the first region in the region between the first region and the second region; And A second auxiliary electrode is disposed between the second intermediate electrode and the bridging pattern in the second region in the region between the second region and the third region.

12. The display device according to claim 11, wherein the conductive pattern in the first region is disposed between the second sub-electrode in the first region and the bridging pattern in the first region, the conductive pattern in the second region is disposed between the second sub-electrode in the second region and the bridging pattern in the second region, and the conductive pattern in the third region is disposed between the second sub-electrode in the third region and the bridging pattern in the third region.

13. The display device according to claim 12, wherein, The conductive pattern in each of the first region, the second region, and the third region, and the first auxiliary electrode and the second auxiliary electrode are disposed on the same layer.

14. A display device, comprising: A substrate including a display region and a non-display region, the display region including a plurality of pixel regions; And Pixels are disposed in each of the plurality of pixel regions, wherein the pixel includes: A first region, a second region, and a third region, separated from each other in one direction; A first sub-electrode and a second sub-electrode are disposed in each of the first region, the second region, and the third region and are spaced apart from each other; A plurality of light-emitting elements are disposed in each of the first region, the second region, and the third region and are disposed between the first sub-electrode and the second sub-electrode; A first bridging pattern extends from the first region to the second region and is disposed under the second sub-electrode in each of the first region and the second region; A second bridging pattern is disposed in the third region and is disposed under the second sub-electrode in the third region; and A connection line is disposed between the first sub-electrode in the second region and the first sub-electrode in the third region and electrically connects the first sub-electrode in the second region to the first sub-electrode in the third region.

15. The display device according to claim 14, wherein, The connection line is integral with one of the first sub-electrodes in the first sub-electrode in the second region and the first sub-electrode in the third region.

16. The display device according to claim 15, wherein, In each of the first region, the second region, and the third region, one of the first sub-electrode and the second sub-electrode has a circular shape, and the other of the first sub-electrode and the second sub-electrode has a shape surrounding the one sub-electrode.

17. The display device according to claim 16, wherein the plurality of light-emitting elements include: A first light-emitting element is disposed between the first sub-electrode and the second sub-electrode in the first region; A second light-emitting element is disposed between the first sub-electrode and the second sub-electrode in the second region; and a third light-emitting element is disposed between the first sub-electrode and the second sub-electrode in the third region, and the first light-emitting element, the second light-emitting element, and the third light-emitting element are each disposed between the one sub-electrode and the other sub-electrode in the circumferential direction of the one sub-electrode in the corresponding region.

18. The display device according to claim 17, wherein the first light-emitting elements connected in parallel between the first sub-electrode and the second sub-electrode in the first region form a first group, the second light-emitting elements connected in parallel between the first sub-electrode and the second sub-electrode in the second region form a second group, the third light-emitting elements connected in parallel between the first sub-electrode and the second sub-electrode in the third region form a third group, the first group and the second group are electrically connected to each other through the first bridging pattern, and the second group and the third group are electrically connected to each other through the connection line.

19. A method of manufacturing a display device, comprising: setting pixels in a pixel region, the pixel region including a first region, a second region, and a third region separated from each other in one direction, wherein setting the pixels includes forming a pixel circuit layer and forming a display element layer, forming the pixel circuit layer includes: forming at least one transistor and bridging patterns corresponding to each of the first region, the second region, and the third region on a substrate; and forming an insulating layer on the transistor and the bridging patterns, forming the display element layer includes: forming a second sub-electrode corresponding to each of the first region, the second region, and the third region and having a circular shape and a first sub-electrode having a shape surrounding the periphery of the second sub-electrode on the insulating layer; providing a plurality of light-emitting elements to each of the first region, the second region, and the third region, and aligning the plurality of light-emitting elements between the first sub-electrode and the second sub-electrode; forming a contact electrode on each of the first sub-electrode and the second sub-electrode; and forming a first intermediate electrode integrated with the contact electrode on the first sub-electrode in the second region, and forming a second intermediate electrode integrated with the contact electrode on the first sub-electrode in the third region, the bridging pattern in the first region and the contact electrode on the first sub-electrode in the second region are electrically connected to each other through the first intermediate electrode, and the bridging pattern in the second region and the contact electrode on the first sub-electrode in the third region are electrically connected to each other through the second intermediate electrode.

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