Methods for balancing timing

Abstract

The present invention provides a method for balancing timing, providing a design layout, the design layout includes multiple design modules, each design module includes multiple ports; defining the design modules that need to be timing balanced; formulating design rules for timing balance, including placing the defined design modules relatively parallel at a set distance, so that when the ports between the defined design modules are connected, the bus length of the connection is the shortest; resetting the positions of multiple design modules according to the design rules, and connecting the ports between the design modules. The method of the present invention finds out the modules related to the address and data, places the units related to the timing balance close to each other, ensures that the bus connection is balanced and the routing is short, and in the redesigned layout, the data register corresponds to the memory port, and the bus connection is balanced and short.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for balancing timing. Background Art

[0002] The memory design kit needs to provide a timing model. When modeling the address setup time and access time, its accuracy is related to the speed of the memory application. Usually the address setup time is only within 1ns (process below 130), and the error between address buses directly affects the accuracy of address setup modeling. Traditional bus circuits and corresponding layouts are as follows Figures 1 to 4 As shown, due to the differences in the placement of the modules or units, the connection lengths between the buses will vary greatly, and the corresponding parasitic capacitances will also vary.

[0003] When placing modules or units, failure to fully consider the length of each path between the high and low bits of the bus will cause unbalanced connections between the high and low bits of the bus (data and address bus), resulting in differences in capacitive loads that affect path delays. When the load difference is even larger, drive units will be added, resulting in greater differences in path delays between the high and low bits of the bus, making it difficult to balance the timing between the buses.

[0004] Therefore, a method of balancing timing is needed to reduce the error between address buses, so as to improve the accuracy of address establishment modeling and reduce the address establishment time. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, the purpose of the present invention is to provide a method for balancing timing, which is used to solve the problem in the prior art that when placing modules or units, the length of each path between the high and low bits of the bus is not fully considered, which will cause unbalanced connections between the high and low bits of the bus, thereby causing the difference in capacitive loads to affect the path delay, and even when the load difference is large, the drive unit will be added, resulting in a greater difference in the path delay between the high and low bits of the bus.

[0006] To achieve the above objectives and other related objectives, the present invention provides a method for balancing timing, comprising:

[0007] Step 1: providing a design layout, wherein the design layout includes a plurality of design modules, and each of the design modules includes a plurality of ports;

[0008] Step 2: define the design module that needs to be time-balanced;

[0009] Step 3, formulating the design rules for the timing balance, the design rules comprising: placing the defined design modules relatively parallel at a set distance, so that when the ports between the defined design modules are connected, the total length of the connection is less than the total length of other positions;

[0010] Step 4: re-arrange the positions of the plurality of design modules according to the design rules, and connect the ports between the design modules.

[0011] Preferably, the multiple design modules in step one include combinational logic circuits, sequential logic circuits and memories.

[0012] Preferably, the sequential logic circuit in step one is a register circuit.

[0013] Preferably, the register in step one includes an address register and a data register.

[0014] Preferably, the design module that needs to perform the timing balance in step 2 is the register.

[0015] Preferably, the set distance in step three is: the distance between two design modules is smaller than the size of the smallest design module.

[0016] Preferably, the bus length in step three includes: the total length of the connection between the address port of the memory and the output port of the address register; and the total length of the connection between the data port of the memory and the input port of the data register.

[0017] Preferably, in step 4, the port connections between the memory and the address register and the data register are reset according to the design rule.

[0018] Preferably, the method further comprises step five, performing circuit timing simulation verification on the design layout reset according to the design rules.

[0019] Preferably, in step five, after resetting the port connections between the memory and the address register and the data register respectively according to the design rules, circuit timing simulation verification is performed so that the delay difference of data transmission between the address register and the data register is less than 0.05ns.

[0020] As described above, the method for balancing timing of the present invention has the following beneficial effects:

[0021] The present invention finds out the modules related to the address and data, places the units related to the timing balance close to each other, ensures the bus connection is balanced and the routing is short, and after the redesigned layout, the data register corresponds to the memory port, and the bus connection is balanced and short. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 Shown is a bus circuit schematic diagram of the prior art;

[0023] Figure 2 A schematic diagram of a layout of the prior art is shown;

[0024] Figure 3 Shown is a schematic diagram of the connection between the memory and the address register of the prior art;

[0025] Figure 4 Shown is a schematic diagram of the connection between the memory and the data register of the prior art;

[0026] Figure 5 Shown is a schematic diagram of the layout of the present invention;

[0027] Figure 6 Shown is a schematic diagram of circuit timing simulation verification of the present invention;

[0028] Figure 7 Shown is a schematic diagram of the process flow of the present invention. DETAILED DESCRIPTION

[0029] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0030] See also Figure 7 The present invention provides a method for balancing timing, comprising:

[0031] Step 1: providing a design layout, the design layout includes multiple design modules, each design module includes multiple ports, and in the design layout, ports between two adjacent design modules usually need to be connected;

[0032] In an optional embodiment, the multiple design modules in step one include combinational logic circuits, sequential logic circuits and memories, the combinational logic circuits include encoders, decoders, data selectors, adders and numerical comparators, etc., the sequential logic circuits include registers, counters, sequential pulse generators and sequence signal generators, etc., and the memories include read-only memories (ROM) and random access memories (RAM).

[0033] In an optional implementation, in an optional implementation, the sequential logic circuit in step one is a register.

[0034] In an optional implementation, the register in step 1 includes an address register and a data register.

[0035] In an optional implementation, the design module that needs to be timing balanced in step 2 is a register circuit.

[0036] The function of a register is to store binary code. It is composed of flip-flops with storage function. One flip-flop can store 1 bit of binary code, so a register that stores n bits of binary code needs to be composed of n flip-flops.

[0037] The memory cell is actually a type of sequential logic circuit. According to the type of memory used, it can be divided into read-only memory (ROM) and random access memory (RAM). The functions of the two are quite different, so the descriptions are also different. The memory is a collection of many storage cells, arranged in order of cell numbers. Each cell is composed of a number of binary bits to represent the value stored in the storage cell.

[0038] Step 2: define the design modules that need to be time-balanced among multiple design modules;

[0039] In an optional implementation, the design module that needs to be time-balanced in step 2 is a module related to address and data, which may be a register.

[0040] Step 3, formulate design rules for timing balance, the design rules include: placing the defined design modules relatively parallel at a set distance, that is, constantly adjusting the positions of the defined design modules, so that when connecting the ports between the defined design modules, the total length of the connection is smaller than the total length of other positions;

[0041] In an optional implementation, the set distance in step three is: the distance between two design modules is smaller than the design module with the smallest size among the design modules.

[0042] In an alternative embodiment, see Figure 6 The bus length in step 3 includes: the total length of the connection between the address port of the memory and the output port of the address register; and the total length of the connection between the data port of the memory and the input port of the data register. Figures 2 to 4 , whose total line length is the shortest.

[0043] Step 4: Reset the positions of multiple design modules according to the design rules and connect the ports between the design modules.

[0044] In an optional implementation, in step 4, the port connections between the memory and the address register and the data register are reset according to the design rules.

[0045] In an optional implementation, the method further includes step five, performing circuit timing simulation verification on the design layout reset according to the design rules.

[0046] In an alternative embodiment, see Figure 6In step 5, after resetting the port connections between the memory and the address register and the data register according to the design rules, circuit timing simulation verification is performed to make the delay difference of data transmission between the address register and the data register less than 0.05ns.

[0047] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0048] In summary, the present invention finds out the modules related to address and data, places the units related to timing balance close to each other, ensures the bus connection is balanced and the routing is short, and after the redesigned layout, the data register corresponds to the memory port, and the bus connection is balanced and short. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0049] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for balancing timing, characterized in that: At least: Step 1: providing a design layout, wherein the design layout includes a plurality of design modules, and each of the design modules includes a plurality of ports; Step 2: define the design module that needs to be time-balanced; Step 3, formulating the design rules for the timing balance, the design rules comprising: placing the defined design modules relatively parallel with a set distance, the set distance being: the distance between two design modules is smaller than the design module with the smallest size among the design modules, so that when the ports between the defined design modules are connected, the total length of the connection is smaller than the total length of other positions; Step 4: re-arrange the positions of the plurality of design modules according to the design rules, and connect the ports between the design modules.

2. The method for balancing timing according to claim 1, characterized in that: The multiple design modules in step one include combinational logic circuits, sequential logic circuits and memories.

3. The method for balancing timing according to claim 2, characterized in that: The sequential logic circuit in step 1 is a register circuit.

4. The method for balancing timing according to claim 3, characterized in that: The registers in step one include an address register and a data register.

5. The method for balancing timing according to claim 4, characterized in that: The design module that needs to perform the timing balance in step 2 is the register.

6. The method for balancing timing according to claim 4, characterized in that: The bus length in step three includes: the total length of the connection between the address port of the memory and the output port of the address register; and the total length of the connection between the data port of the memory and the input port of the data register.

7. The method for balancing timing according to claim 4, characterized in that: In step 4, the port connections between the memory and the address register and the data register are reset according to the design rule.

8. The method for balancing timing according to claim 7, characterized in that: The method further comprises step five of performing circuit timing simulation verification on the design layout reset according to the design rules.

9. The method for balancing timing according to claim 8, characterized in that: The timing simulation verification in step five ensures that the delay difference of data transmission between the address register and the data register is less than 0.05ns.

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