A bias circuit and radio frequency power amplifier

Abstract

The embodiment of the application discloses a bias circuit and a radio frequency power amplifier, and relates to the technical field of electronic circuits. The bias circuit is used for providing a bias signal to a signal amplification circuit, and comprises a bias transistor and a stabilizing unit. The first end of the bias transistor is used for inputting a bias power supply signal, the second end of the bias transistor is coupled to a power supply output node of a power supply, and is used for receiving a power supply voltage output by the power supply, and the third end of the bias transistor is coupled to an input node of the signal amplification circuit. Since the first end of the stabilizing unit is connected with the power supply output node and the second end of the stabilizing unit is coupled to the bias transistor, when voltage fluctuation occurs in the power supply voltage, the stabilizing unit can adjust the bias signal according to the voltage fluctuation amount of the power supply voltage, thereby adaptively adjusting the bias signal according to the voltage fluctuation generated by the power supply, improving the power supply rejection ratio, and further improving the stability and reliability of the bias circuit.

Description

Technical Field

[0001] This application belongs to the field of electronic circuit technology, and in particular relates to a bias circuit and a radio frequency power amplifier. Background Technology

[0002] As users' demands for communication quality from communication equipment continue to increase, the requirements for the stability of radio frequency (RF) signals transmitted and received by terminals and other communication devices are also growing. As a crucial component in RF circuits, the RF power amplifier can operate in different modes depending on actual needs; therefore, a bias circuit is required to provide a stable bias signal for the RF power amplifier.

[0003] However, in existing bias circuits, the power supply is used for power. But when the power supply voltage fluctuates due to faults or electromagnetic influences, the bias current output by the bias circuit can easily carry interference signals. When this bias signal is input to the RF power amplifier, the amplifier amplifies both the input RF signal and the interference signals, thus affecting the transmission and reception quality of the RF signal. Therefore, existing bias circuits suffer from poor stability. Summary of the Invention

[0004] This application provides a bias circuit and an RF power amplifier to solve the problem of poor stability in existing bias circuits.

[0005] In a first aspect, embodiments of this application provide a bias circuit for providing a bias signal to a signal amplification circuit, the bias circuit comprising:

[0006] A bias transistor, wherein the first terminal of the bias transistor is used to input a bias power supply signal, the second terminal of the bias transistor is coupled to the power supply output node of the power supply to receive the power supply voltage output by the power supply, and the third terminal of the bias transistor is coupled to the input node of the signal amplification circuit.

[0007] The stabilization unit has a first end connected to the power supply output node and a second end coupled to the bias transistor. The stabilization unit is used to adjust the bias signal according to the amount of voltage fluctuation when the power supply voltage fluctuates.

[0008] Furthermore, the stabilizing unit includes: a first stabilizing circuit;

[0009] The first terminal of the first stabilizing circuit is connected to the power supply output node, and the second terminal of the first stabilizing circuit is coupled to the first terminal of the bias transistor. The first stabilizing circuit is used to adjust the voltage of the first terminal of the bias transistor according to the amount of voltage fluctuation when the power supply voltage fluctuates.

[0010] Furthermore, a second stabilizing circuit;

[0011] The first terminal of the second stabilizing circuit is connected to the power supply output node, and the second terminal of the second stabilizing circuit is coupled to the third terminal of the bias transistor. The second stabilizing circuit is used to adjust the voltage of the third terminal of the bias transistor according to the amount of voltage fluctuation when the power supply voltage fluctuates.

[0012] Furthermore, the stabilizing unit includes: a first stabilizing unit and a second stabilizing unit;

[0013] The first terminal of the first stabilizing unit is connected to the power supply output node, and the second terminal of the first stabilizing unit is coupled to the first terminal of the bias transistor; the first stabilizing circuit is used to adjust the voltage of the first terminal of the bias transistor according to the amount of voltage fluctuation when the power supply voltage fluctuates.

[0014] The first terminal of the second stabilizing unit is connected to the power supply output node, and the second terminal of the second stabilizing unit is coupled to the third terminal of the bias transistor. The second stabilizing circuit is used to adjust the voltage of the third terminal of the bias transistor according to the amount of voltage fluctuation when the power supply voltage fluctuates.

[0015] Furthermore, the first stabilizing circuit includes a first capacitor;

[0016] The first end of the first capacitor serves as the first end of the first stabilizing circuit and is used to connect to the power supply output node. The second end of the first capacitor serves as the second end of the first stabilizing circuit and is used to couple to the first end of the bias transistor.

[0017] Furthermore, the second stabilizing circuit includes a second capacitor;

[0018] The first end of the second capacitor serves as the first end of the second stabilizing circuit and is used to connect to the power supply output node. The second end of the second capacitor serves as the second end of the second stabilizing circuit and is used to couple to the third end of the bias transistor.

[0019] Furthermore, the first stabilizing circuit also includes a first resistor and / or a first inductor, wherein the first resistor and / or the first inductor are connected in series with the first capacitor.

[0020] Furthermore, the second stabilizing circuit also includes a second resistor and / or a second inductor, wherein the second resistor and / or the second inductor are connected in series with the second capacitor.

[0021] Furthermore, the capacitance value of the first capacitor is positively correlated with the voltage fluctuation frequency of the power supply.

[0022] Furthermore, the capacitance value of the second capacitor is positively correlated with the voltage fluctuation frequency of the power supply.

[0023] Furthermore, the bias circuit also includes: a current source, a first diode, and a second diode;

[0024] The output terminal of the current source is connected to the first terminal of the first diode to form a bias control node. The bias control node is used to output the bias power supply signal to the first terminal of the bias transistor. The second terminal of the first diode is connected to the first terminal of the second diode, and the second terminal of the second diode is connected to the ground terminal.

[0025] Furthermore, the bias transistor is a BJT transistor, including a base, a collector, and an emitter. The base of the BJT transistor serves as the first terminal of the bias transistor, the collector of the BJT transistor serves as the second terminal of the bias transistor, and the emitter of the BJT transistor serves as the third terminal of the bias transistor.

[0026] The first aspect provides a bias circuit for providing a bias signal to a signal amplification circuit. The bias circuit includes a bias transistor and a stabilizing unit. A first terminal of the bias transistor is used to input a bias power supply signal. A second terminal of the bias transistor is coupled to a power supply output node of the power supply for receiving the power supply voltage output by the power supply. A third terminal of the bias transistor is coupled to an input node of the signal amplification circuit. Since the first terminal of the stabilizing unit is connected to the power supply output node, and the second terminal of the stabilizing unit is coupled to the bias transistor, the stabilizing unit can adaptively adjust the voltage of the first and / or third terminals of the bias transistor according to the amount of voltage fluctuation when voltage fluctuation occurs in the power supply voltage. This reduces the impact of voltage fluctuation on the first and / or third terminals of the bias transistor, reduces or eliminates the impact of voltage fluctuation on the bias signal, thereby improving the power supply rejection ratio and power supply stability, reducing memory effect, and ultimately improving the stability and reliability of the bias circuit.

[0027] Furthermore, since the bias circuit provided in the first aspect can adaptively adjust the bias signal according to the voltage fluctuations generated by the power supply, reduce or eliminate the impact of voltage fluctuations on the bias signal, and improve the stability of the bias circuit, it also broadens the application range of the bias circuit.

[0028] Secondly, embodiments of this application also provide a radio frequency power amplifier, including a signal amplification circuit and the bias circuit described in the first aspect;

[0029] The bias signal output terminal of the bias circuit is connected to the bias signal input node of the signal amplification circuit.

[0030] A second aspect provides an RF power amplifier that includes a signal amplification circuit and a bias circuit provided in the first aspect. In the bias circuit provided in the first aspect, a first terminal of a bias transistor is used to input a bias power supply signal, a second terminal of the bias transistor is coupled to the power supply output node of the power supply for receiving the power supply voltage output by the power supply, and a third terminal of the bias transistor is coupled to the input node of the signal amplification circuit. Since the first terminal of a stabilizing unit is connected to the power supply output node and the second terminal of the stabilizing unit is coupled to the bias transistor, when voltage fluctuations occur in the power supply voltage, the stabilizing unit can adaptively adjust the voltage of the first and / or third terminals of the bias transistor according to the amount of voltage fluctuation, reducing the impact of voltage fluctuations on the first and / or third terminals of the bias transistor. This ensures that the bias signal output by the bias transistor is not affected by the voltage fluctuation, guaranteeing the stability of the output bias signal, reducing or eliminating the impact of voltage fluctuations on the bias signal, thereby improving the power supply rejection ratio and power supply stability, reducing memory effects, and ultimately enhancing the reliability and linearity of the RF power amplifier.

[0031] Furthermore, since the bias circuit provided in the first aspect can adaptively adjust the bias signal according to the voltage fluctuations generated by the power supply, reduce or eliminate the impact of voltage fluctuations on the bias signal, and improve the stability of the bias circuit, it also broadens the application range of the bias circuit. Attached Figure Description

[0032] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figure 1 This is a schematic diagram of a bias circuit provided in an embodiment of this application;

[0034] Figure 2 This is a schematic diagram of the specific structure of a bias circuit provided in an embodiment of this application. Figure 1 ;

[0035] Figure 3 This is a schematic diagram of the specific structure of a bias circuit provided in an embodiment of this application. Figure 2 ;

[0036] Figure 4 This is a schematic diagram of the specific structure of a bias circuit provided in an embodiment of this application. Figure 3 ;

[0037] Figure 5 This is a specific circuit of a bias circuit provided in an embodiment of this application. Figure 1 ;

[0038] Figure 6 This is a specific circuit of a bias circuit provided in an embodiment of this application. Figure 2 ;

[0039] Figure 7 This is a specific circuit of a bias circuit provided in an embodiment of this application. Figure 3 ;

[0040] Figure 8 This is a specific circuit diagram of a bias circuit provided in another embodiment of this application;

[0041] Figure 9 This is a schematic diagram of the structure of a radio frequency power amplifier provided in an embodiment of this application. Detailed Implementation

[0042] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0043] Please see Figure 1 , Figure 1 This is a schematic diagram of a bias circuit provided in an embodiment of this application. Figure 1 As shown, the bias circuit 100 provides a bias signal to the signal amplification circuit 110. The bias circuit 100 includes a bias transistor 10 and a stabilizing unit 20. Specifically:

[0044] exist Figure 1 In this circuit, the first terminal 11 of the bias transistor 10 is used to input a bias power supply signal, the second terminal 12 of the bias transistor 10 is coupled to the power supply output node P1 of the power supply 120 to receive the power supply voltage output by the power supply 120, and the third terminal 13 of the bias transistor 10 is coupled to the input node of the signal amplification circuit 110. The first terminal of the stabilization unit 20 is connected to the power supply output node P1, and the second terminal is coupled to the bias transistor 10. The stabilization unit 20 is used to adjust the bias signal according to the amount of voltage fluctuation when voltage fluctuation occurs in the power supply voltage. Optionally, the bias power supply signal can be a bias current source signal or a bias voltage source signal.

[0045] In this embodiment, the bias transistor 10 outputs a bias signal to the signal amplification circuit 110 under the combined action of the bias power supply signal and the supply voltage. Here, the bias power supply signal can be a power supply signal output to the first terminal 11 of the bias transistor 10 by other functional units outside the bias circuit 100. For example, the bias power supply signal is a bias current source signal sent by a bias current source connected to the bias circuit 100, or the bias power supply signal is a bias voltage source signal sent by a bias voltage source connected to the bias circuit 100. In specific implementations, a control unit is usually also included. This control unit can be a controller in the RF circuit where the bias circuit 100 is located, or a controller in the signal amplification circuit connected to the bias circuit 100, used to control the amplification process of the RF signal.

[0046] In all embodiments of this application, the second terminal 12 of the bias transistor 10 is coupled to the power supply output node P1 of the power supply 120. Specifically, the second terminal 12 of the bias transistor 10 can be directly connected to the power supply output node P1, or it can be connected to the power supply output node P1 of the power supply 120 through a series inductive device, such as an inductor. The first terminal of the stabilizing unit 20 is connected to the power supply output node P1, and the second terminal is coupled to the bias transistor 10. That is, the stabilizing unit 20 is connected to the power supply output node P1 so that when voltage fluctuations occur in the power supply, it outputs a corresponding adjustment electrical signal to the bias transistor 10 coupled to the second terminal of the stabilizing unit 20, thereby reducing or eliminating the impact of the voltage fluctuations on the bias signal output by the bias transistor 10.

[0047] As an example, the bias transistor 10 is a BJT transistor, including a base, a collector, and an emitter. The base of the BJT transistor serves as the first terminal 11 of the bias transistor 10, the collector of the BJT transistor serves as the second terminal 12 of the bias transistor 10, and the emitter of the BJT transistor serves as the third terminal 13 of the bias transistor 10.

[0048] It is easy to understand that, in practical implementation, a MOS transistor, similar to a BJT, can also be used as the bias transistor. Since the equivalent replacement devices for the functions or roles of BJT transistors, MOS transistors, and various bias transistors are common knowledge in the field, they will not be elaborated on below.

[0049] In implementation, the second end of the stabilizing unit 20 can be connected to the first end 11 and / or the third end 13 of the bias transistor 10 to achieve coupling with the bias transistor 10.

[0050] As an example, the second terminal of the stabilizing unit 20 is connected to the first terminal 11 of the bias transistor 10. Since the first terminal 11 of the bias transistor 10 is used to input the bias power supply signal, when the supply voltage fluctuates, the stabilizing unit 20 can adaptively adjust the voltage and / or current of the first terminal 11 of the bias transistor 10 according to the amount of voltage fluctuation of the supply voltage, so that the voltage and / or current of the first terminal 11 of the bias transistor 10 can change according to the amount of voltage fluctuation of the supply voltage.

[0051] Similar to the previous example, as another example, the stabilizing unit 20 is connected to the third terminal 131 of the bias transistor 10. Since the third terminal of the bias transistor 10 is used to couple to the input node of the signal amplification circuit 110, that is, the third terminal of the bias transistor 10 is used to output a bias signal to the signal amplification circuit 110, when the supply voltage fluctuates, the stabilizing unit 20 can adaptively adjust the voltage and / or current of the third terminal 131 of the bias transistor 10 according to the amount of voltage fluctuation of the supply voltage, so that the voltage and / or current of the third terminal 131 of the bias transistor 10 can change according to the amount of voltage fluctuation of the supply voltage.

[0052] Combining the two examples above, as one example, when the stabilizing unit 20 is connected to the first terminal 11 and the third terminal 13 of the bias transistor 10, since the first terminal 11 of the bias transistor 10 is used to input the bias power supply signal, and the third terminal 13 of the bias transistor 10 is used to couple to the input node of the signal amplifier circuit 110, when the supply voltage fluctuates, the stabilizing unit 20 can adaptively adjust the voltage and / or current of the first terminal 11 of the bias transistor 10, and adjust the voltage and / or current of the third terminal 13 of the bias transistor 10 according to the amount of voltage fluctuation in the supply voltage, so that the voltage and / or current of the third terminal 13 of the bias transistor 10 can change according to the amount of voltage fluctuation in the supply voltage. In implementation, the stabilizing unit 20 can be configured to have two connection terminals, respectively used to connect the first terminal 11 and the third terminal 13 of the bias transistor 10, thereby enabling the voltage and / or current of the first terminal 11 and the third terminal 13 of the bias transistor 10 to change according to the amount of voltage fluctuation in the supply voltage.

[0053] In a specific implementation, the bias transistor 10 can be a transistor that is already available in the prior art, and under the action of the bias power supply signal and the supply voltage, it outputs a bias signal to the signal amplification circuit 110.

[0054] In other possible implementations, the stabilizing unit 20 can also be a voltage conversion circuit or a current conversion circuit. It takes the voltage fluctuation of the power supply voltage output by the power supply 120 as input. When the power supply voltage fluctuates, it transmits the fluctuating voltage in the power supply voltage to the bias transistor 10 according to the voltage fluctuation. Preferably, the fluctuating voltage is an AC signal, so that the bias signal output by the bias transistor 10 is not affected by the fluctuating voltage when it is affected by the voltage fluctuation, thereby ensuring the stability of the output bias signal.

[0055] In the bias circuit provided by the above scheme, the first terminal of the bias transistor is used to input the bias power supply signal, the second terminal of the bias transistor is coupled to the power supply output node of the power supply to receive the power supply voltage output by the power supply, and the third terminal of the bias transistor is coupled to the input node of the signal amplification circuit. Since the stabilization unit is connected to the power supply output node and coupled to the bias transistor, when the power supply voltage fluctuates, the stabilization unit can adaptively adjust the voltage of the first terminal and / or the third terminal of the bias transistor according to the amount of voltage fluctuation, thereby reducing the impact of voltage fluctuation on the first terminal and / or the third terminal of the bias transistor. This enables adaptive adjustment of the bias signal according to the voltage fluctuation generated by the power supply, ensuring that the bias signal output by the bias transistor is not affected by the voltage fluctuation when it is affected by the voltage fluctuation, thus guaranteeing the stability of the output bias signal, reducing or eliminating the impact of voltage fluctuation on the bias signal, and improving the stability of the bias circuit.

[0056] Furthermore, since the bias circuit provided in the first aspect can adaptively adjust the bias signal according to the voltage fluctuations generated by the power supply, reduce or eliminate the impact of voltage fluctuations on the bias signal, and improve the stability of the bias circuit, it also broadens the application range of the bias circuit.

[0057] Figure 2 This is a schematic diagram of the specific structure of a bias circuit provided in an embodiment of this application. Figure 1 .like Figure 2 As shown, in one embodiment, the stabilization unit 20 includes a first stabilization circuit 21.

[0058] The first terminal of the first stabilizing circuit 21 is connected to the power supply output node, and the second terminal of the first stabilizing circuit 21 is coupled to the first terminal 11 of the bias transistor 10. The first stabilizing circuit 21 is used to adjust the voltage of the first terminal 11 of the bias transistor 10 according to the amount of voltage fluctuation when the power supply voltage fluctuates.

[0059] In this embodiment, the first stabilizing circuit 21 responds to the voltage fluctuation of the supply voltage. Specifically, the first stabilizing circuit 21 is coupled between the power supply output node of the power supply 120 and the first terminal 11 of the bias transistor 10. This allows the first stabilizing circuit 21 to adjust the voltage of the first terminal 11 of the bias transistor 10 according to the magnitude of the supply voltage fluctuation. Here, since the first terminal 11 of the bias transistor 10 is used to input the bias power supply signal, when the supply voltage fluctuates, the first stabilizing circuit 21 can adaptively adjust the voltage of the first terminal 11 of the bias transistor 10 according to the magnitude of the supply voltage fluctuation. This ensures that the bias signal output by the bias transistor 10 is not affected by the voltage fluctuation, thereby guaranteeing the stability of the output bias signal.

[0060] Figure 3 This is a schematic diagram of the specific structure of a bias circuit provided in an embodiment of this application. Figure 2 .like Figure 3 As shown, in one embodiment, the stabilizing unit 20 includes a second stabilizing circuit 22.

[0061] The first terminal of the second stabilizing circuit 22 is connected to the power supply output node, and the second terminal of the second stabilizing circuit 22 is coupled to the third terminal 13 of the bias transistor 10. The second stabilizing circuit 22 is used to adjust the voltage of the third terminal 13 of the bias transistor 10 according to the amount of voltage fluctuation when the power supply voltage fluctuates.

[0062] In this embodiment, the second stabilizing circuit 22 responds to the voltage fluctuation of the supply voltage. Specifically, the second stabilizing circuit 22 is coupled between the power supply output node of the power supply 120 and the third terminal 13 of the bias transistor 10. This allows the second stabilizing circuit 22 to adjust the voltage of the third terminal 13 of the bias transistor 10 according to the magnitude of the supply voltage fluctuation. Here, since the third terminal 13 of the bias transistor 10 is used to couple to the input node of the signal amplification circuit 110, i.e., the third terminal 13 of the bias transistor 10 is used to output a bias signal to the signal amplification circuit 110, when the stabilizing unit 20 detects a voltage fluctuation in the supply voltage, it can adjust the voltage of the third terminal 13 of the bias transistor 10 according to the magnitude of the supply voltage fluctuation. This ensures that the bias signal output by the bias transistor 10 is not affected by the voltage fluctuation, thereby guaranteeing the stability of the output bias signal.

[0063] Figure 4 This is a schematic diagram of the specific structure of a bias circuit provided in an embodiment of this application. Figure 3 .like Figure 4 As shown in the figure, as an embodiment, the stabilizing unit 20 includes a first stabilizing unit 21 and a second stabilizing unit 22.

[0064] The first terminal of the first stabilizing unit 21 is connected to the power supply output node, and the second terminal of the first stabilizing unit 21 is coupled to the first terminal 11 of the bias transistor 10. The first stabilizing circuit 21 is used to adjust the voltage of the first terminal 11 of the bias transistor 10 according to the amount of voltage fluctuation when the power supply voltage fluctuates. The first terminal of the second stabilizing circuit 22 is connected to the power supply output node, and the second terminal of the second stabilizing circuit 22 is coupled to the third terminal 13 of the bias transistor 10. The second stabilizing circuit 22 is used to adjust the voltage of the third terminal 13 of the bias transistor 10 according to the amount of voltage fluctuation when the power supply voltage fluctuates.

[0065] In this embodiment, the stabilization unit 20 includes a first stabilization unit 21 and a second stabilization unit 22. That is, when voltage fluctuations occur in the supply voltage, the first stabilization unit 21 and the second stabilization unit 22 adjust the voltage at the first terminal 11 and the third terminal 13 of the bias transistor 10 respectively according to the amount of voltage fluctuation. Here, since the first terminal 11 of the bias transistor 10 is used to input the bias power supply signal, and the third terminal 13 of the bias transistor 10 is used to couple to the input node of the signal amplification circuit 110, when voltage fluctuations occur in the supply voltage, the first stabilization unit 21 and the second stabilization unit 22 can adjust the voltage at the first terminal 11 and the third terminal 13 of the bias transistor 10 respectively according to the amount of voltage fluctuation, so that the bias signal output by the bias transistor 10 is not affected by the voltage fluctuation, thereby ensuring the stability of the output bias signal. In implementation, both the first stabilizing unit 21 and the second stabilizing unit 22 have connection terminals, which are used to connect the first terminal 11 of the bias transistor 10 and the third terminal 13 of the bias transistor 10, respectively. This ensures that when the supply voltage fluctuates, the bias signal output by the bias transistor 10 is not affected by the voltage fluctuation, thereby guaranteeing the stability of the output bias signal.

[0066] Understandable Figure 4 In the illustrated embodiment, the first stabilizing unit 21 and the second stabilizing unit 22 are respectively in Figure 2 In the corresponding embodiments and Figure 3 The corresponding embodiments illustrate this in detail, so they will not be repeated here.

[0067] Figure 5 This is a specific circuit of a bias circuit provided in an embodiment of this application. Figure 1 .like Figure 5 As shown, with Figure 2Based on the corresponding embodiment, as one implementation of this embodiment, the first stabilizing circuit 21 includes a first capacitor C1. The first end of the first capacitor C1 serves as the first end of the first stabilizing circuit 21 and is used to connect to the power supply output node, and the second end of the first capacitor C1 serves as the second end of the first stabilizing circuit 21 and is used to couple to the first end 11 of the bias transistor 10.

[0068] As an example, the capacitance value of the first capacitor C1 is positively correlated with the voltage fluctuation frequency of the power supply 120.

[0069] Here, the capacitance value of the first capacitor C1 is positively correlated with the voltage fluctuation frequency of the power supply 120. This means that in practical implementation, the selection of the first capacitor C1 is proportional to the voltage fluctuation frequency of the power supply 120. If the frequency of voltage fluctuation in the power supply 120 is higher, then a capacitor with a higher capacitance value should be selected as the first capacitor C1.

[0070] In this embodiment, the first terminal of the first capacitor C1 serves as the first terminal of the first stabilizing circuit 21 and is connected to the power supply output node. The second terminal of the first capacitor C1 is coupled to the first terminal 11 of the bias transistor 10. Here, when voltage fluctuations occur in the power supply voltage, the two electrode plates connected by the first and second terminals of the first capacitor C1 transmit corresponding fluctuating AC signals to the first terminal 11 of the bias transistor 10 through the second terminal of the first capacitor C1 under the influence of the voltage fluctuations. This ensures that the bias signal output by the bias transistor 10 is not affected by the voltage fluctuations, thereby guaranteeing the stability of the output bias signal.

[0071] In practical applications, during the process of the first capacitor C1 outputting an adjustment voltage to the first terminal 11 of the bias transistor 10 according to voltage fluctuations, in order to adjust the voltage or current value of the adjustment voltage, a corresponding voltage divider branch or current limiting branch can be configured for the first capacitor C1. The voltage divider branch or current limiting branch performs current limiting or voltage division operation on the adjustment voltage output from the second terminal of the first capacitor C1, and then the current-limited adjustment voltage is output to the first terminal 11 of the bias transistor 10, or the voltage-divided adjustment voltage is output to the first terminal 11 of the bias transistor 10.

[0072] As one implementation of this embodiment, the first stabilizing circuit 21 further includes a first resistor and / or a first inductor, which are connected in series with the first capacitor.

[0073] In this embodiment, the first resistor and / or the first inductor are connected in series with the first capacitor C1 as a series branch in the first stabilizing circuit 21. Here, the second terminal of the first capacitor C1 is coupled to the first terminal 11 of the bias transistor 10 through the series branch formed by the first resistor and / or the first inductor.

[0074] For example, when the first stabilizing circuit 21 also includes a first resistor, the first resistor is connected in series with the second end of the first capacitor C1, that is, the first end of the first resistor is connected to the second end of the first capacitor C1, the second end of the first resistor is connected to the first end 11 of the bias transistor 10, and the second end of the first capacitor C1 is coupled to the first end 11 of the bias transistor 10 through the first resistor.

[0075] For example, when the first stabilizing circuit 21 also includes a first inductor, the first inductor is connected in series with the second end of the first capacitor C1, that is, the first end of the first inductor is connected to the second end of the first capacitor C1, the second end of the first inductor is connected to the first end 11 of the bias transistor 10, and the second end of the first capacitor C1 is coupled to the first end 11 of the bias transistor 10 through the first inductor.

[0076] For example, when the first stabilizing circuit 21 also includes a first resistor and a first inductor, the first resistor and the first inductor are connected in series to form a series branch. The first end of the series branch is connected in series with the second end of the first capacitor C1, that is, the first end of the series branch is connected to the second end of the first capacitor C1, and the second end of the series branch is connected to the first end 11 of the bias transistor 10. The second end of the first capacitor C1 is coupled to the first end 11 of the bias transistor 10 through the series branch.

[0077] Figure 6 This is a specific circuit of a bias circuit provided in an embodiment of this application. Figure 2 .like Figure 6 As shown, with Figure 3 Based on the corresponding embodiment, as one implementation of this embodiment, the second stabilizing circuit 22 includes a second capacitor C2. The first end of the second capacitor C2 serves as the first end of the second stabilizing circuit 22 and is used to connect to the power supply output node. The second end of the second capacitor C2 serves as the second end of the second stabilizing circuit 22 and is used to couple to the third end 13 of the bias transistor 10.

[0078] As an example, the capacitance value of the second capacitor C2 is positively correlated with the voltage fluctuation frequency of the power supply 120.

[0079] Here, the capacitance value of the second capacitor C2 is positively correlated with the voltage fluctuation frequency of the power supply 120. This means that in practical implementation, the selection of the second capacitor C2 is proportional to the voltage fluctuation frequency of the power supply 120. If the voltage fluctuation frequency of the power supply 120 is higher, then a capacitor with a higher capacitance value should be selected as the second capacitor C2.

[0080] In this embodiment, the first terminal of the second capacitor C2 serves as the first terminal of the second stabilizing circuit 22 and is connected to the power supply output node. The second terminal of the second capacitor C2 is coupled to the third terminal 13 of the bias transistor 10. Here, when voltage fluctuations occur in the power supply voltage, the two electrode plates connected by the first and second terminals of the second capacitor C2 transmit corresponding fluctuating AC signals to the third terminal 13 of the bias transistor 10 through the second terminal of the second capacitor C2 under the influence of the voltage fluctuations. This ensures that the bias signal output by the bias transistor 10 is not affected by the voltage fluctuations, thereby guaranteeing the stability of the output bias signal.

[0081] In practical applications, during the process of the second capacitor C2 outputting an adjustment voltage to the third terminal 13 of the bias transistor 10 according to voltage fluctuations, in order to adjust the voltage or current value of the adjustment voltage, a corresponding voltage divider branch or current limiting branch can be configured for the second capacitor C2. The voltage divider branch or current limiting branch performs current limiting or voltage division operation on the adjustment voltage output from the second terminal of the second capacitor C2, and then the current-limited adjustment voltage is output to the third terminal 13 of the bias transistor 10, or the voltage-divided adjustment voltage is output to the third terminal 13 of the bias transistor 10.

[0082] As one implementation of this embodiment, the second stabilizing circuit 22 further includes a second resistor and / or a second inductor, which are connected in series with the second capacitor.

[0083] In this embodiment, the second resistor and / or the second inductor are connected in series with the second capacitor C2 as a series branch in the second stabilizing circuit 22. Here, the second terminal of the second capacitor C2 is coupled to the third terminal 13 of the bias transistor 10 through the series branch formed by the second resistor and / or the second inductor.

[0084] For example, when the second stabilizing circuit 22 also includes a second resistor, the second resistor is connected in series with the second terminal of the second capacitor C2, that is, the first terminal of the second resistor is connected to the second terminal of the second capacitor C2, the second terminal of the second resistor is connected to the third terminal 13 of the bias transistor 10, and the second terminal of the second capacitor C2 is coupled to the third terminal 13 of the bias transistor 10 through the second resistor.

[0085] For example, when the second stabilizing circuit 22 also includes a second inductor, the second inductor is connected in series with the second terminal of the second capacitor C2, that is, the first terminal of the second inductor is connected to the second terminal of the second capacitor C2, the second terminal of the second inductor is connected to the third terminal 13 of the bias transistor 10, and the second terminal of the second capacitor C2 is coupled to the third terminal 13 of the bias transistor 10 through the second inductor.

[0086] For example, when the second stabilizing circuit 22 also includes a second resistor and a second inductor, the second resistor and the second inductor are connected in series to form a series branch. The first end of the series branch is connected in series with the second end of the second capacitor C2, that is, the first end of the series branch is connected to the second end of the second capacitor C2. The second end of the series branch is connected to the third end 13 of the bias transistor 10. The second end of the second capacitor C2 is coupled to the third end 13 of the bias transistor 10 through the series branch.

[0087] Figure 7 This is a specific circuit of a bias circuit provided in an embodiment of this application. Figure 3 .like Figure 7 As shown, with Figure 4 Based on the corresponding embodiment, as one implementation of this embodiment, the first stabilizing circuit 21 includes a first capacitor C1. The first terminal of the first capacitor C1 serves as the first terminal of the first stabilizing circuit 21, and the second terminal of the first capacitor C1 is used to couple to the first terminal 11 of the bias transistor 10. The second stabilizing circuit 22 includes a second capacitor C2. The first terminal of the second capacitor C2 serves as the first terminal of the second stabilizing circuit 22, and the second terminal of the second capacitor C2 is used to couple to the third terminal 13 of the bias transistor 10.

[0088] In this embodiment, when the supply voltage fluctuates, the first capacitor C1 and the second capacitor C2 adjust the voltage at the first terminal 11 and the third terminal 13 of the bias transistor 10 according to the amount of voltage fluctuation. Here, since the first terminal 11 of the bias transistor 10 is used to input the bias power supply signal, and the third terminal 13 of the bias transistor 10 is used to couple to the input node of the signal amplification circuit 110, when the supply voltage fluctuates, the first capacitor C1 and the second capacitor C2 can adjust the voltage at the first terminal 11 and the third terminal 13 of the bias transistor 10 according to the amount of voltage fluctuation. This ensures that the bias signal output by the bias transistor 10 is not affected by the voltage fluctuation, thereby improving the power supply rejection ratio and power supply stability, reducing memory effect, and ultimately improving the stability and reliability of the bias circuit.

[0089] The following combination Figures 5 to 7 The working principle of the bias circuit 100 provided in this embodiment will be illustrated by an example.

[0090] For example, assume that the voltage at the first terminal 11 of the bias transistor 10 is Vb, the voltage at the second terminal 12 of the bias transistor 10 is Vc, and the voltage at the third terminal 13 of the bias transistor 10 is Ve. When the supply voltage output by the power supply 120 fluctuates, the voltage Vc at the second terminal 12 of the bias transistor 10 is affected by the amount of voltage fluctuation of the supply voltage, resulting in a corresponding voltage fluctuation ΔVc.

[0091] As an example, in Figure 5 In this circuit, since the first terminal of the first capacitor C1 and the second terminal 12 of the bias transistor 10 are both connected to the power supply 120, and since the second terminal of the first capacitor C1 is connected to the first terminal 11 of the bias transistor 10, the first capacitor C1 can adaptively transmit the voltage fluctuation ΔV to the first terminal 11 of the bias transistor 10 according to the power supply 120. Therefore, when the first capacitor C1 is affected by the voltage fluctuation ΔVc, the first capacitor C1 can adaptively output a corresponding voltage fluctuation to the first terminal 11 of the bias transistor 10, that is, based on the voltage Vb at the first terminal 11 of the bias transistor 10, an additional voltage fluctuation is added. The voltage at the first terminal 11 of the bias transistor 10 changes according to the voltage change at the second terminal 12 of the bias transistor 10. This regulates the bias signal output by the bias transistor 10, ensuring that the bias signal output by the bias transistor 10 is not affected by voltage fluctuations, thus guaranteeing the stability of the output bias signal. This weakens or eliminates interference signals carried in the output bias signal caused by voltage fluctuations, thereby improving the power supply rejection ratio and power supply stability, reducing memory effect, and ultimately improving the stability and reliability of the bias circuit.

[0092] Similar to the previous example, in Figure 6 In this circuit, since the first terminal of the second capacitor C2 is connected to the power supply 120 together with the second terminal 12 of the bias transistor 10, and since the second terminal of the second capacitor C2 is connected to the third terminal 13 of the bias transistor 10, the second capacitor C2 can adaptively transmit the voltage fluctuation ΔV to the third terminal 13 of the bias transistor 10 according to the power supply 120. Therefore, when the second capacitor C2 is affected by the voltage fluctuation ΔVc, it can output a corresponding voltage fluctuation to the third terminal 13 of the bias transistor 10. That is, based on the voltage Ve at the third terminal 13 of the bias transistor 10, the voltage fluctuation ΔVc is increased, so that the voltage at the third terminal 13 of the bias transistor 10 can change according to the voltage change at the second terminal 12 of the bias transistor 10. This plays a role in regulating the bias signal output by the bias transistor 10, so that the bias signal output by the bias transistor 10 is not affected by the voltage fluctuation, ensuring the stability of the output bias signal. This weakens or eliminates the interference signal carried in the output bias signal of the bias transistor 10 due to voltage fluctuation, thereby improving the power supply rejection ratio and power supply stability, reducing the memory effect, and thus improving the stability and reliability of the bias circuit.

[0093] Combining the two examples above, in Figure 7In this configuration, the first capacitor C1 and the second capacitor C2 are connected to the same bias transistor. Since the second terminal of the first capacitor C1 is connected to the first terminal 11 of the bias transistor 10, and the second terminal of the second capacitor C2 is connected to the third terminal 13 of the bias transistor 10, when the first capacitor C1 and the second capacitor C2 are affected by voltage fluctuation ΔVc, they can adaptively output corresponding voltage fluctuation ΔVc to the first terminal 11 and the third terminal 13 of the bias transistor 10, respectively. That is, at the first terminal 11 and the third terminal 13 of the bias transistor 10... The third terminal 13 is subjected to a voltage fluctuation ΔVc, so that the voltages of the first terminal 11 and the third terminal 13 of the bias transistor 10 can change according to the voltage change of the second terminal 12 of the bias transistor 10. This plays a role in adjusting the bias signal output by the bias transistor 10, so that the bias signal output by the bias transistor 10 is not affected by the voltage fluctuation, ensuring the stability of the output bias signal, thereby weakening or eliminating the interference signal carried in the bias signal output by the bias transistor 10 due to voltage fluctuation.

[0094] Figure 8 This is a specific circuit diagram of a bias circuit provided in another embodiment of this application. For example... Figure 8 As shown, with Figures 1 to 7 Based on any corresponding embodiment, as one embodiment, the bias circuit 100 further includes: a current source S1, a first diode D1, and a second diode D2.

[0095] The output terminal of the current source S1 is connected to the first terminal of the first diode D1 to form a bias control node P2. The bias control node P2 is used to output a bias power supply signal to the first terminal 11 of the bias transistor 10. The second terminal of the first diode D1 is connected to the first terminal of the second diode D2, and the second terminal of the second diode D2 is connected to the ground terminal.

[0096] In this embodiment, the current source S1, the first diode D1, and the second diode are connected in series. A bias control node P2 is formed at the point where the output terminal of the current source S1 is connected to the first terminal of the first diode D1. The bias control node P2 is used to connect to the first terminal 11 of the bias transistor 10, and the current source S1 outputs a bias power signal to the first terminal 11 of the bias transistor 10 through the bias control node P2.

[0097] It should be noted that, due to the unidirectional conduction characteristic of diodes and the existence of a rated voltage difference across their terminals, the first diode D1 and the second diode D2 are connected in series to form a voltage divider branch. Here, the first terminal of the first diode D1 serves as the first terminal of this voltage divider branch and is connected to the output terminal of the current source S1. The first terminal of the second diode D2 is connected to the second terminal of the first diode D1, and the second terminal of the second diode D2 serves as the second terminal of this voltage divider branch and is connected to the ground terminal. The current source S1 is connected to the first terminal of this voltage divider branch, simultaneously forming a bias control node P2 for connecting the first terminal 11 of the bias transistor 10. The second terminal of the voltage divider branch is connected to the ground terminal, forming a power supply loop.

[0098] It is easy to understand that, in actual implementation, different diodes can be selected as the first diode D1 and the second diode D2 in series according to actual needs, so as to obtain different voltage divider branches, thereby realizing the output of different bias power supply signals to the bias control node P2.

[0099] Figure 9 A schematic diagram of the structure of a radio frequency power amplifier provided in an embodiment of this application is shown. Figure 9 As shown, a radio frequency power amplifier 200 includes a signal amplification circuit 110 and a bias circuit 100 as described in the above embodiment.

[0100] The bias current output terminal of the bias circuit 100 is connected to the input node of the signal amplifier circuit 110.

[0101] The above-described solution provides an RF power amplifier including a signal amplification circuit and a bias circuit as provided in the previous embodiment. In the bias circuit, the first terminal of the bias transistor is used to input a bias power supply signal, the second terminal of the bias transistor is coupled to the power supply output node of the power supply to receive the power supply voltage output by the power supply, and the third terminal of the bias transistor is coupled to the input node of the signal amplification circuit. Since the stabilization unit is connected to the power supply output node and coupled to the bias transistor, when the power supply voltage fluctuates, the stabilization unit can adaptively adjust the voltage of the first and / or third terminals of the bias transistor according to the amount of voltage fluctuation, reducing the impact of voltage fluctuation on the first and / or third terminals of the bias transistor. This ensures that the bias signal output by the bias transistor is not affected by the voltage fluctuation, guaranteeing the stability of the output bias signal, reducing or eliminating the impact of voltage fluctuation on the bias signal, thereby improving the power supply rejection ratio and power supply stability, reducing memory effect, and thus enhancing the reliability and linearity of the RF power amplifier.

[0102] Furthermore, since the bias circuit provided in the first aspect can adaptively adjust the bias signal according to the voltage fluctuations generated by the power supply, reduce or eliminate the impact of voltage fluctuations on the bias signal, and improve the stability of the bias circuit, it also broadens the application range of the bias circuit.

[0103] It is understood that since the content and implementation of the radio frequency power amplifier 200 provided in this embodiment are already described in detail above, they will not be repeated here.

[0104] The units in the terminal of this application embodiment can be merged, divided, and deleted according to actual needs.

[0105] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A radio frequency power amplifier, characterized in that, It includes a signal amplification circuit and a bias circuit, wherein the bias circuit includes: A bias transistor, wherein the first terminal of the bias transistor is used to input a bias power supply signal, the second terminal of the bias transistor is coupled to the power supply output node of the power supply to receive the power supply voltage output by the power supply, and the third terminal of the bias transistor is coupled to the input node of the signal amplification circuit to output a bias signal to the signal amplification circuit. The stabilization unit has a first end connected to the power supply output node and a second end coupled to the bias transistor. The stabilization unit is used to adjust the bias signal according to the amount of voltage fluctuation when the power supply voltage fluctuates. The stabilizing unit includes a first stabilizing circuit and / or a second stabilizing circuit, wherein: The first terminal of the first stabilizing circuit is connected to the power supply output node, and the second terminal of the first stabilizing circuit is coupled to the first terminal of the bias transistor. The first stabilizing circuit is used to adjust the voltage of the first terminal of the bias transistor according to the amount of voltage fluctuation when the power supply voltage fluctuates. The first terminal of the second stabilizing circuit is connected to the power supply output node, and the second terminal of the second stabilizing circuit is coupled to the third terminal of the bias transistor. The second stabilizing circuit is used to adjust the voltage of the third terminal of the bias transistor according to the amount of voltage fluctuation when the power supply voltage fluctuates.

2. The radio frequency power amplifier according to claim 1, characterized in that, The first stabilizing circuit includes a first capacitor; The first end of the first capacitor serves as the first end of the first stabilizing circuit and is used to connect to the power supply output node. The second end of the first capacitor serves as the second end of the first stabilizing circuit and is used to couple to the first end of the bias transistor.

3. The radio frequency power amplifier according to claim 1, characterized in that, The second stabilizing circuit includes a second capacitor; The first end of the second capacitor serves as the first end of the second stabilizing circuit and is used to connect to the power supply output node. The second end of the second capacitor serves as the second end of the second stabilizing circuit and is used to couple to the third end of the bias transistor.

4. The radio frequency power amplifier according to claim 2, characterized in that, The first stabilizing circuit further includes a first resistor and / or a first inductor, wherein the first resistor and / or the first inductor are connected in series with the first capacitor.

5. The radio frequency power amplifier according to claim 3, characterized in that, The second stabilizing circuit further includes a second resistor and / or a second inductor, which are connected in series with the second capacitor.

6. The radio frequency power amplifier according to claim 2, characterized in that, The capacitance value of the first capacitor is positively correlated with the voltage fluctuation frequency of the power supply.

7. The radio frequency power amplifier according to claim 3, characterized in that, The capacitance value of the second capacitor is positively correlated with the voltage fluctuation frequency of the power supply.

8. The radio frequency power amplifier according to claim 1, characterized in that, The bias circuit further includes: a current source, a first diode, and a second diode; The output terminal of the current source is connected to the first terminal of the first diode to form a bias control node. The bias control node is used to output the bias power supply signal to the first terminal of the bias transistor. The second terminal of the first diode is connected to the first terminal of the second diode, and the second terminal of the second diode is connected to the ground terminal.

9. The radio frequency power amplifier according to any one of claims 1 to 8, characterized in that, The bias transistor is a BJT transistor, which includes a base, a collector, and an emitter. The base of the BJT transistor serves as the first terminal of the bias transistor, the collector of the BJT transistor serves as the second terminal of the bias transistor, and the emitter of the BJT transistor serves as the third terminal of the bias transistor.

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