Chip and inter-core communication method

Abstract

A chip and an inter-core communication method are disclosed. The chip comprises: a plurality of processing core groups, each processing core group comprising at least one processing core, any one of the plurality of processing core groups being connected to other processing core groups of the plurality of processing core groups through a network on chip (NOC); a plurality of local shared memory units (LMSUs), the plurality of LMSUs corresponding to the plurality of processing core groups one by one, each LMSU being connected to all processing cores in a corresponding processing core group through a first level node of the NOC; and a broadcast station, the broadcast station being connected to a second level node of the NOC and the plurality of LMSUs respectively.

Description

Technical Field

[0001] This disclosure relates to the field of chip technology, and more specifically, to chips that can improve the efficiency of inter-core communication, reduce the complexity of communication networks, save chip area and reduce costs, as well as inter-core communication methods for said chips. Background Technology

[0002] With increasingly demanding chip performance requirements, integrating multiple processor cores into a single chip has become a development trend. In many-core or multi-core architectures, inter-core communication has always been a key focus and challenge. Although Network on-chip (NOC) has been proposed as a communication method for Systems-on-Chip (SoC), and its performance is significantly better than traditional bus-based systems, the transmission of large amounts of data between cores generally causes congestion on the NOC, leading to excessively long transmission delays. Furthermore, synchronization issues between cores often require the addition of local dedicated memory, resulting in increased chip area and wasted resources. This is because some data is shared but needs to be copied multiple times. Summary of the Invention

[0003] The embodiments of this disclosure provide a chip, an inter-core communication method, an electronic device, and a computer-readable storage medium. By implementing the chip, the inter-core communication method, the electronic device, and the computer-readable storage medium, the efficiency of inter-core communication can be improved, the complexity of the communication network can be reduced, chip area can be saved, and costs can be reduced.

[0004] In one general aspect, a chip is provided, the chip comprising: a plurality of processing core groups, each processing core group including at least one processing core, any one of the plurality of processing core groups being connected to other processing core groups in the plurality of processing core groups via an on-chip network (NOC); a plurality of local shared storage units (LMSUs), each of the plurality of LMSUs corresponding one-to-one with the plurality of processing core groups, the LMSUs being connected to all processing cores within the corresponding processing core group via a first-level node of the NOC; and a broadcast station, the broadcast station being connected to a second-level node of the NOC and the plurality of LMSUs respectively.

[0005] By setting up an LMSU for each processing core group and a corresponding broadcast station within the chip, appropriate scheduling can be achieved in inter-core communication, effectively avoiding data transmission congestion and reducing transmission latency. Furthermore, by including LMSUs and broadcast stations within the chip, the amount of dedicated memory is reduced, thus saving chip area and lowering costs. Simultaneously, since multiple LMSUs correspond one-to-one with multiple processing core groups, the chip can be easily expanded.

[0006] Optionally, the LMSU includes: a receive directory for recording the data indexes of each processing core serving as a receiving core in the corresponding processing core group; a transmit enable chain for configuring each receiving core in this transmission by the processing core serving as a transmit core in the corresponding processing core group; a receive enable chain for configuring the working status of each processing core serving as a receiving core in the corresponding processing core group; a local memory for storing data; and a monitoring queue for monitoring the communication port between the LMSU and the broadcast station.

[0007] The RX directory, transmit enable chain, receive enable chain, and monitoring queue in LMSU can be flexibly configured to be compatible with single-core transmit / single-core receive as well as single-core transmit / multi-core receive scenarios, thus improving the efficiency of inter-core communication and reducing the complexity of the communication network.

[0008] Optionally, the transmit enable chains in the plurality of LMSUs are cascaded and mapped to the broadcast station.

[0009] In another general aspect, an inter-core communication method is provided for a chip including multiple processing core groups, each processing core group including at least one processing core, each processing core group being connected to a local shared memory unit (LMSU) via an on-chip network (NOC); the inter-core communication method includes: one processing core acting as a transmitting core accessing the LMSU corresponding to another processing core acting as a receiving core via the NOC; determining whether the receiving core is ready to receive based on parameters in the corresponding LMSU; and in response to the receiving core being ready to receive, the transmitting core transmitting data to the receiving core via the NOC, a broadcast station, and the corresponding LMSU, wherein the broadcast station is connected to the NOC and all the LMSUs respectively.

[0010] The above-mentioned inter-core communication method can effectively avoid data transmission congestion in the chip, reduce transmission latency in inter-core communication, improve the efficiency of inter-core communication, and reduce the complexity of the communication network.

[0011] Optionally, the inter-core communication method further includes: in response to the receiving core not being ready to receive, the sending core sends data to the corresponding LMSU through the NOC.

[0012] In another general aspect, an inter-core communication method is provided for a chip including multiple processing core groups, each processing core group including at least one processing core, each processing core group being connected to a Local Shared Memory Unit (LMSU) via an on-chip network (NOC); the inter-core communication method includes: a processing core acting as a sending core sending configuration information to the LMSU via the NOC and a broadcast station, the broadcast station being connected to a second-level node of the NOC and all the LMSUs respectively; in response to receiving a configuration completion message sent by the broadcast station, the sending core sending the data to each of the LMSUs via a first-level node of the NOC and the broadcast station.

[0013] The above-mentioned inter-core communication method can effectively avoid data transmission congestion in the chip, reduce transmission latency in inter-core communication, improve the efficiency of inter-core communication, and reduce the complexity of the communication network.

[0014] Optionally, the first LMSU determines, based on the configuration information, that there are multiple processing cores serving as receiving cores in the processing core group connected to the first LMSU; if the first LMSU determines that at least one of the multiple receiving cores is ready to receive, then the first LMSU sends the data to any of the ready receiving cores and saves the data; or if the first LMSU determines that none of the multiple receiving cores is ready to receive, then the first LMSU saves the data, wherein the first LMSU is any one of all the LMSUs.

[0015] In another general aspect, an inter-core communication method is provided for a chip including multiple processing core groups, each processing core group including at least one processing core, each processing core group being connected to a local shared memory unit (LMSU) via an on-chip network (NOC); the inter-core communication method includes: in response to executing an instruction to receive data, a first processing core queries the LMSU corresponding to the first processing core; in response to finding a record in the LMSU indicating that the first processing core is a receiving core, the first processing core reads data from the LMSU.

[0016] The above-mentioned inter-core communication method can effectively avoid data transmission congestion in the chip, reduce transmission latency in inter-core communication, improve the efficiency of inter-core communication, and reduce the complexity of the communication network.

[0017] Optionally, in response to the absence of a record in the LMSU indicating that the first processing core is a receiving core, the first processing core configures the LMSU to generate a record in the LMSU indicating that the first processing core is ready to receive, and a record indicating that the LMSU is monitoring the data transmitted by the broadcasting station.

[0018] Optionally, after the first processing core configures the LMSU to generate a record in the LMSU indicating that the first processing core is ready to receive, the inter-core communication method further includes: in response to the LMSU detecting data transmitted by the broadcasting station, the first processing core obtains the data transmitted by the broadcasting station from the LMSU.

[0019] In another general aspect, a computer-readable storage medium is provided that stores a computer program, which, when executed by a processor, implements the inter-core communication method as described above.

[0020] In another general aspect, an electronic device is provided, comprising: a processor implemented by the chip described above; and a memory storing a computer program to be executed by the processor.

[0021] In another general aspect, a computer program product is provided, the computer program product comprising a computer program that, when executed by a processor, implements the inter-core communication method as described above.

[0022] The chip, inter-core communication method, electronic device, and computer-readable storage medium according to the embodiments of this disclosure can solve the problems of excessive transmission latency, large memory area, and easy deadlock in traditional multi-core architectures, and have many advantages such as short transmission latency, flexible configuration, saving memory area, and easy expansion. Attached Figure Description

[0023] The above and other objects and features of the embodiments of this disclosure will become clearer from the following description taken in conjunction with the accompanying drawings, which exemplarily illustrate the embodiments, wherein:

[0024] Figure 1 This is a schematic diagram illustrating a chip according to an embodiment of the present disclosure;

[0025] Figure 2 This is a flowchart illustrating an inter-core communication method according to an embodiment of the present disclosure;

[0026] Figure 3 This is a flowchart illustrating an inter-core communication method according to another embodiment of the present disclosure;

[0027] Figure 4 This is a flowchart illustrating an inter-core communication method according to yet another embodiment of the present disclosure;

[0028] Figure 5 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure. Detailed Implementation

[0029] The following detailed embodiments are provided to aid the reader in gaining a comprehensive understanding of the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent upon understanding this disclosure. For example, the order of operations described herein is merely illustrative and is not limited to those orders set forth herein, but may be changed as will become clear upon understanding this disclosure, except for operations that must occur in a specific order. Furthermore, for clarity and conciseness, descriptions of features known in the art may be omitted.

[0030] The features described herein may be implemented in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided only to illustrate some of the many feasible ways of implementing the methods, apparatus, and / or systems described herein, which will become clear upon understanding the disclosure of this application.

[0031] As used herein, the term “and / or” includes any one of the associated listed items and any combination of any two or more.

[0032] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, assemblies, regions, layers, or parts, these components, assemblies, regions, layers, or parts should not be limited by these terms. Rather, these terms are used only to distinguish one component, assembly, region, layer, or part from another. Thus, without departing from the teaching of the examples described herein, the first component, first assembly, first region, first layer, or first part referred to as the first component, first assembly, first region, first layer, or first part may also be referred to as the second component, second assembly, second region, second layer, or second part.

[0033] In the specification, when an element (such as a layer, region, or substrate) is described as being "on" another element, "connected to," or "bonded to" another element, the element may be directly "on" another element, directly "connected to," or "bonded to" the other element, or one or more other elements may be present in between. Conversely, when an element is described as being "directly on" another element, "directly connected to," or "directly bonded to" another element, no other elements may be present in between.

[0034] The terminology used herein is for the purpose of describing various examples only and is not intended to limit disclosure. Unless the context clearly indicates otherwise, the singular form is intended to include the plural form as well. The terms “comprising,” “including,” and “having” indicate the presence of the described features, quantities, operations, components, elements, and / or combinations thereof, but do not preclude the presence or addition of one or more other features, quantities, operations, components, elements, and / or combinations thereof.

[0035] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains upon understanding this disclosure. Unless expressly defined herein, terms (such as those defined in a general dictionary) shall be interpreted as having a meaning consistent with their meaning in the context of the relevant field and in this disclosure, and shall not be interpreted in an idealized or overly formalistic manner.

[0036] Furthermore, in the description of the examples, detailed descriptions of well-known related structures or functions will be omitted when it is believed that such detailed descriptions would lead to a vague interpretation of this disclosure.

[0037] In the following description, embodiments will be illustrated with reference to the accompanying drawings. However, embodiments may be implemented in various forms and are not limited to the examples described herein.

[0038] Figure 1 This is a schematic diagram illustrating a chip according to an embodiment of the present disclosure.

[0039] Reference Figure 1 The chip according to embodiments of this disclosure may include multiple processing core groups 11, 12, 13, and 14, multiple local shared memory units (LMSUs) 21, 22, 23, and 24, and a broadcast station 30. Furthermore, the chip according to embodiments of this disclosure may also include a network on-chip (NOC), wherein the NOC includes first-level nodes NOC00, NOC01, NOC02, and NOC03, and a second-level node NOC20. Although the number of multiple processing core groups, multiple LMSUs, and the number of first-level nodes of the NOC are shown as four in the figures, embodiments of this disclosure are not limited thereto. The number of processing core groups, LMSUs, and first-level nodes of the NOC on the chip may be appropriately set according to design specifications.

[0040] Specifically, each processing core group includes at least one processing core, and any one of the processing core groups 11, 12, 13, and 14 is connected to the other processing core groups 11, 12, 13, and 14 via NOCs. For example, processing core group 11 can be connected to processing core groups 12, 13, and 14 via NOCs; processing core group 12 can be connected to processing core groups 11, 13, and 14 via NOCs; processing core group 13 can be connected to processing core groups 11, 12, and 14 via NOCs; and processing core group 14 can be connected to processing core groups 11, 12, and 13 via NOCs. Furthermore, processing core group 11 can be connected to processing core group 12 via NOC00, NOC20, and NOC01; to processing core group 23 via NOC00, NOC20, and NOC02; and to processing core group 13 via NOC00, NOC20, and NOC02.

[0041] Multiple LMSUs 21, 22, 23, and 24 correspond one-to-one with multiple processing core groups 11, 12, 13, and 14, and each LMSU can be connected to all processing cores within its corresponding processing core group via a first-level node of the NOC. For example, LMSU 21 corresponds to processing core group 11, LMSU 22 corresponds to processing core group 12, LMSU 23 corresponds to processing core group 13, and LMSU 24 corresponds to processing core group 14. Furthermore, LMSU 21 can be connected to processing core group 11 via first-level node NOC00, LMSU 22 can be connected to processing core group 12 via first-level node NOC01, LMSU 22 can be connected to processing core group 13 via first-level node NOC02, and LMSU 24 can be connected to processing core group 14 via first-level node NOC03.

[0042] Furthermore, the broadcast station can be connected to the second-level node of the NOC and multiple LMSUs 21, 22, 23, and 24, respectively. For example, the broadcast station can be connected to the second-level node NOC20 and can be directly connected to each LMSU 21, 22, 23, and 24 without going through the NOC. According to embodiments of this disclosure, the broadcast station can be implemented using logic units.

[0043] By incorporating LMSUs and broadcast stations within the chip, the amount of dedicated memory on the chip is reduced, thereby saving chip area and lowering costs. Furthermore, since multiple LMSUs correspond one-to-one with multiple processing core groups within the chip, the chip can be easily expanded.

[0044] According to embodiments of this disclosure, each LMSU may include a receive (RX) directory, a transmit enable chain (TX_EN_CHAIN), a receive enable chain (RX_EN_CHAIN), a local memory, and a snoop queue.

[0045] The RX directory is used to record the data indexes of each processing core acting as the receiving core in the corresponding processing core group. The data index of a processing core may include the data address of the data to be received by the processing core acting as the receiving core in the corresponding processing core group; optionally, the data index may also include the number of data blocks to be received and the size of each data block to be received.

[0046] The transmit enable chain is used by the processing core acting as the transmit core in the corresponding processing core group to configure each receiving core in this transmission; the receive enable chain is used by the processing core acting as the receiving core in the corresponding processing core group to configure its own operating state. The number of bits in the transmit and receive enable chains can be determined according to the number of processing cores included in the processing core group corresponding to the LMSU. For example, when the number of processing cores included in the processing core group is 4, the number of bits in the transmit and receive enable chains in the LMSU can be 4 bits. Optionally, the transmit enable chains of multiple LMSUs 21, 22, 23, and 24 can be cascaded together and mapped to the broadcast station. In this way, the processing core acting as the transmit core can configure each receiving core in this transmission at once. It can be understood that when configuring each receiving core in this transmission for the transmit core, if each receiving core is located in three LMSUs, then the length of the transmit enable chain is the total length of the transmit enable chains in the three LMSUs, which is 12 bits.

[0047] Local memory is used to store data. For example, local memory can be volatile memory (such as dynamic RAM (DRAM) or static RAM (SRAM)) or non-volatile memory (such as flash memory, erasable programmable read-only memory (EPROM) and / or electrical EPROM (EEPROM)).

[0048] The monitoring queue is used to monitor the communication port between the LMSU and the broadcast station. For example, the monitoring queue can monitor the status of the communication port between the LSMU and the broadcast station, and determine whether the data sent to the monitoring queue belongs to the data to be received by the LMSU to which this monitoring queue is located (i.e., the data to be received by the receiving core in the processing core group corresponding to this LMSU).

[0049] For example, when data is sent to the LMSU but is saved to local memory for some reason, the LMSU can configure the RX directory to write the data index of the data to be received by the receiving core in the local memory into the RX directory. For example, the data index includes the address of the data to be received, and optionally, it may also include the number of data blocks to be received and / or the size of each data block to be received.

[0050] For the configuration of the transmit enable chain, specifically, as follows: assuming each processing core group includes 4 processing cores. When the first processing core in processing core group 11 is ready to send data to the second processing core in processing core group 12, the third processing core in processing core group 13, and the first processing core in processing core group 14, the first processing core in processing core group 11 configures the transmit enable chain, setting the bits corresponding to each processing core in the transmit enable chain to preset values. That is, the second bit in the transmit enable chain of LMSU 22 connected to processing core group 12, the third bit in the transmit enable chain of LMSU 23 connected to processing core group 13, and the first bit in the transmit enable chain of LMSU 24 connected to processing core group 14 are set to preset values. The first processing core in processing core group 11 sends the configured transmit enable chain to the broadcast station, and the broadcast station broadcasts the configured transmit enable chain to each LMSU. The LMSU sets the corresponding bits of its internal transmit enable chain to preset values ​​according to the transmit enable chain, thereby completing the configuration of the receiving core for this transmission.

[0051] For the configuration of the receive enable chain, specifically, when the second processing core of processing core group 12, the third processing core of processing core group 13, and the first processing core of processing core group 14 are ready to receive, the second processing core of processing core group 12, the third processing core of processing core group 13, and the first processing core of processing core group 14 can respectively configure the second bit in the receive enable chain of LMSU 22, the third bit in the receive enable chain of LMSU 23, and the first bit in the receive enable chain of LMSU 24, setting the corresponding bits to preset values ​​to indicate that the processing cores corresponding to these bits are ready to receive.

[0052] For monitoring queues, for example, when the LMSU receives configuration information broadcast by a broadcasting station, or when a processing core is ready to receive data but has not found any data to be received, the LMSU can configure the monitoring queue to include the data index of the data to be received. Thus, the monitoring queue can monitor data sent from the broadcasting station, and if the data matches the data index of the data to be received in the monitoring queue, the LMSU receives the data. The data index of the data to be received includes: the address of the data to be received; optionally, the data index may also include the number of data blocks of the data to be received and / or the size of each data block.

[0053] By setting up an LMSU for each processing core group and configuring the RX directory, transmit enable chain, receive enable chain, and monitoring queue in the LMSU, appropriate scheduling can be achieved in inter-core communication, thereby effectively avoiding congestion of data transmission in the chip and reducing transmission latency in inter-core communication.

[0054] The following will refer to Figure 1This section describes in detail how inter-core communication is implemented on the chip. According to embodiments of this disclosure, inter-core communication can be divided into two cases: single-core transmission, single-core reception, and single-core transmission with multiple cores receiving.

[0055] First, we describe the scenario of single-core transmission and single-core reception. Assume that the first processing core in processing core group 11 is the transmitting core, and the second processing core in processing core group 12 is the receiving core.

[0056] When the transmitting core is ready to send data to the receiving core, it can access LMSU 22 via the NOC and determine whether the receiving core is ready to receive data based on the parameters in LMSU 22. If the receiving core is ready, the transmitting core can send data to the receiving core via the NOC, the broadcast station, and LMSU 22. If the receiving core is not ready, the transmitting core can send the data to LMSU 22 for storage via the NOC.

[0057] Specifically, when the sending core is ready to send data to the receiving core (e.g., when the sending core executes an instruction to send data to the receiving core), the sending core determines that the receiving core for this data transmission is a single processing core. Then, the sending core accesses the receive enable chain of the LMSU 22 through the NOC (e.g., through NOC00, NOC20, and NOC01) to determine whether the receiving core is ready to receive. The receiving core is ready when, upon executing an instruction requiring data acquisition, it sets the second bit of the LMSU 22's receive enable chain to 1 (e.g., set to 1 indicates readiness, set to 0 indicates no readiness), indicating that the receiving core is ready to receive. When the receiving core is ready, it also configures the monitoring queue in its LMSU to generate a data index in the monitoring queue that matches the data required by the instruction to acquire data.

[0058] When the transmitting core accesses the receive enable chain of LMSU 22 via NOC and determines that the receiving core is ready to receive, the transmitting core sends data to the broadcasting station via NOC (e.g., via NOC00 and NOC20). The broadcasting station can send the received data directly (without going through NOC) to LMSU 22. LMSU 22 determines whether the data sent by the broadcasting station matches the data index of the data to be received in the monitoring queue. If they match, LMSU 22 forwards the received data to the receiving core (e.g., forwarding the received data to the receiving core via NOC01) without storing the received data in local memory. If they do not match, the data is discarded or left unprocessed.

[0059] Additionally, if the transmitting core accesses the receive enable chain of LMSU 22 via NOC and determines that the receiving core is not ready to receive (i.e., the receiving core has not yet executed the instruction requiring data acquisition), the transmitting core sends the data to LMSU 22 via NOC (e.g., via NOC00 and NOC20) and stores it in local memory. At this time, LMSU 22 updates its RX directory, writing information such as the data address of the received data in local memory into the RX directory. When the receiving core executes the instruction requiring data acquisition, it first checks the LMSU 22's RX directory to determine if the contents of the RX directory match the data required in the data acquisition instruction. If they match, the receiving core can directly read the data from LMSU 22; if they do not match, the receiving core configures the LMSU 22's receive enable chain to indicate that it is ready to receive. Simultaneously, the receiving core configures LMSU 22's monitoring queue to monitor whether the data sent by the broadcast station matches the data index of the data to be received in the monitoring queue.

[0060] The following describes the scenario of single-core sending and multi-core receiving.

[0061] Assume that the first processing core in processing core group 11 is the transmitting core, and the first, second and third processing cores in processing core group 12, the third processing core in processing core group 13, and the second, third and fourth processing cores in processing core group 14 are the receiving cores.

[0062] When a sending core wants to send data to multiple receiving cores, it first sends configuration information to multiple LMSUs via the NOC and the broadcast station. Upon receiving a configuration completion message from the broadcast station, the sending core can then send the data to the multiple LMSUs corresponding to the data via the NOC and the broadcast station.

[0063] The configuration information includes a transmission enable chain and data information to be transmitted. The transmission enable chain is used to configure each processing core in each LMSU as the receiving core in this transmission, and the data information to be transmitted is used to configure the monitoring queue in each LMSU to monitor whether the data sent from the broadcast station to the LMSU belongs to the data to be received by that LMSU, that is, whether the data corresponds to that LMSU.

[0064] Any LMSU determines which processing core in the LMSU-connected processing core group is the receiving core based on the configuration information of the sending core. If there are multiple processing cores acting as receiving cores, and at least one of the multiple receiving cores is ready to receive, then the LMSU can send the data sent by the sending core to any receiving core that is ready to receive, and save the data sent by the sending core (i.e., store the data sent by the sending core in local memory).

[0065] If there are multiple processing cores acting as receiving cores, and none of the receiving cores are ready to receive data, then the LMSU can save the data sent by the sending core (i.e., store the data sent by the sending core in local memory).

[0066] Specifically, when a transmitting core wants to send data to multiple receiving cores, the transmitting core first configures the transmitting enable chain. Since the transmitting enable chains of each LMSU are connected in series, the transmitting core can set the bits corresponding to all the processing cores that act as receiving cores in the transmitting enable chain to preset values ​​to identify each processing core that acts as a receiving core in this transmission. For example, a preset value of 1 indicates that the processing core corresponding to the bit with the preset value in the transmitting enable chain is a receiving core in this transmission. The sending core sends the configured sending enable chain and the data to be sent to the broadcast station via the NOC. The broadcast station then broadcasts the sending enable chain core and the data to be sent to each LMSU. Each LMSU configures its internal processing cores as the receiving cores based on the received sending enable chain and configures its internal monitoring queue based on the data to be sent to monitor whether the data broadcast from the broadcast station to itself belongs to the data to be received by that LMSU. After completing the above configuration, the LMSU sends a configuration completion message to the broadcast station. Upon receiving the configuration completion message from the broadcast station, the sending core can send the data to the broadcast station via the NOC, and then the broadcast station broadcasts the data to each LMSU.

[0067] Optionally, the broadcast station can broadcast the transmission enable chain core and the data information to be transmitted to each LMSU. Specifically, the broadcast station can send the transmission enable chain and the data information to be transmitted to each LMSU with a receiving core indicated in the transmission enable chain to save power.

[0068] It should be noted that in this article, "broadcasting" and "sending" both refer to the broadcasting station transmitting data to LMSU, and there is no substantial difference between them.

[0069] For example, when a sending core wants to send data, it first configures the sending enable chain. The first, second, and third bits of the sending enable chain corresponding to LMSU 22 (i.e., the first, second, and third processing cores in processing core group 12), the third bit of LMSU 23 (i.e., the third processing core in processing core group 13), and the second, third, and fourth bits of the sending enable chain of LMSU 24 (i.e., the second, third, and third processing cores in processing core group 14) are set to preset values ​​to configure these processing cores as receiving cores for this data transmission. The sending core also sends the data information of the data to be sent to the broadcast station. This data information includes the data address of the data to be sent, and may also include the number of data blocks and the size of each data block. The broadcast station broadcasts the data information of the data to be sent to each LMSU, so that each LMSU writes the received data information into its internal monitoring queue, allowing the LMSU to monitor whether the data sent from the broadcast station belongs to the data to be received by that LMSU.

[0070] The transmitting core sends the configured transmit enable chain and the data information to be transmitted to the broadcast station. The broadcast station then broadcasts this configuration information to each LMSU. After LMSU 22, LMSU 23, and LMSU 24 configure their respective processing cores and monitoring queues (acting as receiving cores) according to this configuration information, LMSU 22, LMSU 23, and LMSU 24 send a configuration completion message to the broadcast station. The broadcast station can then send the configuration completion message to the transmitting core via the NOC. Upon receiving the configuration completion message, the transmitting core can send data to the broadcast station via NOC00 and NOC20. The broadcast station then sends the data to LMSU 22, LMSU 23, and LMSU 24.

[0071] When LMSU 22 receives data from the transmitting core at the broadcast station, its internal monitoring queue compares the received data. If the received data matches the data index of the data to be received in the monitoring queue, LMSU 22 accepts the data. LMSU 22 then determines whether the first, second, and third processing cores configured as receiving cores are ready to receive data based on the receive enable chain. For example, if the first and second bits in the receive enable chain are preset values ​​(e.g., 1 indicates ready, 0 indicates not ready), it means that the first and second processing cores are ready to receive data. LMSU 22 can then send the received data to any of the ready receiving cores, such as the first processing core, and store the received data in its local memory. Simultaneously, it updates the RX directory to write the data information stored in the local memory into the RX directory. This data information includes, for example, the data's storage address. Thus, the second processing core can directly retrieve the data sent by the transmitting core from LMSU 22's local memory based on the RX directory. In addition, when the third processing core is ready to receive, it can also retrieve the data sent by the sending core from the local memory of the LMSU 22.

[0072] If only one of the first, second, and third processing cores in processing core group 12 is ready to receive, LMSU 22 can send the received data to the receiving core that is ready to receive, store the received data in local memory, and update the RX directory to write the data information of this data stored in local memory into the RX directory. In this way, after the second and third processing cores are ready, they can directly retrieve this data sent by the sending core from the local memory of LMSU 22 according to the RX directory.

[0073] If none of the first, second, and third processing cores in processing core group 12 are ready to receive data, LMSU 22 can store the received data in local memory and update the RX directory to write the data information of this data stored in local memory into the RX directory. In this way, when any one of the first, second, and / or third processing cores is ready to receive data, it can retrieve the data sent by the transmitting core from the local memory of LMSU 22 according to the RX directory.

[0074] Furthermore, the processing of LMSU 23 and LMSU 24 is similar to that of LMSU 22. Further details will not be provided here.

[0075] The operation of the receiving core is described below using the first, second, and third processing cores in processing core group 12 as examples.

[0076] When the first processing core reaches an instruction that requires data retrieval, it first checks if there is a data index in the LMSU 22's RX directory indicating that the first processing core is the receiving core. As mentioned above, if the LMSU 22's local memory stores data, it will store index information such as the address of the received data in the RX directory. In this case, the RX directory will include the address of the received data. Therefore, when the address of the received data in the LMSU 22's RX directory matches the address of the data to be received by the first processing core, the first processing core can read the data already sent by the sending core from the LMSU 22's local memory. Optionally, the second and third processing cores can perform similar operations to the first processing core when they reach an instruction that requires data retrieval.

[0077] However, when any of the first, second, and third processing cores executes an instruction requiring data acquisition—for example, when the first processing core executes such an instruction—if the first processing core does not exist as a data index for receiving data in the LMSU 22's RX directory (i.e., the sending core has not yet sent data to the LMSU 22), the first processing core can configure the LMSU 22's monitoring queue. For instance, the first processing core configures the LMSU 22's monitoring queue based on the data index of the data to be received. This includes writing the data index of the data to be received into the monitoring queue, where the data index includes the data address of the data to be received, and may also include the number of data blocks and the size of each data block. Simultaneously, the first processing core sets the corresponding first bit in the LMSU 22's receive enable chain to a preset value to indicate readiness for reception. The execution processes of the second and third processing cores are the same as those of the first processing core and will not be described in detail here.

[0078] Once the first processing core is ready, the data transmission process of the transmitting core is as described above: First, the configured transmission enable chain and the data to be transmitted are sent to the broadcast station. The broadcast station then sends the received configuration information to each LMSU. Each LMSU configures the monitoring queue and the receiving core, and after configuration, it sends a completion message back to the broadcast station. The broadcast station then sends the configuration completion message to the transmitting core, at which point the transmitting core can transmit data. The transmitting core transmits the data to LMSU 22 through the NOC and the broadcast station. LMSU 22 compares the data index of the monitoring queue with the data. If they match, the LMSU receives the data and, based on the receiving enable chain, determines that the first processing core is ready to receive, then sends the data directly to the first processing core. Simultaneously, the LMSU determines, based on the receiving enable chain, that the second and third processing cores (excluding the first processing core) are also ready to receive, then the LMSU saves the data in local memory and updates the RX directory, writing the saved data index into the RX directory. The second and third processing cores can then directly read the saved data from their local memory.

[0079] According to embodiments of this disclosure, the RX directory, transmit enable chain, receive enable chain, and monitoring queue in the LMSU can be flexibly configured to be compatible with single-core transmit / single-core receive and single-core transmit / multi-core receive scenarios, thereby improving the efficiency of inter-core communication and reducing the complexity of the communication network.

[0080] The following is for reference Figures 2 to 4 An inter-core communication method according to an embodiment of the present disclosure is described.

[0081] Figure 2 This is a flowchart illustrating an inter-core communication method according to an embodiment of the present disclosure. The inter-core communication method is applicable to reference... Figure 1 The described chip may include multiple processing core groups, each processing core group may include at least one processing core, and may be connected to an LMSU via a NOC.

[0082] Reference Figure 2 In step S201, one of the processing cores that is the sending core can access the LMSU corresponding to another processing core that is the receiving core through the NOC.

[0083] In step S202, the transmitting core can determine whether the receiving core is ready to receive based on the parameters in the corresponding LMSU.

[0084] In step S203, in response to the receiving core being ready to receive, the sending core can send data to the receiving core via the NOC, broadcast station, and corresponding LMSU.

[0085] As mentioned above, the broadcasting station can be connected to the NOC (e.g., NOC20) and all LMSUs respectively.

[0086] Alternatively, in step S204, in response to the receiving core not being ready to receive, the sending core can send the data to the corresponding LMSU via the NOC.

[0087] For a detailed description of the process in this embodiment, please refer to the foregoing embodiment description, which will not be repeated here.

[0088] Figure 3 This is a flowchart illustrating an inter-core communication method according to another embodiment of the present disclosure. As described above, the inter-core communication method is applicable to reference... Figure 1 The described chip may include multiple processing core groups, each processing core group may include at least one processing core, and may be connected to an LMSU via a NOC.

[0089] Reference Figure 3 In step S301, a processing core, acting as a sending core, sends configuration information to the LMSU via the NOC and the broadcast station. As described above, the broadcast station is connected to the second-level node of the NOC (e.g., NOC20) and all LMSUs.

[0090] In step S302, in response to receiving a configuration complete message from the broadcasting station, the sending core sends data to all LMSUs through the first-level nodes of the NOC (e.g., NOC00, NOC01, NOC02, and NOC03) and the broadcasting station.

[0091] After step S302, the inter-core communication method may further include: the first LMSU determining, based on the configuration information, that there are multiple processing cores acting as receiving cores in the processing core group connected to the first LMSU. If the first LMSU determines that at least one of the multiple receiving cores is ready to receive, the first LMSU sends the data to any of the ready receiving cores and saves the data; or if the first LMSU determines that none of the multiple receiving cores is ready to receive, the first LMSU saves the data, wherein the first LMSU can be any one of all LMSUs.

[0092] For a detailed description of the process in this embodiment, please refer to the foregoing embodiment description, which will not be repeated here.

[0093] Figure 4 This is a flowchart illustrating an inter-core communication method according to another embodiment of the present disclosure. As described above, the inter-core communication method is applicable to reference... Figure 1 The described chip may include multiple processing core groups, each processing core group may include at least one processing core, and may be connected to an LMSU via a NOC.

[0094] Reference Figure 4 In step S401, in response to the instruction to receive data, the processing core queries its corresponding LMSU. In step S402, in response to finding a record in the corresponding LMSU indicating that the processing core is a receiving core, the processing core can read data from the corresponding LMSU.

[0095] Alternatively, in step S403, in response to the absence of a record in the corresponding LMSU indicating that the processing core is a receiving core, the processing core configures the corresponding LMSU to generate a record in the corresponding LMSU indicating that the processing core is a receiving core, the record being used by the corresponding LMSU to monitor data transmitted by the broadcasting station.

[0096] According to an embodiment of this disclosure, after the processing core is configured with a corresponding LMSU to generate a record in the corresponding LMSU indicating that the processing core is a receiving core, in step S404, in response to the corresponding LMSU detecting data transmitted by the broadcasting station, the processing core can obtain the data transmitted by the broadcasting station from the corresponding LMSU.

[0097] For a detailed description of the process in this embodiment, please refer to the foregoing embodiment description, which will not be repeated here.

[0098] Figure 5 This is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0099] Reference Figure 5 The electronic device 500 may include a processor 510 and a memory 520. The processor 510 may include (but is not limited to) a central processing unit (CPU), a graphics processing unit (GPU), a neural processing unit (NPU), an application processor (AP), a digital signal processor (DSP), a system-on-a-chip (SoC), a microprocessor, etc. The processor may be implemented by a chip according to embodiments of the present disclosure. Inter-core communication methods according to embodiments of the present disclosure may be implemented in the chip. The memory 520 stores computer programs to be executed by the processor 510. The memory 520 includes high-speed random access memory and / or a non-volatile computer-readable storage medium.

[0100] Alternatively, electronic device 500 may also include display device 525, storage device 530, input device 540, output device 550, and communication device 560. The various components of electronic device 500 can communicate with each other via a communication bus. Display device 525 can display various user interfaces and / or application interfaces. Storage device 530 includes computer-readable storage media. Storage device 530 stores a larger amount of information and for a longer time than memory 520. For example, storage device 530 includes storage media such as hard disks, optical disks, and solid-state drives. Input device 540 receives input from a user via tactile, video, audio, or touch input. For example, input device 540 includes a keyboard, mouse, touchscreen, microphone, or any other device that detects input from the user and sends the detected input to electronic device 500. Output device 550 provides output from electronic device 500 to the user through visual, auditory, or tactile channels. Output device 550 includes, for example, a display, touchscreen, speaker, vibration generator, or any other device that provides output to the user. The communication device 560 communicates with external devices via wired or wireless networks.

[0101] The inter-core communication method according to embodiments of this disclosure can be programmed into a computer program and stored on a computer-readable storage medium. When the computer program is executed by a processor, the inter-core communication method described above can be implemented. Examples of computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disc storage, hard disk drive (HDD), solid-state drive (SSD), card storage (such as multimedia cards, secure digital (SD) cards, or ultra-fast digital (XD) cards), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid-state drive, and any other device configured to store a computer program and any associated data, data files, and data structures in a non-transitory manner and to provide the computer program and any associated data, data files, and data structures to a processor or computer so that the processor or computer can execute the computer program. In one example, the computer program and any associated data, data files, and data structures are distributed across a networked computer system, such that the computer program and any associated data, data files, and data structures are stored, accessed, and executed in a distributed manner through one or more processors or computers.

[0102] The chip, inter-core communication method, electronic device, and computer-readable storage medium according to the embodiments of this disclosure can solve the problems of excessive transmission latency, large memory area, and easy deadlock in traditional multi-core architectures, and have many advantages such as short transmission latency, flexible configuration, saving memory area, and easy expansion.

[0103] Although this disclosure has been specifically shown and described with reference to its embodiments, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of this disclosure as defined by the claims.

Claims

1. A chip, characterized in that, The chip includes: Multiple processing core groups, each processing core group including at least one processing core, and any one of the multiple processing core groups is connected to the other processing core groups in the multiple processing core groups through an on-chip network NOC; Multiple Local Shared Storage Units (LMSUs) are provided, and each LMSU corresponds one-to-one with a processing core group. Each LMSU is connected to all processing cores within the corresponding processing core group through the first-level node of the NOC. A broadcasting station, which is connected to the second-level node of the NOC and multiple LMSUs respectively; The LMSU includes: A receiving directory is used to record the data indexes of each processing core that serves as the receiving core in the corresponding processing core group; Send enable chain, used by the processing core in the corresponding processing core group that acts as the sending core to configure each receiving core in this transmission; A receive enable chain is used to configure the working state of each processing core in the corresponding processing core group that serves as the receiving core. Local memory, used to store data; and A monitoring queue is used to monitor the communication port between the LMSU and the broadcasting station.

2. The chip as described in claim 1, characterized in that, The transmit enable chains in multiple LMSUs are cascaded and mapped to the broadcast station.

3. An inter-core communication method for a chip comprising multiple processing cores, characterized in that, The processing core group includes at least one processing core, and each processing core group is connected to a local shared memory unit (LMSU) via an on-chip network (NOC). The LMSU includes: The receiving directory is used to record the data indexes of each processing core that serves as the receiving core in a connected group of processing cores; Send enable chain, used by the processing cores in the connected processing core group that act as sending cores to configure each receiving core in this transmission; A receive enable chain is used for each of the processing cores in the connected processing core group, which acts as the receiving core, to configure its own operating state. Local memory, used to store data; and A monitoring queue is used to monitor the communication port between the LMSU and the broadcasting station; The inter-core communication method includes: One of the processing cores, acting as the sending core, accesses the LMSU corresponding to another processing core, acting as the receiving core, through the NOC. The receiving core is determined to be ready to receive data based on the parameters in the corresponding LMSU. Specifically, when the receiving core executes an instruction requiring data acquisition, it sets the second bit of the receive enable chain in the corresponding LMSU to indicate that it is ready to receive data, and configures the monitoring queue in the corresponding LMSU to generate a data index in the monitoring queue that matches the data required by the data acquisition instruction; and In response to the receiving core being ready to receive, the sending core sends data to the receiving core through the NOC, the broadcast station, and the corresponding LMSU, wherein the broadcast station is connected to the NOC and all the LMSUs respectively.

4. The inter-core communication method as described in claim 3, characterized in that, The inter-core communication method further includes: In response to the receiving core not being ready to receive, the sending core sends the data to the corresponding LMSU through the NOC.

5. An inter-core communication method for a chip comprising multiple processing cores, characterized in that, The processing core group includes at least one processing core, and each processing core group is connected to a local shared memory unit (LMSU) via an on-chip network (NOC). The LMSU includes: The receiving directory is used to record the data indexes of each processing core that serves as the receiving core in a connected group of processing cores; Send enable chain, used by the processing cores in the connected processing core group that act as sending cores to configure each receiving core in this transmission; A receive enable chain is used for each of the processing cores in the connected processing core group, which acts as the receiving core, to configure its own operating state. Local memory, used to store data; and A monitoring queue is used to monitor the communication port between the LMSU and the broadcasting station; The inter-core communication method includes: As a transmitting core, a processing core sends configuration information to the LMSU via the on-chip network NOC and broadcast stations. The broadcast stations are connected to the second-level nodes of the NOC and all the LMSUs. In response to receiving a configuration completion message from the broadcasting station, the sending core sends data to each of the LMSUs through the first-level node of the NOC and the broadcasting station; The first LMSU determines, based on the configuration information, that there are multiple processing cores acting as receiving cores in the processing core group connected to the first LMSU. If the first LMSU determines that at least one of the plurality of receiving cores is ready to receive, then the first LMSU sends the data to any one of the ready receiving cores and saves the data; or If the LMSU determines in the first step that none of the multiple receiving cores are ready to receive data, then the LMSU in the first step saves the data. Wherein, the first LMSU is any one of all the LMSUs.

6. An inter-core communication method for a chip comprising multiple processing cores, characterized in that, The processing core group includes at least one processing core, and each processing core group is connected to a local shared memory unit (LMSU) via an on-chip network (NOC). The LMSU includes: The receiving directory is used to record the data indexes of each processing core that serves as the receiving core in a connected group of processing cores; Send enable chain, used by the processing cores in the connected processing core group that act as sending cores to configure each receiving core in this transmission; A receive enable chain is used for each of the processing cores in the connected processing core group, which acts as the receiving core, to configure its own operating state. Local memory, used to store data; and A monitoring queue is used to monitor the communication port between the LMSU and the broadcasting station; The inter-core communication method includes: In response to the instruction to receive data, the first processing core queries the LMSU corresponding to the first processing core; In response to a query in the LMSU indicating that the first processing core is a receiving core, the first processing core reads data from the LMSU; In response to the absence of a record in the LMSU indicating that the first processing core is a receiving core, the first processing core configures the LMSU to generate a record in the LMSU indicating that the first processing core is ready to receive, and a record indicating that the LMSU is monitoring the data transmitted by the broadcasting station. In response to the LMSU detecting data transmitted by the broadcasting station, the first processing core obtains the data transmitted by the broadcasting station from the LMSU.

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