Semiconductor packaging method and semiconductor packaging structure
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CR RUNAN TECHNOLOGIES (CHONGQING) CO LTD
- Filing Date
- 2020-11-30
- Publication Date
- 2026-06-26
Smart Images
Figure CN114582735B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and more particularly to a semiconductor packaging method and a semiconductor packaging structure. Background Technology
[0002] Currently, during the packaging process, a protective layer is placed on the active surface of the die to be packaged, while the back side of the die is exposed. When the protective layer deforms, the active surface of the die to be packaged is stretched by the protective layer, resulting in warping. When this die is packaged into a semiconductor package structure, stress is stored in each die. When the semiconductor package structure undergoes reliability tests such as thermal shock, abnormalities such as cracking and delamination may occur. Summary of the Invention
[0003] This application provides a semiconductor packaging method and a semiconductor packaging structure that can reduce or avoid warping of semiconductor wafers.
[0004] According to a first aspect of this application, a semiconductor packaging method is provided, the semiconductor packaging method comprising:
[0005] A first protective layer is formed on the first surface of the semiconductor wafer;
[0006] Thinning the semiconductor wafer;
[0007] A second protective layer is formed on the second surface of the semiconductor wafer;
[0008] Cut semiconductor wafers and form bare dies to be packaged;
[0009] The first surface and the second surface are disposed opposite to each other, and the difference in the coefficients of thermal expansion between the first protective layer and the second protective layer is less than or equal to 6.
[0010] Furthermore, the semiconductor packaging method further includes:
[0011] Secure the die to be packaged to the lead frame;
[0012] A second opening is formed in the second protective layer, the second opening exposing the second surface;
[0013] A second redistribution layer is formed on the side of the second protective layer away from the first protective layer, and the second redistribution layer passes through the second opening and is connected to the second surface;
[0014] The coefficient of thermal expansion of the second protective layer is located between the coefficients of thermal expansion of the second redistribution layer and the die to be packaged.
[0015] Furthermore, fixing the die to be packaged to the lead frame includes:
[0016] Provide substrate;
[0017] A lead frame is fixed on a substrate, the lead frame comprising a plurality of spaced conductive posts;
[0018] The die to be packaged is fixed to the substrate, the first protective layer is connected to the substrate, and the die to be packaged is disposed between two adjacent conductive pillars;
[0019] A first molding layer is formed, which encapsulates the conductive pillar and the die to be packaged.
[0020] Furthermore, after forming the first protective layer on the first surface of the semiconductor wafer and before thinning the semiconductor wafer, the following steps are performed:
[0021] A first opening is formed on the first protective layer, the first opening exposing the pins on the first surface.
[0022] Furthermore, the semiconductor packaging method further includes:
[0023] The die to be packaged is fixed to the lead frame using the first molding layer;
[0024] A first redistribution layer is formed on the side of the first protective layer away from the second protective layer, and the first redistribution layer passes through the first opening and is connected to the pin.
[0025] On the side away from the first protective layer, the first molding layer is thinned to expose the end faces of the second protective layer and the lead frame.
[0026] According to a second aspect of this application, a semiconductor packaging structure is provided, the semiconductor packaging structure being manufactured by the semiconductor packaging method described above; the semiconductor packaging structure includes:
[0027] A bare die to be packaged includes a first surface and a second surface disposed opposite to each other, and pins are provided on the first surface;
[0028] A first protective layer is disposed on the first surface of the bare die to be packaged;
[0029] A second protective layer is disposed on the second surface of the bare die to be packaged;
[0030] The difference in the coefficients of thermal expansion between the first protective layer and the second protective layer is less than or equal to 6.
[0031] Furthermore, a first opening is formed on the first protective layer, the first opening exposing the pin; a second opening is formed on the second protective layer, the second opening exposing the second surface;
[0032] The semiconductor packaging structure further includes:
[0033] A lead frame includes a plurality of spaced-apart conductive posts, the conductive posts being disposed around the periphery of the die to be packaged;
[0034] A first redistribution layer is disposed on the first protective layer and electrically connected to the pin and the conductive post;
[0035] A second redistribution layer is disposed on the second protective layer and electrically connected to the second surface and the conductive pillar.
[0036] The coefficient of thermal expansion of the second protective layer is located between the coefficients of thermal expansion of the second redistribution layer and the die to be packaged.
[0037] Furthermore, there are multiple second openings, which are evenly distributed on the second protective layer.
[0038] Furthermore, the coefficient of thermal expansion of the first protective layer and / or the second protective layer is greater than or equal to 5 and less than or equal to 13.
[0039] Furthermore, the material of the first protective layer and / or the second protective layer is epoxy resin; and / or,
[0040] The thickness of the first protective layer and / or the second protective layer is greater than or equal to 25 micrometers and less than or equal to 50 micrometers.
[0041] The technical solutions provided by the embodiments of this disclosure may include the following beneficial effects:
[0042] In the above configuration, the difference in the coefficients of thermal expansion of the first and second protective layers is limited, ensuring that the deformation of the first and second protective layers on both sides of the semiconductor wafer is similar under the same temperature environment. This makes the forces acting on the first and second surfaces of the semiconductor wafer as balanced as possible, reducing or avoiding warping of the semiconductor wafer due to uneven stress. Simultaneously, when using the aforementioned die to be packaged to form a semiconductor package structure, stress is prevented from being stored in the die, ensuring the stability of the semiconductor package structure during reliability tests such as thermal shock.
[0043] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0044] Figure 1 This is a cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0045] Figure 2 This is another cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0046] Figure 3 This is a simplified flowchart illustrating a semiconductor packaging method according to an embodiment of this application.
[0047] Figure 4 This is another cross-sectional schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0048] Figure 5 This is another cross-sectional structural schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0049] Figure 6 This is another cross-sectional structural schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0050] Figure 7 This is another cross-sectional structural schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0051] Figure 8 This is another cross-sectional structural schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0052] Figure 9 This is another cross-sectional structural schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0053] Figure 10 This is another cross-sectional structural schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0054] Figure 11 This is another cross-sectional structural schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0055] Figure 12 This is another cross-sectional structural schematic diagram of a semiconductor packaging structure according to an embodiment of this application.
[0056] Figure 13 This is a cross-sectional schematic diagram of a semiconductor packaging structure.
[0057] Explanation of reference numerals in the attached figures
[0058] Semiconductor packaging structure 10
[0059] Semiconductor wafer 100
[0060] First surface 101
[0061] Second surface 102
[0062] 110 bare dies to be packaged
[0063] Active Surface 111
[0064] Back 112
[0065] Pin 113
[0066] Insulation layer 114
[0067] First protective layer 200
[0068] First opening 210
[0069] Second protective layer 300
[0070] Second opening 310
[0071] Substrate 400
[0072] Adhesive layer 410
[0073] Leadframe 500
[0074] Conductive post 510
[0075] First sealing layer 600
[0076] First rewiring layer 700
[0077] Second sealing layer 800
[0078] Second rewiring layer 900 Detailed Implementation
[0079] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses consistent with some aspects of this application as detailed in the appended claims.
[0080] The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application. Unless otherwise defined, the technical or scientific terms used in this application should be understood in their ordinary sense by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application specification and claims do not indicate any order, quantity, or importance, but are only used to distinguish different components. Similarly, the terms "a" or "one," etc., do not indicate a quantity limitation, but rather indicate the presence of at least one, which will be separately stated if only "a" is referred to. "A plurality" or "several" means two or more. Unless otherwise indicated, the terms "front," "rear," "lower," and / or "upper," etc., are for ease of description only and are not limited to a location or spatial orientation. The terms "comprising" or "including," etc., mean that the elements or objects preceding "comprising" or "including" encompass the elements or objects listed following "comprising" or "including" and their equivalents, and do not exclude other elements or objects. The terms “connection” or “link” are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The singular forms “a,” “the,” and “the” used in this specification and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0081] The embodiments of this application will now be described in detail with reference to the accompanying drawings. Unless otherwise specified, the features in the following embodiments can be combined with each other.
[0082] According to various embodiments of this application, a semiconductor packaging method is provided. This semiconductor packaging method can be used to fabricate semiconductors such as… Figure 1 The semiconductor packaging structure 10 shown is a chip package.
[0083] Combination Figure 1 and Figure 3As shown, the semiconductor packaging method requires packaging multiple dies 110 to be packaged on a semiconductor wafer 100. Each die 110 includes an active surface 111 and a back surface 112. Metal pins 113 are disposed on the active surface 111, and adjacent pins 113 are isolated by an insulating layer 114. The planes of the active surfaces 111 of the multiple dies 110 overlap, forming a first surface 101 of the semiconductor wafer 100. The planes of the back surfaces 112 of the multiple dies 110 overlap, forming a second surface 102 of the semiconductor wafer 100. The pins 113 on the active surface 111 need to be connected to a metal wiring layer to form one of a gate, drain, and source. The back surface 112 needs to be connected to a metal wiring layer to form the other of a drain and source.
[0084] like Figure 3 As shown, combine with if necessary Figure 1 As shown, the semiconductor packaging method includes the following steps:
[0085] Step 1000: Form a first protective layer 200 on the first surface 101 of the semiconductor wafer 100.
[0086] Step 2000: Thin the semiconductor wafer 100 and form a second surface 102 of the semiconductor wafer 100, the second surface 102 being disposed opposite to the first surface 101.
[0087] Step 3000: A second protective layer 300 is formed on the second surface 102 of the semiconductor wafer 100. At this time, the structure of the formed semiconductor package structure 10 is as follows: Figure 2 As shown.
[0088] Step 4000: Cut the semiconductor wafer 100 and form the bare die 110 to be packaged.
[0089] The difference in the coefficient of thermal expansion between the first protective layer 200 and the second protective layer 300 is less than or equal to 6.
[0090] In the above configuration, the first protective layer 200 and the second protective layer 300 respectively cover the upper and lower sides of the semiconductor wafer 100, and the difference in the coefficients of thermal expansion of the first protective layer 200 and the second protective layer 300 is less than or equal to 6. By limiting the difference in the coefficients of thermal expansion of the first protective layer 200 and the second protective layer 300, the deformation of the first protective layer 200 and the second protective layer 300 on both sides of the semiconductor wafer 100 under the same temperature environment is made similar. Through the above configuration, the forces acting on the first surface 101 and the second surface 102 of the semiconductor wafer 100 are made as balanced as possible, reducing or avoiding warping of the semiconductor wafer 100 due to uneven force. For example, if the difference in the coefficients of thermal expansion is large, when the first protective layer 200 expands, the second protective layer 300 contracts, and the directions of the forces acting on both sides of the semiconductor wafer 100 are opposite, causing the semiconductor wafer 100 to bulge upwards or dent upwards, resulting in warping. In this embodiment, at a specified temperature, both the first protective layer 200 and the second protective layer 300 expand. Since the difference in the coefficients of thermal expansion between the first protective layer 200 and the second protective layer 300 is small, their deformations are similar, both exerting an outward pulling force on the semiconductor wafer 100. The forces acting on both sides of the semiconductor wafer 100 are in the same direction, preventing warping. Simultaneously, the die 110 to be packaged, fabricated from the semiconductor wafer 100, is packaged, resulting in a semiconductor package structure 10 with the die 110 to be packaged. This avoids stress storage in the die 110, ensuring the stability of the semiconductor package structure 10 during reliability tests such as thermal shock.
[0091] In one setting, such as Figure 13 As shown, semiconductor wafers (in) Figure 13 In the example shown, only the second surface 102 of the bare die 110 to be packaged is shown without the second protective layer 300. Furthermore, after the semiconductor wafer is thinned, it is directly cut. The cutting edge of the cutting blade directly contacts the second surface 102 of the semiconductor wafer. The contact area is small, the semiconductor wafer has low toughness, and it is very easy for the edge to chip.
[0092] like Figure 3As shown, in this embodiment, before dicing the semiconductor wafer 100, a first protective layer 200 is formed on the first surface 101, and a second protective layer 300 is formed on the second surface 102. Both the first protective layer 200 and the second protective layer 300 can protect the semiconductor wafer 100. The toughness of both the first protective layer 200 and the second protective layer 300 is greater than that of the semiconductor wafer 100. When dicing the semiconductor wafer 100, the cutting edge of the dicing blade first contacts the tougher second protective layer 300, preventing edge chipping of the second protective layer 300. Simultaneously, it protects the semiconductor wafer 100, preventing edge chipping.
[0093] In this embodiment, both the first protective layer 200 and the second protective layer 300 are made of epoxy resin, and they have the same coefficient of thermal expansion. Of course, in other embodiments, the first protective layer 200 and the second protective layer 300 can be made of other materials.
[0094] Furthermore, such as Figure 3 As shown, combine with if necessary Figure 2 As shown. After step 1000: forming a first protective layer 200 on the first surface 101 of the semiconductor wafer 100; before step 2000: thinning the semiconductor wafer 100, the following steps are also performed:
[0095] Step 1100: A first opening 210 is formed on the first protective layer 200, the first opening 210 exposing the pin 113 on the first surface 101.
[0096] In the above configuration, the first opening 210 is formed on the first protective layer 200 without thinning the semiconductor wafer 100. This configuration ensures that the semiconductor wafer 100 has sufficient thickness to provide support during the formation of the first opening 210. In this embodiment, the first opening 210 can be formed above the first protective layer 200 using laser drilling. Of course, in other embodiments, when the material of the first protective layer 200 is a photosensitive material, the first opening 210 can also be formed using photolithography with a mask.
[0097] Furthermore, Figure 3 As shown, combine with if necessary Figure 1 As shown. The semiconductor packaging method further includes the following steps:
[0098] Step 5000: Provide substrate 400.
[0099] Step 6000: Fix a lead frame 500 on the substrate 400. The lead frame 500 includes a plurality of spaced conductive posts 510.
[0100] Step 7000: The die to be packaged 110 is fixed to the substrate 400, the first protective layer 200 is connected to the substrate 400, and the die to be packaged 110 is disposed between two adjacent conductive pillars 510. At this time, the structure diagram of the semiconductor package structure 10 formed is as follows. Figure 4 As shown.
[0101] The substrate 400 provides support for the die to be packaged 110 and the lead frame 500, thereby facilitating the processing of the die to be packaged 110. In this embodiment, the substrate 400 is made of metal, which has high strength and rigidity. Of course, in other embodiments, the substrate 400 can also be made of high-temperature resistant, high-strength materials such as tempered glass.
[0102] The substrate 400 and lead frame 500 can be attached to the substrate 400 via an adhesive layer 410. The adhesive layer 410 can be made of an easily peelable material to allow the lead frame 500 and / or the die to be packaged 110 to be separated from the substrate 400 in subsequent processes. For example, a heat-release material that loses its adhesiveness upon heating can be used. In other embodiments, the adhesive layer 410 can have a two-layer structure, comprising a heat-release material layer and an adhesive layer 410. The heat-release material layer is adhered to the substrate 400 and loses its adhesiveness upon heating, thus allowing it to be peeled off the substrate 400. The adhesive layer 410, on the other hand, is an adhesive material layer that can be adhered to the lead frame 500 and / or the die to be packaged 110. After the lead frame 500 and / or the die to be packaged 110 are peeled from the substrate 400, the adhesive layer 410 on the surface of the lead frame 500 and / or the die to be packaged 110 can be removed by chemical cleaning. In one embodiment, an adhesive layer 410 may be formed on the substrate 400 by means of lamination, printing or other methods.
[0103] Step 8000: Form a first molding compound 600, which encapsulates the conductive pillar 510 and the die to be packaged 110. At this point, the structure of the formed semiconductor package structure 10 is shown in the diagram below. Figure 5 As shown.
[0104] In the above configuration, the first molding compound 600 enters the gap between the conductive post 510 and the die to be packaged 110, and covers the surfaces of the conductive post 510 and the die to be packaged 110 that are away from the substrate 400, thereby fixing the die to be packaged 110 and the conductive post 510 into a single unit. A certain distance is spaced between the conductive post 510 and the die to be packaged 110 to facilitate the first molding compound 600 penetrating into the gap between them; in other words, at least a portion of the first molding compound 600 enters the gap between the conductive post 510 and the die to be packaged 110. Simultaneously, the first molding compound 600 is formed above the substrate 400, that is, the first molding compound 600 covers the substrate 400. At this point, the lower surface of the first molding layer 600, the lower surface of the conductive pillar 510, and the lower surface of the first protective layer 200 are flush, and a flat plate structure is reconstructed so that after the substrate 400 is peeled off, redistribution and encapsulation can continue on the reconstructed flat plate structure, which is particularly convenient for the subsequent formation of a redistribution layer thereon.
[0105] Step 9000: Flip the entire structure formed by the first molding layer 600, conductive pillar 510, and die to be packaged 110, so that the adhesive layer 410 and the substrate 400 are on top.
[0106] Step 9001: Remove the substrate 400 from the side of the first molding compound 600 away from the second protective layer 300, thereby exposing the first protective layer 200 for further processing. Furthermore, the substrate 400 is fixed to the side of the first molding compound 600 away from the first protective layer 200 using an adhesive layer 410, providing support for the structure fixed thereto. At this point, the structure of the formed semiconductor package structure 10 is as follows: Figure 6 As shown.
[0107] Since the adhesive layer 410 between the substrate 400 and the first protective layer 200, conductive pillar 510, and first molding compound 600 on the die to be packaged 110 is a thermally release film, the adhesive layer 410 can be heated to reduce its stickiness, thereby allowing the substrate 400 to be peeled off. By heating the adhesive layer 410 to peel off the substrate 400, damage to the first protective layer 200, conductive pillar 510, and first molding compound 600 during the peeling process can be minimized. In other embodiments, the substrate 400 can also be peeled off directly by mechanical means.
[0108] In the embodiments of this application, after the substrate 400 is peeled off, the first molding layer 600, conductive pillars 510, first protective layer 200, first opening 210, and pins 113 communicating with the first opening 210 are exposed. The surfaces of the first molding layer 600, conductive pillars 510, and first protective layer 200 may also have an adhesive layer 410 attached, which can be removed chemically. After completely removing the adhesive layer 410, if encapsulating material was previously incorporated, the surfaces of the first molding layer 600, conductive pillars 510, and first protective layer 200 are further smoothed using methods such as chemical cleaning or dry etching, which facilitates subsequent wiring.
[0109] Step 9002: A first redistribution layer 700 is formed on the side of the first protective layer 200 away from the second protective layer 300. The first redistribution layer 700 passes through the first opening 210 and connects to the pin 113. The connection between the first redistribution layer 700 and the pin 113 forms one of the gate, drain, and source. At this time, the structural diagram of the formed semiconductor package structure 10 is as follows. Figure 7 As shown.
[0110] In this embodiment, the first opening 210 needs to expose the pin 113 so that the first redistribution layer 700 can pass through the first opening 210 and connect to the pin 113. Although there is a certain positional error in the method of forming the first opening 210 by laser drilling, such error is not enough to cause an excessive deviation between the position of the first opening 210 and the position of the pin 113. However, if the first opening 210 is formed on the first protective layer 200 after the die to be packaged 110 and the lead frame 500 are fixed, the process of fixing the die to be packaged 110 and the lead frame 500 also has a certain positional error. The positional error of this process, combined with the positional error in the laser drilling process, can easily cause the first opening 210 to be far away from the pin 113, that is, the first opening 210 cannot expose the pin 113, and the first redistribution layer 700 cannot connect to the pin 113. Therefore, in this embodiment, before fixing the die to be packaged 110 and the lead frame 500, the first protective layer 200 and the first opening 210 are formed first. This helps to ensure that the first opening 210 exposes the pin 113 and helps to ensure a stable connection between the first redistribution layer 700 and the pin 113.
[0111] Step 9003: Form a second molding compound 800, which encapsulates the first redistribution layer 700. At this point, the structure of the formed semiconductor package structure 10 is shown in the diagram below. Figure 8 As shown.
[0112] Step 9004: On the side away from the first protective layer 200, the second molding compound 800 is thinned to expose the first redistribution layer 700. Of course, in other embodiments, the second molding compound 800 can be further thinned in subsequent steps. At this point, the structure of the formed semiconductor package structure 10 is as follows... Figure 9 As shown.
[0113] Step 9005: Flip the entire structure formed by the first molding layer 600, conductive pillar 510, die to be packaged 110, first redistribution layer 700, and second molding layer 800, so that the second protective layer 300 is located above the first protective layer 200, and the adhesive layer 410 and substrate 400 are located above it.
[0114] Step 9006: Remove the substrate 400 from the side of the first molding compound 600 away from the first protective layer 200, thereby exposing the first molding compound 600 to facilitate further operations on the first molding compound 600 and the second protective layer 300. Furthermore, the substrate 400 is fixed to the side of the first molding compound 600 away from the second protective layer 300 using an adhesive layer 410, providing fixed support for the structure fixed thereto. At this point, the structure of the formed semiconductor package structure 10 is as follows: Figure 10 As shown.
[0115] It should be noted that the process flow for step 9006: removing substrate 400 is the same as the process flow for step 9001: removing substrate 400.
[0116] Step 9007: On the side away from the first protective layer 200, thin the first molding layer 600 to expose the end faces of the second protective layer 300 and the lead frame 500 (conductive pillar 510). At this point, the structure of the formed semiconductor package structure 10 is as follows: Figure 11 As shown.
[0117] In this embodiment, the first molding compound 600 is thinned only after the first redistribution layer 700 is fabricated. Although the steps are relatively cumbersome, the above-mentioned setup ensures that the overall thickness of the structure formed by the die to be packaged 110, the first molding compound 600, the lead frame 500, etc., remains within a suitable range before this step, thus giving the whole structure a certain thickness and strength, and improving its structural stability. After step 9006, the whole structure formed by the die to be packaged 110, the first molding compound 600, the lead frame 500, etc., already has a large number of film layers, and its thickness is already within a suitable range. At this point, further thinning of the first molding compound 600 will not affect the overall structural strength and stability.
[0118] At the same time, such as Figure 12As shown, in one configuration, without a second protective layer, the process of thinning the first molding compound 600 will inevitably grind down to the die 110 to be packaged, causing some damage to the already thin die 110. In this embodiment, by providing a second protective layer 300, the process of thinning the first molding compound 600 will only grind down to the second protective layer 300. The second protective layer 300 can protect the die 110 to be packaged, preventing damage to the die 110 during the grinding process and avoiding breakage, chipping, or other issues.
[0119] Step 9008: A second opening 310 is formed on the second protective layer 300, exposing the second surface 102. At this time, the structure of the formed semiconductor package structure 10 is shown in the diagram below. Figure 12 As shown.
[0120] In this embodiment, the second opening 310 can be formed above the second protective layer 300 using laser drilling. Of course, in other embodiments, when the material of the second protective layer 300 is a photosensitive material, the second opening 310 can also be formed using photolithography with a mask. The second opening 310 only needs to expose the second surface 102, and its positional precision requirements are low. Therefore, the second opening 310 can be formed on the second protective layer 300 after the die to be packaged 110 and the lead frame 500 are fixed.
[0121] Step 9009: A second redistribution layer 900 is formed on the side of the second protective layer 300 away from the first protective layer 200. The second redistribution layer 900 passes through the second opening 310 and connects to the second surface 102. The second redistribution layer 900 connects the back surface 112 and the conductive pillars 510 in the lead frame 500, and forms another of the drain and source electrodes. At this time, the structural diagram of the formed semiconductor package structure 10 is as follows. Figure 1 As shown. Subsequently, the second redistribution layer 900 can be encapsulated again using a molding compound, or the second redistribution layer 900 can be left unencapsulated, thus exposing the second redistribution layer 900.
[0122] It should be noted that both the first redistribution layer 700 and the second redistribution layer 900 are made of copper, which has a coefficient of thermal expansion of 17.5. Of course, in other embodiments, the second redistribution layer 900 can also be made of other metals. The die 110 to be packaged is a silicon wafer, which has a coefficient of thermal expansion of 2.
[0123] like Figure 13As shown, in one design, the semiconductor package structure 10 only includes a first protective layer 200, and the back side 112 of the die to be packaged 110 is directly connected to a second redistribution layer 900 made of copper. However, the difference in their coefficients of thermal expansion is huge, resulting in poor adhesion between the second redistribution layer 900 and the die to be packaged 110. During reliability tests such as high temperature and high humidity tests, delamination is very likely to occur, causing the semiconductor package structure 10 to be scrapped or fail during use or manufacturing.
[0124] like Figure 1 As shown, in this embodiment, a second protective layer 300 is provided, and a second opening 310 is provided on the second protective layer 300 for the second redistribution layer 900 to pass through, thereby connecting the second redistribution layer 900 and the back surface 112 of the die to be packaged 110 using the second protective layer 300. The coefficient of thermal expansion of the second protective layer 300 is between that of the second redistribution layer 900 and the die to be packaged 110, thus serving as a transition interconnect between the second redistribution layer 900 and the die to be packaged 110, and also serving as an auxiliary heat dissipation mechanism. Through the above arrangement, the occurrence of delamination is avoided or reduced, thereby improving the overall structural stability of the semiconductor package structure 10 during use or fabrication.
[0125] In this embodiment, the second protective layer 300 is made of epoxy resin, with a coefficient of thermal expansion between 7 and 12. It can effectively connect the second redistribution layer 900 and the die to be packaged 110, thereby improving the stability of the connection between them. Of course, in other embodiments, the second protective layer 300 can also be made of other materials with coefficients of thermal expansion between those of the second redistribution layer 900 and the die to be packaged 110. The material of the second protective layer 300 can be a conductive material or an insulating material.
[0126] Furthermore, the second protective layer 300 may also include multiple sub-layers stacked vertically. At least two sub-layers have different coefficients of thermal expansion, and the coefficients of thermal expansion of the sub-layers are between those of the second redistribution layer 900 and the die 110 to be packaged. In step 3000, the sub-layers may be formed layer by layer on the second surface 102 of the semiconductor wafer 100. The sub-layers closer to the die 110 have a smaller coefficient of thermal expansion, thus better bonding with the die 110. The sub-layers farther from the die 110 have a larger coefficient of thermal expansion, thus better bonding with the second redistribution layer 900. Preferably, the materials of the multiple sub-layers are all different, and the coefficients of thermal expansion of the sub-layer materials gradually increase from the first protective layer 200 towards the second protective layer 300. With the above arrangement, a tighter bond between the second redistribution layer 900 and the die 110 to be packaged can be achieved.
[0127] Figure 1 This is a schematic diagram of a semiconductor package structure 10 obtained using the above-described semiconductor packaging method according to an exemplary embodiment of this application. Figure 1 As shown, the semiconductor packaging structure 10 includes a die to be packaged 110, a first protective layer 200, and a second protective layer 300.
[0128] The die to be packaged 110 includes a first surface 101 and a second surface 102 disposed opposite to each other, and pins 113 are provided on the first surface 101. A first protective layer 200 is disposed on the first surface 101 of the die to be packaged 110. A second protective layer 300 is disposed on the second surface 102 of the die to be packaged 110. Furthermore, the difference in the coefficients of thermal expansion between the first protective layer 200 and the second protective layer 300 is less than or equal to 6.
[0129] In the above configuration, by limiting the difference in the coefficients of thermal expansion of the first protective layer 200 and the second protective layer 300, the deformation of the first protective layer 200 and the second protective layer 300 located on both sides of the semiconductor wafer 100 under the same temperature environment is made similar. This configuration ensures that the forces acting on the first surface 101 and the second surface 102 of the semiconductor wafer 100 are as balanced as possible, reducing or avoiding warping of the semiconductor wafer 100 due to uneven force. Simultaneously, it ensures the stability of the semiconductor packaging structure 10 during reliability tests such as thermal shock.
[0130] Furthermore, the semiconductor package structure 10 also includes a lead frame 500, a first redistribution layer 700, and a second redistribution layer 900.
[0131] A first opening 210 is formed on the first protective layer 200, exposing the pin 113. A second opening 310 is formed on the second protective layer 300, exposing the second surface 102. The lead frame 500 includes a plurality of spaced conductive posts 510 disposed around the periphery of the die 110 to be packaged. A first redistribution layer 700 is disposed on the first protective layer 200 and electrically connected to the pin 113 and the conductive posts 510. A second redistribution layer 900 is disposed on the second protective layer 300 and electrically connected to the second surface 102 and the conductive posts 510. The coefficient of thermal expansion of the second protective layer 300 is between that of the second redistribution layer 900 and the die 110 to be packaged.
[0132] Through the above configuration, the second protective layer 300 can serve as a transitional interconnect between the second redistribution layer 900 and the die to be packaged 110, avoiding or reducing delamination and thus improving the overall structural stability of the semiconductor package structure 10 during use or fabrication. Simultaneously, its coefficient of thermal expansion is greater than that of the die to be packaged 110, which can assist in heat dissipation.
[0133] Furthermore, the coefficient of thermal expansion of the first protective layer 200 and / or the second protective layer 300 is greater than or equal to 5 and less than or equal to 13. This configuration ensures that the second protective layer 300 can more tightly connect the second redistribution layer 900 and the die to be packaged 110, achieving effective interconnection.
[0134] Furthermore, there are multiple second openings 310, which are evenly distributed on the second protective layer 300. This arrangement increases the contact area between the second protective layer 300 and the second redistribution layer 900, thereby achieving a tighter connection between the second redistribution layer 900 and the die to be packaged 110.
[0135] Furthermore, the thickness of the first protective layer 200 and / or the second protective layer 300 is greater than or equal to 25 micrometers and less than or equal to 50 micrometers.
[0136] By limiting the minimum thickness of the first protective layer 200 and the second protective layer 300, sufficient strength can be ensured for both layers to effectively protect the die 110 to be packaged. Simultaneously, the contact area between the second protective layer 300 and the second redistribution layer 900 can be guaranteed, thus ensuring effective interconnection between the second protective layer 300 and the die 110. Limiting the minimum thickness of the first and second protective layers 200 also ensures that the thickness of the die 110 to be packaged is within a suitable range, facilitating the thinner and lighter design of electronic devices.
[0137] The above description is merely a preferred embodiment of this application and is not intended to limit this application in any way. Although this application has disclosed the preferred embodiment as above, it is not intended to limit this application. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content to create equivalent embodiments without departing from the scope of the technical solution of this application. Any simple modifications, equivalent changes, and alterations made to the above embodiments based on the technical essence of this application without departing from the content of the technical solution of this application shall still fall within the scope of the technical solution of this application.
Claims
1. A semiconductor packaging method, characterized in that, The semiconductor packaging method includes: A first protective layer is formed on a first surface of a semiconductor wafer; a first opening is formed on the first protective layer; Thinning the semiconductor wafer; A second protective layer is formed on the second surface of the semiconductor wafer; Semiconductor wafers are cut to form bare dies to be packaged. The bare die to be packaged includes an active side and a back side. The back side is the second surface, the active side is the first surface, the back side is the drain, and pins are provided on the active side. Wherein, the first surface and the second surface are disposed opposite to each other, and the difference in the coefficients of thermal expansion of the first protective layer and the second protective layer is less than or equal to 6; The semiconductor packaging method further includes: Secure the die to be packaged to the lead frame; A second opening is formed in the second protective layer, the second opening exposing the second surface; A second redistribution layer is formed on the side of the second protective layer away from the first protective layer. The second redistribution layer passes through the second opening and is connected to the second surface. The second redistribution layer is also connected to the lead frame. The coefficient of thermal expansion of the second protective layer is located between the coefficients of thermal expansion of the second redistribution layer and the die to be packaged. The semiconductor packaging method further includes: A first redistribution layer is formed on the side of the first protective layer away from the second protective layer, and the first redistribution layer passes through the first opening and is connected to the pin. The second protective layer comprises multiple sub-layers stacked in a vertical direction, at least two of which have different coefficients of thermal expansion, and the coefficients of thermal expansion of the sub-layers are located between the coefficients of thermal expansion of the second redistribution layer and the die to be packaged; wherein the multiple sub-layers are formed layer by layer on the second surface of the semiconductor wafer, and the coefficients of thermal expansion of the sub-layers closer to the die to be packaged are smaller, while the coefficients of thermal expansion of the sub-layers farther from the die to be packaged are larger.
2. The semiconductor packaging method as described in claim 1, characterized in that, The step of fixing the die to be packaged to the lead frame includes: Provide substrate; A lead frame is fixed on a substrate, the lead frame comprising a plurality of spaced conductive posts; The die to be packaged is fixed to the substrate, the first protective layer is connected to the substrate, and the die to be packaged is disposed between two adjacent conductive pillars; A first molding layer is formed, which encapsulates the conductive pillar and the die to be packaged.
3. The semiconductor packaging method as described in claim 1, characterized in that, After forming the first protective layer on the first surface of the semiconductor wafer and before thinning the semiconductor wafer, the following steps are performed: A first opening is formed on the first protective layer, the first opening exposing the pins on the first surface.
4. The semiconductor packaging method as described in claim 1, characterized in that, The semiconductor packaging method further includes: Before the first redistribution layer is formed, the die to be packaged is fixed to the lead frame using a first molding layer; After the first redistribution layer is formed, the first molding layer is thinned on the side away from the first protective layer to expose the end faces of the second protective layer and the lead frame.
5. A semiconductor packaging structure, characterized in that, The semiconductor packaging structure is manufactured by the semiconductor packaging method according to any one of claims 1-4; the semiconductor packaging structure includes: The die to be packaged includes a first surface and a second surface disposed opposite to each other. The first surface is provided with pins, and the back side is the drain. A first protective layer is disposed on the first surface of the bare die to be packaged; A second protective layer is disposed on the second surface of the bare die to be packaged; Wherein, the difference in the coefficients of thermal expansion between the first protective layer and the second protective layer is less than or equal to 6; A first opening is formed on the first protective layer, the first opening exposing the pin; a second opening is formed on the second protective layer, the second opening exposing the second surface; The semiconductor packaging structure further includes: A lead frame includes a plurality of spaced-apart conductive posts, the conductive posts being disposed around the periphery of the die to be packaged; A first redistribution layer is disposed on the first protective layer and electrically connected to the pin and the conductive post; A second redistribution layer is disposed on the second protective layer and electrically connected to the second surface and the conductive pillar; The coefficient of thermal expansion of the second protective layer is located between the coefficients of thermal expansion of the second redistribution layer and the die to be packaged. The second protective layer comprises multiple sub-layers stacked in a vertical direction, at least two of which have different coefficients of thermal expansion, and the coefficients of thermal expansion of the sub-layers are located between the coefficients of thermal expansion of the second redistribution layer and the die to be packaged; wherein the multiple sub-layers are formed layer by layer on the second surface of the semiconductor wafer, and the coefficients of thermal expansion of the sub-layers closer to the die to be packaged are smaller, while the coefficients of thermal expansion of the sub-layers farther from the die to be packaged are larger.
6. The semiconductor packaging structure as described in claim 5, characterized in that, The number of the second openings is multiple, and the multiple second openings are evenly arranged on the second protective layer.
7. The semiconductor packaging structure as described in claim 5, characterized in that, The coefficient of thermal expansion of the first protective layer and / or the second protective layer is greater than or equal to 5 and less than or equal to 13.
8. The semiconductor packaging structure according to any one of claims 5-7, characterized in that, The material of the first protective layer and / or the second protective layer is epoxy resin; and / or, The thickness of the first protective layer and / or the second protective layer is greater than or equal to 25 micrometers and less than or equal to 50 micrometers.