Packaging structure

Abstract

A packaging structure includes a carrier board, a re-distribution layer, and a plurality of dummy patterns. The re-distribution layer is on the carrier board and includes a plurality of dielectric layers and a plurality of conductive patterns, each of which is in one of the plurality of dielectric layers. The plurality of dummy patterns is in each of the plurality of dielectric layers and on the re-distribution layer and is separate from the conductive patterns.

Description

TECHNICAL FIELD

[0001] The present application relates to a packaging structure. BACKGROUND

[0002] With the booming development of the technology industry, 3C electronic products are developing towards the trend of multi-function and high performance, and various packaging technologies applied to chips are also valued. There are many kinds of packaging technologies at present, including fan-out panel level package (FOPLP), chip scale package (CSP), direct chip attached package (DCA) or multi-chip module package (MCM) and other flip chip type packaging modules, or chip stacking technology that integrates chips into three-dimensional integrated circuits (3D IC).

[0003] However, during the packaging process, the mismatch of the thermal expansion coefficients of the materials of each layer will cause the packaging structure to warp, resulting in alignment deviation between the layers and / or reduced packaging alignment accuracy, which reduces the reliability of the packaging structure. SUMMARY

[0004] The purpose of the present application is to provide a packaging structure with reduced warpage.

[0005] One embodiment of the present application provides a packaging structure, comprising: a carrier plate; a redistribution layer on the carrier plate, and comprising: a plurality of dielectric layers; and a plurality of conductive patterns respectively in the plurality of dielectric layers; and a plurality of dummy patterns respectively in the plurality of dielectric layers and on the redistribution layer, and separated from the conductive patterns.

[0006] In one embodiment of the present application, the dummy patterns and the conductive patterns belong to the same film layer.

[0007] In one embodiment of the present application, the thermal expansion coefficient of the dummy patterns is not greater than the thermal expansion coefficient of the conductive patterns.

[0008] In one embodiment of the present application, the thickness of the dummy patterns is not greater than the thickness of the conductive patterns.

[0009] In one embodiment of the present application, the dummy patterns have floating potentials.

[0010] In one embodiment of the present application, the redistribution layer further comprises a plurality of pads on the redistribution layer, and the thickness of the dummy patterns on the redistribution layer is not greater than the thickness of the pads.

[0011] In an embodiment of the present application, a portion of the dummy patterns are evenly distributed in a first dielectric layer of the plurality of dielectric layers.

[0012] In an embodiment of the present application, the package structure has a central region and a peripheral region located at the side of the central region, and the distribution area of the dummy patterns in the peripheral region is greater than the distribution area of the dummy patterns in the central region.

[0013] In an embodiment of the present application, the dummy pattern has a circular, diamond or square shape.

[0014] In an embodiment of the present application, the dummy pattern is made of metal.

[0015] The package structure of the present application can reduce the volume ratio of the dielectric layer by setting the dummy pattern, so as to adjust the stress matching of the redistribution layer, thereby reducing the warpage of the package structure and improving the reliability of the package structure.

[0016] In order to make the above features and advantages of the present application more obvious and easy to understand, the following embodiments are described in detail below, and the accompanying drawings are described as follows. BRIEF DESCRIPTION OF DRAWINGS

[0017] Figure 1 is a cross-sectional view of a package structure according to an embodiment of the present application.

[0018] Figure 2 is a partial top view of a package structure according to an embodiment of the present application.

[0019] Figure 3 is a partial top view of a package structure according to an embodiment of the present application.

[0020] Figure 4 is a partial top view of a package structure according to an embodiment of the present application.

[0021] The following are the reference signs:

[0022] 10, 20, 30, 40: package structure

[0023] 110: carrier plate

[0024] 120: redistribution layer

[0025] C1, C2, C3, C4: conductive pattern

[0026] CA: central region

[0027] D1, D2, D21, D22, D3, D4: dummy pattern

[0028] HC1, HC2, HC3, HC4: thickness

[0029] HD1, HD2, HD3, HD4: thickness

[0030] HPD: thickness

[0031] I1, I2, I3, I4: dielectric layer

[0032] PA: peripheral area

[0033] PD: pad

[0034] V1, V2, V3: via DETAILED DESCRIPTION

[0035] In the drawings, the thickness of layers, films, panels, regions, etc., can be exaggerated for clarity. Like reference numerals may designate like elements throughout the specification. It should be understood that when a element such as a layer, film, region, or substrate is referred to as being "on" or "connected to" another element, it can be directly on or connected to the other element or intervening elements can also be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element, there are no intervening elements present. As used herein the term "connected" can mean physically and / or electrically connected. Further, "electrically connected" or "coupled" can be two elements exist other elements.

[0036] It will be understood that, although the terms "first", "second", "third", etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first "element", "component", "region", "layer" or "section" discussed below could be termed a second "element", "component", "region", "layer" or "section" without departing from the teachings herein.

[0037] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms, including "at least one", unless the content clearly indicates otherwise. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising", or "includes" and / or "including" when used in this specification, specify the presence of stated features, regions, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0038] Further, relative terms such as "lower" or "bottom" and "upper" or "top" can be used herein to describe one element's or another's relationship to another element as illustrated in the Figures. It will be understood that relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the Figures. For example, if the device in one of the figures is turned over, elements described as being on the "lower" side of other elements would then be oriented on "upper" sides of the other elements. The exemplary term "lower" can therefore encompass both an orientation of lower and upper, depending on the particular orientation of the figure. Similarly, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented "above" the other elements. The exemplary term "below" or "beneath" can therefore encompass both an orientation of above and below.

[0039] Exemplary embodiments are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments described herein are not to be construed as limited to the particular shapes of regions as illustrated herein but are to include deviations in shapes that result, for example, from manufacturing. For example, an area illustrated or described as flat can often have rough and / or nonlinear features. Moreover, the illustrated acute angles can be rounded. Thus, the regions illustrated in the figures are schematic and their shapes are not intended to illustrate the precise shape of a region and are not intended to limit the scope of the claims.

[0040] Figure 1 FIG. 1 is a schematic cross-sectional view of a package structure 10 according to an embodiment of the present application. The package structure 10 includes a carrier board 110, a redistribution layer 120 disposed on the carrier board 110, and a plurality of dummy patterns D1, D2, D3, D4 (D1-D4) disposed in the redistribution layer 120 and separated from a plurality of conductive patterns C1, C2, C3, C4 (C1-C4) disposed in the redistribution layer 120.

[0041] In the package structure 10 according to an embodiment of the present application, the dummy patterns D1-D4 are provided to reduce the volume ratio of the dielectric layers I1-I4 to reduce the overall coefficient of thermal expansion of the redistribution layer 120, thereby reducing the warpage of the package structure 10.

[0042] Hereinafter, the embodiments of the respective elements of the package structure 10 will be described in detail with reference to the accompanying drawings, but the present application is not limited thereto. Figure 1

[0043] ​In the present embodiment, the carrier plate 110 is, for example, a carrier to carry the redistribution layer 120. In some embodiments, the carrier plate 110 can have a coefficient of thermal expansion of 3-10 ppm / °C. The material of the carrier plate 110 can be glass, wafer, or other applicable material. For example, in the present embodiment, the material of the carrier plate 110 is glass having a coefficient of thermal expansion of about 8.5 ppm / °C, but the present application is not limited thereto. In other embodiments, the carrier plate 110 can be a wafer, and the wafer can have a coefficient of thermal expansion of about 3 ppm / °C.

[0044] In the present embodiment, the redistribution layer 120 can include four dielectric layers I1-I4, but the present application is not limited thereto. In other embodiments, the redistribution layer 120 can include fewer or more layers of dielectric layers, such as three or five layers of dielectric layers, as needed.

[0045] In the present embodiment, the multiple dielectric layers I1-I4 of the redistribution layer 120 can be sequentially stacked on the carrier plate 110, and the dielectric layers I1-I4 can have a coefficient of thermal expansion of 30-80 ppm / °C, respectively, but the present application is not limited thereto. The materials of the dielectric layers I1-I4 can be selected from polyimide (PI), polybenzoxazole (PBO), benzocyclobutene (BCB), and other suitable materials, respectively. In addition, the dielectric layers I1-I4 can have a single-layer structure or a multi-layer structure, such as a stack of any two or more of the above-mentioned materials, respectively, which can be combined and varied as needed.

[0046] In the present embodiment, the multiple conductive patterns C1-C4 of the redistribution layer 120 can be located in the dielectric layers I2, I3, I4 and on the dielectric layer I4, respectively. For example, in the present embodiment, the conductive pattern C1 can be located in the dielectric layer I2, the conductive pattern C2 can be located in the dielectric layer I3, the conductive pattern C3 can be located in the dielectric layer I4, and the conductive pattern C4 can be located on the dielectric layer I4. Alternatively, the conductive pattern C1 can be located between the dielectric layer I1 and the dielectric layer I2, the conductive pattern C2 can be located between the dielectric layer I2 and the dielectric layer I3, and the conductive pattern C3 can be located between the dielectric layer I3 and the dielectric layer I4.

[0047] In some embodiments, the dielectric layer I2 can have a via V1, and a portion of the conductive pattern C2 can pass through the via V1 to connect the conductive pattern C1. In some embodiments, the dielectric layer I3 can have a via V2, and a portion of the conductive pattern C3 can pass through the via V2 to connect the conductive pattern C2. In some embodiments, the dielectric layer I4 can have a via V3, and a portion of the conductive pattern C4 can pass through the via V3 to connect the conductive pattern C3.

[0048] In some embodiments, the redistribution layer 120 can further include a plurality of pads PD, which can be located on the redistribution layer 120, for example, on the dielectric layer I4, and which can be electrically connected to the conductive pattern C3 through the via V3 of the dielectric layer I4. In this way, the conductive pattern C1 can be electrically connected to the pad PD through the conductive pattern C2 and the conductive pattern C3.

[0049] The conductive patterns C1-C4 and the pads PD can include a metal or an alloy with good electrical conductivity, such as aluminum, molybdenum, titanium, copper, nickel, gold, tin, silver, an alloy thereof, or a combination thereof. For example, in an embodiment, the conductive patterns C1-C4 and the pads PD can each independently be a single-layer structure or a multi-layer structure, such as a multi-layer structure including a titanium layer, an aluminum layer, and a titanium layer stacked in sequence, but the disclosure is not limited thereto.

[0050] The positions, pitches, thicknesses, shapes, and the like of the dummy patterns D1-D4 of the package structure 10 are not particularly limited. For example, in the present embodiment, the dummy patterns D1-D4 can be located in the dielectric layers I2-I4 and on the dielectric layer I4, respectively. That is, the dummy pattern D1 can be located in the dielectric layer I2, the dummy pattern D2 can be located in the dielectric layer I3, the dummy pattern D3 can be located in the dielectric layer I4, and the dummy pattern D4 can be located on the dielectric layer I4 of the redistribution layer 140, but the disclosure is not limited thereto. In some embodiments, the dummy pattern D1 can be located between the dielectric layer I1 and the dielectric layer I2, the dummy pattern D2 can be located between the dielectric layer I2 and the dielectric layer I3, and the dummy pattern D3 can be located between the dielectric layer I3 and the dielectric layer I4.

[0051] In some embodiments, the dummy patterns D1 can belong to the same film layer as the conductive patterns C1 and be separated from each other, and the pitches between the dummy patterns D1 can be determined according to the distribution positions of the conductive patterns C1. In some embodiments, the dummy patterns D2 can belong to the same film layer as the conductive patterns C2 and be separated from each other, and the pitches between the dummy patterns D2 can be determined according to the distribution positions of the conductive patterns C2. In some embodiments, the dummy patterns D3 can belong to the same film layer as the conductive patterns C3 and be separated from each other, and the pitches between the dummy patterns D3 can be determined according to the distribution positions of the conductive patterns C3. In some embodiments, the dummy patterns D4 can belong to the same film layer as the conductive patterns C4 and the pads PD and be separated from each other, and the pitches between the dummy patterns D4 can be determined according to the distribution positions of the conductive patterns C4. In some embodiments, part or all of the dummy patterns D1-D4 can have a floating electric potential.

[0052] In some embodiments, the dummy patterns D1-D4 can have a coefficient of thermal expansion that is not greater than a coefficient of thermal expansion of the conductive patterns C1-C4. For example, when the conductive patterns C1-C4 each have a single layer structure, the dummy patterns D1-D4 can each belong to the same film layer as the conductive patterns C1-C4, and thus the dummy patterns D1-D4 can each have a coefficient of thermal expansion that is equal to a coefficient of thermal expansion of the conductive patterns C1-C4, and the dummy patterns D1-D4 can each have a thickness HD1, HD2, HD3, HD4 (HD1- HD4) that is equal to a thickness HC1, HC2, HC3, HC4 (HC1-HC4) of the conductive patterns C1-C4, respectively.

[0053] Alternatively, in other embodiments, when the conductive patterns C1-C4 each have a multi-layer structure, the dummy patterns D1-D4 can each belong to the same film layer as one of the layers of the multi-layer structure of the conductive patterns C1-C4, and the dummy patterns D1-D4 can each have a coefficient of thermal expansion that is less than, equal to, or greater than a coefficient of thermal expansion of the conductive patterns C1-C4 as a whole, and the dummy patterns D1-D4 can each have a thickness HD1-HD4 that is less than a thickness HC1-HC4 of the conductive patterns C1-C4, respectively.

[0054] Further, in other embodiments, the dummy patterns D1-D4 can each belong to a different film layer than the conductive patterns C1-C4, that is, the dummy patterns D1-D4 can not be formed in the same process step as the conductive patterns C1-C4. Additionally, in some embodiments, the dummy patterns D1-D4 can each independently have a thickness HD1-HD4 that is less than, equal to, or greater than a thickness HC1-HC4 of the conductive patterns C1-C4, respectively.

[0055] In some embodiments, the dummy pattern D4 can have a thickness HD4 that is not greater than a thickness HPD of the pad PD. For example, in some embodiments, the dummy pattern D4 can have a thickness HD4 that is equal to the thickness HPD of the pad PD. In some embodiments, the dummy pattern D4 can have a thickness HD4 that is less than the thickness HPD of the pad PD.

[0056] The dummy patterns D1-D4 can each include a metal or an alloy having good electrical conductivity, such as aluminum, molybdenum, titanium, copper, nickel, gold, tin, silver, an alloy thereof, or a combination thereof. For example, in some embodiments, the dummy patterns D1-D4 can each independently have a single layer structure or a multi-layer structure.

[0057] Hereinafter, the embodiments of the present application will be described using Figures 2-3 Further embodiments of the present application will be described below, and the elements of the embodiments of the present application will be described using Figure 1 the same reference numerals to represent the same or similar elements, and the description of the same technical content will be omitted. For the omitted portions, reference can be made to the description of the embodiments of the present application described above. Figure 1The embodiments are not described again in the following description.

[0058] Figure 2 is a partial top view of a package structure 20 according to an embodiment of the present application. For the sake of simplicity of the drawings, Figure 2 The dielectric layer I3, the conductive pattern C2, and the dummy pattern D2 are schematically shown, and other components are omitted.

[0059] As compared with the package structure 10 shown in Figure 1 As compared with the package structure 20 shown in Figure 2 The package structure 30 shown in differs from the package structure 20 shown in that the dummy pattern D2 of the package structure 30 is uniformly distributed in the dielectric layer I3, and the shape of the dummy pattern D2 can be a rhombus.

[0060] Similarly, in some embodiments, the dummy pattern Dl can be uniformly distributed in the dielectric layer I2. Alternatively, in some embodiments, the dummy pattern D3 can be uniformly distributed in the dielectric layer I4. Alternatively, in some embodiments, the dummy pattern D4 can be uniformly distributed on the dielectric layer I4.

[0061] Figure 3 is a partial top view of a package structure 30 according to an embodiment of the present application. For the sake of simplicity of the drawings, Figure 3 The dielectric layer I3, the conductive pattern C2, and the dummy pattern D2 are schematically shown, and other components are omitted.

[0062] As compared with the package structure 20 shown in Figure 2 As compared with the package structure 30 shown in Figure 3 The package structure 40 shown in differs from the package structure 20 shown in that the shape of the dummy pattern D2 of the package structure 40 is a square.

[0063] Figure 4 is a partial top view of a package structure 40 according to an embodiment of the present application. For the sake of simplicity of the drawings, Figure 4 The dielectric layer I3, the conductive pattern C2, and the dummy pattern D2 are schematically shown, and other components are omitted.

[0064] As compared with the package structure 20 shown in Figure 2 As compared with the package structure 40 shown in Figure 4 The package structure 40 shown in differs from the package structure 20 shown in that the shape of the dummy pattern D2 of the package structure 40 is a square.

[0065] In the present embodiment, the packaging structure 40 can have a central area CA and a peripheral area PA located at the side of the central area CA, and the dummy pattern D2 can include a dummy pattern D21 and a dummy pattern D22, wherein the dummy pattern D21 can be uniformly distributed in the central area CA, the dummy pattern D22 can be distributed in the peripheral area PA, and the distribution area of the dummy pattern D22 can be greater than the distribution area of the dummy pattern D21. In this way, the warping of the peripheral area PA of the packaging structure 40 can be further inhibited.

[0066] In summary, the packaging structure of the present application can reduce the volume ratio of the dielectric layer by setting the dummy pattern, so as to adjust the stress matching of the redistribution layer. In this way, the warping amount of the packaging structure can be reduced, and the reliability of the packaging structure can be improved.

[0067] Although the present application has been disclosed with the above embodiments, it is not intended to limit the present application, and those skilled in the art can make some changes and modifications without departing from the spirit and scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1.A package structure, wherein the package structure has a central region and a peripheral region located at the side of the central region, the package structure comprising: a carrier board, the material of the carrier board is glass with a coefficient of thermal expansion of 8.5ppm / ℃; a redistribution layer comprising a plurality of dielectric layers and a plurality of conductive patterns, located on the carrier board, the carrier board is a carrier to carry the redistribution layer, wherein: the plurality of dielectric layers comprises a first dielectric layer, a second dielectric layer, a third dielectric layer and a fourth dielectric layer stacked in sequence on the carrier board; the first dielectric layer, the second dielectric layer, the third dielectric layer and the fourth dielectric layer have a coefficient of thermal expansion of 30-80ppm / ℃ respectively; the first dielectric layer and the carrier board do not have any via; and the plurality of conductive patterns are located in the plurality of dielectric layers respectively; and a plurality of central region dummy patterns located in the central region, comprising a first central region dummy pattern, a second central region dummy pattern, a third central region dummy pattern and a fourth central region dummy pattern stacked in sequence on the carrier board, the first central region dummy pattern, the second central region dummy pattern, the third central region dummy pattern and the fourth central region dummy pattern are located in the plurality of dielectric layers respectively and separated from the conductive patterns, the first central region dummy pattern is uniformly distributed in the second dielectric layer, the second central region dummy pattern is uniformly distributed in the third dielectric layer, and the third central region dummy pattern is uniformly distributed in the fourth dielectric layer; and a plurality of peripheral region dummy patterns located in the peripheral region, each of the peripheral region dummy patterns has an area greater than that of each of the central region dummy patterns. 2.The package structure of claim 1, wherein the dummy patterns and the conductive patterns belong to the same film layer. 3.The package structure of claim 1, wherein the coefficient of thermal expansion of the dummy patterns is not greater than that of the conductive patterns, any one of the plurality of conductive patterns has a multi-layer structure, and the dummy patterns and one layer of the multi-layer structure belong to the same film layer. 4.The package structure of claim 1, wherein the thickness of the dummy patterns is not greater than that of the conductive patterns. 5.The package structure of claim 1, wherein the dummy patterns have floating potentials. 6.The package structure of claim 1, wherein the redistribution layer further comprises a plurality of pads located on the redistribution layer, and the thickness of the dummy patterns located on the redistribution layer is not greater than that of the pads. 7.The package structure of claim 1, wherein the dummy patterns have a circular, diamond or square shape. 8.The package structure of claim 1, wherein the material of the dummy patterns is metal.

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