Crystal oscillator start-up circuit and method

Abstract

A crystal resonator is configured to be coupled to a start-up circuit, the start-up circuit comprising an H-bridge circuit having a number of switches. A number of switch control signals are generated in response to detecting a zero-crossing event of a motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator with a first polarity during a first switch control phase and with a second, opposite polarity during a second switch control phase. During a respective first sub-phase of the respective switch control phase, the number of switches are configured in a first configuration to couple a power supply node to the respective crystal resonator terminal. During a respective second sub-phase of the respective switch control phase, the number of switches are configured in a second configuration to couple the power supply node to the respective crystal resonator terminal. In the second configuration, a resistance between the power supply node and the respective crystal resonator terminal is greater than in the first configuration. A zero-crossing is detected during each respective second sub-phase.

Description

Technical Field

[0001] This disclosure relates to a circuit and method for starting a crystal oscillator. Background Technology

[0002] Short startup time and low power consumption are key features for many products. This is especially true for low-power wireless duty cycle systems (IoT, BLE, car keys), where energy is often scarce because it is transferred via batteries or even energy harvesting. The system's startup time and startup energy are typically determined primarily by the crystal oscillator (XO) and resonators such as MEMS resonators, crystals, ceramics, or RLC circuits.

[0003] A typical way to start up an XO is through noise amplified by a gain stage. However, the initial noise is small and not well-defined. The start-up time is relatively long and limited to a certain minimum, depending on the initial noise value. The first step in improving the start-up time is to provide an initial "kick" or pulse to the XO at startup. In this way, the initial motional current in the crystal (Xtal) is well-defined. However, the maximum initial motional current is limited by the maximum possible kick amplitude on the crystal, and therefore by the supply voltage. The start-up time can be further improved by periodically providing pulses in a well-defined manner. By applying pulses in a well-defined manner, the motional current can be continuously increased to a final value. If the frequency and phase of the injected energy are exactly the same as the motional current in the crystal, then the start-up time is optimized to the minimum possible value. Summary of the Invention

[0004] Various aspects of this disclosure are defined in the appended claims. In a first aspect, a crystal oscillator startup circuit is defined, comprising: an H-bridge circuit including a plurality of switches, the H-bridge circuit being configured to be coupled to a crystal resonator; a comparator having a first comparator input configured to be switchably coupled to a terminal of the crystal resonator, a second comparator input configured to be coupled to a power node, a comparator clock input, and a comparator output configured to transition between a first state and a second state in response to a zero-crossing event of a motional current in the crystal resonator; a comparator clock generator having a first comparator clock generator input coupled to the comparator output, a second comparator clock generator input configured to receive a start signal, and a comparator clock generator output coupled to the comparator clock input; and a switch control generator coupled to the comparator clock output and configured to generate a plurality of switches synchronized with the comparator clock. A control signal is used to control the plurality of switches, which are configured to apply a voltage source to the crystal resonator terminal with a first polarity during a first switch control phase and with an opposite second polarity during a second switch control phase. The plurality of switches are configured in a first configuration to couple a power node to the corresponding crystal resonator terminal during a corresponding first sub-phase of the respective switch control phase; and in a second configuration to couple the power node to the corresponding crystal resonator terminal during a corresponding second sub-phase. In the second configuration, the resistance between the power node and the corresponding crystal resonator terminal is greater than the resistance in the first configuration. The switch control generator is further configured to couple the first comparator input to the corresponding crystal resonator terminal during each second sub-phase of the respective second sub-phase.

[0005] In one or more embodiments, the crystal oscillator startup circuit may be configured to alternate between the first switch control phase and the second switch control phase for each comparator clock cycle.

[0006] In one or more embodiments, the comparator may be configured to calibrate the comparator offset voltage during a first phase of the comparator clock cycle and to compare the input during a second phase of the comparator clock cycle.

[0007] In one or more embodiments, the comparator may be enabled during each corresponding second sub-stage.

[0008] In one or more embodiments, the comparator may include: a differential amplifier stage comprising: an operational transconductance amplifier (OTA); a first capacitor coupled to a first OTA input; and a second capacitor coupled to a second OTA input, wherein the comparator is configured to receive a comparator clock defining a calibration phase and a comparison phase, wherein during the calibration phase, the comparator is configured to control a plurality of comparator switches to: switchably couple the first comparator input to the first OTA input via the first capacitor; and switchably couple the second comparator input to the second OTA input via the second capacitor; and wherein during the comparison phase, the comparator is configured to control the plurality of comparator switches to: switchably couple the first comparator input to the first OTA input via the first capacitor and to the second OTA input via the second capacitor; and switchably couple a first OTA output to the first OTA input and a second OTA output to the second OTA input.

[0009] In one or more embodiments, the comparator may include a single-ended output stage OTA coupled to the output of the differential amplifier stage, and having a first input coupled to a first OTA output of the differential amplifier stage, a second input coupled to a second OTA output, and an output coupled to a buffer, wherein the buffer is configured to have a shifted voltage disconnect level.

[0010] In one or more embodiments, the plurality of switches may further include: a first switch and a third switch, which are arranged in series between the power node and the second power node; a second switch and a fourth switch, which are arranged in series between the power node and the second power node; a first sensing switch, which is arranged in parallel with the first switch; a second sensing switch, which is arranged in parallel with the second switch; a first common node of the first switch and the third switch is configured to be coupled to a first crystal resonator terminal, and a second common node of the second switch and the fourth switch is configured to be coupled to a second crystal resonator terminal.

[0011] In one or more embodiments, during the first switch control phase, the switch control generator may be further configured to: close the first sensing switch and the fourth switch, and close the first switch during the first sub-phase of the first switch control phase; and open the first switch during the second sub-phase of the first switch control phase; and during the second switch control phase, the switch control generator may be configured to: close the second sensing switch and the third switch, and close the second switch during the first sub-phase of the second switch control phase; and open the second switch during the second sub-phase of the second switch control phase.

[0012] In one or more embodiments, the crystal oscillator startup circuit may further include: a first comparator switch coupled between the first crystal resonator terminal and the first comparator input; and a second comparator switch coupled between the second crystal resonator terminal and the first comparator input; wherein the switch control generator is further configured to: close the first comparator switch during a second sub-phase of the first switch control phase; and close the second comparator switch during a second sub-phase of the second switch control phase.

[0013] In one or more embodiments, after at least two comparator clock cycles: during a corresponding first sub-phase of the corresponding switch control phase, the plurality of switches may be configured in a third configuration to couple the power node to the corresponding crystal resonator terminal; and during a corresponding second sub-phase, the plurality of switches are configured in a fourth configuration to couple the power node to the corresponding crystal resonator terminal; wherein in the fourth configuration, the resistance between the power node and the corresponding crystal resonator terminal is greater than the resistance in the third configuration and less than the resistance in the second configuration.

[0014] In one or more embodiments, the switch control generator may be configured to control the plurality of switches to be configured according to the first configuration and the second configuration or the third configuration and the fourth configuration, depending on at least one of the number of comparator clock cycles and the amplitude of the crystal resonator signal.

[0015] In one or more embodiments, the crystal oscillator startup circuit may additionally include current leakage and delay compensation circuitry coupled between the power supply node and the second comparator input.

[0016] In one or more embodiments, the crystal oscillator startup circuit may additionally include a single trigger circuit having an input coupled to a start-up input and an output coupled to the second comparator clock generator input.

[0017] In one or more embodiments, the comparator clock generator may further include a series arrangement of a first flip-flop, a delay element, and a second flip-flop, and an OR gate having a first input coupled to the input of the first comparator clock generator, a second input coupled to the input of the second comparator clock generator, and an output coupled to the clock inputs of the first and second flip-flops, wherein the first flip-flop is configured as an inverting flip-flop, and wherein the comparator clock output is the XOR of the delayed output of the first flip-flop and the output of the second flip-flop.

[0018] In one or more embodiments, the switch control generator may further include: a logic gate having a first input switch coupled to a start-up input, a second input coupled to the output of the comparator clock generator, and a switch control flip-flop configured as an inverting flip-flop having a clock input coupled to the output of the logic gate and an output coupled to a second delay element; and a switch control logic module coupled to the switch control flip-flop output and the delayed switch control flip-flop output, and configured to generate the switch control signal from the switch control flip-flop output and generate the delayed switch control flip-flop output from the second delay element.

[0019] In one or more embodiments, the first switch control stage signal may correspond to the output of the switch control trigger, and the second switch control stage signal may correspond to the inverted output of the switch control trigger.

[0020] In one or more embodiments, the startup circuit may include a crystal oscillator circuit, the crystal oscillator circuit further including a steady-state circuit configured to be switchably coupled to a resonator crystal, wherein during the startup phase, the steady-state circuit is decoupled from the resonator crystal, and after the startup phase, the H-bridge circuit is decoupled from the resonator crystal, and the resonator crystal is coupled to the steady-state circuit.

[0021] In one or more embodiments, an amplitude detector may be coupled to the resonator crystal, wherein the circuitry is configured to switch from the startup phase to a steady-state phase in response to the amplitude exceeding a predetermined value.

[0022] Embodiments of the startup circuit may be included in one of an Internet of Things (IoT) device, a Bluetooth device, and an ultra-wideband (UWB) device.

[0023] In a second aspect, a method for starting a crystal resonator is defined, the crystal resonator being configured to be coupled to a startup circuit including an H-bridge circuit comprising a plurality of switches, the method comprising: generating a plurality of switch control signals in response to detecting a zero-crossing event of a motional current in the crystal resonator; controlling the plurality of switches of the H-bridge circuit with the switch control signals to apply a voltage to terminals of the crystal resonator with a first polarity during a first switch control phase and with an opposite second polarity during a second switch control phase; configuring the plurality of switches with a first configuration to couple a power node to a corresponding crystal resonator terminal during a corresponding first sub-phase of the respective switch control phase; and configuring the plurality of switches with a second configuration to couple the power node to the corresponding crystal resonator terminal during a corresponding second sub-phase of the respective switch control phase; wherein, in the second configuration, the resistance between the power node and the corresponding crystal resonator terminal is larger than that in the first configuration; and detecting each zero-crossing during each corresponding second sub-phase. Attached Figure Description

[0024] In the accompanying drawings and description, similar reference numerals denote similar features. Embodiments will now be described in detail only by way of examples illustrated in the accompanying drawings, in which:

[0025] Figure 1 An example crystal oscillator circuit and operating waveforms are shown, illustrating the injection voltage and dynamic current.

[0026] Figure 2 A simplified example diagram illustrating a crystal resonator using a self-timing energy injection technique is shown.

[0027] Figure 3 A crystal oscillator startup circuit according to an embodiment is shown.

[0028] Figure 4 It shows in Figure 3 The waveform during the operation of the startup circuit.

[0029] Figure 5 A crystal oscillator circuit including a startup circuit is shown according to an embodiment.

[0030] Figure 6 It shows in Figure 5 The waveform during the operation of the circuit.

[0031] Figure 7A A comparator for a startup circuit according to an embodiment is shown.

[0032] Figure 7B It shows in Figure 7A The waveform during the operation of the comparator.

[0033] Figure 7C It shows Figure 7A The circuit implementation scheme for the output stage of the comparator.

[0034] Figure 7D It shows the use of Figure 7A A circuit implementation scheme for a differential OTA comparator.

[0035] Figure 8 It shows the use of Figure 5 An example of a leakage compensation circuit for a crystal oscillator circuit.

[0036] Figure 9 An example implementation of the logic for generating the switching clock is shown.

[0037] Figure 10 A method for self-timing startup of a crystal resonator according to an embodiment is shown. Detailed Implementation

[0038] Figure 1 A schematic block diagram of an example crystal oscillator circuit 100, including a self-timing start-up circuit 110 and a steady-state oscillator circuit 120, is shown. The schematic block diagram of the crystal oscillator design 100 also includes an example voltage waveform 130 and a resulting motional current waveform 140. The crystal resonator 150 can be represented by a circuit of resistor 152, inductor 154, and capacitor 156 (RLC), wherein the motional current 158... It passes through the RLC circuit and is positioned in parallel with capacitor 160.

[0039] In operation, firstly, the startup circuit 110 is connected to the crystal resonator 150 via switches 112 and 114 for a certain period of time. During this period, the injected switching voltage 130 alternates its polarity near the zero-crossing point 132, thereby increasing the amplitude of the induced current 140 over time. After the injection time provided by the startup circuit 110 has sufficiently increased the oscillation amplitude of the induced current of the crystal oscillator, the crystal is then connected to the steady-state oscillator circuit 120 via switches 112 and 114 to maintain oscillation.

[0040] Figure 1 The square wave injection waveform 130 and the resulting increased motional current are also shown. Example 140. Assuming a high crystal quality factor (R... m If the current is relatively small, then the motional current is generated. 140 can be calculated as increasing linearly with time, where the slope is: Where A is the amplitude of the fundamental wave of the injected waveform. Unlike circuits based on negative resistance, the startup slope does not depend on the parasitic capacitance C. P 160.

[0041] The circuit implementation of the power supply sets a voltage step on the crystal oscillator, thereby responding to changes in the sign of the current flowing through the crystal oscillator, i.e., by detecting... The zero-crossing of 140° switches the polarity of the voltage source applied to the crystal oscillator, and this circuit implementation can provide a self-timed energy injection waveform to the crystal oscillator.

[0042] Figure 2 A simplified diagram illustrating a crystal resonator 200 using a self-timing energy injection technique is shown. As illustrated, any voltage source 204 used to drive the crystal resonator 200 (the polarity of which depends on the sign of the current flowing through the crystal resonator 200) can be used as an injection waveform applied to the crystal resonator 200, wherein the injection waveform can be switched based on the sign of the current 202 flowing through the crystal resonator 200. Because the injection waveform is self-timing, the signal frequency of the injection waveform automatically matches the crystal frequency without the need for a separate injection oscillator to create the waveform.

[0043] Self-timed energy injection depends on the dynamic current I. m The measurement of I. However, I cannot be directly measured. m Because of the dynamic branching and C p Parallel connection; any current measured at the crystal oscillator terminals may flow into the motional branch or C. p In the middle. This can be achieved by ensuring that current does not flow into the parasitic capacitance C. p This limitation is overcome by creating a branch in the crystal oscillator so that the current measured at the crystal oscillator terminals can only flow through the moving branch. In some examples, this is achieved by applying a (quasi-)constant voltage to the crystal oscillator.

[0044] In a self-timed injection scheme, the zero-crossing of the induced current must be detected, and energy must be injected with minimal delay. The total delay (phase error) should be less than 90° of the crystal's oscillation period. This is achieved by measuring the switching resistance (R) of the H-bridge. sw The zero-crossing is detected by the voltage polarity on the circuit, and the polarity is measured using a comparator.

[0045] The switching resistor should be large enough to create a voltage swing, thus enabling the detection of the zero-crossing of the motional current with a sufficiently small delay. However, if the switching resistor is too large, the settling time is too long, and therefore the relatively small motional voltage swing cannot be detected. To shorten the settling time, X can be reduced during startup by disabling the capacitor bank implementing the load capacitance. p and X n The load capacitor C on load .

[0046] For switches implemented with MOS transistors, the settling time can be shortened by using a self-quenching NMOS switch connected in parallel to the PMOS switch to pull the voltage up to the supply voltage minus the NMOS threshold voltage (Vdd-Vth). The settling time is not optimized because it still must settle from Vdd-Vth to approximately Vdd. An excessively large PMOS switch resistor cannot be chosen, as it introduces a phase shift (phase error) between the zero-crossing of the induced current and the zero-crossing of the voltage across the switch resistor. Therefore, depending on the transistor specifications and (parasitic) load capacitance, the amplitude of the initial induced voltage swing Vsw_pk across the switch can be very small, for example, only in the range of approximately 0.1mV-2mV.

[0047] Furthermore, only when the amplitude of the voltage swing is greater than the comparator offset and the offset voltage V is generated due to leakage (from the switch and pads) offset The motional current can only be detected when the offset caused by the voltage fluctuation is detected. Even if the zero-crossing of a small voltage swing can be detected, it is difficult to reduce the phase error α. error Keep it small enough. Startup time is proportional to phase error, and if the phase error is greater than 90°, the XO may not start at all.

[0048] The total phase error is equal to α error =α offset +α comp +α i-v ,in:

[0049] The phase error caused by comparator offset is: α offset =arcsin(V offset / V sw_pk )

[0050] The phase error caused by the delay in the comparator and switching circuit system is: α comp

[0051] The zero-crossing of the dynamic current and the voltage across the sensing resistor are related by the capacitive load C. load The resulting phase error: α i-v =arctan(ω*R) sw *C load )

[0052] Example 1:

[0053] In this example, the maximum tolerable comparator latency at startup is calculated.

[0054] Assumption

[0055] F xtal =50MHz

[0056] For the maximum swing V sw_pkOptimized R sw (R sw =X Cload )

[0057] V sw_pk = 1mV (initial peak voltage of the swing across the sensing resistor)

[0058] V offset_max = 0.5mV (leakage + comparator)

[0059] This is given: α offset =30° and α i-v =45°. Therefore, the maximum comparator phase shift should be less than α. comp =90-30-45=15° or ΔT comp <15 / 360*1 / 50*10 6 <833ps. Therefore, in addition to an acceptable low offset, the comparator should also have a large gain-bandwidth product to keep the delay sufficiently small.

[0060] In the example startup circuits described in European Patent 19153629.1 and U.S. Patent Application 16 / 751233, the margin ΔT is increased by detecting the polarity of the comparator offset and swapping the input if the comparator offset is not negative. comp As shown in Example 2 below.

[0061] Example 2:

[0062] In this example, α is increased by swapping the comparator inputs when the comparator offset is not negative. comp The margin on.

[0063] Assumption

[0064] F xtal =50MHz

[0065] For the maximum swing V sw_pk Optimized R sw (R sw =X Cload )

[0066] V sw_pk =1mV

[0067] V offset <0mV (Comparator, offset due to leakage is assumed to be zero)

[0068] This is given: α offset =0°, α i-v =45° and α comp <45°→ΔT comp<2.5ns. Now, the margin on the comparator delay is increased. However, the startup offset should still be less than 1mV (V). offset <V sw_pk ).

[0069] However, in many applications, the initial peak voltage across the sense resistor swing is often even smaller, making it difficult to robustly detect this initial peak voltage while keeping the delay sufficiently small. Therefore, detecting the polarity of the comparator offset and swapping the inputs when the comparator offset is not negative can lead to unreliable startup. For inexpensive crystals with small package sizes, the motional inductance can be large, further reducing the maximum initial motional current and thus the switching current Vs. sw_pk The maximum initial motional voltage swing on the crystal. Additionally, a crystal with a higher frequency reduces the maximum allowable delay.

[0070] Figure 3 A startup circuit 300 for a crystal oscillator according to an embodiment is shown. The startup circuit 300 includes a comparator clock generator 320, a switch control generator 330, a comparator 340, and an H-bridge circuit 350.

[0071] The H-bridge circuit 350 includes a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, and a first sensing switch SR. P Second sensing switch SR N First sensing switch SR P A third switch S3 is connected in series between the first power supply node 302 and the second power supply node 304. The first power supply node 302 can be an analog power supply VDDA, and the second power supply node 304 can be ground. In other examples, the first power supply node 302 can be ground, and the second power supply node 304 can be an analog power supply VDDA. In these examples, the connections to the non-inverting input and the inverting input of comparator 340 should also be swapped.

[0072] Second sensing switch SR N The fourth switch S4 is connected in series between the first power node 302 and the second power node 304. The crystal resonator 310 has a connection that can be connected to the switch SR. P The first end X of the first common node 314 between S3 and S3 P and can be connected to switch SR N The second end X of the second common node 316 between S4 and S4 N The first switch S1 can be connected between the first common node 314 and the first power node 302. The second switch S2 can be connected between the second common node 316 and the first power node 302.

[0073] First sensing switch SR P Second sensing switch SR N It can have a higher on-resistance value than the first switch S1 and the second switch S2.

[0074] The first power supply node 302 can be connected to the inverting input of comparator 340. The first comparator switch SX... P It can be connected between the first common node 314 and the non-inverting input 306 of the comparator 340. The second comparator switch SX N It can be connected between the second common node 316 and the non-inverting input 306 of comparator 340. Comparator output 322 can be connected to comparator clock generator 320. It is configured to output comparator clock φ. comp The comparator clock output 308 can be connected to comparator 340 and to the input of switch control generator 330. Comparator clock generator 320 can have a start pulse input 318. Switch control generator outputs 312_1 to 312_6 output corresponding timing control signals φ. p φ psub1 φ psub2 φ n φ nsub1 φ nsub2 These corresponding timing control signals φ p φ psub1 φ psub2 φ n φ nsub1 φ nsub2 They can be connected to control the first switch S1(φ) separately. psub1 ), second switch S2 (φ nsub1 ), third switch S3 (φ n ), fourth switch (φ p ), first sensing switch SR P (φ p ), second sensing switch SR N (φ n First comparison switch SX P (φ psub2 ) and the second comparator switch SX N (φ nsub2 ).

[0075] Switches S1-S4, SR N SX P It can typically be implemented as an NMOS or PMOS transistor, where the control signal φ from the switch control generator 330... p φ psub1 φ psub2 φ n φ nsub1 φnsub2 The corresponding gates are connected to each MOS transistor. For the startup circuit 300 shown, the first switch S1, the second switch S2, and the first sensing switch SR... P Second sensing switch SR N This can be implemented using a PMOS transistor. The third switch S3 and the fourth switch S4 can initially be implemented as NMOS transistors. The first comparator switch SX... P Second comparator switch SX N This can be implemented using a PMOS transistor, where vdda is the reference of comparator 340.

[0076] In the following description, the term "activity" is used to indicate a phase of a switch control signal in which a switch or circuit system controlled by the signal is closed or activated.

[0077] The term "inactive" is used to indicate a phase of the switch control signal in which the switch or circuit system controlled by the signal is turned off or deactivated. The switch control signal waveform used to illustrate the operation of the startup circuit in various embodiments is shown as active high. However, it should be understood that, for example, if the switch is implemented as a PMOS transistor, a low-active signal is required, and therefore the signal will be inverted to implement the desired operation of the corresponding switch.

[0078] refer to Figure 4 Describe the operation of the startup circuit 300. Figure 4 Example waveform 400 is shown during operation of the startup circuit 300. Startup is enabled by a "start" signal on a start pulse input 318, which can be generated, for example, by a single trigger circuit or any other suitable circuit system. The signal φ generated by the comparator clock generator 320... comp It has an initial transition from high to low in response to the start pulse, as shown, and then after a predetermined delay time Δφ comp_start Then it transitions from low to high again. Whenever comparator 340 detects a zero crossing, it triggers a subsequent high-to-low transition from comparator output 322 (“compout”). Comparator clock signal φ comp The comparator is controlled to be active when it compares the signals at the input, and to be inactive during which, in some cases, the comparator may perform calibration.

[0079] The switch control generator 330 receives the comparator clock signal φ comp The switch control generator 330 generates a clock signal φ from the comparator. comp The obtained switch control signal.

[0080] When the control signal φn When inactive, the control signal φ p It is in the active phase, and vice versa. Control signal φ psub1 In the control signal φ p The signal that is active during the first sub-phase 402 of the active phase. Control signal φ psub2 In the control signal φ p The signal is active during the second sub-phase 404 of the active phase. Similarly, signal φ nsub1 φ nsub2 In the control signal φ n The activity phase is active during the first sub-phase 406 and the second sub-phase 408.

[0081] The first sub-stages 402 and 406 can be represented as Δφ pulse The duration of the activity. Waveforms Xp and X N The voltage changes at common nodes 314 and 316 connected to the corresponding terminals of crystal resonator 320 are shown. The signal “comp IN+” represents the signal at the non-inverting input 306 of comparator 340, and the signal I... m The dynamic current is shown.

[0082] Table 1 below shows the operation of the switch during the active phase of the switch control signal. Unless otherwise specified, the switch is open.

[0083]

[0084] Table 1

[0085] In φ p During each comparison cycle in the active state, at φ psub1 During the first active sub-phase 402, in the first configuration, switches S1 and SR are active. p It can be connected in parallel between the first common node 314 and the power rail, with the first common node 314 connected to the crystal resonator terminal (Xp). The effective resistance will be between switches S1 and SR. p The combination of resistors. Compared to SRp, switch S1 can have a much lower on-resistance, which reduces the settling time of the voltage at node Xp. Specifically, if a PMOS transistor is used to implement switch S1, this ensures that node Xp is always pulled up to vdda.

[0086] In the second sub-stage 404, in the second configuration, switch S1 is open and SR pKeep closed. Compared to the first configuration, the effective resistance between power rail 302 and the crystal resonator terminal Xp is now higher. This allows for easier zero-crossing detection because the voltage drop across the resistance will be larger. In the second sub-stage 404, node Xp can also be controlled via switch SX. P Coupled to comparator 340. After the start of the second sub-stage 404, via φ comp Enabling comparator 340 can be achieved by selecting Δφ. comp_start >Δφ pulse To ensure.

[0087] Comparator 340 can detect a zero-crossing of the voltage at some point during the second sub-stage 404, which will correspond to a phase delay Δφ. i-v The subsequent motional current I m The zero-crossing. In another delay Δφ performed by the comparator. comp_delay Then, the polarity of the voltage applied to crystal 310 is reversed, i.e., φ p It becomes inactive, while φ n It becomes active. Then, the period is compared at φ. n It repeats in a similar manner when it is active.

[0088] The startup circuit 300 can provide a more robust self-timing startup for the crystal oscillator. Since the comparator has a defined comparison enable time in each cycle (which occurs during the corresponding second sub-stage), the comparator can perform offset compensation when not comparing to improve detection sensitivity. Furthermore, because the startup circuit has a defined first sub-stage, optimal transistors can be used to implement the additional switches S1, S2 of the H-bridge circuit to minimize settling time by reducing the resistance between the power supply node 302 and the corresponding terminals of the crystal resonator 310.

[0089] In some examples, the first sensing switch SR P Second sensing switch SR N This can be implemented using multiple transistors connected in parallel, each of which can be individually selected, and can be represented as SR. P1 SR P2 SR P3 , ..., SR Pn and SR N1 SR N2 SR N3 , ..., SR NnThis allows the effective sense resistance to change with each comparator clock cycle. For example, during initial startup, the sense resistance value may need to be relatively high to detect a voltage drop because the initial amplitude of the oscillation is relatively small. The switch can be configured in a first and second configuration during different sub-stages as described above, and by selecting, for example, SR, only depending on the switch clock phase. P1 or SR N1 This provides a relatively high sensing resistance. After several comparator clock cycles, the amplitude can increase, and therefore the sensing resistance value per cycle can decrease. In this case, the first and second configurations described above can be replaced by a third and a fourth configuration, where, for example, when φ p When active, select SR P1 SR P2 SR P3 Instead of just choosing SR P1 And similarly, when φ n When active, select SRN1, SRN2, SRN3 instead of SR. N1 In the third and fourth configurations, the effective sense resistance value is reduced compared to the first and second configurations.

[0090] Reducing the sensing resistance value can reduce the required startup time. This can be achieved, for example, through a counter (not shown) coupled to the comparator clock output or connected to the crystal resonator terminal X. N X P An amplitude detector (not shown) is used to determine when the sense resistance value changes.

[0091] Startup circuits using an external clock require a very accurate clock, which can be an integrated oscillator. The required accuracy (frequency deviation << 0.2%) of integrated oscillators is difficult to achieve and also requires significant area and power. The requirements for integrated oscillators can be relaxed using techniques such as calibration, jitter injection, chirped injection, or synchronous injection. However, the efficiency is quite low in terms of startup time reduction and energy saving. The self-timing injection startup circuit 300 solves the accuracy problem because it does not require an (accurate) external clock and allows energy to be injected with a sufficiently small delay (phase difference) relative to the motional current phase for reliable startup operation.

[0092] Figure 5 A crystal oscillator circuit 500 according to an embodiment is shown. The crystal oscillator circuit 500 has a startup circuit and a steady-state oscillator circuit 580, which is connected via a switch S1. EN and S2 EN It is coupled to the crystal resonator 510 and controlled by the steady-state control line 548 (ss_enable).

[0093] The crystal's startup circuit includes a comparator clock generator 520, a switch control generator 530, and a comparator 540. The startup circuit of the crystal oscillator circuit 500 may include a first switch S1, a second switch S2, a third switch S3, a fourth switch, and a first sensing switch SR. P Second sensing switch SR N H-bridge circuit. First sensing switch SR P The first power node 502 is connected in series with the third switch S3 between the first power node 502 and the second power node 504. The first power node 502 can be an analog power supply VDDA, and the second power node 504 can be grounded. The first sensing switch SR P Second sensing switch SR N It can be a single switch and sensing resistor, or multiple individually selectable switches and sensing resistors arranged in parallel. In some examples, the sensing resistor can be the channel resistance of a MOS switch, and therefore the switch and R... sense The functions of the resistors can be combined. In other examples, the first power supply node 502 can be ground, and the second power supply node 504 can be an analog power supply VDDA. In these examples, the connections to the non-inverting input and the inverting input of comparator 540 should also be swapped.

[0094] Second sensing switch SR N The fourth switch S4 is connected in series between the first power node 502 and the second power node 504. The crystal resonator 510 can be connected to the first terminal X. P With the second end X N Between, the first end X P Connected to switch SR P The first common node 514 between S3 and the second end X N Connected to switch SR N The second common node 516 between S4 and S4. The first switch S1 can be connected between the first common node 514 and the first power node 502. The second switch S2 can be connected between the second common node 516 and the first power node 502.

[0095] First capacitor C1 OSC and the first capacitor switch S1 CAP It can be connected between the first common node 514 and ground 504. Second capacitor C2 OSC Second capacitor switch S2 CAP It can be connected between the second common node 516 and ground 504. First capacitor switch S1 CAP Second capacitor switch S2 CAPIt can be controlled by selection input 546 (capbank_sel). In some examples, a set of capacitors and switches can be arranged in parallel between the first common node 514 and ground 504 and between the second common node 516 and ground 504, so that the load capacitance can be changed.

[0096] First sensing switch SR P Second sensing switch SR N It can have a higher on-resistance R than the first switch S1 and the second switch S2. sense value.

[0097] First comparator switch SX P It can be connected between the first common node 514 and the non-inverting input 506 of the comparator 540. The second comparator switch SX N It can be connected between the second common node 516 and the non-inverting input 506 of comparator 540. Comparator output 522 can be connected to comparator clock generator 520. The inverting input of comparator 540 can be connected to the first power node 502 via optional leakage and delay compensation module 570.

[0098] The comparator clock generator 520 includes an OR gate OR1 having a start input 518 connected to the output of a single-trigger circuit 542. The input of the single-trigger circuit 542 is connected to a faster enable 544. The output 526 of the OR gate OR1 can be connected to the clock inputs of the first flip-flop FF1 and the second flip-flop FF2. The inverted output Qbar of the first flip-flop FF1 can be connected to the D input of the first flip-flop FF1. The non-inverted output Q can be connected to the comparator clock delay element 524, having a predetermined delay time Δφ. comp_start The output of comparator clock delay element 524 can be connected to the D input of the second flip-flop FF2. The output of comparator clock delay element 524 can also be connected to the input of comparator clock generation module 522, which can be an exclusive-or (EXOR) function. The non-inverting output Q of the second flip-flop FF2 can be connected to the second input of comparator clock generation module 522. The output of comparator clock generation module 522 is connected to a function providing φ. comp The clock generator outputs 508.

[0099] Comparator clock output 508 (φ) compThe first input of the NOR gate 544 can be connected to comparator 540 and to the NOR gate 530. The second inverting input of the NOR gate 544 can be connected to the fast start enable input 544. The NOR gate output 536 can be connected to the clock input of the third flip-flop FF3, which can be referred to as the switch-controlled flip-flop. The data input of the third flip-flop FF3 can be connected to the inverting output Qbar of the third flip-flop FF3 to configure the third flip-flop as an inverting flip-flop. The non-inverting output Q of the third flip-flop FF3 can be connected to a circuit that can be represented as Δφ. pulse A second delay element 532 with a predetermined delay time. The non-inverting output Q of the third flip-flop FF3 can be connected to the first input 538 of the switch control generation module 534. The output of the second delay element 532 can be connected to the second input 539 of the switch control generation module 534. The switch control generation module 534 can have a first control input 552 for selecting the sense resistance value (Rsense_sel). The switch control generation module 534 can have a second control input connected to the fast start enable input 544. The switch control generation module 534 can have a third control input connected to the steady-state enable input 548.

[0100] The switch control generator outputs 512_1 to 512_6, which output the corresponding control output 512_1 (φ). p ), 512_2(φ psub1 ), 512_3(φ psub2 ), 512_4(φ n ), 512_5(φ nsub1 ), 512_6(φ nsub2 ).

[0101] The switch control generator output 512_1 can be connected to the first sensing switch SR. P And the fourth switch S4. The switch control generator output 512_2 can be connected to the first switch S1. The switch control generator output 512_2 can be connected to the first comparator switch SX. P The switch control generator output 512_4 can be connected to the second sensing switch SR. N And the third switch S3. The switch control generator output 512_5 can be connected to the second switch S2. The switch control generator output 512_6 can be connected to the second comparator switch SX. N .

[0102] The control outputs 512_1 and 512_4 can be a single wire or multiple wires. Multiple connections are possible depending on the required sensing resistance value R. sense And select the first sensing switch SR P Second sensing switch SRN Different combinations of switches in the process.

[0103] Depending on the reference voltage used with the control lines 516_1 to 516_6 from the switch control generator 530 connected to the respective gates of each MOS transistor, the switches can typically be implemented as NMOS or PMOS transistors. For the circuit 500 shown, the first switch S1, the second switch S2, and the first sensing switch SR... P Second sensing switch SR N This can be implemented using one or more PMOS transistors. The third switch S3 and the fourth switch S4 can be implemented as NMOS transistors. The first comparator switch SX... P Second comparator switch SX N It can be implemented as a PMOS transistor because vdda is the reference used.

[0104] Switches S1 and S2 connected to vdda node 502 are controlled by signal φ psub1 and φ nsub1 Control. Switches S3 and S4 connected to ground 504 are controlled by signal φ. p and φ n Control. These switches are low-ohm to ensure that Δφ pulse Internally stable. A low-ohmic resistance can correspond to a switching resistor R with a resistance satisfying the following relationship. sw :

[0105]

[0106] The switch should have sufficiently low resistance to ensure that Δφ pulse Internally stable, where the final error is approximately smaller than R. sense The detectable motional voltage oscillation. R typically depends on the application. sw It should be less than several hundred ohms.

[0107] By measuring R sense The voltage on the device is used to measure the motional current I. m R sense It can be the switching resistor itself, or a separate resistor connected in series with the switch. In Δφ pulse Then, the corresponding closed switch S1 or S2 of vdda 502 is opened to start sensing the corresponding sensor switch SR. N SR P resistance R sense The voltage on the switch R. SW The resistance is low, so the settling time can be shortened.

[0108] R sense The maximum allowable value depends on X respectively.P and X N The maximum allowable Δφ i-v and capacitor C osc R sense The voltage across is equal to:

[0109]

[0110] Therefore, for R sense =|Xc|=1 / ωC osc (Δφ i-v =45°), to achieve V Rsense Maximum value:

[0111]

[0112] R sense The value is selectable to obtain The value of Δφ i-v The optimal balance between them. For example, R can be reduced during startup depending on the increase in the induced current Im(t). sense To reduce phase shift Δφ i-v And further shorten the startup time.

[0113] Comparator 540 can sense voltage The state changes when the value flips within a specific time after crossing zero. However, amplitude This could be much smaller than 1mV (e.g., 200μV). Comparator 540 should also change state within a certain time frame to ensure the increase of the induced current Im:

[0114]

[0115] Therefore, the comparator offset should be much smaller than The minimum amplitude is therefore much smaller than 200 μV (e.g., <20 μV). The gain-bandwidth product should be large enough to amplify small signals without much delay. The reference voltage at the inverting input in_n of comparator 540 can be vdda (Vin_n = vdda). To further improve performance, the reference voltage at the inverting input in_n of the comparator can be reduced by a "leakage delay and compensation circuit" 570, which can compensate for voltage drops that may occur at the non-inverting input 506 (in_p) due to switching of devices including the crystal oscillator circuitry caused by the ESD clamp and leakage from the pads. The leakage delay and compensation circuit 570 can also compensate for the delay (Δφ) between the zero-crossing of the dynamic current and the switching moment. comp_delay_max +Δφ i-vThe voltage drop due to leakage on in_p can be compensated by replicating the switch and pads. In other examples, the voltage drop on the non-inverting input 506 (in_p) of comparator 540 can be measured and added to the voltage at the inverting input in_n of comparator 540. The delay Δφ can be compensated by subtracting the voltage value. i-v and Δφ comp_delay :

[0116]

[0117] Therefore, through leakage and delay compensation, the voltage V in_n equal

[0118] V in_n =vdda-ΔV leakage -ΔV compensation

[0119] In Δφ pulse Then, depending on which of the two switches S1 or S2 has just been opened, the signal at Xp or Xn is approximately equal to vdda, and can be expressed through φ. psub2 / φ nsub2 Switch to the non-inverting input of the comparator (in_p). The comparison should be performed when the signal level drops below vdda-ΔV. compensation Then begin. In the absence of delay compensation and negligible offset in the comparator, the comparison should begin between the following:

[0120] Δφ pulse <Δφ comp_start <180°

[0121] Δφ pulse The actual value is approximately 45°, which is not important, as long as Rsw is chosen to be low enough. Furthermore, Δφ comp_start It is not important and can be easily achieved within the range of process, voltage, and temperature.

[0122] In some cases, sensing can be performed at the ground side 504 instead of VDDA. In other cases, sensing can also be performed on the capacitor bank; however, this requires an integrated capacitor bank or two additional pins.

[0123] In the operation of the start-up circuit 500, when the control signal φ n When inactive, the control signal φ p It is active, and vice versa.

[0124] Reference circuit 500 and Figure 6 Describe the operation. Figure 6Example waveform 600 is shown during the operation and transition of the startup circuit 500.

[0125] At startup, a fast start enable signal (fs_enable) is asserted, and a single initial pulse, the "start pulse," can be generated by a single trigger circuit 542 and received at the start pulse input 518. This start pulse (fs_en_pulse) is output as the first clock pulse (clk) on the OR gate OR1. Subsequent clock pulses on the OR gate output 526 are generated by comparator 540. The comparator clock output φ generated by comparator clock generator 520... comp The predetermined delay time Δφ after the first clock pulse comp_start It has an initial transition from low to high. Whenever comparator 540 detects a zero crossing of the induced current Im, a high-to-low transition of the comparator clock output is triggered from the output of comparator 540. In this example, the low-to-high transition of the comparator clock output occurs during a delay time Δφ determined by delay element 524. comp_start Then, the comparator clock signal φ comp The comparator is controlled to be active when it is comparing the signals at its input, and also to be inactive during which, in some examples, the comparator may perform actions based on the waveform φ. cal Indicated calibration.

[0126] The switch control generator 330 receives the comparator clock signal φ comp When fast start is enabled, the switch control generator 330 receives the comparator clock signal φ comp Generate the switching clock signal sw_clk. The third flip-flop FF3 acts as a divide-by-two circuit to generate a frequency of φ. comp Half of the signal. The second delay element 532 can delay the output of the third toggle switch clock signal and provide a delay Δφ. pulse The delay switch control signal.

[0127] Similar to the starting circuit 300, when the control signal φv is inactive, the control signal φ is inactive, and vice versa.

[0128] When the control signal φ n When inactive, the control signal φ p It is in an active state, and vice versa. Control signal φ psub1 In the control signal φ p The signal that is active during the first sub-phase 602 of the active phase. Control signal φ psub2 In the control signal φ p The signal is active during the second sub-phase 604 of the active phase. Similarly, signal φnsub1 φ nsub2 In the control signal φ n It is in an active state during the first sub-phase 606 and the second sub-phase 608 of the active phase.

[0129] The first sub-stages 602 and 606 can be represented as Δφ pulse The duration of the waveform Xp and X. N The voltage changes at common nodes 514 and 516 are shown. The signal "in_p" represents the signal at the non-inverting input 506 of comparator 540, and signal I... m The dynamic current is shown.

[0130] The switching operation during the active phase of the switch control signal when fast start is enabled (fs_enable=HIGH) is the same as described in Table 1. Oscillator capacitor C1 osc and C2 osc The connection is preferably disconnected during the startup phase (capbank_sel = LOW). Unless otherwise specified, the switch is open.

[0131] In φ p During each comparison cycle in the active state, in the first sub-phase 602, when φ psub1 When also in an active state, switches S1 and SR p It connects between the first common node 514 and the power rail 502. Compared to SRp, switch S1 can have a much lower on-resistance, which reduces the voltage settling time at node 514. Specifically, if a PMOS transistor is used to implement switch S1, this ensures that node 514 is always pulled up to vdda. In the second sub-stage 604, when φ psub2 When active, node 514 activates via switch SX. P Coupled to comparator 540. After the start of the second sub-stage 604, via φ comp Enabling comparator 540 can be achieved by selecting Δφ. comp_start >Δφ pulse To ensure.

[0132] Comparator 540 can detect the zero-crossing of the voltage, which will correspond to a phase delay Δφ. i-v The current then crosses zero. An additional delay Δφ is applied via the comparator. comp_delay Then, the polarity of the voltage applied to the crystal 510 is reversed, i.e., φ p It becomes inactive, while φ n It becomes active. Then, the period is compared at φ. n It repeats in a similar manner when it is active.

[0133] The startup circuit 500 provides a more robust self-timing startup for the crystal oscillator. Because the comparator has a defined comparison enable time in each cycle, it can perform offset compensation when not comparing to improve detection sensitivity. Furthermore, since the startup circuit has a defined first sub-stage, optimal transistors can be used to implement the additional switches S1 and S2 of the H-bridge circuit to minimize the settling time.

[0134] Once the startup phase is complete, the fast-start circuitry can be disabled (fs_enable = LOW) and the steady-state circuitry enabled (ss_enable = HIGH). Then, the H-bridge switches can be open, and comparator 540 is de-energized. The gm stage 580 will then keep the crystal resonator 510 oscillating.

[0135] In some examples, the input is selected from capbank_sel and R. sense The fixed capacitor bank value can be varied during startup to improve performance (e.g., reducing Δφ). i-v To achieve faster startup. In some examples, this can be done by counting the number of clock pulses generated from the comparator output and comparing them with one or more predetermined values, or by using an "amplitude detector" (not shown) that measures R. sense The voltage drop across the input is measured and the result is compared with one or more predetermined values. Similarly, the determination of the transition from startup mode to steady-state mode can also depend on the counter value from a counter coupled to the comparator output (not shown) or on the voltage drop measured using an amplitude detector.

[0136] Figure 7A A possible implementation of a comparator 700 with offset cancellation is shown, which can be used to implement comparator 340 or comparator 540. Waveforms are shown below. Figure 7B As shown. Comparator 540 not only has offset cancellation but also the very high gain-bandwidth product required to measure the zero-crossing of a very small signal and toggle it shortly after the zero-crossing. Comparator 700 has a series arrangement of two operational transconductance amplifiers (OTAs) 710, 710' with offset cancellation and a final comparator stage 720, which can generate sufficiently high gain while keeping the delay between sensing the zero-crossing and the toggling output sufficiently low. During the comparison period, the comparison clock φ... COMP Control switch S1 COMP and S2 COMP The inputs in_n and in_p are coupled to the corresponding inputs of OTA1 710 via capacitors C1 and C2. The output of OTA1 is coupled to the input of OTA2 via the corresponding capacitors C3 and C4.

[0137] From the calibration clock signal φ CAL Controlled calibration switch S1 CAL and S2 CAL A series connection is made between the inverting input in_n and the non-inverting input in_p of comparator 700. The inverting input in_n of comparator 700 is connected to the calibration clock signal φ. CAL Control switch S1 CAL With S2 CAL The common node between them is 702.

[0138] During the calibration cycle, the inverting input in_n is coupled to both inputs of the OTA1710 via capacitors C1 and C2. Additionally, the inputs of the OTA1710 use the calibration clock signal φ. CAL Control switch S3 CAL and S4 CAL Connect to the output. Similarly, the input of the OTA2 710' uses a calibration clock signal φ. CAL Control switch S5 CAL and S6 CAL Connect to the output.

[0139] The output common-mode voltage, including the reverse offset voltage, is then stored in capacitors C1 and C2. Because the reverse offset voltage is stored in capacitors C1 and C2 before comparator 700 changes to comparison mode, this reverse offset voltage compensates for the comparator's offset. This offset compensation improves the sensitivity of comparator 700, thus allowing comparator 700 to compare smaller voltages.

[0140] The final comparator 720 is a simple single-ended OTA followed by an inverter 722. The inverter 722 can have a shifted-off level (vtrip) to ensure that the output (out) does not flip due to the offset at the final comparator input and the offset of the inverter 722. Because of the large amplification of OTA1 710 and OTA2 710', no offset calibration is required for the final stage. In some examples, offset calibration may also be performed on the final stage 720.

[0141] Because there is a trade-off between gain and speed, gain can be reduced, for example, by removing a gain stage (OTA2), which will decrease sensitivity but increase response time. Sensitivity can also be increased by increasing the gain, which may shorten the response time.

[0142] Figure 7C An example implementation of a single-ended OTA720 for use as the final comparator in a novel and robust offset elimination comparator scheme is shown.

[0143] Figure 7DAn example transistor-level implementation of a fully differential OTA710 with a self-biased common-mode output including a cascode and a common-source design is shown. Transistor MN51 is the current source for the differential input pairs MN12, MN42, and the bias branch therebetween. If the differential voltage between in_n and in_p is zero, then the differential voltage between out_p and out_n is zero, where the common-mode voltage is equal to the rail voltage 701. During calibration, in_n is connected to out_p, and in_p is connected to out_n. Since the inputs are capacitively coupled, both the common-mode output and the inputs are equal to the rail voltage 701. NMOS devices MN11, MN21, MN31, and MN41 are connected to rail vbias_casn, and PMOS devices MP12, MP22, MP32, and MP42 are cascode and common-source designs used to increase the gain of the OTA.

[0144] Figure 8 An example embodiment of a leakage and delay compensation circuit 800 is shown, which can be used, for example, to implement a leakage and delay compensation circuit 570. The leakage and delay compensation circuit 800 includes an H-bridge virtual switch 802, a pulse virtual switch 806, an ESD protection virtual device 808, and a comparator virtual switch 804. A reference 810 is provided to an inverting comparator input that compensates for leakage and delay at a non-inverting comparator input.

[0145] Figure 9 An example logic circuit 900 for implementing a portion of the switch control module 534 is shown. Input 538 corresponds to the switch control signal output of the third flip-flop FF3, and input 539 corresponds to the delayed switch control signal output from the second delay element 532.

[0146] Figure 10 A method for self-timing startup of a crystal oscillator 1000 is illustrated. In step 1002, a plurality of switching control signals may be generated in response to the detection of a zero-crossing event of a motional current in the crystal resonator. In step 1004, the switching control signals may control a plurality of switches in the H-bridge circuit to apply a voltage source to the crystal resonator terminals with a first polarity during a first switching control phase and with an opposite second polarity during a second switching control phase. In step 1006, the switches may be controlled to selectively decrease the resistance between a power supply node and a corresponding crystal resonator terminal coupled to the power supply node during a corresponding first sub-phase of the corresponding switching control phase. In step 1008, the resistance between the power supply node and the corresponding crystal resonator terminal is selectively increased during a corresponding second sub-phase of the corresponding switching control phase. In step 1010, each zero-crossing is detected during each corresponding second sub-phase of the corresponding switching control phase.

[0147] A circuit and method for starting a crystal oscillator are described. The crystal resonator is configured to be coupled to a startup circuit, the startup circuit including an H-bridge circuit with a plurality of switches. A plurality of switch control signals are generated in response to detecting a zero-crossing event of a motional current in the crystal resonator. The switches of the H-bridge circuit are controlled by the switch control signals to apply a voltage to the terminals of the crystal resonator with a first polarity during a first switch control phase and with an opposite second polarity during a second switch control phase. During a corresponding first sub-phase of the corresponding switch control phase, the plurality of switches are configured in a first configuration to couple a power node to a corresponding crystal resonator terminal. During a corresponding second sub-phase of the corresponding switch control phase, the plurality of switches are configured in a second configuration to couple the power node to the corresponding crystal resonator terminal. In the second configuration, the resistance between the power node and the corresponding crystal resonator terminal is greater than the resistance in the first configuration. A zero-crossing is detected during each corresponding second sub-phase.

[0148] The embodiments described herein depict robust fast-start crystal oscillator (XO) schemes that reduce startup time and energy consumption. These embodiments do not require an external clock and provide a robust solution. They can reduce total startup time and average power consumption in systems typically such as Bluetooth Low Energy (BLE), car key applications, and IoT systems.

[0149] Although the appended claims are directed to specific combinations of features, it should be understood that the scope of the disclosure of this invention also includes any novel feature or combination of novel features or any generalized form thereof explicitly or implicitly disclosed herein, regardless of whether it relates to the same invention as claimed in any of the present claims, or whether it alleviates any or all of the same technical problems as this invention.

[0150] Features described in the context of a single embodiment may also be provided in combination in a single embodiment. Conversely, for the sake of brevity, the various features described in the context of a single embodiment may also be provided individually or in any suitable sub-combination.

[0151] The applicant hereby reminds that new claims may be formulated based on such features and / or combinations of such features during the examination of this application or any other application derived therefrom.

[0152] For the sake of completeness, it is also stipulated that the term "comprising" does not exclude other elements or steps, the term "a" does not exclude multiple, a single processor or other unit may perform the functions of several components recited in the claims, and the reference numerals in the claims should not be interpreted as limiting the scope of the claims.

Claims

1. A crystal oscillator startup circuit, characterized in that, include: An H-bridge circuit, comprising multiple switches, is configured to be coupled to a crystal resonator; A comparator having a first comparator input configured to be switchably coupled to an end of the crystal resonator, a second comparator input configured to be coupled to a power supply node, a comparator clock input, and a comparator output configured to transition between a first state and a second state in response to a zero-crossing event of a motional current in the crystal resonator; A comparator clock generator having a first comparator clock generator input coupled to the comparator output, a second comparator clock generator input configured to receive a start signal, and a comparator clock generator output coupled to the comparator clock input; A switch control generator, coupled to a comparator clock output and configured to generate a plurality of switch control signals synchronized with the comparator clock to control the plurality of switches, the plurality of switches being configurable to apply a voltage to the crystal resonator terminals with a first polarity during a first switch control phase and with an opposite second polarity during a second switch control phase, wherein... During the corresponding first sub-phase of the corresponding switch control phase, the plurality of switches are configured in a first configuration to couple the power node to the corresponding crystal resonator terminal; and During the corresponding second sub-phase, the plurality of switches are configured in a second configuration to couple the power node to the corresponding crystal resonator terminal; In the second configuration, the resistance between the power node and the corresponding crystal resonator terminal is greater than the resistance in the first configuration; and The switch control generator is further configured to couple the first comparator input to the corresponding crystal resonator terminal during each of the respective second sub-stages.

2. The crystal oscillator startup circuit according to claim 1, characterized in that, The comparator is configured to calibrate the comparator offset voltage during a first phase of the comparator clock cycle and to compare the input during a second phase of the comparator clock cycle.

3. The crystal oscillator startup circuit according to claim 2, characterized in that, The comparator includes: A differential amplifier stage, comprising: Operational transconductance amplifier (OTA); A first capacitor, which is coupled to a first OTA input; A second capacitor, coupled to a second OTA input, wherein the comparator is configured to receive a comparator clock defining a calibration phase and a comparison phase, wherein during the calibration phase, the comparator is configured to control a plurality of comparator switches to perform the following operations: The first comparator input can be switchably coupled to the first OTA input via the first capacitor; and the second comparator input can be switchably coupled to the second OTA input via the second capacitor; and During the comparison phase, the comparator is configured to control the plurality of comparator switches to perform the following operations: Switchably couple the first comparator input to the first OTA input via the first capacitor and to the second OTA input via the second capacitor; and The first OTA output can be switched to the first OTA input and the second OTA output can be switched to the second OTA input.

4. The crystal oscillator startup circuit according to claim 3, characterized in that, The comparator further includes a single-ended output stage OTA coupled to the output of the differential amplifier stage, and has a first input coupled to a first OTA output of the differential amplifier stage, a second input coupled to a second OTA output, and an output coupled to a buffer, wherein the buffer is configured to have a shifted voltage disconnect level.

5. The crystal oscillator startup circuit according to any one of the preceding claims, characterized in that, The plurality of switches further includes: The first switch and the third switch are connected in series between the power node and the second power node; The second and fourth switches are connected in series between the power node and the second power node. A first sensing switch is arranged in parallel with the first switch; The second sensing switch is arranged in parallel with the second switch; The first common node of the first switch and the third switch is configured to be coupled to the first crystal resonator terminal, and the second common node of the second switch and the fourth switch is configured to be coupled to the second crystal resonator terminal.

6. The crystal oscillator startup circuit according to claim 5, characterized in that, During the first switching control phase, the switching control generator is further configured to: Close the first sensing switch and the fourth switch, and close the first switch during the first sub-phase of the first switch control phase; and open the first switch during the second sub-phase of the first switch control phase; and During the second switching control phase, the switching control generator is configured to: Close the second sensing switch and the third switch, and close the second switch during the first sub-phase of the second switch control phase; and open the second switch during the second sub-phase of the second switch control phase.

7. The crystal oscillator startup circuit according to claim 5, characterized in that, In addition, including: A first comparator switch is coupled between the first crystal resonator terminal and the first comparator input; as well as A second comparator switch is coupled between the second crystal resonator terminal and the first comparator input; The switch control generator is further configured to: The first comparison switch is closed during the second sub-phase of the first switch control phase; as well as The second comparison switch is closed during the second sub-stage of the second switch control phase.

8. The crystal oscillator startup circuit according to claim 1, characterized in that, After at least two comparator clock cycles: During the respective first sub-phase of the respective switch control phase, the plurality of switches are configured in a third configuration to couple the power node to the respective crystal resonator terminal; and During the corresponding second sub-phase, the plurality of switches are configured in a fourth configuration to couple the power node to the corresponding crystal resonator terminal; In the fourth configuration, the resistance between the power node and the corresponding crystal resonator terminal is greater than the resistance in the third configuration and less than the resistance in the second configuration.

9. The crystal oscillator startup circuit according to claim 1, characterized in that, The comparator clock generator further includes a series arrangement of a first flip-flop, a delay element, and a second flip-flop, and an OR gate having a first input coupled to the input of the first comparator clock generator, a second input coupled to the input of the second comparator clock generator, and an output coupled to the clock inputs of the first and second flip-flops, wherein the first flip-flop is configured as an inverting flip-flop, and wherein the comparator clock output is the XOR of the delayed output of the first flip-flop and the output of the second flip-flop.

10. A method for starting a crystal resonator, characterized in that, The crystal resonator is configured to be coupled to a startup circuit including an H-bridge circuit comprising a plurality of switches, and the method includes: Multiple switching control signals are generated in response to the detection of a zero-crossing event of the motional current in the crystal resonator: The switch control signal is used to control multiple switches of the H-bridge circuit to apply voltage to the terminals of the crystal resonator with a first polarity during a first switch control phase and with an opposite second polarity during a second switch control phase. During the corresponding first sub-phase of the corresponding switch control phase, the plurality of switches are configured with a first configuration to couple power nodes to the corresponding crystal resonator terminals; and During the corresponding second sub-phase of the corresponding switch control phase, the plurality of switches are configured in a second configuration to couple the power node to the corresponding crystal resonator terminal; In the second configuration, the resistance between the power node and the corresponding crystal resonator terminal is greater than the resistance in the first configuration; and the method further includes detecting each zero crossing during each corresponding second sub-stage.

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