Excess light amount detection circuit, light receiving element, and electronic device

Abstract

An over-light-amount detection circuit (1) according to the present disclosure includes a MOS transistor and a high-impedance element (Ca). A source of the MOS transistor (Mn1) is connected to a vertical signal line (VSL) of an image sensor. The high-impedance element (Ca) is connected to a drain of the MOS transistor (Mn1). The over-light-amount detection circuit (1) detects a potential fluctuation of the vertical signal line (VSL) based on a potential defined by a gate potential of the MOS transistor (Mn1), and outputs a potential at a junction between the drain of the MOS transistor (Mn1) and the high-impedance element (Ca) as a signal representing an over-light-amount detection result.

Description

Technical Field

[0001] This disclosure relates to light intensity detection circuits, light receiving elements, and electronic devices. Background Technology

[0002] When extremely bright light (such as sunlight) shines on an image sensor, the sensor may mistakenly identify pixels that are actually white as black, resulting in an abnormal output known as sunspots in the captured image.

[0003] To this end, there exists an image sensor that includes a comparison circuit that compares the potential of a vertical signal line used to read out the photoelectric converted signal charge from each camera pixel with a predetermined threshold to detect light reception of excess light (e.g., Patent Document 1).

[0004] Reference List

[0005] Patent documents

[0006] Patent Document 1: JP 2008-283557 A Summary of the Invention

[0007] Technical issues

[0008] However, in image sensors that detect excess light through comparison circuits, comparison circuits are required for each column of the matrix-arranged camera pixels. Furthermore, comparison accuracy is needed to detect anomalies. This necessitates a large-scale comparison circuit, resulting in an increased circuit size.

[0009] In this regard, this disclosure proposes an overlight detection circuit, light receiving element, and electronic device that can detect the overlight amount of an image sensor with high precision without increasing the circuit size.

[0010] Technical solutions to the problem

[0011] The light overload detection circuit according to this disclosure includes a MOS transistor and a high-impedance element. The source of the MOS transistor is connected to a vertical signal line of an image sensor. The high-impedance element is connected to the drain of the MOS transistor. The light overload detection circuit detects potential fluctuations in the vertical signal line based on a potential defined by the gate potential of the MOS transistor, and outputs the potential of the junction between the drain of the MOS transistor and the high-impedance element as a signal representing the light overload detection result. Attached Figure Description

[0012] Figure 1 This is an illustrative diagram showing an example of the construction of an image sensor according to the present disclosure.

[0013] Figure 2 This is an explanatory diagram showing an example of the circuit construction of a camera unit according to the present disclosure.

[0014] Figure 3 This is a diagram illustrating the operation of the AD conversion circuit according to this disclosure.

[0015] Figure 4 This is an illustrative diagram showing an example of the circuit construction of a comparator according to this disclosure.

[0016] Figure 5 This is a diagram illustrating the state of a pixel unit according to the present disclosure when it receives an excessive amount of light.

[0017] Figure 6 This is a diagram illustrating VSL waveforms related to the subject matter of this disclosure.

[0018] Figure 7 This is a diagram illustrating an example of a sunspot countermeasure circuit according to a comparative example of this disclosure.

[0019] Figure 8 This is an explanatory diagram showing the operating timing and output waveform of a sunspot countermeasure circuit according to a comparative example of this disclosure.

[0020] Figure 9 This is an explanatory diagram showing the changes in current and VSL waveforms when the clamp circuit is operating, according to a comparative example of this disclosure.

[0021] Figure 10 This is a diagram illustrating another example of a sunspot countermeasure circuit according to a comparative example of this disclosure.

[0022] Figure 11 This is a diagram illustrating an example of a light transmission detection circuit according to the present disclosure.

[0023] Figure 12 This is an illustrative diagram showing the changes in current and VSL waveforms when the light intensity detection circuit according to this disclosure is operated.

[0024] Figure 13 This is a diagram illustrating an example of an overlight detection circuit for detecting overlight from a Hall sensor, according to the present disclosure.

[0025] Figure 14 This is a schematic plan view showing a schematic configuration of a light receiving element suitable for a light intensity detection circuit according to the present disclosure.

[0026] Figure 15 It shows along Figure 14 A schematic diagram of the cross-section structure taken by the B-B' line.

[0027] Figure 16 This is a cross-sectional view showing a pixel structure suitable for the light transmission detection circuit according to the present disclosure.

[0028] Figure 17 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system.

[0029] Figure 18 This is a block diagram illustrating an example of the functional architecture of a camera and a CCU.

[0030] Figure 19 This is a block diagram illustrating a schematic example of the construction of a vehicle control system.

[0031] Figure 20 This is an explanatory diagram showing an example of the placement of the vehicle exterior information detection unit and the camera unit.

[0032] Figure 21 This is a block diagram illustrating an example of the construction of a camera device as an electronic device to which the technology is applicable according to this disclosure. Detailed Implementation

[0033] In the following description, embodiments of the present disclosure will be detailed with reference to the accompanying drawings. Note that in the following embodiments, the same parts will be indicated by the same reference numerals, and therefore repeated descriptions will be omitted.

[0034] [1. The Structure of an Image Sensor]

[0035] First, refer to Figure 1 The structure of the image sensor 100 equipped with the light transmission detection circuit according to this disclosure is described. Figure 1 This is an illustrative diagram showing an example of the construction of an image sensor 100 according to the present disclosure.

[0036] The image sensor 100 is a device that forms an image of a subject on an imaging surface, performs photoelectric conversion on the light through a photoelectric conversion unit, and outputs the signal charge as a video signal. Figure 1 As shown, the image sensor 100 includes an AD conversion circuit 11 and a plurality of pixel units 10 arranged in a matrix.

[0037] Each pixel unit 10 includes an imaging unit 12, an amplifying transistor AMP, and a selection transistor SEL. See below for further details. Figure 2 An example illustrating the circuit structure of pixel unit 10 is provided. Camera unit 12 is an electronic sensor that converts incident light photoelectrically into electrons. Camera unit 12 outputs a video signal having a voltage amplitude corresponding to the signal charge after photoelectric conversion to an amplifying transistor AMP.

[0038] The amplifying transistor AMP amplifies the video signal input from the camera unit 12 and outputs the amplified video signal. One end of the selector transistor SEL is connected to the amplifying transistor AMP, and the other end is connected to the vertical signal line VSL.

[0039] Multiple pixel units 10 with identical construction are connected to the vertical signal line VSL. The image sensor 100 selects one pixel from the multiple pixel units 10 by selecting the selection transistor SEL and transmits the video signal to the AD conversion circuit 11 via the vertical signal line VSL.

[0040] The AD conversion circuit 11 includes comparators 22 for each column. (Refer to...) Figure 3 This section illustrates the construction and operation of the AD conversion circuit 11. After performing correlated double sampling (CDS) and analog-to-digital conversion (ADC), the AD conversion circuit 11 outputs the video signal input via the vertical signal line VSL to the horizontal signal line HSL via switches SW configured for each column.

[0041] [2. Circuit construction and operation of pixel units]

[0042] Next, we will refer to Figure 2 Explain the circuit structure and operation of pixel unit 10. Figure 2 This is an illustrative diagram showing an example of the circuit construction of the pixel unit 10 according to the present disclosure. Figure 2 As shown, pixel unit 10 includes photodiode PD, transmission transistor TG, floating diffuser FD, reset transistor RST, amplification transistor AMP, and selection transistor SEL.

[0043] The photodiode PD includes a grounded anode and a cathode connected to the source of the transfer transistor TG. The drain of the transfer transistor TG is connected to the floating diffuser FD.

[0044] In addition, the floating diffuser FD is connected to the source of the reset transistor RST and the gate of the amplifying transistor AMP. The drain of the amplifying transistor AMP is connected to the power supply. The source of the amplifying transistor AMP is connected to the drain of the select transistor SEL. The source of the select transistor SEL is connected to the vertical signal line VSL.

[0045] When capturing an image, pixel unit 10 first exposes the photodiode PD. The photodiode PD converts the incident light into a signal charge corresponding to the amount of incident light received, and accumulates the signal charge. Then, when the selection transistor SEL is selected, pixel unit 10 turns on the reset transistor RST to clear the charge held in the floating diffuser FD. This operation is called reset.

[0046] Afterward, pixel unit 10 turns off the reset transistor RST. However, due to the effects of charge injection or charge absorption by the reset transistor RST, a certain amount of charge remains in the floating diffuser FD. In the following text, this state will be referred to as the P phase.

[0047] Next, the transfer transistor TG is turned on to transfer the signal charge accumulated in the photodiode PD to the floating diffuser FD. This state will be referred to as phase D below. A voltage corresponding to the signal charge transferred to the floating diffuser FD is applied to the gate of the amplifying transistor AMP.

[0048] The amplifying transistor AMP converts the signal charge into a voltage amplitude corresponding to the amount of charge. In each of the above-mentioned reset mode, P-phase mode, and D-phase mode, a voltage with a voltage amplitude corresponding to the signal charge held in the floating diffuser FD is propagated to the vertical signal line VSL via the selection transistor SEL.

[0049] [3. Operation of the AD conversion circuit]

[0050] Next, we will refer to Figure 3 Explain the construction and operation of the AD conversion circuit 11. Figure 3 This is a diagram illustrating the operation of the AD conversion circuit 11 according to this disclosure. (See diagram for example.) Figure 3 As shown, the AD conversion circuit 11 includes a digital-to-analog converter (DAC) 21, a comparator 22, a counter 23, and a phase-locked loop circuit (PLL) 24.

[0051] DAC 21 generates a ramp wave and inputs it to the positive terminal of comparator 22. A P-phase potential is applied from the amplifying transistor AMP to the negative terminal of comparator 22 via the vertical signal line VSL.

[0052] Starting from phase P, the Ramp wave begins to decrease in voltage. At the point when phase P begins, the Ramp wave is set to have a higher potential than the waveform of phase P potential applied via the vertical signal line VSL (hereinafter referred to as the VSL waveform).

[0053] That is, for a certain period of time starting from phase P, the Ramp wave has a higher potential than the VSL waveform, and the output value VCO of comparator 22 is high. Subsequently, when the potential of the Ramp wave decreases and becomes lower than the potential of the VSL waveform, the output value VCO of comparator 22 changes to low. Comparator 22 outputs the output value VCO to counter 23 connected to comparator 22.

[0054] PLL 24 generates a reference clock and outputs it to counter 23. Counter 23 measures the time from the start of phase P to the occurrence of a logic inversion. Through this operation, AD conversion circuit 11 converts the voltage amplitude of the VSL waveform, which is an analog signal, into time information (count value) as a digital signal. After the P-phase measurement, AD conversion circuit 11 also performs the D-phase measurement in the same manner.

[0055] [4. Construction of a comparator]

[0056] Next, we will refer to Figure 4 Explain the circuit construction and operation of comparator 22. Figure 4 This is an illustrative diagram showing an example of the circuit construction of comparator 22 according to this disclosure.

[0057] like Figure 4 As shown, comparator 22 is a differential amplifier circuit including a first transistor MN1 and a second transistor MN2 constituting a differential input stage, a third transistor MP1 and a fourth transistor MP2 constituting a current mirror circuit, a current source 25, an automatic zero-adjustment switch AZSW, a first capacitor C1, and a second capacitor C2.

[0058] Here, in order to improve the comparison accuracy between the Ramp wave and the VSL waveform, preferably, when the differential amplifier circuit has no offset voltage, that is, when the potential of the Ramp wave and the potential of the VSL wave are equal to each other, the output value VCO of comparator 22 is 0.

[0059] However, in reality, offset voltages can be generated due to the relative differences between the first transistor MN1, the second transistor MN2, the third transistor MP1, and the fourth transistor MP2, or the influence of DC operating points, etc.

[0060] like Figure 1 As shown, comparator 22 is configured for each vertical signal line VSL, that is, for each column. However, differences in the offset voltage of each vertical signal line VSL may cause anomalies such as vertical stripes in the captured image. Therefore, it is necessary to eliminate the offset voltage.

[0061] Therefore, in comparator 22, the automatic zeroing switch AZSW is turned on when the reference voltage is applied to the positive terminal of the input Ramp wave and the P-phase potential is applied to the negative terminal of the input VSL wave.

[0062] By doing so, a voltage that has dropped from the power supply voltage VDD by up to the gate-source voltage Vgs of the third transistor MP1 is applied to one terminal of the first capacitor C1 on the side of the first transistor MN1, and a reference voltage is applied from the positive terminal to the other terminal of the first capacitor C1. The first capacitor C1 then maintains the potential difference between its opposite terminals.

[0063] Furthermore, negative feedback is applied to the gate of the second transistor MN2 in such a way that the drain current of the second transistor MN2 is equal to the drain current of the fourth transistor MP2.

[0064] Due to the aforementioned negative feedback, the gate potential of the second transistor MN2 becomes a potential obtained by superimposing the residual offset voltage, which has not been eliminated by the negative feedback of the differential amplifier circuit, onto the gate potential of the first transistor MN1. This potential is applied to one terminal of the second capacitor C2 on the side of the second transistor MN2, and the P-phase potential is applied to the other terminal of the second capacitor C2. The second capacitor C2 maintains the potential difference between its opposite terminals.

[0065] When the auto-zero switch AZSW is open in this state, the fluctuation of the Ramp wave from the reference potential is applied to the gate of the first transistor MN1 via the first capacitor C1. On the other hand, the offset voltage of the differential amplifier circuit is eliminated by applying the voltage obtained by subtracting the offset voltage from the P-phase potential to the gate of the second transistor MN2 on the vertical signal line VSL side. The above operation of comparator 22 is called auto-zero (AZ) operation.

[0066] Furthermore, after performing AZ at the P-phase potential, comparator 22 performs a comparison of the D-phase potential. That is, in comparator 22, the potential difference between the P-phase and D-phase is applied to the gate of the second transistor MN2 to similarly perform CDS of the P-phase and D-phase potentials. This series of operations, including AZ, AD conversion, and CDS, is the function of a single-slope ADC.

[0067] [5. Topic]

[0068] Next, we will refer to Figure 5 and Figure 6 This explains the phenomenon that is the subject of this disclosure. Figure 5 This is a diagram illustrating the state of the pixel unit 10 according to the present disclosure when it receives an excessive amount of light. Figure 6 This is a diagram illustrating VSL waveforms related to the subject matter of this disclosure.

[0069] Notice, Figure 5 The cross-sectional view in the image shows the vertical structure of pixel unit 10. Furthermore, Figure 5 The potential diagram shows the state of pixel unit 10. Here, in Figure 5 Among the constituent elements shown, and Figure 2 The constituent elements shown are the same as those of the constituent elements shown. Figure 2 The same reference numerals are used in the accompanying drawings, so repeated descriptions will be omitted.

[0070] also, Figure 6 The high-level periods in the timing diagram AZ represent the time periods during AZ. The high-level periods in the timing diagram SEL represent the time periods during which the select transistor SEL is turned on.

[0071] The high-level period in the timing diagram RST represents the period during which the reset transistor RST is turned on. The high-level period in the timing diagram TG represents the period during which the transfer transistor TG is turned on.

[0072] The VSL, shown by the thick solid line, represents the high-brightness VSL waveform under non-overexposure conditions. The VSL, shown by the dashed line, represents the VSL waveform when the photodiode PD is illuminated with ultra-high brightness light and generates a charge exceeding Qs, where Qs is the maximum amount of charge that can accumulate in the photodiode PD. The Ramp, shown by the dotted line, represents the Ramp wave.

[0073] A problem related to this disclosure occurs during the AZ period in the over-light condition. As described above, during the AZ period, a P-phase potential is applied to comparator 22 on the VSL side to eliminate the offset voltage of comparator 22. However, when ultra-high brightness light, such as sunlight, is incident on the photodiode PD, the P-phase potential may change.

[0074] Specifically, such as Figure 5 As shown, in pixel unit 10, light SL is incident on photodiode PD through an opening provided in the metal light-shielding film ML. Here, Figure 5 The Qs shown represents the maximum amount of charge that can accumulate in the photodiode PD. The Qfd represents the maximum amount of charge that can accumulate in the floating diffuser FD.

[0075] Figure 5 The figure below shows the potential of phase P after the RST operation is completed. The floating diffuser FD retains the charge e- generated by charge injection through the reset transistor RST, etc.

[0076] In this state, if the light irradiation on the photodiode PD is strong and the charge e- generated by photoelectric conversion exceeds Qs, the charge e- will cross the potential barrier of the transfer transistor TG and leak into the floating diffuser FD.

[0077] The charge e- exceeding Qfd recombines with holes and disappears after crossing the reset transistor RST and reaching the power supply voltage VDD line. That is, the amount of charge e- held in the floating diffuser FD continues to increase until the charge e- is consumed to Qfd.

[0078] Figure 6 The potential fluctuation of the vertical signal line VSL when this change occurs is shown. When the amount of light irradiated does not exceed Qs, as shown by the thick solid line, the P-phase potential does not fluctuate, which means that AZ is performed normally at this potential.

[0079] Subsequently, when the transmission transistor TG turns on to switch to phase D, the potential of the vertical signal line VSL decreases due to signal charge transfer to the floating diffuser FD. However, this change exceeds... Figure 4 The second capacitor C2 shown is applied to the gate of the second transistor MN2, which means that CDS is being executed normally.

[0080] In contrast, when light intensity exceeding Qs is incident, as shown by the dashed line in the VSL potential image, the charge e- exceeding Qs arrives at the floating diffuser FD immediately after the reset of the floating diffuser FD is completed, and the potential of the vertical signal line VSL drops to the potential determined as Qfd.

[0081] Therefore, even if the transmission transistor TG is turned on and the signal charge is read out, the charge e- above Qfd will not be retained in the floating diffuser FD, and no potential fluctuation will occur on the vertical signal line VSL. That is, although the phase transitions to D, no potential difference will be generated between the P phase and the D phase. However, in comparator 22, AZ is performed at the P phase potential, which has dropped to the potential determined to be Qfd.

[0082] As described above, since there is no potential difference between the P and D phases, the time from the start of the Ramp waveform's decline to its logical inversion with the VSL waveform in the P phase is the same as the time from the start of the Ramp waveform's decline to its logical inversion with the VSL waveform in the D phase. That is, the brightness of the incident light before and after exposure is determined to be the same. As a result, due to sunlight, white pixels are incorrectly identified as black. This phenomenon is called sunspots.

[0083] [6. Sunspot Countermeasure Circuit Based on Comparative Example]

[0084] Next, we will refer to Figure 7 and Figure 8This invention describes a sunspot countermeasure circuit according to a comparative example for suppressing the generation of sunspots. Figure 7 This is a diagram illustrating an example of a sunspot countermeasure circuit according to a comparative example of this disclosure. Figure 8 This is an explanatory diagram showing the operating timing and output waveform of a sunspot countermeasure circuit according to a comparative example of this disclosure.

[0085] Note that in Figure 7 Among the constituent elements shown, and Figure 2 The constituent elements shown are the same as those of the constituent elements shown. Figure 2 The same reference numerals are used in the accompanying drawings, therefore repeated descriptions will be omitted. For example... Figure 7 As shown, the sunspot countermeasure circuit according to the comparative example includes a clamping circuit 101 provided for each pixel unit 10.

[0086] The clamping circuit 101 includes a P-channel metal oxide semiconductor (MOS) transistor (hereinafter referred to as a "PMOS transistor") MP3 and an N-channel MOS transistor (hereinafter referred to as a "NMOS transistor") MN3.

[0087] In PMOS transistor MP3, the source is connected to the power supply, the drain is connected to the drain of NMOS transistor MN3, and a predetermined gate voltage XSUNEN is applied to the gate. In NMOS transistor MN3, the source is connected to the vertical signal line VSL, and a predetermined threshold voltage Vth3 is applied to the gate.

[0088] During the AZ period, the clamping circuit 101 turns on the PMOS transistor MP3 by setting the gate voltage XSUNEN low. When light of excessive intensity is received, charge reaches the floating diffuser FD, and the potential of the vertical signal line VSL decreases.

[0089] Then, while the potential of the vertical signal line VSL has not dropped to the clamping level defined by the predetermined threshold voltage Vth3, the NMOS transistor MN3 is turned off. Subsequently, when the potential of the vertical signal line VSL drops to the potential defined by the predetermined threshold voltage Vth3, the NMOS transistor MN3 is turned on to begin its operation.

[0090] Then, when the potential of the vertical signal line VSL drops to a level where the gate potential of the NMOS transistor MN3 is sufficiently higher than the gate potential of the amplifying transistor AMP, the amplifying transistor AMP is turned off.

[0091] Even if the charge of the floating diffuser FD increases further, the potential of the vertical signal line VSL will not decrease. Through this operation, the clamping circuit 101 clamps the potential of the vertical signal line VSL to a potential defined by a predetermined threshold voltage Vth3.

[0092] After AZ is completed, clamping circuit 101 turns off NMOS transistor MN3 by setting the gate voltage XSUNEN high and turning off PMOS transistor MP3. Therefore, amplifying transistor AMP is turned on as follows: Figure 9 As shown, the voltage is reduced by bringing the potential of the vertical signal line VSL back to the potential corresponding to the amount of charge in the floating diffuser FD.

[0093] The potential fluctuations after AZ cross Figure 4 The second capacitor C2 is shown, and it transmits voltage fluctuations as the gate potential of the second transistor MN2. It is set in such a way that the gate potential of the second transistor MN2 is sufficiently lower than the gate potential of the first transistor MN1, and the logic inversion of the comparator 22 output value VCO does not occur. Figure 7 The predetermined threshold voltage Vth3 is shown.

[0094] When no logic inversion occurs during the P-phase counting period, that is, when the count reaches the upper limit of the count value, Figure 3 The counter 23 shown determines that a pixel has sunspots and converts its video signal to white. In this way, the clamping circuit 101 can suppress the generation of sunspots.

[0095] However, the clamping circuit 101 has the following problems. The first problem is that when the difference between the gate voltage of the amplifying transistor AMP (i.e., the potential of the floating diffusion section FD (hereinafter referred to as "Vfd")) and the threshold voltage Vth3, which is the gate voltage of the NMOS transistor MN3, becomes small, the NMOS transistor MN3 starts to operate.

[0096] Here, we will refer to Figure 9 Explain the current flow when clamping circuit 101 is operating. Figure 7 The current in the circuit shown. Figure 9 This is an explanatory diagram showing the changes in current and VSL waveforms when the clamping circuit 101 is operating, according to a comparative example of this disclosure.

[0097] Figure 9 The above potential difference (Vfd-Vth3) is shown to be related to... Figure 7 The diagram shows the relationship between the current I1 flowing from the amplifying transistor AMP, the current I2 flowing from the NMOS transistor MN3, and the potential fluctuation of the vertical signal line VSL.

[0098] Specifically, in Figure 9In the above figure, the solid lines and dashed lines represent the changes in current I1 and current I2 as a result of the change in potential difference (Vfd-Vth3), respectively. Figure 9 The figure below shows the potential fluctuations of the vertical signal line VSL accompanied by changes in the potential difference (Vfd-Vth3).

[0099] Here, the potential of the vertical signal line VSL is represented by the following equation (1). Furthermore, the gate-source voltage Vgs(AMP) of the amplifying transistor AMP in equation (1) is represented by the following equation (2). Furthermore, Figure 7 The currents I1, I2 and I3 shown satisfy the relationship expressed by the following equation (3).

[0100] [Mathematical Expression 1]

[0101] VSL=Vfd-Vgs(AMP)·····(1)

[0102] [Mathematical Expression 2]

[0103]

[0104] [Mathematical Expression 3]

[0105] I3=I1+I2 ·····(3)

[0106] In the above equation, current I1 is the drain current of the amplifier transistor AMP, W / L is the aspect ratio of the amplifier transistor AMP, μn is the carrier mobility, Cox is the gate capacitance per unit area, and Vth is the threshold voltage of the amplifier transistor AMP.

[0107] Figure 7 The amplifying transistor AMP and the NMOS transistor MN3 shown constitute a differential circuit, and the shunt ratio of the current I3 varies according to the potential difference between the gates. Therefore, when the potential difference between the gates is small, the NMOS transistor MN3 allows the current I2 to flow, and the current I1 decreases accordingly (see equation (3)). Then, as the current I1 decreases, the gate-source voltage Vgs(AMP) also decreases (see equation (2)).

[0108] The amplifying transistor AMP and the NMOS transistor MN4 through which current I3 flows form a source follower configuration. Therefore, when current I1 does not fluctuate, that is, when the gate-source voltage Vgs(AMP) does not fluctuate, the source potential fluctuates according to the fluctuation of the potential Vfd of the floating diffuser FD, and maintains its linearity.

[0109] However, if the current I1 fluctuates, the gate-source voltage Vgs(AMP) also changes according to the amount of its fluctuation, which leads to the intervention of factors other than the fluctuation of the potential Vfd of the floating diffuser FD, thus disrupting the linearity (see equations (1) and (2)).

[0110] Therefore, the potential that can be used as a source follower is only greater than that of a source follower. Figure 9 The potential Vfd of the floating diffuser FD within the high potential range at point A is shown. The potential of the vertical signal line VSL to be clamped is... Figure 9 The potential at point B shown is such that the potential of the vertical signal line VSL further drops to that potential, causing the amplifying transistor AMP to turn off. That is, from... Figure 9 The potential drop of the vertical signal line VSL to be clamped, starting from point A, stops only at point B, and the output D (dynamic) range of the vertical signal line VSL is reduced due to this potential (Problem 1).

[0111] As a countermeasure to problem 1, for example, a comparator circuit equivalent to comparator 22 can be used to detect the voltage drop of the vertical signal line VSL. However, in order to reduce the dead time related to problem 1 ( Figure 9 The range from point A to point B (as shown) requires the same precision as comparator 22, resulting in a large-scale circuit. Furthermore, circuitry for detecting the voltage drop across the vertical signal line VSL must be provided for each column, further increasing the circuit size (Problem 2).

[0112] As passed Figure 7 The method of clamping the potential of the vertical signal line VSL, other than the clamping circuit 101 shown, can be achieved by connecting the gate of the PMOS transistor to the vertical signal line VSL and connecting the source of the PMOS transistor to the power supply, thereby clamping the potential of the vertical signal line VSL to the gate-source voltage Vgs of the PMOS transistor.

[0113] However, in this configuration, the clamping level can only be adjusted by the gate-source voltage Vgs of the PMOS transistor. In this case, the clamping level can only be adjusted by the aspect ratio of the PMOS transistor MP3, making adjustment difficult (Problem 3).

[0114] In addition, although it has already been Figure 7 The example illustrates the case where pixel unit 10 is an electronic sensor, but problems also arise when pixel unit 10 is a Hall sensor. Specifically, Figure 7 The clamping circuit 101 shown is as follows: when the pixel unit 10 is an electronic sensor, a clamping operation is performed when the threshold voltage Vth3 is exceeded due to the decrease of the potential Vfd relative to the floating diffuser FD.

[0115] In contrast, when pixel unit 10 is a Hall sensor, the potential Vfd of the floating diffuser FD increases when the overlight level is reached. Therefore, clamping circuit 101 cannot clamp the potential of vertical signal line VSL through NMOS transistor MN3.

[0116] In addition, for example, such as Figure 10 The detection circuit 102 shown can easily be assumed to replace the NMOS transistor MN3 with a PMOS transistor MP3. However, in this configuration, the amplifying transistor AMP and the PMOS transistor MP3 are short-circuited due to their low impedance, and as... Figure 10 As indicated by the thick arrow, a large current flows between the power supply and ground. Therefore, the clamping circuit 101 according to the comparative example of this disclosure (Problem 4) cannot be used for Hall sensors.

[0117] [7. Light transmission detection circuit according to this disclosure]

[0118] Therefore, the light transmission detection circuit according to this disclosure, made to solve the aforementioned problems 1 to 4, can detect the light transmission of an image sensor with high accuracy without increasing the circuit size or reducing the output D range. Next, reference will be made to... Figure 11 This describes the light transmission detection circuit according to the present disclosure.

[0119] Figure 11 This is a diagram illustrating an example of the light transmission detection circuit 1 according to this disclosure. Note that in Figure 11 Among the constituent elements shown, and Figure 7 The constituent elements shown are the same as those of the constituent elements shown. Figure 7 The same reference numerals are used in the accompanying drawings, so repeated descriptions will be omitted.

[0120] like Figure 11 As shown, the light intensity detection circuit 1 consists of an NMOS transistor Mn1 and a capacitor Ca. When light intensity, represented by sunlight, is received, the light intensity detection circuit 1 detects fluctuations in the P-phase potential. The capacitor Ca can be replaced by a resistor, provided that the resistor is a high-impedance element.

[0121] In NMOS transistor Mn1, the source is connected to the vertical signal line VSL of the image sensor, and the drain is connected to one terminal of capacitor Ca. The other terminal of capacitor Ca is connected to the power supply voltage VDD line. Furthermore, a predetermined threshold voltage Vth1 is applied to the gate of NMOS transistor Mn1 via switch SW1.

[0122] Here, the operation of the over-light detection circuit 1 will be explained. Specifically, the operation will be explained when the floating diffuser FD is reset, the P-phase potential remains in the floating diffuser FD, and the AZ period begins. In this case, in the over-light detection circuit 1, it is assumed that capacitor Ca is pre-discharged by a circuit not shown, and the potential at point P remains at the power supply voltage VDD.

[0123] When excessive light is incident on the photodiode PD of pixel unit 10, and the signal charge formed by the photoelectric conversion exceeds Qs and reaches the floating diffuser FD, the potential of the floating diffuser FD decreases. Therefore, the potential of the vertical signal line VSL also decreases.

[0124] When the potential of the vertical signal line VSL is above the threshold level (hereinafter referred to as the threshold voltage Vth1) defined by the gate potential of the NMOS transistor Mn1, the NMOS transistor Mn1 is in the off state, and therefore the capacitor Ca maintains the supply voltage VDD. Subsequently, when the potential of the vertical signal line VSL is below the threshold voltage Vth1, the NMOS transistor Mn1 turns on to supply current to the capacitor Ca.

[0125] The potential of capacitor Ca decreases linearly in proportion to the time constant Q = CV = IT. However, when it drops to the potential where the potential difference between the drain and source of NMOS transistor Mn1 disappears, NMOS transistor Mn1 enters transistor operation and the current decreases, eventually becoming zero.

[0126] In this way, when pixel unit 10 receives excess light and the potential of vertical signal line VSL drops to a potential defined by threshold voltage Vth1, excess light detection circuit 1 can clamp the potential of vertical signal line VSL to the potential at that moment.

[0127] At this time, when pixel unit 10 receives light of excessive amount, the potential at the connection point P connecting capacitor Ca and NMOS transistor Mn1 changes from high to low.

[0128] Therefore, the over-light detection circuit 1 transmits the potential at connection point P as the over-light detection result from the over-light detection terminal to the subsequent circuit, thereby conveying that the potential of phase P fluctuates due to the over-light, so that the video signal of the relevant pixel is converted to white while ignoring subsequent operations.

[0129] After the AZ period, the over-light detection circuit 1 grounds the gate potential of the NMOS transistor Mn1 via switch SW1 to complete the detection and return to normal operation. In this way, since the NMOS transistor Mn1 is turned off during the period when the P-phase potential or D-phase potential propagates through the vertical signal line VSL, the over-light detection circuit 1 does not affect signal transmission even during normal operation when the P-phase potential does not fluctuate.

[0130] Note that although it has been described herein that the light reception of the light source by the light source detection circuit 1 is connected to the pixel unit 10 to detect the light source of the pixel unit 10, the pixel circuit connected to the light source detection circuit 1 is not limited to the pixel unit 10. When connected to, for example, an image sensor with a memory-retaining global shutter function, the light source detection circuit 1 can detect the light reception of the light source of the image sensor.

[0131] [8. Discussion of the Problem]

[0132] Next, we will refer to Figure 12 and Figure 13 Let's discuss questions 1 through 4 above. Figure 12 This is an illustrative diagram showing the changes in current and VSL waveforms when the light intensity detection circuit 1 according to this disclosure is operated. Figure 13 This is a diagram illustrating an example of an overlight detection circuit 1a for detecting overlight from a Hall sensor, according to the present disclosure.

[0133] Figure 12 The potential difference (Vfd-Vth1) and its relationship are shown. Figure 11 The diagram shows the relationship between the current I1 flowing from the amplifying transistor AMP, the current I2 flowing from the NMOS transistor Mn1, and the potential fluctuation of the vertical signal line VSL.

[0134] Specifically, in Figure 12 In the above figure, the solid lines and dashed lines represent the changes of current I1 and current I2 with the change of potential difference (Vfd-Vth1), respectively. Figure 12 The figure below shows the potential fluctuations of the vertical signal line VSL accompanied by changes in the potential difference (Vfd-Vth1).

[0135] Regarding question 1, as Figure 12 As shown, since the logic inversion is performed using only the instantaneous current at the start of operation of the NMOS transistor Mn1, and then the current is cut off, the linearity during inversion is not degraded. The threshold level can be set to the maximum value of the output D range, and a wide output D range can be ensured.

[0136] Next, regarding question 2, since the light detection circuit 1, which can be composed of NMOS transistor Mn1 and capacitor Ca, has almost no dead zone and its number of circuit elements is similar to... Figure 7 The clamping circuit 101 shown has almost the same number of circuit elements, so the light intensity detection circuit 1 can perform high-precision detection over a wide range. Next, regarding question 3, by setting the gate potential of the NMOS transistor Mn1, the threshold level of the potential used to clamp the vertical signal line VSL can be freely adjusted.

[0137] Next, regarding question 4, when the photoelectric conversion element is a Hall sensor, such as... Figure 13 As shown, the detection element can be a PMOS transistor Mp1. Specifically, when the photoelectric conversion element is a Hall sensor, the light intensity detection circuit 1a consists of a PMOS transistor Mp1 and a capacitor Cb. As long as the resistor is a high-impedance element, the capacitor Cb can be replaced by a resistor.

[0138] In PMOS transistor Mp1, the source is connected to the vertical signal line VSL of the image sensor, and the drain is connected to one terminal of capacitor Cb. The other terminal of capacitor Cb is connected to the source of NMOS transistor MN4. Furthermore, a predetermined threshold voltage Vth1 is applied to the gate of PMOS transistor Mp1 via switch SW1. In this way, when the photoelectric conversion element is a Hall sensor, [the signal is transmitted through the gate of the NMOS transistor Mp1]. Figure 11 Similar to the light transmission detection circuit 1 shown, the light transmission detection circuit 1a can detect the light transmission with high accuracy over a wide output D range.

[0139] Furthermore, the light reception of the light excess detection circuit 1 or 1a is based on the potential change of the vertical signal line VSL itself. Therefore, the light reception of the light excess detection circuit 1 or 1a can output a signal corresponding to the binary value indicating whether light excess has been received as the light reception result to the subsequent circuit.

[0140] Here, the light intensity detection circuit 1 or 1a outputs a signal indicating the light intensity detection result to the counter 23. When a signal indicating the amount of light received is input from the light intensity detection circuit 1 or 1a to the counter 23, the counter 23 stops counting. Therefore, the image sensor 100 can prevent the generation of sunspots by forcing the pixels receiving the detected light intensity to be white.

[0141] Furthermore, the over-light detection circuit 1 or 1a outputs a signal indicating the over-light detection result to the comparator 22 connected to the over-light detection circuit 1 or 1a. When a signal indicating the amount of light received is input from the over-light detection circuit 1 or 1a to the comparator 22, the comparator 22 stops comparing the potential of the vertical signal line VSL with the Ramp wave. Therefore, the image sensor 100 can prevent the generation of sunspots by forcing the pixels receiving the detected over-light to be white.

[0142] Furthermore, when excessive light reception is detected, the excessive light reception circuit 1 or 1a outputs a pseudo-potential signal, instead of the potential of the vertical signal line VSL, to the positive terminal of the comparator 22. The pseudo-potential signal corresponds to the case where the received high-brightness light with a charge e- generated by photoelectric conversion does not exceed Qs. Therefore, the image sensor 100 can prevent the generation of sunspots.

[0143] [9. Application Examples of Light Transmission Detection Circuits]

[0144] Next, we will refer to Figure 14 and Figure 15 This describes the light receiving element suitable for the light transmission detection circuit according to this disclosure. Figure 14 and Figure 15 A schematic configuration of a light receiving element 110 suitable for a light transmission detection circuit 1 or 1a according to the present disclosure is shown. Figure 14 The planar structure of the light receiving element 110 is shown. Figure 15 It shows along Figure 14 The cross-sectional structure taken by the B-B' line.

[0145] For example, the light receiving element 110 is suitable for infrared sensors using compound semiconductor materials such as III-V semiconductors, and the light receiving element 110 has photoelectric conversion functionality for light having wavelengths ranging from the visible region (e.g., above 380 nm and below 780 nm) to the short infrared region (e.g., above 780 nm and below 2400 nm). For example, the light receiving element 110 includes a plurality of light receiving unit regions P1 (pixels P1) arranged in a two-dimensional manner. Figure 15 ).

[0146] The optical receiving element 110 has an element region R1 disposed in its central part and a peripheral region R2 disposed outside the element region R1 to surround the element region R1. Figure 14 The light receiving element 110 includes a conductive film 15B disposed from the element region R1 to the peripheral region R2. The conductive film 15B has an opening in a region facing the central portion of the element region R1.

[0147] The optical receiving element 110 has a stacked structure including an element substrate 30 and a readout circuit board 40, the readout circuit board 40 being an example of a circuit board. Figure 15 One side of the component substrate 30 is the light incident surface (light incident surface S1), and the other side of the component substrate 30 opposite to the light incident surface S1 is the bonding surface (bonding surface S2) that is bonded to the readout circuit board 40.

[0148] The component substrate 30, starting from the position closest to the readout circuit board 40, sequentially includes a wiring layer 10W, a first electrode 31, a semiconductor layer 10S (first semiconductor layer), a second electrode 15, and a passivation film 16. The surface and end face (side face) of the semiconductor layer 10S facing the wiring layer 10W are covered by an insulating film 17. The readout circuit board 40 is a so-called read-out integrated circuit (ROIC), and includes a wiring layer 20W, a multilayer wiring layer 22C, and a semiconductor substrate 35 that are in contact with the bonding surface S2 of the component substrate 30. The semiconductor substrate 35 faces the component substrate 30, with the wiring layer 20W and the multilayer wiring layer 22C sandwiched in between.

[0149] The component substrate 30 has a semiconductor layer 10S disposed in the component region R1. In other words, the region where the semiconductor layer 10S is disposed is the component region R1 of the light receiving element 110. In the component region R1, the area exposed from the conductive film 15B (the area facing the opening of the conductive film 15B) is the light receiving region. In the component region R1, the area covered by the conductive film 15B is the optical black (OPB) region R1B. The OPB region R1B is configured to surround the light receiving region. The OPB region R1B is used to obtain a black level pixel signal. The component substrate 30 includes an embedding layer 18 and an insulating film 17 in the peripheral region R2. In the peripheral region R2, holes H1 and H2 are provided that penetrate the component substrate 30 and reach the readout circuit board 40. In the light receiving element 110, light is incident from the light incident surface S1 of the component substrate 30 through the passivation film 16, the second electrode 15, and the second contact layer 34 onto the semiconductor layer 10S. The signal charge generated by photoelectric conversion in the semiconductor layer 10S moves to the readout circuit board 40, where the readout signal charge is located, via the first electrode 31 and the wiring layer 10W. The structure of each part will be described below.

[0150] A wiring layer 10W is provided throughout the component region R1 and the peripheral region R2, and the wiring layer 10W has a bonding surface S2 for bonding with the readout circuit board 40. In the light receiving element 110, the bonding surface S2 of the component substrate 30 is provided in the component region R1 and the peripheral region R2. For example, the bonding surface S2 of the component region R1 and the bonding surface S2 of the peripheral region R2 form the same plane. As will be described later, in the light receiving element 110, the bonding surface S2 of the peripheral region R2 is formed by providing an embedding layer 18.

[0151] For example, wiring layer 10W has contact electrodes 19E and dummy electrodes 19ED in interlayer insulating films 19A and 19B. For example, interlayer insulating film 19B is disposed on the readout circuit board 40 side, interlayer insulating film 19A is disposed on the first contact layer 32 side, and these interlayer insulating films 19A and 19B are stacked. Interlayer insulating films 19A and 19B are formed of, for example, inorganic insulating materials. Examples of inorganic insulating materials include silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), and hafnium oxide (HfO2), etc. Interlayer insulating films 19A and 19B can be formed of the same inorganic insulating material.

[0152] For example, contact electrodes 19E are disposed in component region R1. Contact electrodes 19E are disposed for each pixel P1 in component region R1 to electrically connect the first electrode 31 and the readout circuit board 40 to each other. Adjacent contact electrodes 19E are electrically separated by the embedding layer 18 and interlayer insulating films 19A and 19B. For example, contact electrodes 19E are formed from copper (Cu) pads and are exposed at the bonding surface S2. For example, dummy electrodes 19ED are disposed in peripheral region R2. This dummy electrode 19ED is connected to the dummy electrode 22ED of wiring layer 20W, described later. By disposing of dummy electrodes 19ED and 22ED, the strength of peripheral region R2 can be improved. Dummy electrodes 19ED and contact electrodes 19E are formed, for example, in the same steps. For example, dummy electrodes 19ED are formed from copper (Cu) pads and are exposed at the bonding surface S2.

[0153] The first electrode 31, disposed between the contact electrode 19E and the semiconductor layer 10S, is an electrode (anode) supplied with a voltage for reading out the signal charge (holes or electrons, referred to as holes below for convenience) generated in the photoelectric conversion layer 33, and the first electrode 31 is disposed for each pixel P1 in the element region R1. The first electrode 31 is disposed embedded in an opening in the insulating film 17 and in contact with the semiconductor layer 10S (more specifically, the diffusion region 32A described later). For example, the first electrode 31 is larger than the opening in the insulating film 17, and a portion of the first electrode 31 is disposed in the embedding layer 18. That is, the upper surface (the surface on the semiconductor layer 10S side) of the first electrode 31 is in contact with the diffusion region 32A, and a portion of the lower surface and side surface of the first electrode 31 is in contact with the embedding layer 18. Adjacent first electrodes 31 are electrically separated from each other by the insulating film 17 and the embedding layer 18.

[0154] The first electrode 31 is formed, for example, of any element selected from titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), germanium (Ge), palladium (Pd), zinc (Zn), nickel (Ni), and aluminum (Al), or an alloy containing at least one of these materials. The first electrode 31 can be a single-layer film of any of these constituent materials, or a laminated film composed of two or more of these constituent materials. For example, the first electrode 31 is formed of a laminated film comprising titanium and tungsten. For example, the thickness of the first electrode 31 is from tens of nm to hundreds of nm.

[0155] For example, the semiconductor layer 10S includes a first contact layer 32, a photoelectric conversion layer 33, and a second contact layer 34, starting from the position near the wiring layer 10W. The first contact layer 32, the photoelectric conversion layer 33, and the second contact layer 34 have the same planar shape, and their end faces are located at the same position in the plan view.

[0156] The first contact layer 32 is configured to be shared by all pixels P1, and is disposed between the insulating film 17 and the photoelectric conversion layer 33. The first contact layer 32 is used to electrically isolate adjacent pixels P1 from each other. For example, a plurality of diffusion regions 32A are provided in the first contact layer 32. For the first contact layer 32, dark current can be suppressed by using a compound semiconductor material with a band gap larger than that of the compound semiconductor material constituting the photoelectric conversion layer 33. For example, n-type indium phosphide (InP) can be used for the first contact layer 32.

[0157] The diffusion regions 32A disposed in the first contact layer 32 are arranged to be spaced apart from each other. The diffusion regions 32A are disposed for each pixel P1, and the first electrode 31 is connected to each diffusion region 32A. A diffusion region 32A is also disposed in the OPB region R1B. The diffusion regions 32A are used to read out the signal charge generated in the photoelectric conversion layer 33 for each pixel P1, and the diffusion regions 32A contain, for example, p-type impurities. Examples of p-type impurities include zinc (Zn). In this way, a pn bonding interface is formed between the diffusion regions 32A and the first contact layer 32 outside the diffusion regions 32A, such that adjacent pixels P1 are electrically separated from each other. The diffusion regions 32A are disposed, for example, in the thickness direction of the first contact layer 32, and also in a portion of the photoelectric conversion layer 33 in the thickness direction.

[0158] The photoelectric conversion layer 33 between the first electrode 31 and the second electrode 15, and more specifically, between the first contact layer 32 and the second contact layer 34, is configured to be shared by all pixels P1. The photoelectric conversion layer 33 absorbs light of a predetermined wavelength and generates a signal charge, and is formed, for example, of a compound semiconductor material such as a type I III-V semiconductor. Examples of compound semiconductor materials constituting the photoelectric conversion layer 33 include indium gallium arsenide (InGaAs), indium antimony arsenide (InAsSb), indium arsenide (InAs), indium antimonide (InSb), and mercury cadmium telluride (HgCdTe). The photoelectric conversion layer 33 may be formed of germanium (Ge). In the photoelectric conversion layer 33, photoelectric conversion is performed, for example, on light having wavelengths ranging from the visible region to the short infrared region.

[0159] The second contact layer 34 is configured to be shared by all pixels P1. The second contact layer 34 is disposed between the photoelectric conversion layer 33 and the second electrode 15, and is in contact with both the photoelectric conversion layer 33 and the second electrode 15. The second contact layer 34 is a region through which charges discharged from the second electrode 15 move, and the second contact layer 34 is formed, for example, of a compound semiconductor containing n-type impurities. For example, n-type indium phosphide (InP) can be used for the second contact layer 34.

[0160] The second electrode 15 is disposed on the second contact layer 34 (light incident side) as an electrode shared by each pixel P1, and is in contact with the second contact layer 34. The second electrode 15 is used to discharge the charge (cathode) generated in the photoelectric conversion layer 33 that is not used as a signal charge. For example, when a hole is read out as a signal charge from the first electrode 31, electrons can be discharged through the second electrode 15. The second electrode 15 is formed, for example, of a conductive film that allows incident light, such as infrared light, to pass through. For the second electrode 15, for example, indium tin oxide (ITO) or In2O3-TiO2 (ITiO) can be used. The second electrode 15 can be arranged, for example, in a lattice pattern to separate adjacent pixels P1 from each other. For the second electrode 15, a conductive material with low light transmittance can be used.

[0161] A passivation film 16 covers the second electrode 15 from the light incident surface S1 side. The passivation film 16 may have anti-reflection properties. For example, silicon nitride (SiN), aluminum oxide (Al2O3), silicon oxide (SiO2), or tantalum oxide (Ta2O3) can be used for the passivation film 16. The passivation film 16 has an opening 16H in the OPB region R1B. The opening 16H is configured, for example, in a frame shape surrounding the light receiving region. Figure 14 In a plan view, for example, opening 16H can be a quadrilateral hole or a circular hole. The conductive film 15B is electrically connected to the second electrode 15 through opening 16H of the passivation film 16.

[0162] An insulating film 17 is disposed between the first contact layer 32 and the embedded layer 18, and covers the end faces of the first contact layer 32, the photoelectric conversion layer 33, the second contact layer 34, and the second electrode 15. The insulating film 17 is in contact with the passivation film 16 in the peripheral region R2. The insulating film 17 contains an oxide, such as silicon oxide (SiO2). X The insulating film 17 can be formed as a stacked structure comprising multiple films, such as silicon oxynitride (SiON), silicon oxycarbonate (SiOC), silicon nitride (SiN), or silicon carbide (SiC). For example, the thickness of the insulating film 17 can be from tens of nm to hundreds of nm.

[0163] A conductive film 15B is disposed from the OPB region R1B to the aperture H1 of the peripheral region R2. The conductive film 15B contacts the second electrode 15 not only through the opening 16H of the passivation film 16 disposed in the OPB region R1B, but also through the aperture H1 to the wiring (wiring 22CB, described later) of the readout circuit board 40. In this way, voltage is supplied from the readout circuit board 40 to the second electrode 15 via the conductive film 15B. The conductive film 15B forms the OPB region R1B while acting not only as a path for supplying voltage to the second electrode 15, but also as a light-shielding film. For example, the conductive film 15B is formed of a metallic material including tungsten (W), aluminum (Al), titanium (Ti), molybdenum (Mo), tantalum (Ta), or copper (Cu). A passivation film may be disposed on the conductive film 15B.

[0164] An adhesive layer B may be disposed between the end of the second contact layer 34 and the second electrode 15. As described later, the adhesive layer B is used when forming the light-receiving element 110, and it serves to bond the semiconductor layer 10S to a temporary substrate. For example, the adhesive layer B is formed of tetraethoxysilane (TEOS) or silicon oxide (SiO2). For example, the adhesive layer B is configured to extend beyond the end face of the semiconductor layer 10S and is covered by the embedding layer 18 together with the semiconductor layer 10S. An insulating film 17 is disposed between the adhesive layer B and the embedding layer 18.

[0165] In the light receiving element 110, a photoelectric conversion layer 33 (photodiode PD) is formed in the element substrate 30. Furthermore, the transmission transistor TG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL, as well as the NMOS transistor Mn1, switch SW1, and capacitor Ca included in the light intensity detection circuit 1, or the PMOS transistor Mp1, switch SW1, and capacitor Cb included in the light intensity detection circuit 1a, are all formed in the readout circuit board 40.

[0166] The components disposed in the readout circuit board 40, including the transmission transistor TG, the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL, as well as the NMOS transistor Mn1, the switch SW1, and the capacitor Ca included in the light intensity detection circuit 1, or the PMOS transistor Mp1, the switch SW1, and the capacitor Cb included in the light intensity detection circuit 1a, can be separately formed in multiple substrates or chips, or some of these components can be formed in a substrate on which the photoelectric conversion layer 33 is formed.

[0167] In this way, when applied to the light receiving element 110, the light transmission detection circuit 1 or 1a is provided in the readout circuit board 40. Therefore, the light transmission detection circuit 1 or 1a can detect the light transmission of the image sensor with high accuracy without increasing the circuit size of the light receiving element 110.

[0168] Reference Figure 16 An example of a pixel structure applicable to the light transmission detection circuit according to this disclosure is provided. Figure 16 This is a cross-sectional view showing a pixel structure suitable for the light transmission detection circuit according to the present disclosure.

[0169] On the upper side (i.e., the light incident side) of the semiconductor substrate 60, which serves as an example of a circuit board, a component substrate is provided. In the component substrate, an N-type semiconductor thin film 41, serving as a photoelectric conversion unit, is formed on the entire surface of the pixel array region. For the N-type semiconductor thin film 41, a compound semiconductor with an InGaP, InAlP, InGaAs, InAlAs, or chalcopyrite structure is used. Chalcopyrite-structured compound semiconductors are materials capable of achieving high light absorption coefficients and high sensitivity over a wide wavelength range, and are preferably used as the N-type semiconductor thin film 41 for photoelectric conversion. Such chalcopyrite-structured compound semiconductors are formed using elements surrounding group IV elements such as Cu, Al, Ga, In, S, and Se, and examples include CuGaInS mixed crystals, CuAlGaInS mixed crystals, and CuAlGaInSSe mixed crystals.

[0170] In addition to the aforementioned compound semiconductors, amorphous silicon (Si), germanium (Ge), quantum dot photoelectric conversion films, or organic photoelectric conversion films can also be used as materials for the N-type semiconductor thin film 41. In this embodiment, it is assumed that InGaAs compound semiconductor is used as the N-type semiconductor thin film 41.

[0171] On the underside of the N-type semiconductor thin film 41 (i.e., on the semiconductor substrate 60 side), a high-concentration P-type layer 42 constituting a pixel electrode is formed for each pixel. Then, between the high-concentration P-type layers 42 formed for each pixel, an N-type layer 43, serving as a pixel separation region separating the pixels from each other, is formed of a compound semiconductor such as InP. The N-type layer 43 not only serves as a pixel separation region but also prevents dark current.

[0172] On the other hand, by using a compound semiconductor such as InP, an N-type layer 44, which also serves as a pixel separation region, is formed on the upper side (i.e., the light incident side) of the N-type semiconductor thin film 41, and the concentration of the N-type layer 44 is higher than that of the N-type semiconductor thin film 41. The high-concentration N-type layer 44 acts as a barrier layer to prevent the backflow of charges generated in the N-type semiconductor thin film 41. As a material for the high-concentration N-type layer 44, for example, compound semiconductors such as InGaAs, InP, or InAlAs can be used.

[0173] An antireflective film 45 is formed on a high-concentration N-type layer 44, which serves as a barrier layer. Materials used for the antireflective film 45 may include, for example, silicon nitride (SiN), hafnium oxide (HfO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), or titanium oxide (TiO2).

[0174] The high-concentration N-type layer 44 or anti-reflective film 45 also serves as the upper electrode in the electrodes that hold the N-type semiconductor thin film 41 in the vertical direction, and a predetermined voltage Va is applied to the high-concentration N-type layer 44 or anti-reflective film 45 as the upper electrode.

[0175] A color filter 46 and an on-chip lens 47 are further formed on the anti-reflective film 45. The color filter 46 is a filter that allows red (R), green (G) and blue (B) light (light with wavelengths) to pass through, and is arranged, for example, in a so-called Bayer array in the pixel array region.

[0176] A passivation layer 51 and an insulating layer 52 are formed beneath the high-concentration P-type layer 42 constituting the pixel electrode and the N-type layer 43 serving as the pixel separation region. Then, connecting electrodes 53A and 53B, as well as a bump electrode 54, are formed penetrating the passivation layer 51 and the insulating layer 52. The connecting electrodes 53A and 53B, along with the bump electrode 54, electrically connect the high-concentration P-type layer 42 constituting the pixel electrode to a capacitor element storing charge.

[0177] When applicable Figure 16 In the pixel structure shown, the light intensity detection circuit 1 or 1a is provided on the semiconductor substrate 60, which serves as an example of a circuit board. Therefore, the light intensity detection circuit 1 or 1a can achieve the desired effect without increasing the light intensity. Figure 16 The illustrated pixel structure allows for high-precision detection of the amount of light received by the image sensor.

[0178] [10. Examples of the application of endoscopic surgical systems]

[0179] The technology disclosed herein (the technology) can be applied to a variety of products. As a specific example, the light intensity detection circuit 1 or 1a can be applied to an infrared light receiving element or a camera device or electronic device using the infrared light receiving element, etc.

[0180] The light intensity detection circuit 1 or 1a is not only used for imaging and sensing in ordinary digital cameras and cameras installed in smartphones, but also for imaging and sensing in surveillance cameras, cameras for industrial equipment used in factory inspections, ranging sensors such as Time of Flight (ToF) sensors, and infrared sensors. For example, the technology according to this disclosure can be applied to endoscopic surgical systems.

[0181] Figure 17 This is a diagram illustrating an example of a schematic construction of an endoscopic surgical system to which the technology (the present technology) is applicable.

[0182] exist Figure 17 The image shows an operator (doctor) 11131 performing surgery on a patient 11132 on a bed 11133 using an endoscopic surgical system 11000. As shown, the endoscopic surgical system 11000 includes an endoscope 11100, other surgical instruments 11110 such as a pneumoperitoneum tube 11111 and an energy therapy device 11112, a support arm device 11120 supporting the endoscope 11100, and a trolley 11200 equipped with various devices for endoscopic surgery.

[0183] Endoscope 11100 includes: a tube 11101, which is inserted into a body cavity of patient 11132 at a predetermined distance from its tip; and a camera 11102 connected to the rear end of the tube 11101. In the example shown, endoscope 11100 is configured as a so-called rigid endoscope with a rigid tube 11101. However, endoscope 11100 can also be configured as a so-called flexible endoscope with a flexible tube.

[0184] An opening is provided at the front end of the endoscope tube 11101, and the objective lens is installed in this opening. A light source device 11203 is connected to the endoscope 11100. Light generated by the light source device 11203 is guided to the front end of the endoscope tube via a light guide that extends inside the endoscope tube 11101, and this light is then directed through the objective lens toward the target to be observed in the body cavity of the patient 11132. It should be noted that the endoscope 11100 can be a forward-looking endoscope, a slant-looking endoscope, or a side-looking endoscope.

[0185] An optical system and an image sensor are housed inside the camera 11102. Reflected light from the observed target (observation light) is focused onto the image sensor by the optical system. The observation light is photoelectrically converted by the image sensor, generating an electrical signal corresponding to the observation light, i.e., an image signal corresponding to the observed image. This image signal is transmitted as RAW data to the camera control unit (CCU) 11201.

[0186] The CCU 11201 includes a central processing unit (CPU), a graphics processing unit (GPU), etc., and the CCU 11201 controls the operation of the endoscope 11100 and the display device 11202 as a whole. Furthermore, the CCU 11201 receives image signals from the camera 11102 and performs various image processing operations on the image signals, such as image processing (de-mosaic processing), for displaying images based on the image signals.

[0187] Under the control of CCU 11201, display device 11202 displays an image based on an image signal that has been image processed by CCU 11201.

[0188] For example, the light source device 11203 includes a light source such as a light emitting diode (LED) and supplies illumination light to the endoscope 11100 when imaging the surgical site.

[0189] Input device 11204 is the input interface of endoscopic surgery system 11000. Users can input various information or commands into endoscopic surgery system 11000 through input device 11204. For example, users can input commands to change the imaging conditions of endoscope 11100 (such as the type of illumination light, magnification, or focal length).

[0190] The treatment tool control device 11205 controls the drive of the energy treatment tool 11112 used for tissue ablation, cutting, or vascular closure. The pneumoperitoneum device 11206 feeds gas into the patient's body cavity 11132 via the pneumoperitoneum tube 11111 to inflate the cavity, thereby ensuring the field of vision of the endoscope 11100 and ensuring the operator's working space. The recorder 11207 is a device capable of recording various information related to the surgery. The printer 11208 is a device capable of printing various information related to the surgery in various forms such as text, images, or charts.

[0191] It should be noted that the light source device 11203, which supplies illumination light to the endoscope 11100 during imaging of the surgical site, may include, for example, an LED, a laser light source, or a white light source composed of a combination thereof. When the white light source is composed of a combination of RGB laser light sources, the output intensity and timing of each color (wavelength) can be controlled with high precision, thereby adjusting the white balance of the captured image within the light source device 11203. Furthermore, in this case, by illuminating the observation target with laser beams from each of the RGB laser light sources in a time-division manner, and controlling the driving of the imaging element in the camera 11102 in sync with the illumination timing, images corresponding to each of the RGB light sources can also be captured in a time-division manner. According to this method, color images can be obtained without a color filter in the imaging element.

[0192] Furthermore, the drive of the light source device 11203 can be controlled by changing the intensity of the light to be output at predetermined time intervals. By controlling the drive of the imaging element in the camera 11102 in time-division multiplexing to acquire and synthesize images, high dynamic range images without underexposure or overexposure can be produced.

[0193] Furthermore, the light source device 11203 can be configured to supply light having a predetermined wavelength band corresponding to special light observation. In special light observation, for example, narrow-band imaging (narrow-band imaging) is performed to image a predetermined tissue, such as blood vessels in a mucosal surface portion, with high contrast by irradiating a narrow-band light compared to the irradiation light used in ordinary observation (i.e., white light) using wavelength dependence of light absorption in body tissue. Alternatively, in special light observation, fluorescence observation can be performed to obtain an image based on fluorescence generated by irradiating an excitation light. In fluorescence observation, the observation of fluorescence from a body tissue can be performed by irradiating the tissue with an excitation light (autofluorescence observation), or a fluorescence image can be obtained by locally injecting a reagent such as indocyanine green (ICG) into the body tissue and irradiating the tissue with an excitation light corresponding to the fluorescence wavelength of the reagent. The light source device 11203 can be configured to supply narrow-band light and / or excitation light corresponding to such special light observation.

[0194] Figure 18 It shows Figure 17 A block diagram illustrating an example of the functional configuration of the camera 11102 and CCU 11201.

[0195] Camera 11102 includes a lens unit 11401, an image capture unit 11402, a drive unit 11403, a communication unit 11404, and a camera control unit 11405. CCU 11201 includes a communication unit 11411, an image processing unit 11412, and a control unit 11413. Camera 11102 and CCU 11201 are communicatively connected to each other via a transmission cable 11400.

[0196] Lens unit 11401 is an optical system disposed in the portion connected to lens barrel 11101. Observation light obtained from the front end of lens barrel 11101 is guided to camera 11102 and incident on lens unit 11401. Lens unit 11401 is constructed by combining multiple lenses, including zoom lenses and focusing lenses.

[0197] The camera unit 11402 includes camera elements. The camera unit 11402 may include one camera element (so-called single-plate type) or multiple camera elements (so-called multi-plate type). For example, when the camera unit 11402 is configured as a multi-plate type, image signals corresponding to R, G, and B respectively can be generated by each camera element, and the generated image signals can be combined to obtain a color image. Alternatively, the camera unit 11402 may include a pair of camera elements for acquiring right-eye and left-eye image signals corresponding to three-dimensional (3D) display respectively. Through 3D display, the surgeon 11131 can more accurately determine the depth of living tissue in the surgical site. Note that when the camera unit 11402 is configured as a multi-plate type, multiple lens units 11401 can be provided corresponding to each camera element.

[0198] Furthermore, the camera unit 11402 is not necessarily located within the camera 11102. For example, the camera unit 11402 may be located directly behind the objective lens inside the lens barrel 11101.

[0199] The drive unit 11403 includes an actuator, and under the control of the camera control unit 11405, the drive unit 11403 moves the zoom lens and focusing lens of the lens unit 11401 a predetermined distance along the optical axis. Therefore, the magnification and focus of the image captured by the imaging unit 11402 can be appropriately adjusted.

[0200] The communication unit 11404 includes communication means for transmitting various information to and receiving various information from the CCU 11201. The communication unit 11404 transmits the image signal obtained from the camera unit 11402 as RAW data to the CCU 11201 via the transmission cable 11400.

[0201] Additionally, the communication unit 11404 receives control signals from the CCU 11201 for controlling the camera 11102 and supplies these control signals to the camera control unit 11405. The control signals include information related to shooting conditions, such as information specifying the frame rate of the captured image, information specifying the exposure value during shooting, and / or information specifying the magnification and focus of the captured image.

[0202] Note that imaging conditions such as frame rate, exposure value, magnification, and focus can be appropriately specified by the user, or can be automatically set by the control unit 11413 of CCU 11201 based on the acquired image signal. In the latter case, endoscope 11100 has so-called automatic exposure (AE), automatic focus (AF), and automatic white balance (AWB) functions.

[0203] The camera control unit 11405 controls the driving of the camera 11102 based on the control signals received from the CCU 11201 via the communication unit 11404.

[0204] The communication unit 11411 includes a communication device for transmitting various information to and receiving various information from the camera 11102. The communication unit 11411 receives image signals transmitted from the camera 11102 via the transmission cable 11400.

[0205] In addition, the communication unit 11411 transmits control signals for controlling the camera 11102 to the camera 11102. The image signals and control signals can be transmitted via electrical communication or optical communication, etc.

[0206] The image processing unit 11412 performs various image processing on the image signal transmitted from the camera 11102 as RAW data.

[0207] The control unit 11413 performs various controls related to photographing the surgical site, etc., through the endoscope 11100 and displaying the images obtained by photographing the surgical site, etc. For example, the control unit 11413 generates control signals for controlling the drive of the camera 11102.

[0208] Furthermore, based on the image signal that has already been processed by the image processing unit 11412, the control unit 11413 causes the display device 11202 to display the captured image of the surgical site, etc. At this time, the control unit 11413 can use various image recognition technologies to identify various objects in the captured image. For example, the control unit 11413 can identify surgical tools such as forceps, specific living sites, bleeding, and mist when using the energy therapy tool 11112 by detecting the shape and color of the edges of objects included in the captured image. When the captured image is displayed on the display device 11202, the control unit 11413 can overlay various surgical assistance information onto the image of the surgical site using the recognition results. Since the overlaid surgical assistance information is presented to the surgeon 11131, the burden on the surgeon 11131 can be reduced, and the surgeon 11131 can perform the surgery with peace of mind.

[0209] The transmission cable 11400 that connects the camera 11102 and the CCU 11201 to each other is an electrical signal cable for handling electrical signal communication, an optical fiber for handling optical communication, or a composite cable for handling both electrical and optical communication.

[0210] Here, in the example shown, communication is performed in a wired manner using transmission cable 11400. However, communication between camera 11102 and CCU 11201 can also be performed wirelessly.

[0211] The examples of endoscopic surgical systems to which the technology according to this disclosure is applicable have been described above. The technology according to this disclosure is applicable to, for example, the endoscope 11100, the camera unit 11402 of the camera 11102, or the image processing unit 11412 of the CCU 11201, among the aforementioned components. Specifically, for example, Figure 11 The light intensity detection circuit 1 can be applied to the camera unit 11402. By applying the technology according to this disclosure to the camera unit 11402, the influence of light intensity can be eliminated, thereby obtaining a clearer image of the surgical site, enabling the surgeon to reliably identify the surgical site.

[0212] Note that although an endoscopic surgical system has been used as an example here, the techniques disclosed herein can also be applied to other microsurgical systems, for example.

[0213] [11. Examples of applications of moving objects]

[0214] Furthermore, the technology according to this disclosure (the technology) can be implemented as a device mounted on any type of mobile body, such as a car, electric car, hybrid car, motorcycle, bicycle, personal mobile device, airplane, drone, ship, or robot.

[0215] Figure 19 This is a block diagram illustrating a schematic example of the construction of a vehicle control system, which is an example of a mobile body control system to which the technology according to this disclosure is applicable.

[0216] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 19 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as part of the functional configuration of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0217] The drive system control unit 12010 controls the operation of equipment related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 acts as a control device for the following equipment: a drive force generating device for generating the vehicle's driving force, such as an internal combustion engine or drive motor; a drive force transmission mechanism for transmitting the driving force to the wheels; a steering mechanism for adjusting the vehicle's steering angle; and a braking device for generating the vehicle's braking force.

[0218] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 acts as a control device for devices such as: keyless entry systems; smart key systems; power windows; or various lights such as headlights, taillights, brake lights, turn signals, and fog lights. In this case, radio waves or signals from various switches transmitted from a portable device that replaces the key can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locking devices, power windows, lights, etc.

[0219] The exterior information detection unit 12030 detects information about the exterior of the vehicle on which the vehicle control system 12000 is installed. For example, the exterior information detection unit 12030 is connected to a camera unit 12031. The exterior information detection unit 12030 causes the camera unit 12031 to capture images of the exterior of the vehicle and receives the captured images. Based on the received images, the exterior information detection unit 12030 can perform object detection processing or distance detection processing for people, vehicles, obstacles, signs, or text on the road surface.

[0220] The camera unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The camera unit 12031 can output this electrical signal as an image or as ranging information. Furthermore, the light received by the camera unit 12031 can be visible light or non-visible light such as infrared light.

[0221] The in-vehicle information detection unit 12040 detects information inside the vehicle. For example, the in-vehicle information detection unit 12040 is connected to a driver state detection unit 12041 for detecting the driver's state. For example, the driver state detection unit 12041 includes a camera for capturing images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off.

[0222] Based on information about the exterior or interior of the vehicle acquired by the exterior information detection unit 12030 or the interior information detection unit 12040, the microcomputer 12051 can calculate target control values ​​for the drive force generating device, steering mechanism, or braking device, and can output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform coordinated control for implementing functions of an advanced driver assistance system (ADAS), including collision avoidance or impact mitigation, distance-based following, constant speed driving, collision warning, and lane departure warning.

[0223] Furthermore, the microcomputer 12051 can control the drive force generating device, steering mechanism, or braking device based on information about the vehicle's surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, thereby performing cooperative control for achieving autonomous driving and other functions that do not depend on the driver's operation.

[0224] Furthermore, based on information about the exterior of the vehicle obtained from the exterior information detection unit 12030, the microcomputer 12051 can output control commands to the body system control unit 12020. For example, the microcomputer 12051 can control the headlights according to the position of the preceding or oncoming vehicle detected by the exterior information detection unit 12030, thereby performing cooperative control for anti-glare, such as switching the high beams to the low beams.

[0225] The audio-visual output unit 12052 transmits at least one of the audio and visual signals to an output device capable of visually or audibly notifying vehicle occupants or the outside of the vehicle. Figure 19In the example, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown as output devices. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0226] Figure 20 This is a diagram showing an example of the location where the camera unit 12031 is installed.

[0227] exist Figure 20 In the vehicle 12100, camera units 12101, 12102, 12103, 12104 and 12105 are camera units 12031.

[0228] For example, camera units 12101, 12102, 12103, 12104, and 12105 are installed at the front nose, rearview mirrors, rear bumper, rear door, and upper part of the interior windshield of vehicle 12100. Camera unit 12101 at the front nose and camera unit 12105 at the upper part of the interior windshield primarily acquire images of the front of vehicle 12100. Camera units 12102 and 12103 at the rearview mirrors primarily acquire images of the sides of vehicle 12100. Camera unit 12104 at the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. The front images acquired by camera units 12101 and 12105 are mainly used to detect vehicles, pedestrians, obstacles, traffic lights, traffic signs, and lanes.

[0229] Notice, Figure 20 An example of the camera range of camera units 12101 to 12104 is shown. Camera range 12111 represents the camera range of camera unit 12101 located at the front nose; camera ranges 12112 and 12113 represent the camera ranges of camera units 12102 and 12103 located at the rearview mirrors, respectively; and camera range 12114 represents the camera range of camera unit 12104 located at the rear bumper or rear door. For example, by superimposing the image data acquired by camera units 12101 to 12104, a bird's-eye view of the vehicle 12100 viewed from above is obtained.

[0230] At least one of the camera units 12101 to 12104 may have the function of acquiring distance information. For example, at least one of the camera units 12101 to 12104 may be a stereo camera including multiple camera elements, or may be a camera element having pixels for phase difference detection.

[0231] For example, the microcomputer 12051 can calculate the distance to each three-dimensional object within the camera range 12111-12114 and the change of that distance over time (relative speed to the vehicle 12100) based on distance information obtained from camera units 12101-12104. This allows it to extract three-dimensional objects, especially those closest to the vehicle 12100 on the road and traveling at a predetermined speed (e.g., 0 km / h or higher) in approximately the same direction as the vehicle 12100, as the preceding vehicle. Furthermore, the microcomputer 12051 can preset the distance to be maintained with the preceding vehicle to perform automatic braking control (including follow-stop control) and automatic acceleration control (including follow-start control), etc. As described above, cooperative control can be performed to achieve autonomous driving, etc., that does not rely on driver operation.

[0232] For example, based on distance information obtained from camera units 12101-12104, microcomputer 12051 can classify three-dimensional object data about three-dimensional objects into two-wheeled vehicles, ordinary vehicles, large vehicles, pedestrians, and other three-dimensional objects such as utility poles, extract the classified three-dimensional object data, and use it for automatic obstacle avoidance. For example, microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, microcomputer 12051 can determine the collision risk, which represents the degree of risk of collision with each obstacle. When the collision risk is higher than or equal to a set value (which indicates that a collision may occur), microcomputer 12051 can perform driving assistance to avoid collision by outputting a warning to the driver via audio speaker 12061 or display unit 12062, or by performing forced deceleration or collision avoidance steering via drive system control unit 12010.

[0233] At least one of the camera units 12101 to 12104 can be an infrared camera for detecting infrared light. For example, the microcomputer 12051 can identify a pedestrian by determining whether a pedestrian exists in the images captured by the camera units 12101 to 12104. For example, the pedestrian is identified by: extracting feature points from the images captured by the camera units 12101 to 12104, which are infrared cameras; and determining whether the object is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of the object. When the microcomputer 12051 identifies a pedestrian by determining that a pedestrian exists in the images captured by the camera units 12101 to 12104, the sound image output unit 12052 controls the display unit 12062 to overlay and display a rectangular outline for emphasis on the identified pedestrian. Furthermore, the sound image output unit 12052 can control the display unit 12062 to display an icon or the like representing a pedestrian at a desired location.

[0234] Examples of vehicle control systems to which the technology of this disclosure is applicable have been described above. The technology of this disclosure is applicable, for example, to the camera unit 12031 among the aforementioned components. Specifically, Figure 11 The light intensity detection circuit 1 can be applied to the camera unit 12031. By applying the technology according to this disclosure to the camera unit 12031, the generation of sunspots can be suppressed, thereby obtaining images that are easier to observe and thus reducing driver fatigue.

[0235] [12. Examples of application of electronic devices]

[0236] The aforementioned light transmission detection circuit 1 or 1a can be applied to various electronic devices, such as camera devices like digital cameras or digital video cameras, mobile phones with camera functions, or other devices with camera functions.

[0237] Figure 21 This is a block diagram illustrating an example of the construction of a camera device for an electronic device to which the light intensity detection circuit 1 or 1a according to this disclosure is applicable.

[0238] Figure 21 The camera device 201 shown includes an optical system 202, a shutter device 203, a solid-state imaging element 204, a control circuit 205, a signal processing circuit 206, a monitor 207, and a memory 208, and the camera device 201 is capable of capturing still images and moving images.

[0239] The optical system 202 includes one or more lenses and guides light (incident light) from the subject to the solid-state imaging element 204 to form an image on the light-receiving surface of the solid-state imaging element 204.

[0240] The shutter device 203 is disposed between the optical system 202 and the solid-state imaging element 204, and according to the control of the control circuit 205, the shutter device 203 controls the illumination period and the shading period of the solid-state imaging element 204.

[0241] The solid-state imaging element 204 is comprised of a package including the aforementioned light intensity detection circuit 1 or 1a. The solid-state imaging element 204 accumulates signal charge over a certain period of time based on the imaging light received on the light-receiving surface via the optical system 202 and the shutter device 203. In response to a drive signal (timing signal) supplied from the control circuit 205, the signal charge stored in the solid-state imaging element 204 is transferred.

[0242] The control circuit 205 outputs drive signals to control the transmission operation of the solid-state imaging element 204 and the shutter operation of the shutter device 203, so as to drive the solid-state imaging element 204 and the shutter device 203.

[0243] The signal processing circuit 206 performs various signal processing operations on the signal charge output from the solid-state imaging element 204. The image (image data) obtained by the signal processing circuit 206 is supplied to the monitor 207 for display or to the memory 208 for storage (recording).

[0244] By installing the light transmission detection circuit 1 or 1a in the solid-state imaging element 204, the imaging device 201 constructed as described above can also detect the light transmission with high precision without increasing the circuit size.

[0245] [13. Effect]

[0246] The overlight detection circuit 1 or 1a includes a MOS transistor Mn1 or Mp1 and a capacitor Ca or Cb as a high-impedance element. The source of the MOS transistor Mn1 or Mp1 is connected to the vertical signal line VSL of the image sensor. The capacitor Ca or Cb, as a high-impedance element, is connected to the drain of the MOS transistor Mn1 or Mp1. The overlight detection circuit 1 or 1a detects the potential fluctuation of the vertical signal line VSL based on a potential defined by a threshold voltage Vth1, which is the gate potential of the MOS transistor Mn1 or Mp1, and outputs the potential of the junction between the drain of the MOS transistor Mn1 or Mp1 and the high-impedance element as a signal representing the overlight detection result. Therefore, the overlight detection circuit 1 or 1a can detect the overlight of the image sensor 100 without increasing the circuit size, while ensuring a wide D range.

[0247] The high-impedance component is a capacitor Ca or Cb. Therefore, the light reception of the image sensor 100 can be detected using a simple construction, while ensuring a wide D range.

[0248] The high-impedance component is a resistor. Therefore, the light reception of the image sensor 100 can be detected using a simple construction, while ensuring a wide D range.

[0249] The imaging element of the image sensor 100 is an electronic sensor that converts incident light into electrons. The MOS transistor is an NMOS transistor Mn1. Therefore, the light reception circuit 1 can detect the amount of light received by the electronic sensor.

[0250] The imaging element of the image sensor 100 is a Hall sensor that converts incident light into holes. The MOS transistor is a PMOS transistor Mp1. Therefore, the light transmission detection circuit 1a is capable of detecting the light transmission amount received by the Hall sensor.

[0251] The light intensity detection circuit 1 or 1a outputs a signal indicating the light intensity detection result to the counter 23. The output signal of the comparator 22 is input to the counter 23, and the comparator 22 compares the potential of the vertical signal line VSL with the Ramp wave, which serves as a predetermined reference signal. When a signal indicating the amount of light received is input from the light intensity detection circuit 1 or 1a to the counter 23, the counter 23 stops counting. Therefore, the image sensor 100 can prevent the generation of sunspots.

[0252] The light intensity detection circuit 1 or 1a outputs a signal indicating the light intensity detection result to comparator 22, which compares the potential of the vertical signal line VSL with a Ramp wave as a predetermined reference signal. When a signal indicating the amount of light received is input from the light intensity detection circuit 1 or 1a to comparator 22, comparator 22 stops comparing the potential of the vertical signal line VSL with the Ramp wave. Therefore, the image sensor 100 is able to prevent the generation of sunspots.

[0253] When receiving excessive light, the excessive light detection circuit 1 or 1a outputs a pseudo-potential signal instead of the potential of the vertical signal line VSL to the comparator. For example, when excessive light reception is detected, the excessive light detection circuit 1 or 1a outputs a pseudo-potential signal instead of the potential of the vertical signal line VSL to the positive terminal of the comparator 22. The pseudo-potential signal corresponds to the case of receiving high-brightness light with a charge e- generated by photoelectric conversion not exceeding Qs. Therefore, the image sensor 100 can prevent the generation of sunspots.

[0254] Furthermore, the light receiving element 110 includes an element substrate 30 and a readout circuit board 40. The photoelectric conversion unit of the image sensor is disposed in the element substrate 30. An over-light detection circuit 1 or 1a is included in the readout circuit board 40. The over-light detection circuit 1 or 1a includes a MOS transistor Mn1 or Mp1 and a capacitor Ca or Cb as a high-impedance element. The source of the MOS transistor Mn1 or Mp1 is connected to the vertical signal line VSL of the image sensor. The capacitor Ca or Cb as a high-impedance element is connected to the drain of the MOS transistor Mn1 or Mp1. Therefore, the over-light detection circuit 1 or 1a can detect the over-light amount of the image sensor 100 without increasing the circuit size, while ensuring a wide D range.

[0255] Note that the effects described in this manual are illustrative and not limiting, and other effects are possible.

[0256] Note that this technology can also have the following configurations. (1)

[0258] A light intensity detection circuit, comprising:

[0259] A metal-oxide-semiconductor (MOS) transistor whose source is connected to the vertical signal line of an image sensor; and

[0260] A high-impedance element connected to the drain of the MOS transistor.

[0261] Specifically, the potential fluctuation of the vertical signal line is detected based on the potential defined by the gate potential of the MOS transistor, and the potential of the junction between the drain of the MOS transistor and the high-impedance element is output as a signal representing the result of the light intensity detection. (2)

[0263] According to the light transmission detection circuit described in (1),

[0264] The high-impedance element is a capacitor. (3)

[0266] According to the light transmission detection circuit described in (1),

[0267] The high-impedance element is a resistor. (4)

[0269] According to any one of (1) to (3) of the light transmission detection circuit,

[0270] The image sensor's camera element is an electronic sensor that converts incident light into electrons, and

[0271] The MOS transistor is an N-channel MOS transistor. (5)

[0273] According to any one of (1) to (3) of the light transmission detection circuit,

[0274] The image sensor's camera element is a Hall sensor that converts incident light into holes, and

[0275] The MOS transistor is a P-channel MOS transistor. (6)

[0277] According to any one of (1) to (5) the light transmission detection circuit,

[0278] Specifically, the signal representing the light intensity detection result is output to a counter, and the output signal of a comparator is input to the counter. The comparator compares the potential of the vertical signal line with a predetermined reference signal. (7)

[0280] According to any one of (1) to (5) the light transmission detection circuit,

[0281] The signal representing the light intensity detection result is output to a comparator, which compares the potential of the vertical signal line with a predetermined reference signal. (8)

[0283] According to the light transmission detection circuit described in (7),

[0284] Specifically, when excessive light reception is detected, a pseudo-potential signal, instead of the potential of the vertical signal line, is output to the comparator. (9)

[0286] A light receiving element comprising:

[0287] A component substrate, wherein a photoelectric conversion unit is disposed in the component substrate; and

[0288] circuit board

[0289] The circuit board includes a light transmission detection circuit, which includes:

[0290] A metal-oxide-semiconductor (MOS) transistor, the source of which is connected to the vertical signal line of the photoelectric conversion unit; and

[0291] A high-impedance element is connected to the drain of the MOS transistor. (10)

[0293] According to the optical receiving element described in (9),

[0294] The circuit board includes:

[0295] A transmission transistor, the source of which is connected to the photoelectric conversion unit;

[0296] A reset transistor, the source of which is connected to the drain of the transmission transistor; and

[0297] An amplifying transistor, the gate of which is connected to the drain of the transmission transistor. (11)

[0299] According to the optical receiving element described in (10), it further includes:

[0300] Select a transistor whose drain is connected to the source of the amplifying transistor. (12)

[0302] According to the optical receiving element described in (11),

[0303] The vertical signal line is connected to the source of the selection transistor. (13)

[0305] According to the optical receiving element described in (12),

[0306] The source of the selection transistor is electrically connected to the source of the MOS transistor. (14)

[0308] The optical receiving element according to any one of (9) to (13) further comprises:

[0309] A comparator is connected to the light transmission detection circuit. (15)

[0311] According to the optical receiving element described in (14), it further includes:

[0312] A counter, which is connected to the comparator. (16)

[0314] An electronic device comprising:

[0315] Optical system;

[0316] A photoelectric conversion unit that performs photoelectric conversion on light incident via the optical system;

[0317] The signal processing circuit processes the signal charge formed by the photoelectric conversion of light by the photoelectric conversion unit; and

[0318] The light intensity detection circuit includes a metal-oxide-semiconductor (MOS) transistor and a high-impedance element, wherein the source of the MOS transistor is connected to the vertical signal line of the photoelectric conversion unit, and the high-impedance element is connected to the drain of the MOS transistor.

[0319] List of reference numerals

[0320] 1.1a Light Detection Circuit

[0321] 100 Image Sensor

[0322] 10, 10a pixel unit

[0323] 11 AD Conversion Circuit

[0324] 12 camera units

[0325] 21 DAC

[0326] 22 Comparators

[0327] 23 Counter

[0328] 24 PLL

[0329] Mn1 NMOS transistor

[0330] Mp1 PMOS transistor

[0331] Ca, Cb capacitors

Claims

1. A light intensity detection circuit, comprising: A MOS transistor whose source is connected to the vertical signal line of the image sensor; and A high-impedance element connected to the drain of the MOS transistor. During the over-light detection operation, a predetermined threshold level is applied to the gate of the MOS transistor via a switch, and a ground potential is applied to the gate of the MOS transistor via the switch to turn off the MOS transistor and return it to normal operation. Specifically, the potential fluctuation of the vertical signal line is detected based on the potential defined according to the threshold level, where the threshold level is the gate potential of the MOS transistor, and the potential of the junction between the drain of the MOS transistor and the high-impedance element is output as a signal representing the result of the light intensity detection.

2. The light transmission detection circuit according to claim 1, in, The high-impedance element is a capacitor.

3. The light transmission detection circuit according to claim 1, in, The high-impedance element is a resistor.

4. The light transmission detection circuit according to claim 1, in, The image sensor's camera element is an electronic sensor that converts incident light into electrons, and The MOS transistor is an N-channel MOS transistor.

5. The light transmission detection circuit according to claim 1, in, The image sensor's camera element converts incident light into holes, and The MOS transistor is a P-channel MOS transistor.

6. The light transmission detection circuit according to any one of claims 1 to 5, in, The signal representing the light intensity detection result is output to a counter, and the output signal of a comparator is input to the counter. The comparator compares the potential of the vertical signal line with a predetermined reference signal.

7. The light transmission detection circuit according to any one of claims 1 to 5, in, The signal representing the light intensity detection result is output to a comparator, which compares the potential of the vertical signal line with a predetermined reference signal.

8. The light transmission detection circuit according to claim 7, in, When excessive light reception is detected, a pseudo-potential signal, instead of the potential of the vertical signal line, is output to the comparator.

9. A light receiving element, comprising: A component substrate, wherein a photoelectric conversion unit is disposed in the component substrate; and circuit board The circuit board includes a light transmission detection circuit according to any one of claims 1-8.

10. The optical receiving element according to claim 9, in, The circuit board includes: A transmission transistor, the source of which is connected to the photoelectric conversion unit; A reset transistor, the source of which is connected to the drain of the transmission transistor; and An amplifying transistor, the gate of which is connected to the drain of the transmission transistor.

11. The optical receiving element according to claim 10, further comprising: Select a transistor whose drain is connected to the source of the amplifying transistor.

12. The optical receiving element according to claim 11, in, The vertical signal line is connected to the source of the selection transistor.

13. The optical receiving element according to claim 12, in, The source of the selection transistor is electrically connected to the source of the MOS transistor.

14. The optical receiving element according to any one of claims 9 to 13, further comprising: A comparator is connected to the light transmission detection circuit.

15. The optical receiving element according to claim 14, further comprising: A counter, which is connected to the comparator.

16. An electronic device comprising: Optical system; A photoelectric conversion unit that performs photoelectric conversion on light incident via the optical system; A signal processing circuit that processes the signal charge formed by the photoelectric conversion unit through photoelectric conversion of the light; and The light transmission detection circuit according to any one of claims 1-8.

Images