Method, apparatus, device, and medium for generating algorithm model and layout of electronic device

Abstract

The embodiment of the present application provides a method, device, equipment and medium for generating an algorithm model and layout of an electronic device, which relates to the field of electronic device design. The method includes: perturbing the initial configuration of the electronic device to obtain the initial configuration of the electronic device after the perturbation, and performing simulation and solution calculation on the initial configuration after the perturbation to obtain the simulation result of the initial configuration after the perturbation; extracting indicators from the simulation result of the initial configuration after the perturbation to obtain the indicators of the initial configuration after the perturbation; in response to determining that the indicators of the initial configuration after the perturbation meet the requirements of the design indicators of the electronic device, the indicators of the initial configuration after the perturbation are stored in a database to construct a database that meets the requirements of the design indicators; based on the database that meets the requirements of the design indicators, an algorithm model for generating the layout of the electronic device is generated. This solution can effectively solve the technical problems of long design cycle and high design cost of electronic devices.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of electronic device design, and in particular to a method for generating an algorithm model of an electronic device, a method and device for generating a layout of an electronic device, an electronic device, and a computer storage medium. Background Art

[0002] Analog integrated circuits (such as arithmetic units, comparators, and oscillators), as general-purpose integrated circuit modules, are widely used in a variety of high-performance analog and mixed-analog chips (such as power management chips and analog-to-digital converters) and monolithic integrated systems (SoCs). As a type of analog integrated circuit architecture with well-defined and essential functions, it has been extensively studied over the past three decades. With in-depth research and widespread adoption, the design of circuit architectures in mainstream applications has gradually converged. When designing the same circuit for different application scenarios (specifications), designers typically focus on parameter adjustment of front-end devices such as transistors, resistors, and capacitors, and back-end layout design, and verify the performance of the designed circuits using simulation results. RF devices generally consist of four components: an antenna, an RF front-end, an RF transceiver module, and a baseband signal processor. They are the fundamental components for converting digital signals into wireless RF signals and are core components of wireless communication systems. With the advent of the 5G era, the demand and value of RF devices are rapidly increasing.

[0003] However, with the advancement of process nodes for each generation of RF products and analog integrated circuits, the design of RF devices and analog integrated circuits still consumes a large amount of technical manpower. This is because the design of RF devices and analog integrated circuits involves too many parameters, making it difficult for designers to complete performance modeling of the designed devices and find the optimal layout through simple formula derivation. A large amount of design experience and knowledge is required during the device and circuit design and parameter adjustment process. Designers who lack design experience and theoretical knowledge often cannot achieve the required performance indicators even after multiple parameter adjustments. Even designers with certain design experience and theoretical knowledge can spend one to three months to complete the entire design process of an RF device or analog integrated circuit, from indicators to layout design and verification. This leads to problems such as long design cycles and high costs in the entire RF or integrated circuit industry, seriously hindering the rapid development of RF or integrated circuit related industries.

[0004] It can be seen that how to effectively solve the technical problems of long design cycle and high design cost of electronic devices has become a technical problem that needs to be solved urgently. Summary of the Invention

[0005] In view of this, one of the technical problems solved by the embodiments of the present invention is to provide a method for generating an algorithm model of an electronic device, a layout generation method, device, electronic device and computer storage medium for an electronic device, so as to solve the technical problems existing in the prior art of how to effectively solve the long design cycle and high design cost of electronic devices.

[0006] According to a first aspect of an embodiment of the present invention, a method for generating an algorithmic model of an electronic device is provided, the method comprising: perturbing an initial configuration of an electronic device to obtain a perturbed initial configuration of the electronic device, and performing simulation and solution calculation on the perturbed initial configuration of the electronic device to obtain a simulation result of the perturbed initial configuration of the electronic device; extracting indicators from the simulation result of the perturbed initial configuration of the electronic device to obtain indicators of the perturbed initial configuration of the electronic device; in response to determining that the indicators of the perturbed initial configuration of the electronic device meet the requirements of the design indicators of the electronic device, storing the indicators of the perturbed initial configuration of the electronic device in a database to construct the database that meets the requirements of the design indicators; and generating an algorithmic model for generating a layout of the electronic device based on the database that meets the requirements of the design indicators.

[0007] According to a second aspect of an embodiment of the present invention, a method for generating a layout of an electronic device is provided, the method comprising: determining an algorithm model for generating a layout of the target electronic device according to a type of the target electronic device, wherein the algorithm model is an algorithm model generated by the method for generating an algorithm model of an electronic device according to the first aspect of an embodiment of the present invention; and generating a layout of the target electronic device that meets design indicator requirements according to performance indicators of the target electronic device through the algorithm model.

[0008] According to a third aspect of an embodiment of the present invention, a device for generating an algorithm model of an electronic device is provided, the device comprising: a simulation module for perturbing an initial configuration of the electronic device to obtain the perturbed initial configuration of the electronic device, and performing simulation and solution calculation on the perturbed initial configuration of the electronic device to obtain a simulation result of the perturbed initial configuration of the electronic device; an index extraction module for extracting indexes from the simulation result of the perturbed initial configuration of the electronic device to obtain indexes of the perturbed initial configuration of the electronic device; a construction module for storing the indexes of the perturbed initial configuration of the electronic device in a database in response to determining that the indexes of the perturbed initial configuration of the electronic device meet the requirements of the design indexes of the electronic device, so as to construct the database that meets the requirements of the design indexes; a first generation module for generating an algorithm model for generating a layout of the electronic device based on the database that meets the requirements of the design indexes.

[0009] According to a fourth aspect of an embodiment of the present invention, a layout generation device for an electronic device is provided, the device comprising: a determination module for determining, according to the type of a target electronic device, an algorithm model for generating a layout of the target electronic device, wherein the algorithm model is an algorithm model generated by the device for generating an algorithm model of an electronic device according to the third aspect of an embodiment of the present invention; and a second generation module for generating, by using the algorithm model, a layout of the target electronic device that meets design indicator requirements according to performance indicators of the target electronic device.

[0010] According to a fifth aspect of an embodiment of the present invention, there is provided an electronic device, comprising: a processor, a memory, a communication interface and a communication bus, wherein the processor, the memory and the communication interface communicate with each other via the communication bus; the memory is used to store at least one executable instruction, and the executable instruction enables the processor to execute an operation corresponding to the method for generating an algorithm model of an electronic device as described in the first aspect, or to execute an operation corresponding to the method for generating a layout of an electronic device as described in the second aspect.

[0011] According to the sixth aspect of an embodiment of the present invention, a computer storage medium is provided, on which a computer program is stored. When the program is executed by a processor, it implements the method for generating an algorithm model of an electronic device as described in the first aspect, or implements the method for generating a layout of an electronic device as described in the second aspect.

[0012] Through the generation scheme of the algorithm model of the electronic device provided by the embodiment of the present invention, the initial configuration of the electronic device is perturbed to obtain the perturbed initial configuration of the electronic device, and the perturbed initial configuration of the electronic device is simulated and solved to obtain the simulation result of the perturbed initial configuration of the electronic device, and then the simulation result of the perturbed initial configuration of the electronic device is subjected to index extraction to obtain the index of the perturbed initial configuration of the electronic device. In response to determining that the index of the perturbed initial configuration of the electronic device meets the requirements of the design index of the electronic device, the index of the perturbed initial configuration of the electronic device is stored in a database to construct the database that meets the requirements of the design index, and based on the database that meets the requirements of the design index, an algorithm model for generating the layout of the electronic device is generated. The algorithm model can be effectively generated, so that the generated algorithm model can effectively generate the layout of the electronic device that meets the requirements of the design index, thereby effectively solving the technical problems of long design cycle and high design cost of electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For ordinary technicians in this field, other drawings can also be obtained based on these drawings.

[0014] Figure 1A This is a flowchart of the steps of the method for generating an algorithm model of an electronic device in the first embodiment;

[0015] Figure 1B A schematic diagram of building a database that meets the indicators according to the first embodiment;

[0016] Figure 1C A schematic diagram of constructing an optimized intelligent agent based on deep learning according to the first embodiment;

[0017] Figure 1D A schematic diagram of an algorithm model generated based on a database that meets the index requirements according to the first embodiment;

[0018] Figure 2A This is a flow chart of the steps of the method for generating a layout of an electronic device in the second embodiment;

[0019] Figure 2B A schematic diagram of the use process of the algorithm model provided according to the second embodiment;

[0020] Figure 3 Schematic diagram of the structure of the device for generating the algorithm model of the electronic device in the third embodiment;

[0021] Figure 4 Schematic diagram of the structure of the layout generation device of the electronic device in the fourth embodiment;

[0022] Figure 5 This is a structural diagram of the electronic device in the fifth embodiment. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by those skilled in the art based on the embodiments in the embodiments of the present invention should fall within the scope of protection of the embodiments of the present invention.

[0024] The specific implementation of the embodiment of the present invention is further described below with reference to the accompanying drawings of the embodiment of the present invention.

[0025] Reference Figure 1A, shows a flowchart of the steps of the method for generating an algorithm model of an electronic device in the first embodiment.

[0026] Specifically, the method for generating an algorithm model of an electronic device provided in this embodiment includes the following steps:

[0027] In step S101, the initial configuration of the electronic device is disturbed to obtain the disturbed initial configuration of the electronic device, and the disturbed initial configuration of the electronic device is simulated and solved to obtain a simulation result of the disturbed initial configuration of the electronic device.

[0028] In this embodiment, the electronic device includes an analog integrated circuit or a radio frequency device. The initial configuration of the electronic device is provided by a designer and can be the initial configuration of a radio frequency device or an integrated circuit. Specifically, a simulation solver can be used to perform a simulation calculation on the perturbed initial configuration of the electronic device to obtain a simulation result of the perturbed initial configuration of the electronic device. It will be understood that the above description is merely exemplary and is not intended to be limiting in this embodiment.

[0029] In step S102 , an index is extracted from a simulation result of the initial configuration of the electronic device after the disturbance, so as to obtain an index of the initial configuration of the electronic device after the disturbance.

[0030] In this embodiment, the indicators of the initial configuration of the electronic device after disturbance refer to indicators that can reflect the operating performance of the electronic device. For example, the indicators of the coupler of an RF device may include frequency range, coupling degree, coupling flatness, isolation, insertion loss, typical input and output standing waves, port impedance, etc. It will be understood that the above description is merely exemplary and this embodiment does not impose any limitation thereto.

[0031] In step S103, in response to determining that the index of the initial configuration of the electronic device after the disturbance meets the requirements of the design index of the electronic device, the index of the initial configuration of the electronic device after the disturbance is stored in a database to construct the database that meets the requirements of the design index.

[0032] In this embodiment, the parameters of the initial configuration of the electronic device after the disturbance are checked to see if they meet the design parameters of the electronic device. If so, the corresponding parameters of the RF device or analog integrated circuit that meets the requirements are stored in a database. Otherwise, the optimization module is executed to perform optimization. It should be understood that the above description is merely exemplary and is not intended to be limiting in this embodiment.

[0033] In a specific example, Figure 1BAs shown, the indicator generator generates an indicator to be designed. The indicator generator is a module used to generate indicators of radio frequency devices or integrated circuits. The indicators refer to indicators that can reflect the working performance of the product. The indicators of the coupler of the radio frequency device refer to frequency range, coupling degree, coupling flatness, isolation, insertion loss, typical input and output standing waves, port impedance, etc. The initial configuration is disturbed. The initial configuration comes from the designer, where the initial configuration refers to the initial configuration of the radio frequency device or integrated circuit. Based on the simulation solver, the initial configuration is simulated and solved. Indicators are extracted for the simulation results after solution. Check whether the design indicator requirements are met. If they are met, the indicators corresponding to the radio frequency devices or analog integrated circuits that meet the requirements are stored in the database, otherwise enter the optimization module to perform optimization. It can be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0034] In some optional embodiments, the method further includes: in response to determining that the index of the initial configuration of the electronic device after the disturbance does not meet the requirements of the design index of the electronic device, optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device. Thus, by optimizing the initial configuration of the electronic device after the disturbance, the index of the optimized initial configuration of the electronic device can be made to meet the requirements of the design index of the electronic device. It will be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0035] In some optional embodiments, when optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device, the initial configuration of the electronic device after the disturbance is optimized by an optimizer based on a global optimization algorithm or a local optimization algorithm so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device. Thus, by optimizing the initial configuration of the electronic device after the disturbance by an optimizer based on a global optimization algorithm or a local optimization algorithm, the index of the optimized initial configuration of the electronic device can be effectively made to meet the requirements of the design index of the electronic device. It can be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0036] In a specific example, the optimization algorithms of the optimizer based on the global or local optimization algorithm include Quasi-Newton Method, Conjugate Gradient Method, Classic Powell Method, Particle Swarm Optimization Algorithm, Genetic Algorithm, Covariance Adaptive Adjustment Evolutionary Strategy (CMAEvolution Strategy, CMA-ES), Pattern Search Method, and Nelder Mead Simplex Algorithm. It is understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0037] In some optional embodiments, when optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device, the initial configuration of the electronic device after the disturbance is optimized by an optimization agent constructed based on deep learning so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device. Thus, by optimizing the initial configuration of the electronic device after the disturbance through an optimization agent constructed based on deep learning, the index of the optimized initial configuration of the electronic device can be effectively made to meet the requirements of the design index of the electronic device. It can be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0038] In some optional embodiments, before optimizing the initial configuration of the electronic device after the disturbance using the optimization agent constructed based on deep learning, the method further includes: collecting multiple sets of parameter sets for various parts of the initial configuration of the electronic device that affect the working performance of the electronic device; performing simulation and solution calculations on the multiple sets of parameter sets for various parts of the initial configuration of the electronic device that affect the working performance of the electronic device to obtain simulation results; constructing the optimization agent based on deep learning, and using the multiple sets of parameter sets and the simulation results as sample sets to train the optimization agent. In this way, the optimization agent can be effectively trained using the multiple sets of parameter sets and the simulation results. It will be understood that the above description is merely exemplary and this embodiment does not impose any limitation on this.

[0039] In a specific example, Figure 1CAs shown, the data sampler generates multiple sets of parameter sets for various parts that affect the working performance of the RF device or integrated circuit. For example, the coupler of the RF device is composed of a transmission line, wherein the line width of the transmission line can affect the impedance index of the coupler. Then, the change of the line width within a certain range can be used as the multiple sets of parameter sets generated by the data sampler. Then, the data collected by the data sampler is applied to the simulation solver, and the simulation solver can calculate the simulation results. Finally, an optimization agent is constructed based on deep learning, and multiple sets of parameter sets and simulation results are used as sample sets to train the optimization agent created based on deep learning, wherein the optimization agent is constructed using a deep neural network. The types of neural networks include convolutional neural networks, fully connected neural networks, graph neural networks, etc. The deep neural network learns which part of the product performance should be adjusted in the current state to better meet the index requirements. It can be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0040] In some optional embodiments, the electronic device includes an analog integrated circuit. When optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device, the initial configuration of the analog integrated circuit after the disturbance is optimized by a simulation layout optimization agent built based on an expert system, an unsupervised algorithm, a deep learning and an optimization algorithm, so that the index of the optimized initial configuration of the analog integrated circuit meets the requirements of the design index of the analog integrated circuit. Thus, by optimizing the initial configuration of the analog integrated circuit after the disturbance through a simulation layout optimization agent built based on an expert system, an unsupervised algorithm, a deep learning and an optimization algorithm, the index of the optimized initial configuration of the analog integrated circuit can be effectively made to meet the requirements of the design index of the analog integrated circuit. It can be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0041] In some optional embodiments, before optimizing the initial configuration of the analog integrated circuit after disturbance by a simulation layout optimization agent built based on an expert system, an unsupervised algorithm, a deep learning algorithm, and an optimization algorithm, the method further includes: generating an initial configuration of the simulation layout based on a self-learning expert system, and establishing a parameterized layout based on the initial configuration of the simulation layout; performing dimensionality reduction and simplification on the post-simulation parameters of the parameterized layout to obtain the simplified parameterized layout; and iteratively optimizing the simplified parameterized layout based on an optimization algorithm, and outputting an optimal layout that meets the index requirements after the iteration reaches the optimal solution. In this way, the optimal layout that meets the index requirements can be effectively output. It will be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0042] In a specific example, to address the issues of extremely slow simulation speed and long search for the optimal layout caused by the large number of parameters in the post-simulation netlist of an analog integrated circuit and the extraction of all parasitic parameters (R+C+CC), a simulation layout optimization agent is built based on an expert system, unsupervised algorithms, deep learning, and optimization algorithms (global optimization algorithms and local optimization algorithms) to quickly and efficiently generate an optimal layout that meets design specifications. Specifically, the initial configuration of the layout is first generated based on the expert system; then, the layout is parameterized, and the impact of each parameter on the design specifications is studied based on an unsupervised algorithm. The large number of parameters is summarized into a small set of parameters to simplify the post-simulation parameters of the layout. The simplified layout is then iteratively optimized based on the optimization algorithm. After the iteration terminates at the optimal solution, a layout that meets the specification requirements is output. At the same time, a rule extractor is used to extract the design rules for the optimal layout, which is similar to the designer's experience, and the expert system's knowledge base is updated. This helps to enhance the robustness, accuracy, and robustness of the layout generation module. It is understood that the above description is only exemplary and this embodiment does not impose any limitations on this.

[0043] In some optional embodiments, before generating the initial configuration of the simulation layout based on the self-learning expert system, the method further includes: constructing a comprehensive database that maps the schematic diagram generated by the designer to the layout, and generating the knowledge rules used to map the schematic diagram to the layout based on the comprehensive database, and then forming an inference engine for memorizing the rule program used to control the layout generation based on the knowledge rules; inputting the schematic diagram of the layout to be generated into the inference engine for inference to generate the initial layout, and parameterizing the initial layout to obtain a parameterized layout, and then simplifying the parameterized layout through parameter sensitivity analysis to obtain a simplified layout; optimizing the simplified layout to obtain an optimized layout, and making the optimized layout and the schematic diagram of the optimized layout into a data set to update the comprehensive database, thereby updating the knowledge base and inference engine of the self-learning expert system. In this way, the knowledge base and inference engine of the self-learning expert system can be effectively updated. It can be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0044] In a specific example, a comprehensive database of schematics generated by experienced designers is first constructed, mapping them to layouts. Based on this comprehensive database, knowledge rules are generated to map schematics to layouts. Simultaneously, based on these rules, an inference engine is formed, which memorizes the rules governing layout generation. Finally, the schematics for the layout to be generated are input into the inference engine, where they are inferred to generate the initial layout. It should be understood that the above description is merely illustrative and is not intended to be limiting in any way.

[0045] In a specific example, the initial layout is first input into the layout simplification module, and the layout is parameterized to obtain a parameterized layout. At the same time, the parameters are simplified through parameter sensitivity analysis to obtain a simplified layout. Then, the simplified layout is optimized using a combination of global and local optimization algorithms. Finally, the optimized layout and its schematic diagram are compiled into a data set to update the comprehensive database, thereby updating the knowledge base and inference engine, and realizing the self-learning function of the expert system. It will be understood that the above description is only exemplary and this embodiment does not impose any limitations on this.

[0046] In some optional embodiments, when generating the initial configuration of the simulation layout based on the self-learning expert system, a diagram representing the topology, device information, and connection information of the simulated integrated circuit is input into the inference engine of the self-learning expert system to automatically generate the initial configuration of the simulation layout. In this way, the initial configuration of the simulation layout can be automatically generated. It should be understood that the above description is merely exemplary and is not intended to be limiting in any way in this embodiment.

[0047] In some optional embodiments, when establishing a parameterized layout based on the initial configuration of the simulation layout, the initial configuration of the simulation layout is processed according to the designer's parameterization rules to obtain the parameterized layout; or the initial configuration of the simulation layout is discretized to obtain the parameterized layout. In this way, the parameterized layout can be effectively obtained. It should be understood that the above description is merely exemplary and is not limited in this embodiment.

[0048] In some optional embodiments, when performing dimensionality reduction simplification on the post-simulation parameters of the parameterized layout to obtain the simplified parameterized layout, the post-simulation parameters of the parameterized layout are perturbed using a control variable method to obtain layout simulation results before and after the perturbation. An unsupervised clustering algorithm is then used to summarize the mapping relationship between the post-simulation parameters of the parameterized layout and the layout simulation results, thereby establishing a relational model for identifying parameters that characterize the operating performance of the analog integrated circuit. This effectively establishes a relational model for identifying parameters that characterize the operating performance of the analog integrated circuit. It should be understood that the above description is merely exemplary and is not intended to be limiting in any way in this embodiment.

[0049] In some optional embodiments, when the simplified parameterized layout is iteratively optimized based on an optimization algorithm, and the iteration is terminated to the optimal solution, and the optimal layout that meets the index requirements is output, the first step is: based on the global optimization algorithm, the key parameters characterizing the working performance of the analog integrated circuit in the simplified parameterized layout are optimized, and the historical data of the optimization process is saved; the second step is: based on the historical data of the optimization process, a world model is created, and the post-simulation parameter variable values based on the world model are input into a post-simulation solver to perform real simulation calculations to obtain real simulation calculation results, and then check whether the indicators obtained based on the real simulation calculation results meet the design indicators; in response to determining that the indicators obtained based on the real simulation calculation results meet the design indicators, the iterative optimization is terminated and the optimal layout is output; in response to determining that the indicators obtained based on the real simulation calculation results do not meet the design indicators, the first step and the second step are iteratively performed until the indicators obtained based on the real simulation calculation results meet the design indicators. In this way, the optimal layout that meets the index requirements can be effectively output. It should be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0050] In a specific example, a layout generation module based on a self-learning expert system is first constructed to create a minimalist parametric simulation layout. Specifically, traditional expert systems face issues with integrity (i.e., limited designer experience), portability, learning capabilities, and flexibility, leading to various problems during the automatic layout generation process. Therefore, self-learning capabilities are introduced into traditional expert systems to construct a layout generation module based on a self-learning expert system with improved flexibility, scalability, and practicality. The implementation process is as follows: a graph representing the topology, device information, and connectivity information of the simulated integrated circuit is input into the expert system's inference engine to automatically generate the initial configuration of the simulation layout. Specifically, the layout description, process rules (DRCs), and designer experience are incorporated into the expert system's knowledge base as expert knowledge. The device (e.g., inductor, resistor) layout (device center point location, 2D / 3D graphical description of the device) and the inter-device connections (2D / 3D graphical description of the lines) are incorporated into the expert system's inference component. The layout display component serves as the human-computer interaction display for the expert system, visualizing the initial configuration generated by the expert system. A parameterized layout is established based on the initial configuration. Two approaches are proposed for this purpose. The first approach involves processing the initial configuration according to the parametrization rules used by human designers, abstracting the rectangular wiring into positions (x, y), lengths, and widths. However, this approach is limited by the initial configuration, which may not include the optimal design area. In this case, the human designer must intervene and modify the layout. The second approach involves discretizing the initial configuration, describing the circuit shape as a surface or plane composed of a series of vertices. The vertex spacing can be uniform or random, but the spacing must be constrained within the processing technology of the analog circuit model. As the vertex parameters change, the layout shape (circuit layout) also changes. Therefore, this approach is not restricted to the initial configuration containing the optimal design area. Then, the analog circuit post-simulation parameters are simplified based on the relational model. Specifically, regardless of the parameterization method used, the post-simulation parameters are extremely large, making layout optimization costly. Therefore, unsupervised techniques are proposed to reduce the dimensionality of the post-simulation parameters. The specific process is as follows: First, the post-simulation parameters of the layout are perturbed using the control variable method to obtain layout simulation results before and after the perturbation. Second, an unsupervised clustering algorithm is used to summarize the mapping relationship between post-simulation parameters and layout simulation results, thereby establishing a relationship model that can identify key parts (i.e., parameters that can characterize the operating performance of the analog circuit). Specifically, parts with the same functional mode (the same operating performance changes) are divided into the same subset. Each subset serves as the parameter to be optimized in the simulation layout, i.e., the key part, thus reducing the layout optimization solution space. Finally, the parameter optimization and iteration of the simulation circuit post-simulation are carried out.Specifically, in the traditional analog circuit post-simulation optimization parameter adjustment design process, there are problems such as complex optimization objectives, many optimization variables, and low optimization efficiency. Traditional optimization algorithms continuously adjust design variables so that the design results are constantly approaching the optimal target value. By minimizing the objective function, the best degree of fit is achieved between the model output and the actual observation data. Due to the complexity of the analog circuit itself, traditional optimization algorithms often find it difficult to reach the optimal solution in the parameter space. Even if the optimal solution is reached, there is still the problem of a long time period for iterative optimization solution. Therefore, it is proposed to solve the problem of obtaining the optimal solution by constructing an efficient and robust post-simulation optimization module based on multiple local extreme value optimization algorithms and global optimization algorithms. At the same time, the optimization historical data is reused to build a world model, reducing the number of iterative interactions between the optimization algorithm and the post-simulation solver, and accelerating the optimization design. We have verified this solution in RF circuit design, and its performance can be improved by at least 40%. The specific optimization steps are as follows:

[0051] Step 1: Based on the global optimization algorithm (Particle Swarm Optimization, PSO), the simplified key parameters that can characterize the working performance of the analog circuit are optimized according to the design goals by calling the post-simulation solver. At the same time, the historical data of the optimization process is saved. After the optimization data iteration number reaches a certain number (for example, 20 times), step 2 is carried out.

[0052] Step 2: First, a world model is created based on the historical data of the optimization process (1) (i.e., the mapping relationship between the post-simulation parameters and the simulation results can be represented). The world model can be created using deep learning techniques (e.g., convolutional neural networks, graph neural networks) or based on the response surface method. Secondly, a local extreme value optimization algorithm is used to interact with the world model to search for the optimal solution. It is worth mentioning that no matter which method is used to interact with the world model created by the optimization algorithm (i.e., the simplified post-simulation parameter variable values are input into the world model), the world model can give the corresponding simulation results at the ms level. However, since the world model has low accuracy when reaching the variable limit, a gradient descent quasi-Newton optimization algorithm with a superlinear convergence rate is used to interact with the world model to search for the optimal solution.

[0053] Step 3: Input the results of world model optimization (post-simulation parameter variable values) into the post-simulation solver for real simulation calculation, and check whether they meet the design indicators. If they meet the design indicators, terminate the iterative optimization; otherwise, go to the above steps for iterative optimization.

[0054] In some optional embodiments, the method further includes: utilizing a rule extractor to extract rules from the optimal layout, and modifying the knowledge base of the self-learning expert system based on the extracted rules, wherein the rule extractor extracts rules based on a mapping relationship between layout design metrics and the device graphics, device positions, and wiring graphics of the optimal layout. Thus, the extracted rules can effectively modify the knowledge base of the self-learning expert system. It will be understood that the above description is merely exemplary and is not intended to be limiting in any way in this embodiment.

[0055] In a specific example, rules in the knowledge base are added, deleted, and modified to complete the self-learning and updating of the expert system. Specifically, a rule extractor is used to extract rules for the optimal layout and modify the knowledge base of the expert system in the layout generation module. The rule extractor extracts rules based on the mapping relationship between layout design indicators and the device graphics, device positions, and wiring graphics of the optimal layout. It should be understood that the above description is merely exemplary and is not intended to be limiting in any way in this embodiment.

[0056] In step S104, an algorithm model for generating a layout of the electronic device is generated based on the database that meets the design index requirements.

[0057] In some optional embodiments, when generating an algorithmic model for generating a layout of the electronic device based on the database that meets the design index requirements, a set of indicators corresponding to the electronic device is extracted from the database that meets the design index requirements as a sample set, and the algorithmic model is trained based on the sample set. In this way, the algorithmic model can be effectively trained using the extracted set of indicators corresponding to the electronic device. It will be understood that the above description is merely exemplary and is not intended to be limiting in any way in this embodiment.

[0058] In a specific example, Figure 1D As shown, first, based on the database that meets the index requirements, an index set corresponding to the RF device set or the integrated circuit set is extracted as a sample set. Then, based on the sample set, an algorithm model is trained, and the input of the algorithm model is the index output RF device layout or the integrated circuit layout (the layout can be the size parameter of the modified initial configuration), wherein the algorithm model can be a neural network, a support vector machine, or an interpolation algorithm (Lagrange interpolation, polynomial interpolation, piecewise interpolation, spline interpolation, etc.). It can be understood that the above description is only exemplary and this embodiment does not impose any limitation on this.

[0059] In practical applications, the algorithm model generation system consists of two parts, namely the first part of building a database that meets the index requirements and the second part of generating an algorithm model based on the database that meets the index requirements.

[0060] According to the method for generating an algorithm model of an electronic device provided by an embodiment of the present invention, an initial configuration of the electronic device is perturbed to obtain the perturbed initial configuration of the electronic device, and a simulation and solution calculation is performed on the perturbed initial configuration of the electronic device to obtain a simulation result of the perturbed initial configuration of the electronic device, and then an index extraction is performed on the simulation result of the perturbed initial configuration of the electronic device to obtain an index of the perturbed initial configuration of the electronic device. In response to determining that the index of the perturbed initial configuration of the electronic device meets the design index requirements of the electronic device, the index of the perturbed initial configuration of the electronic device is stored in a database to construct the database that meets the design index requirements, and based on the database that meets the design index requirements, an algorithm model for generating a layout of the electronic device is generated. The algorithm model can be effectively generated, so that the generated algorithm model can effectively generate a layout of the electronic device that meets the design index requirements, thereby effectively solving the technical problems of long design cycle and high design cost of electronic devices.

[0061] The method for generating the algorithm model of the electronic device provided in this embodiment can be executed by any appropriate device with data processing capabilities, including but not limited to: cameras, terminals, mobile terminals, PCs, servers, vehicle-mounted equipment, entertainment equipment, advertising equipment, personal digital assistants (PDAs), tablet computers, laptop computers, handheld game consoles, smart glasses, smart watches, wearable devices, virtual display devices or display enhancement devices, etc.

[0062] Reference Figure 2A , shows a flow chart of the steps of the method for generating a layout of an electronic device in the second embodiment.

[0063] Specifically, the method for generating a layout of an electronic device provided in this embodiment includes the following steps:

[0064] In step S201 , an algorithm model for generating a layout of a target electronic device is determined according to the type of the target electronic device.

[0065] In this embodiment, the type of the target electronic device may include an analog integrated circuit or a radio frequency device. The algorithm model is generated according to the method for generating an algorithm model of an electronic device described in the first embodiment. It will be understood that the above description is merely exemplary and is not intended to limit this embodiment in any way.

[0066] In step S202, a layout of the target electronic device that meets design index requirements is generated according to the performance index of the target electronic device through the algorithm model.

[0067] In a specific example, Figure 2BAs shown, first, the specifications are input. For example, the coupler's input frequency range, coupling degree, coupling flatness, isolation, insertion loss, typical input and output standing wave, and port impedance. Then, the corresponding machine learning algorithm model is retrieved based on the product type, and the specifications are input into the algorithm model. Finally, the algorithm model generates a layout that meets the specified specifications. It should be understood that the above description is merely illustrative and is not intended to be limiting in this embodiment.

[0068] In specific applications, the generation system of an algorithmic model for an analog integrated circuit or RF device uses artificial intelligence technology to explore the impact of various components of an analog / RF device on its indicators, thereby generating an algorithmic model that can characterize the impact of these components on the indicators, namely, the algorithmic model of the analog integrated circuit or the algorithmic model of the RF device. The algorithmic model of the analog integrated circuit or the algorithmic model of the RF device is used by inputting the indicators into the algorithmic model to directly generate an analog integrated circuit layout or RF device layout that meets the user's requirements.

[0069] Through the layout generation method of electronic devices provided by the embodiment of the present invention, an algorithm model for generating the layout of the target electronic device is determined according to the type of the target electronic device, wherein the algorithm model is an algorithm model generated by the method for generating the algorithm model of the electronic device described in the first embodiment of the present invention, and through the algorithm model, a layout of the target electronic device that meets the design index requirements is generated according to the performance indicators of the target electronic device. The layout of the electronic device that meets the design index requirements can be effectively generated, thereby effectively solving the technical problems of long design cycle and high design cost of electronic devices.

[0070] The layout generation method of the electronic device provided in this embodiment can be executed by any appropriate device with data processing capabilities, including but not limited to: cameras, terminals, mobile terminals, PCs, servers, vehicle-mounted equipment, entertainment equipment, advertising equipment, personal digital assistants (PDAs), tablet computers, laptop computers, handheld game consoles, smart glasses, smart watches, wearable devices, virtual display devices or display enhancement devices, etc.

[0071] Reference Figure 3 , shows a structural schematic diagram of the device for generating the algorithm model of the electronic device in the third embodiment.

[0072] The device for generating an algorithm model of an electronic device provided in this embodiment includes: a simulation module 301, which is used to perturb the initial configuration of the electronic device to obtain the perturbed initial configuration of the electronic device, and perform simulation and solution calculation on the perturbed initial configuration of the electronic device to obtain a simulation result of the perturbed initial configuration of the electronic device; an index extraction module 302, which is used to extract indexes from the simulation result of the perturbed initial configuration of the electronic device to obtain indexes of the perturbed initial configuration of the electronic device; a construction module 303, which is used to store the indexes of the perturbed initial configuration of the electronic device in a database in response to determining that the indexes of the perturbed initial configuration of the electronic device meet the requirements of the design index of the electronic device, so as to construct the database that meets the requirements of the design index; a first generation module 304, which is used to generate an algorithm model for generating a layout of the electronic device based on the database that meets the requirements of the design index.

[0073] Optionally, the device also includes: an optimization module for optimizing the initial configuration of the electronic device after the disturbance in response to determining that the indicators of the initial configuration of the electronic device after the disturbance do not meet the requirements of the design indicators of the electronic device, so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

[0074] Optionally, the optimization module is specifically used to optimize the initial configuration of the electronic device after disturbance through an optimizer based on a global optimization algorithm or a local optimization algorithm, so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

[0075] Optionally, the optimization module includes: a first optimization sub-module, used to optimize the initial configuration of the electronic device after disturbance through an optimization agent constructed based on deep learning, so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

[0076] Optionally, before the first optimization submodule, the optimization module also includes: an acquisition submodule, which is used to acquire multiple groups of parameter sets of various parts in the initial configuration of the electronic device that affect the working performance of the electronic device; a calculation submodule, which is used to simulate and solve the multiple groups of parameter sets of various parts in the initial configuration of the electronic device that affect the working performance of the electronic device to obtain simulation results; and a training submodule, which is used to construct the optimization intelligent agent based on deep learning, and use the multiple groups of parameter sets and the simulation results as sample sets to train the optimization intelligent agent.

[0077] Optionally, the electronic device includes an analog integrated circuit, and the optimization module includes: a second optimization sub-module, which is used to optimize the initial configuration of the analog integrated circuit after disturbance through an analog layout optimization agent built based on an expert system, an unsupervised algorithm, deep learning and an optimization algorithm, so that the indicators of the optimized initial configuration of the analog integrated circuit meet the requirements of the design indicators of the analog integrated circuit.

[0078] Optionally, before the second optimization submodule, the optimization module also includes: an establishment submodule, which is used to generate an initial configuration of the simulation layout based on a self-learning expert system, and establish a parameterized layout based on the initial configuration of the simulation layout; a first simplification submodule, which is used to perform dimensionality reduction and simplification on the post-simulation parameters of the parameterized layout to obtain the simplified parameterized layout; an iterative optimization submodule, which is used to iteratively optimize the simplified parameterized layout based on an optimization algorithm, and output the optimal layout that meets the index requirements after the iteration is terminated at the optimal solution.

[0079] Optionally, before the establishment submodule, the optimization module also includes: a formation submodule, which is used to construct a comprehensive database for mapping the schematic diagram generated by the designer into the layout, and generate the knowledge rules to be used for mapping the schematic diagram into the layout based on the comprehensive database, and then form an inference engine for memorizing the rule program used to control the layout generation based on the knowledge rules; a second simplification submodule, which is used to input the schematic diagram of the layout to be generated into the inference engine for inference to generate an initial layout, and parameterize the initial layout to obtain a parameterized layout, and then simplify the parameterized layout through parameter sensitivity analysis to obtain a simplified layout; an update submodule, which is used to optimize the simplified layout to obtain an optimized layout, and make the optimized layout and the schematic diagram of the optimized layout into a data set to update the comprehensive database, thereby updating the knowledge base and inference engine of the self-learning expert system.

[0080] Optionally, the establishment submodule is specifically used to: input a graph representing the topological structure, device information and connection information of the analog integrated circuit into the inference engine of the self-learning expert system to automatically generate an initial configuration of the analog layout.

[0081] Optionally, the establishment submodule is specifically used to: process the initial configuration of the simulation layout according to the designer's parameterization rules to obtain the parameterized layout; or, perform shape discretization processing on the initial configuration of the simulation layout to obtain the parameterized layout.

[0082] Optionally, the first simplification submodule is specifically used to: perturb the post-simulation parameters of the parameterized layout through the control variable method to obtain the layout simulation results before and after the disturbance; and use the clustering algorithm of unsupervised technology to summarize the mapping relationship between the post-simulation parameters of the parameterized layout and the layout simulation results, so as to establish a relationship model for identifying parameters that characterize the working performance of the analog integrated circuit.

[0083] Optionally, the iterative optimization submodule is specifically used to: first step: based on the global optimization algorithm, optimize the key parameters characterizing the working performance of the analog integrated circuit in the simplified parameterized layout, and save the historical data of the optimization process; second step: create a world model based on the historical data of the optimization process, and input the post-simulation parameter variable values based on the world model into the post-simulation solver to perform real simulation calculations, obtain real simulation calculation results, and then check whether the indicators obtained based on the real simulation calculation results meet the design indicators; in response to determining that the indicators obtained based on the real simulation calculation results meet the design indicators, terminate the iterative optimization and output the optimal layout; in response to determining that the indicators obtained based on the real simulation calculation results do not meet the design indicators, iteratively execute the first step and the second step until the indicators obtained based on the real simulation calculation results meet the design indicators.

[0084] Optionally, the optimization module also includes: a modification submodule, which is used to use a rule extractor to extract rules from the optimal layout, and modify the knowledge base of the self-learning expert system based on the extracted rules, wherein the rule extractor extracts rules according to the mapping relationship between the layout design indicators and the device graphics, device position, and wiring graphics of the optimal layout.

[0085] Optionally, the first generating module 304 is specifically configured to extract an indicator set corresponding to the electronic device as a sample set based on the database that meets the design indicator requirements, and train the algorithm model based on the sample set.

[0086] The device for generating an algorithm model of an electronic device provided in this embodiment is used to implement the generation method of the algorithm model of an electronic device corresponding to the aforementioned multiple method embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0087] Reference Figure 4 , shows a schematic structural diagram of the layout generation device of the electronic device in the fourth embodiment.

[0088] The layout generation device for electronic devices provided in this embodiment includes: a determination module 401, used to determine the algorithm model used to generate the layout of the target electronic device according to the type of the target electronic device, wherein the algorithm model is the algorithm model generated by the generation device of the algorithm model of the electronic device described in the third embodiment; a second generation module 402, used to generate a layout of the target electronic device that meets the design index requirements according to the performance indicators of the target electronic device through the algorithm model.

[0089] The layout generation apparatus for an electronic device provided in this embodiment is used to implement the layout generation methods for electronic devices corresponding to the aforementioned multiple method embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be described in detail here.

[0090] Reference Figure 5 , shows a schematic structural diagram of an electronic device according to embodiment 5 of the present invention. The specific embodiment of the present invention does not limit the specific implementation of the electronic device.

[0091] like Figure 5 As shown, the electronic device may include: a processor (processor) 502 , a communication interface (Communications Interface) 504 , a memory (memory) 506 , and a communication bus 508 .

[0092] in:

[0093] The processor 502 , the communication interface 504 , and the memory 506 communicate with each other via a communication bus 508 .

[0094] The communication interface 504 is used to communicate with other electronic devices or servers.

[0095] The processor 502 is used to execute the program 510, and specifically can execute the above-mentioned embodiment of the method for generating the algorithm model of the electronic device, or the relevant steps in the embodiment of the method for generating the layout of the electronic device.

[0096] Specifically, the program 510 may include program codes, which include computer operation instructions.

[0097] Processor 502 may be a central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. The one or more processors included in the smart device may be processors of the same type, such as one or more CPUs, or processors of different types, such as one or more CPUs and one or more ASICs.

[0098] The memory 506 is used to store the program 510. The memory 506 may include a high-speed RAM memory, and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.

[0099] The program 510 can be specifically used to enable the processor 502 to perform the following operations: perturb the initial configuration of the electronic device to obtain the perturbed initial configuration of the electronic device, and perform simulation and solution calculation on the perturbed initial configuration of the electronic device to obtain a simulation result of the perturbed initial configuration of the electronic device; extract an index from the simulation result of the perturbed initial configuration of the electronic device to obtain an index of the perturbed initial configuration of the electronic device; in response to determining that the index of the perturbed initial configuration of the electronic device meets the requirements of the design index of the electronic device, the perturbed initial configuration of the electronic device is extracted. The configuration indicators are stored in a database to construct the database that meets the design indicator requirements; based on the database that meets the design indicator requirements, an algorithm model for generating the layout of the electronic device is generated, or it can also be used to enable the processor 502 to perform the following operations: according to the type of the target electronic device, determine the algorithm model for generating the layout of the target electronic device, wherein the algorithm model is an algorithm model generated according to the method for generating the algorithm model of the electronic device described in the first embodiment of the present invention; through the algorithm model, according to the performance indicators of the target electronic device, a layout of the target electronic device that meets the design indicator requirements is generated. In an optional embodiment, the program 510 is also used to enable the processor 502 to optimize the initial configuration of the electronic device after the disturbance in response to determining that the indicators of the initial configuration of the electronic device after the disturbance do not meet the requirements of the design indicators of the electronic device, so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

[0100] In an optional embodiment, the program 510 is also used to enable the processor 502 to optimize the initial configuration of the electronic device after the disturbance so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device, by using an optimizer based on a global optimization algorithm or a local optimization algorithm, to optimize the initial configuration of the electronic device after the disturbance so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

[0101] In an optional embodiment, the program 510 is also used to enable the processor 502 to optimize the initial configuration of the electronic device after the disturbance so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device, by using an optimization agent constructed based on deep learning, to optimize the initial configuration of the electronic device after the disturbance so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

[0102] In an optional embodiment, the program 510 is also used to enable the processor 502 to collect multiple sets of parameter sets for various parts of the initial configuration of the electronic device that affect the working performance of the electronic device before optimizing the initial configuration of the electronic device after disturbance through an optimization agent constructed based on deep learning; simulate and solve the multiple sets of parameter sets for various parts of the initial configuration of the electronic device that affect the working performance of the electronic device to obtain simulation results; construct the optimization agent based on deep learning, and use the multiple sets of parameter sets and the simulation results as sample sets to train the optimization agent.

[0103] In an optional embodiment, the electronic device includes an analog integrated circuit, and the program 510 is also used to enable the processor 502 to optimize the initial configuration of the electronic device after the disturbance so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device, and to optimize the initial configuration of the analog integrated circuit after the disturbance through an analog layout optimization agent built based on an expert system, an unsupervised algorithm, deep learning and an optimization algorithm so that the indicators of the optimized initial configuration of the analog integrated circuit meet the requirements of the design indicators of the analog integrated circuit.

[0104] In an optional embodiment, the program 510 is also used to enable the processor 502 to generate an initial configuration of the simulation layout based on a self-learning expert system and establish a parameterized layout based on the initial configuration of the simulation layout before optimizing the initial configuration of the analog integrated circuit after disturbance through a simulation layout optimization agent built based on an expert system, an unsupervised algorithm, deep learning and an optimization algorithm; perform dimensionality reduction and simplification on the post-simulation parameters of the parameterized layout to obtain the simplified parameterized layout; perform iterative optimization on the simplified parameterized layout based on the optimization algorithm, and output the optimal layout that meets the index requirements after the iteration is terminated at the optimal solution.

[0105] In an optional embodiment, the program 510 is also used to enable the processor 502 to construct a comprehensive database that maps the schematic diagram generated by the designer to the layout before generating the initial configuration of the simulation layout based on the self-learning expert system, and generate knowledge rules to be used for mapping the schematic diagram to the layout based on the comprehensive database, and then form an inference engine for memorizing the rule program used to control the layout generation based on the knowledge rules; input the schematic diagram of the layout to be generated into the inference engine for inference to generate an initial layout, and parameterize the initial layout to obtain a parameterized layout, and then simplify the parameterized layout through parameter sensitivity analysis to obtain a simplified layout; optimize the simplified layout to obtain an optimized layout, and make the optimized layout and the schematic diagram of the optimized layout into a data set to update the comprehensive database, thereby updating the knowledge base and inference engine of the self-learning expert system.

[0106] In an optional embodiment, the program 510 is also used to enable the processor 502 to input a diagram representing the topological structure, device information and connection information of the analog integrated circuit into the inference engine of the self-learning expert system when generating the initial configuration of the analog layout based on the self-learning expert system, so as to automatically generate the initial configuration of the analog layout.

[0107] In an optional embodiment, the program 510 is also used to enable the processor 502 to process the initial configuration of the simulation layout according to the designer's parameterization rules when establishing a parameterized layout based on the initial configuration of the simulation layout to obtain the parameterized layout; or, to perform shape discretization processing on the initial configuration of the simulation layout to obtain the parameterized layout.

[0108] In an optional embodiment, the program 510 is also used to enable the processor 502 to perform dimensionality reduction simplification on the post-simulation parameters of the parameterized layout to obtain the simplified parameterized layout, and then perturb the post-simulation parameters of the parameterized layout by using a control variable method to obtain layout simulation results before and after the perturbation; and to use an unsupervised clustering algorithm to summarize the mapping relationship between the post-simulation parameters of the parameterized layout and the layout simulation results, thereby establishing a relationship model for identifying parameters that characterize the working performance of analog integrated circuits.

[0109] In an optional embodiment, the program 510 is further configured to enable the processor 502 to iteratively optimize the simplified parameterized layout based on an optimization algorithm, and output an optimal layout that meets the index requirements after the iteration is terminated at the optimal solution. The first step is: optimizing the key parameters characterizing the working performance of the analog integrated circuit in the simplified parameterized layout based on the global optimization algorithm, and saving historical data during the optimization process; the second step is: creating a world model based on the historical data during the optimization process, and inputting the post-simulation parameter variable values based on the world model into a post-simulation solver to perform real simulation calculations to obtain real simulation calculation results, and then checking whether the indicators obtained based on the real simulation calculation results meet the design indicators; in response to determining that the indicators obtained based on the real simulation calculation results meet the design indicators, terminating the iterative optimization and outputting the optimal layout; in response to determining that the indicators obtained based on the real simulation calculation results do not meet the design indicators, iteratively executing the first step and the second step until the indicators obtained based on the real simulation calculation results meet the design indicators.

[0110] In an optional embodiment, the program 510 is also used to enable the processor 502 to use a rule extractor to extract rules from the optimal layout, and modify the knowledge base of the self-learning expert system based on the extracted rules, wherein the rule extractor extracts rules according to the mapping relationship between the layout design indicators and the device graphics, device position, and wiring graphics of the optimal layout.

[0111] In an optional embodiment, the program 510 is also used to enable the processor 502 to extract the indicator set corresponding to the electronic device as a sample set based on the database that meets the design indicator requirements when generating an algorithm model for generating the layout of the electronic device based on the database that meets the design indicator requirements, and train the algorithm model based on the sample set.

[0112] The specific implementation of each step in program 510 can be found in the above-mentioned embodiment of the method for generating an algorithm model of an electronic device, or the corresponding description of the corresponding steps and units in the embodiment of the method for generating a layout of an electronic device, and will not be repeated here. Those skilled in the art will clearly understand that for the convenience and brevity of description, the specific working process of the above-described devices and modules can refer to the corresponding process description in the above-mentioned method embodiment, and will not be repeated here.

[0113] Through the electronic device of this embodiment, the initial configuration of the electronic device is disturbed to obtain the initial configuration of the electronic device after the disturbance, and the initial configuration of the electronic device after the disturbance is simulated and calculated to obtain the simulation result of the initial configuration of the electronic device after the disturbance, and then the index extraction is performed on the simulation result of the initial configuration of the electronic device after the disturbance to obtain the index of the initial configuration of the electronic device after the disturbance, in response to determining that the index of the initial configuration of the electronic device after the disturbance meets the requirements of the design index of the electronic device, the index of the initial configuration of the electronic device after the disturbance is stored in a database to construct the database that meets the requirements of the design index, and based on the database that meets the requirements of the design index, an algorithm model for generating the layout of the electronic device is generated, which can effectively generate the algorithm model, so that the generated algorithm model can effectively generate the layout of the electronic device that meets the requirements of the design index, thereby effectively solving the technical problems of long design cycle and high design cost of electronic devices. In addition, based on the type of the target electronic device, an algorithm model for generating the layout of the target electronic device is determined, wherein the algorithm model is an algorithm model generated according to the method for generating the algorithm model of the electronic device described in the first embodiment of the present invention, and through the algorithm model, based on the performance indicators of the target electronic device, a layout of the target electronic device that meets the design indicator requirements is generated. This can effectively generate a layout of the electronic device that meets the design indicator requirements, thereby effectively solving the technical problems of long design cycle and high design cost of electronic devices.

[0114] It should be pointed out that, according to the needs of implementation, the various components / steps described in the embodiments of the present invention can be split into more components / steps, or two or more components / steps or partial operations of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0115] The method according to the embodiment of the present invention described above can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CDROM, RAM, floppy disk, hard disk or magneto-optical disk), or as computer code that is originally stored in a remote recording medium or a non-transitory machine-readable medium and will be stored in a local recording medium, which is downloaded via a network, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor or programmable or dedicated hardware (such as an ASIC or FPGA). It can be understood that a computer, a processor, a microprocessor controller or programmable hardware includes a storage component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor or hardware, the method for generating an algorithmic model of an electronic device or the method for generating a layout of an electronic device described herein is implemented. In addition, when a general-purpose computer accesses the code for implementing the method for generating an algorithmic model of an electronic device or the method for generating a layout of an electronic device shown herein, the execution of the code converts the general-purpose computer into a dedicated computer for executing the method for generating an algorithmic model of an electronic device or the method for generating a layout of an electronic device shown herein.

[0116] Those skilled in the art will appreciate that the units and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the embodiments of the present invention.

[0117] The above implementation methods are only used to illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the scope of patent protection of the embodiments of the present invention should be defined by the claims.

Claims

1. A method for generating an algorithm model of an electronic device, characterized in that: The method comprises: perturbing an initial configuration of the electronic device to obtain a perturbed initial configuration of the electronic device, and performing simulation and solution calculation on the perturbed initial configuration of the electronic device to obtain a simulation result of the perturbed initial configuration of the electronic device; Performing index extraction on a simulation result of the initial configuration of the electronic device after the disturbance to obtain an index of the initial configuration of the electronic device after the disturbance; In response to determining that the index of the initial configuration of the electronic device after the disturbance meets the requirements of the design index of the electronic device, storing the index of the initial configuration of the electronic device after the disturbance in a database to construct the database that meets the requirements of the design index; generating an algorithm model for generating a layout of the electronic device based on the database that meets the design index requirements; In response to determining that an index of the initial configuration of the electronic device after the disturbance does not meet the requirements of the design index of the electronic device, optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device; Optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device includes: Collecting multiple sets of parameter sets of various parts of the electronic device that affect the working performance of the electronic device in the initial configuration of the electronic device; Performing simulation calculations on multiple sets of parameter sets of various parts of the initial configuration of the electronic device that affect the working performance of the electronic device to obtain simulation results; Constructing an optimization agent based on deep learning, and using the multiple parameter sets and the simulation results as sample sets to train the optimization agent; The initial configuration of the electronic device after disturbance is optimized by an optimization intelligent agent constructed based on deep learning, so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

2. The method for generating an algorithm model of an electronic device according to claim 1, wherein: Optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device includes: The disturbed initial configuration of the electronic device is optimized by an optimizer based on a global optimization algorithm or a local optimization algorithm, so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

3. The method for generating an algorithm model of an electronic device according to claim 1, wherein: The electronic device includes an analog integrated circuit, Optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device includes: Through the simulation layout optimization intelligent agent built based on expert system, unsupervised algorithm, deep learning and optimization algorithm, the initial configuration of the analog integrated circuit after disturbance is optimized so that the indicators of the optimized initial configuration of the analog integrated circuit meet the requirements of the design indicators of the analog integrated circuit.

4. The method for generating an algorithm model of an electronic device according to claim 3, wherein: Before optimizing the disturbed initial configuration of the analog integrated circuit using the analog layout optimization agent constructed based on the expert system, unsupervised algorithm, deep learning, and optimization algorithm, the method further includes: Generate an initial configuration of a simulation layout based on a self-learning expert system, and establish a parameterized layout based on the initial configuration of the simulation layout; Performing dimensionality reduction and simplification on the post-simulation parameters of the parameterized layout to obtain a simplified parameterized layout; Based on the optimization algorithm, the simplified parameterized layout is iteratively optimized, and after the iteration is terminated at the optimal solution, the optimal layout that meets the index requirements is output.

5. The method for generating an algorithm model of an electronic device according to claim 4, wherein: Before generating the initial configuration of the simulation layout based on the self-learning expert system, the method further includes: Constructing a comprehensive database of schematics generated by designers mapped to layouts, generating knowledge rules used to map the schematics to the layouts based on the comprehensive database, and then forming an inference engine based on the knowledge rules for memorizing the rule program used to control layout generation; Inputting the schematic diagram of the layout to be generated into the inference engine for inference to generate an initial layout, parameterizing the initial layout to obtain a parameterized layout, and then simplifying the parameterized layout through parameter sensitivity analysis to obtain a simplified layout; The simplified layout is optimized to obtain an optimized layout, and the optimized layout and the schematic diagram of the optimized layout are made into a data set to update the comprehensive database, thereby updating the knowledge base and inference engine of the self-learning expert system.

6. The method for generating an algorithm model of an electronic device according to claim 4, wherein: The self-learning expert system is used to generate an initial configuration of the simulation layout, including: A graph representing the topological structure, device information and connection information of the analog integrated circuit is input into the inference engine of the self-learning expert system to automatically generate an initial configuration of the analog layout.

7. The method for generating an algorithm model of an electronic device according to claim 4, wherein: The establishing of a parameterized layout based on the initial configuration of the simulation layout comprises: According to the designer's parameterization rules, the initial configuration of the simulation layout is processed to obtain the parameterized layout; or, The initial configuration of the simulation layout is subjected to shape discretization processing to obtain the parameterized layout.

8. The method for generating an algorithm model of an electronic device according to claim 4, wherein: The step of performing dimensionality reduction and simplification on the post-simulation parameters of the parameterized layout to obtain the simplified parameterized layout includes: By using a control variable method, the post-simulation parameters of the parameterized layout are disturbed to obtain layout simulation results before and after the disturbance; A clustering algorithm based on unsupervised technology is used to summarize the mapping relationship between the post-simulation parameters of the parameterized layout and the layout simulation results, thereby establishing a relationship model for identifying parameters that characterize the working performance of the analog integrated circuit.

9. The method for generating an algorithm model of an electronic device according to claim 4, wherein: The simplified parameterized layout is iteratively optimized based on the optimization algorithm, and after the iteration reaches the optimal solution, the optimal layout that meets the index requirements is output, including: Step 1: Optimizing key parameters characterizing the operating performance of the analog integrated circuit in the simplified parameterized layout based on a global optimization algorithm, and saving historical data during the optimization process; Step 2: Creating a world model based on historical data in the optimization process, and inputting the post-simulation parameter variable values based on the world model into a post-simulation solver to perform real simulation calculations, obtain real simulation calculation results, and then check whether the indicators obtained based on the real simulation calculation results meet the design indicators; In response to determining that the index obtained based on the real simulation calculation result meets the design index, terminating the iterative optimization and outputting the optimal layout; In response to determining that the index obtained based on the actual simulation calculation result does not meet the design index, the first step and the second step are iteratively performed until the index obtained based on the actual simulation calculation result meets the design index.

10. The method for generating an algorithm model of an electronic device according to claim 4, wherein: The method further comprises: A rule extractor is used to extract rules from the optimal layout, and based on the extracted rules, the knowledge base of the self-learning expert system is modified, wherein the rule extractor extracts rules according to the mapping relationship between layout design indicators and the device graphics, device position, and wiring graphics of the optimal layout.

11. The method for generating an algorithm model of an electronic device according to claim 1, wherein: The step of generating an algorithm model for generating a layout of the electronic device based on the database meeting the design index requirements includes: Based on the database that meets the design index requirements, an index set corresponding to the electronic device is extracted as a sample set, and the algorithm model is trained based on the sample set.

12. A method for generating a layout of an electronic device, characterized in that: The method comprises: Determining, according to the type of the target electronic device, an algorithm model for generating a layout of the target electronic device, wherein the algorithm model is an algorithm model generated by the method for generating an algorithm model of an electronic device according to any one of claims 1 to 11; By using the algorithm model, a layout of the target electronic device that meets the design index requirements is generated according to the performance index of the target electronic device.

13. A device for generating an algorithm model of an electronic device, characterized in that: The device comprises: a simulation module, configured to perturb the initial configuration of the electronic device to obtain a perturbed initial configuration of the electronic device, and perform simulation and solution calculation on the perturbed initial configuration of the electronic device to obtain a simulation result of the perturbed initial configuration of the electronic device; An index extraction module, configured to extract an index from a simulation result of the initial configuration of the electronic device after the disturbance, so as to obtain an index of the initial configuration of the electronic device after the disturbance; a construction module, configured to, in response to determining that the index of the initial configuration of the electronic device after the disturbance meets the requirements of the design index of the electronic device, store the index of the initial configuration of the electronic device after the disturbance in a database to construct the database meeting the requirements of the design index; A first generating module is configured to generate an algorithm model for generating a layout of the electronic device based on the database meeting the design index requirements; In response to determining that an index of the initial configuration of the electronic device after the disturbance does not meet the requirements of the design index of the electronic device, optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device; Optimizing the initial configuration of the electronic device after the disturbance so that the index of the optimized initial configuration of the electronic device meets the requirements of the design index of the electronic device includes: Collecting multiple sets of parameter sets of various parts of the electronic device that affect the working performance of the electronic device in the initial configuration of the electronic device; Performing simulation calculations on multiple sets of parameter sets of various parts of the initial configuration of the electronic device that affect the working performance of the electronic device to obtain simulation results; Constructing an optimization agent based on deep learning, and using the multiple parameter sets and the simulation results as sample sets to train the optimization agent; The initial configuration of the electronic device after disturbance is optimized by an optimization intelligent agent constructed based on deep learning, so that the indicators of the optimized initial configuration of the electronic device meet the requirements of the design indicators of the electronic device.

14. A layout generation device for an electronic device, characterized in that: The device comprises: A determination module is used to determine the layout for generating the target electronic device according to the type of the target electronic device. An algorithm model, wherein the algorithm model is an algorithm model generated by the device for generating an algorithm model of an electronic device according to claim 13; The second generating module is used to generate a layout of the target electronic device that meets the design index requirements according to the performance index of the target electronic device through the algorithm model.

15. An electronic device, characterized in that: The device comprises: A processor, a memory, a communication interface, and a communication bus, wherein the processor, the memory, and the communication interface communicate with each other via the communication bus; The memory is used to store at least one executable instruction, which enables the processor to perform operations corresponding to the method for generating an algorithm model of an electronic device as described in any one of claims 1 to 11, or to perform operations corresponding to the method for generating a layout of an electronic device as described in claim 12.

16. A computer storage medium, characterized in that A computer program is stored thereon, which, when executed by a processor, implements the method for generating an algorithm model of an electronic device as claimed in any one of claims 1 to 11, or implements the method for generating a layout of an electronic device as claimed in claim 12.

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