Semiconductor integrated circuit

Abstract

The object of the present application is to provide a semiconductor integrated circuit capable of realizing high-speed transmission while maintaining a fault-tolerant function. The semiconductor integrated circuit of the embodiment includes: a first MOS transistor to which an input signal of a signal level corresponding to a voltage range of a first voltage is applied to a gate, and which controls conduction and non-conduction between a reference potential point and an intermediate node; a second MOS transistor connected to the first MOS transistor via the intermediate node and constituting a stack with the first MOS transistor, to which a bias voltage is supplied to a gate, and which applies a voltage lower than a withstand voltage of the first MOS transistor to the intermediate node; a third MOS transistor to which a second voltage higher than the first voltage is supplied, to which a signal of a level corresponding to a dynamic of the first MOS transistor is applied to a gate, and which outputs an output signal of a signal level corresponding to a voltage range of the second voltage; and a switching circuit to make the intermediate node a fixed voltage at the time of the cutoff of the first MOS transistor.

Description

[0001] This application claims priority based on Japanese Patent Application No. 2020-201175 (filed on December 3, 2020). This application incorporates the entire contents of that basic application by reference. Technical Field

[0002] Embodiments of the present invention relate to semiconductor integrated circuits. Background Technology

[0003] In the past, level shift circuits were sometimes used when transmitting signals to electrical circuits using different power supply voltages. These level shift circuits included fault-tolerant features that took into account the voltage withstand capabilities of the mounted components. Fault tolerance prevents the application of voltages exceeding the withstand voltage to the components in the circuit. To achieve this, fault-tolerant circuits, for example, sometimes employ a fault-tolerant structure implemented using stacked MOS transistors.

[0004] However, because the MOS transistors are stacked, there is a delay in the state transition of the output node. Additionally, there are cases where the output duty cycle is less than 50%.

[0005] Therefore, in level shift circuits with fault-tolerant structures, there is a problem that high-speed transmission is difficult. Summary of the Invention

[0006] The purpose of this invention is to provide a semiconductor integrated circuit that can perform high-speed transmission while maintaining fault tolerance.

[0007] The semiconductor integrated circuit of the embodiment includes: a first MOS transistor, whose gate is supplied with an input signal of a signal level corresponding to a voltage range of a first voltage and controls the conduction / non-conduction between a reference potential point and an intermediate node; a second MOS transistor, which is connected to the first MOS transistor via the intermediate node and stacked together with the first MOS transistor, whose gate is supplied with a bias voltage and applies a voltage below the withstand voltage of the first MOS transistor to the intermediate node; a third MOS transistor, which is supplied with a second voltage higher than the first voltage, whose gate is supplied with a signal of a level corresponding to the operation of the first MOS transistor, and outputs an output signal of a signal level corresponding to the voltage range of the second voltage; and a switching circuit that keeps the intermediate node at a fixed voltage when the first MOS transistor is turned off. Attached Figure Description

[0008] Figure 1 This is a circuit diagram illustrating the semiconductor integrated circuit according to the first embodiment of the present invention.

[0009] Figure 2 It means including Figure 1 A block diagram of a semiconductor integrated circuit memory system.

[0010] Figure 3 This is a circuit diagram illustrating a comparative example of the semiconductor integrated circuit in this embodiment.

[0011] Figure 4 This is a circuit diagram illustrating a comparative example of the semiconductor integrated circuit in this embodiment.

[0012] Figure 5 It is a timeline used to illustrate the topic.

[0013] Figure 6 It is a timeline used to illustrate the topic.

[0014] Figure 7 This is a timeline used to explain the actions of the implementation method.

[0015] Figure 8 This is a circuit diagram illustrating the second embodiment of the present invention. Detailed Implementation

[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

[0017] (First Implementation)

[0018] Figure 1 This is a circuit diagram illustrating the semiconductor integrated circuit according to the first embodiment of the present invention. Additionally, Figure 2 It means including Figure 1 A block diagram of a semiconductor integrated circuit memory system.

[0019] The semiconductor integrated circuit in this embodiment incorporates a fault-tolerant function implemented by stacked MOS transistors, and a level shifting circuit that improves the duty cycle by stabilizing the delay time of the output node by fixing the potential of the intermediate node connected to the terminals of the stacked MOS transistors using a switching circuit. Furthermore, the semiconductor integrated circuit in this embodiment further improves the duty cycle by combining differential outputs. Through the improvement of the duty cycle, the semiconductor integrated circuit in this embodiment enables high-speed signal transmission.

[0020] exist Figure 2In the memory system, host 1 and memory controller 2 are connected via a defined interface. For example, this interface can be a parallel interface of eMMC (embedded Multi Media Card), a serial expansion interface of PCIe (Peripheral Component Interconnect-Express), a high-speed serial interface of M-PHY, or other similar interfaces. Furthermore, both host 1 and memory controller 2 have built-in interface circuits that utilize these various interfaces.

[0021] The storage controller 2 and the NAND flash memory 4 are connected via the NAND interface (I / F) circuit 3. The NAND I / F circuit 3 uses various interfaces, such as high-speed data transfer modes like ToggleDDR and Open NAND Flash Components (ONFI), to transfer data between the storage controller 2 and the NAND flash memory 4.

[0022] Host 1 generates write and read requests to storage controller 2. Storage controller 2 controls the writing of data to NAND flash memory 4 and the reading of data from NAND flash memory 4 based on the requests from the host.

[0023] The storage controller 2 and the NAND flash memory 4 transmit various signals, including data signals DQ<7:0>, data strobe signals DQS and / DQS, chip enable signal CE, instruction latch enable signal CLE, address latch enable signal ALE, write enable signal / WE, read enable signal RE and / RE, and write protection signal WP, via the NAND I / F circuit 3.

[0024] The NAND flash memory circuit 3 includes a level shifting circuit 3a and an output buffer 3b. The level shifting circuit 3a shifts the voltage level of data supplied from the memory controller 2 and processed internally in the NAND flash memory circuit 3 to a high voltage, and then outputs the data to the memory controller 2 via the output buffer 3b. Similarly, the level shifting circuit 3a shifts the voltage level of data supplied from the NAND flash memory 4 and processed internally in the NAND flash memory circuit 3 to a high voltage, and then outputs the data to the memory controller 2 via the output buffer circuit 3b.

[0025] Furthermore, the level shifting circuit with the same configuration as the level shifting circuit 3a in this embodiment can be integrated not only into the NAND I / F circuit 3, but also into the host 1, the storage controller 2, and the NAND flash memory 4. Alternatively, the NAND I / F circuit 3 can be omitted, and an interface circuit with the same function as the NAND I / F circuit 3 can be integrated into the storage controller 2 and the NAND flash memory 4.

[0026] An example of applying this embodiment to an interface circuit (NAND interface circuit) between NAND flash memory and a memory controller, which is a non-volatile semiconductor memory device, will be described, but it can also be applied to various interface circuits.

[0027] (Topic)

[0028] Next, refer to Figures 3 to 6 This paper explains the difficulty in achieving high speed in fault-tolerant level shift circuits. Figure 3 as well as Figure 4 This is a circuit diagram illustrating a comparative example of the semiconductor integrated circuit in this embodiment. Figure 3 This refers to a level shift circuit that does not have a fault-tolerant design. Figure 4 This represents a level shift circuit with a fault-tolerant configuration. Specifically, in... Figure 1 , Figure 3 as well as Figure 4 In this drawing, the same reference numerals are assigned to the same constituent elements, and repeated descriptions of the same constituent elements are omitted.

[0029] Figure 3 The level shifting circuit consists of an input buffer 10 and a level shifter 40. The input buffer 10 has two inverters, INV1 and INV2, that generate differential outputs (signals Oa and Ob) based on the input differential input signals Ia and Ib. Inverter INV1 is composed of a PMOS transistor M1 and an NMOS transistor M2, and inverter INV2 is composed of a PMOS transistor M3 and an NMOS transistor M4. Input signal Ia is supplied to the gates of transistors M1 and M2, and input signal Ib is supplied to the gates of transistors M3 and M4.

[0030] For transistor M1, a power supply voltage VDDA is applied from the power supply line to its source, and its drain is connected to the drain of transistor M2. The source of transistor M2 is connected to a reference potential. For transistor M3, a power supply voltage VDDA is applied from the power supply line to its source, and its drain is connected to the drain of transistor M4. The source of transistor M4 is connected to a reference potential.

[0031] The input signal Ia is inverted by inverter INV1, and the inverted signal Oa appears at the junction of the drains of transistors M1 and M2 (hereinafter referred to as node A). Meanwhile, the input signal Ib, which is the inverted signal of input signal Ia, is inverted by inverter INV2. The inverted signal Ob, which is the inverted signal of signal Oa, appears at the junction of the drains of transistors M3 and M4 (hereinafter referred to as node B).

[0032] The input buffer 10 is configured to operate at a relatively low power supply voltage VDDA, and the transistors M1 to M4 are configured, for example, by a circuit composed of thin-film transistors with relatively low voltage tolerance (hereinafter referred to as LVMOS).

[0033] Level shifter 40 is a differential input, single output. Level shifter 40 takes signals Oa and Ob from input buffer 10 as differential inputs and outputs signal O from output terminal OUT (hereinafter also referred to as the OUT node). Level shifter 40 has a cross-coupled circuit composed of PMOS transistors M6 and M9, and NMOS transistors M29 and M30. Transistors M29 and M30 constitute a transmission circuit that transmits signals Oa and Ob to the cross-coupled circuit.

[0034] For transistor M6, a power supply voltage VDDB is supplied to its source from the power supply line, and its drain is connected to the gate of transistor M9. For transistor M9, a power supply voltage VDDB is supplied to its source from the power supply line, and its drain is connected to the gate of transistor M6. The drains of transistors M6 and M9 are connected to the drains of transistors M29 and M30, respectively. For transistor M29, its source is connected to a reference potential point, and its gate is supplied with a signal Ob. For transistor M30, its source is connected to a reference potential point, and its gate is supplied with a signal Oa.

[0035] When node B is at a high level (hereinafter referred to as H level) and node A is at a low level (hereinafter referred to as L level), transistor M29 is turned on and transistor M30 is turned off. In this case, the connection point between the drain of transistor M6 and the drain of transistor M29 (hereinafter referred to as node C) is at L level, transistor M9 is turned on, and the connection point between the drain of transistor M9 and the drain of transistor M30 (output terminal OUT) is at H level. Through the cross-coupling circuit based on transistors M6 and M9, transistor M6 is turned off, thus maintaining the L level at node C and the H level at output terminal OUT.

[0036] Conversely, when node A is at H level and node B is at L level, transistor M29 is off and transistor M30 is on. In this case, the output terminal OUT is at L level. Through the cross-coupling circuit based on transistors M6 and M9, node C is made at H level, transistor M9 is off, and the output terminal OUT remains at L level.

[0037] The level shifter 40 is configured to operate at a relatively high power supply voltage VDDB. Transistors M6, M9, M29, and M30 are constructed, for example, using a circuit composed of a thick-film transistor with a high voltage withstand capability (hereinafter referred to as HVMOS).

[0038] If an H-level input signal Ia is input to input buffer 10, an H-level signal is output from output terminal OUT; if an L-level input signal Ia is input to input buffer 10, an L-level signal is output from output terminal OUT. Input buffer 10 is supplied with power supply voltage VDDA, and level shifter 40 is supplied with power supply voltage VDDB. As a result, the signals Oa and Ob at nodes A and B, which vary within the range of 0 to VDDA, are level-shifted into an output signal O that varies within the range of 0 to VDDB and is then output.

[0039] Furthermore, transistors M29 and M30 in level shifter 40 are thick-film transistors with relatively high threshold voltages Vth. In contrast, the power supply voltage VDDA has been set to a lower voltage due to the trend towards lower power consumption in recent LSIs and other technologies. That is, the signal levels Oa and Ob at nodes A and B become lower. As a result, the levels of signals Oa and Ob sometimes do not exceed the threshold voltage Vth of transistors M29 and M30, which can cause malfunctions in the level shifting circuit.

[0040] In view of this, sometimes the following is adopted Figure 4 The circuit, Figure 4 The circuit uses thin-film transistors as the transistors that constitute the transmission circuit. Figure 4 The circuit will Figure 3 Transistors M29 and M30 were replaced with LVMOS transistors, which have lower threshold voltages, and used as transistors M19 and M20. Therefore, transistors M19 and M20 can reliably turn on and off according to changes in node B and node A.

[0041] However, simply replacing thick-film transistors M29 and M30 with thin-film transistors M19 and M20 would apply a relatively high voltage VDDB to transistors M19 and M20, raising concerns about characteristic changes and potential damage to transistors with lower voltage withstand capabilities. Therefore, in Figure 4 The level shifting circuit incorporates a fault-tolerant design that protects transistors M19 and M20. That is, Figure 4 The level shifting circuit uses LVMOS to form the transmission circuit 21, and the level shifter 31, which is composed of HVMOS, is equipped with a protection circuit based on thick film transistors M7 and M10.

[0042] An NMOS transistor M7 is positioned between the drain of transistor M6 (C node) and the drain of transistor M19 (hereinafter referred to as G node). Additionally, an NMOS transistor M10 is positioned between the drain of transistor M9 (output terminal OUT) and the drain of transistor M20 (hereinafter referred to as H node). Transistors M7 and M10 are thick-film transistors. Furthermore, the G node and H node will also be referred to as intermediate nodes below.

[0043] The drain of transistor M7 is connected to the drain of transistor M6, and its source is connected to the drain of transistor M19. A specified bias voltage VBIAS is applied to the gate of transistor M7. The drain of transistor M10 is connected to the drain of transistor M9, and its source is connected to the drain of transistor M20. A specified bias voltage VBIAS is applied to the gate of transistor M10. Transistors M7 and M10 are constructed from thick-film transistors to protect transistors M19 and M20.

[0044] When transistor M7 is turned on, the drain-source voltage Vds becomes a value corresponding to the bias voltage VBIAS. Therefore, by setting the bias voltage VBIAS appropriately, the source (G node) of transistor M7 can be kept below a specified voltage. Similarly, when transistor M10 is turned on, the drain-source voltage Vds becomes a value corresponding to the bias voltage VBIAS. Therefore, by setting the bias voltage VBIAS appropriately, the source (H node) of transistor M10 can be kept below a specified voltage. The bias voltage VBIAS is set appropriately such that the voltages at both the G and H nodes do not exceed the withstand voltages of transistors M19 and M20.

[0045] so, Figure 4 The level shifting circuit, through the transmission circuit 21 composed of thin-film transistors M19 and M20, can reliably transmit changes in the input signal to the level shifter 31, and through the protection circuit based on transistors M7 and M10, prevents the application of a voltage higher than the withstand voltage between the drain and source of thin-film transistors M19 and M20.

[0046] However, Figure 4 The problem is that level shifting circuits cannot transmit signals at high speed. Figure 5 as well as Figure 6 This is a timeline used to illustrate the topic. Figure 5 as well as Figure 6 This represents the input signals Ia, Ib, and the signals displayed at nodes A, B, C, G, H, and OUT.

[0047] Assuming that after the power supply voltages VDDA and VDDB are switched on, the input signal Ia is at low level (input signal Ib is at high level), signal Oa is at high level, and signal Ob is at low level. In this state, transistor M20 is turned on, and transistor M19 is turned off.

[0048] Because transistor M20 is turned on, node H becomes the value on the L level side. Specifically, in... Figure 5 as well as Figure 6 In this context, V1 represents the voltage V1 at node H, which becomes the L-level side due to the bias voltage VBIAS. On the other hand, since transistor M19 is off, node G becomes Hi-Z (high impedance). Here, Hi-Z means that the node's potential is variable and can take various positive and negative values. Figure 5 as well as Figure 6 The example shown illustrates a potential below VDDB / 2 for nodes G and H at Hi-Z.

[0049] Since the voltage V1 at node H is the low-level side when transistor M20 is on, the output terminal OUT is at the low level. Therefore, when transistor M6 is on, node C is at the high level. When transistor M9 is off, the output terminal OUT remains at the low level.

[0050] Next, let's assume the input signal Ia transitions from a low-level (L) state to a high-level (H) state (with input signal Ib at a low-level). Input signals Ia and Ib are inverted by inverters INV1 and INV2, respectively. At nodes A and B, signals Oa and Ob, representing the inverted signals of input signals Ia and Ib, are displayed, respectively. That is, node A transitions from a high-level (H) state to a low-level (L) state, and node B transitions from a low-level (L) state to a high-level (H) state. Consequently, transistor M19 switches from off to on, and transistor M20 switches from on to off.

[0051] A transistor M7, stacked together with transistor M19, is positioned between node C and transistor M19. Additionally, a transistor M10, stacked together with transistor M20, is positioned between the output terminal OUT and transistor M20. Therefore, the voltage levels of node C and the output terminal OUT transition after a predetermined delay from the switching on / off state of transistors M19 and M20. When transistor M19 turns on, node C transitions to the L level. Consequently, transistor M9 turns on, causing the output terminal OUT to transition to the H level. As a result, transistor M6 turns off, maintaining the L level at node C.

[0052] Next, let's assume the input signal Ia transitions from a high-level (H) state to a low-level (L) state (where input signal Ib is at a high-level) state. Input signals Ia and Ib are inverted by inverters INV1 and INV2, respectively. Node A transitions from a low-level (L) state to a high-level (H) state, and node B transitions from a high-level (H) state to a low-level (L) state. Consequently, transistor M19 switches from on to off, and transistor M20 switches from off to on.

[0053] The voltage levels at nodes C and OUT transition after a predetermined delay, starting from the switching of transistors M19 and M20 between their on and off states. Specifically, when transistor M20 is turned on, the output terminal OUT transitions to the low (L) level. Consequently, transistor M6 turns on, causing node C to transition to the high (H) level. As a result, transistor M9 is turned off, maintaining the low (L) level at the output terminal OUT.

[0054] Subsequently, the input signals Ia and Ib are similarly transferred between H and L levels, causing the output terminal OUT level to also transfer. In this case, especially by stacking transistors M19 and M20 to form transistors M7 and M10 respectively, a relatively large delay time is generated in the transfer between the C and OUT nodes. If this delay time is evenly generated in both the C and OUT nodes and in both the transfer from H level to L level (hereinafter referred to as falling transfer) and the transfer from L level to H level (hereinafter referred to as rising transfer), there is no particular problem. However, there is a problem that the G and H nodes become Hi-Z, and the uneven generation of delay time in falling and rising transfers hinders high-speed operation.

[0055] exist Figure 5 In order to clarify Figure 4 The topic of level shifting circuits is illustrated, focusing on the delay of signals involved in each component, specifically the Hi-Z delay caused by the impediment to high-speed operation; other delays are omitted from the illustration.

[0056] exist Figure 5 In the example, during the initial rising transition of the input signal Ia after power-on, node G transitions from Hi-Z to voltage V1 after a delay time ΔT1, starting from the rising transition of node B. Simultaneously, node H transitions from voltage V1 to Hi-Z after a delay time ΔT1, starting from the falling transition of node A. As described above, the transitions of nodes G and H cause transitions of nodes C and OUT, with node C at level L and the output terminal OUT at level H.

[0057] The delay time ΔT1 corresponds to the time between the Hi-Z level and the potential difference ΔV1 between the voltage and the voltage V1. Since the Hi-Z level is variable, the delay time ΔT1 changes whenever the input signals Ia and Ib change. As a result, the pulse width and duty cycle vary, and inter-symbol interference (ISI) increases.

[0058] Furthermore, for example, when the input signals Ia and Ib are clock signals, there are cases where Hi-Z converges to a specified value when the clock period, voltage, temperature, etc. are constant. Figure 5 This indicates that Hi-Z converges to a specified value. Although there are no particular problems after Hi-Z convergence, the duty cycle deviation increases during initial operations when Hi-Z is uncertain.

[0059] For example, in I / F, there are cases where DDR (Double Data Rate) is used. In DDR, data is sampled using the rising and falling edges of the clock. Therefore, when the delay time ΔT1 is not constant and the clock edge timing varies, and the duty cycle is not 50%, the effective sampling timing for reliably acquiring data becomes narrow. As a result, setup and hold times need to be increased, and it is difficult to shorten the clock cycle, making high-speed operation impossible.

[0060] Figure 6 To clarify Figure 4 The problem of level shifting circuits is addressed by illustrating the delays of the signals involved in each component, specifically the rise and fall shift delays that hinder high-speed operation. Other delays are omitted from the illustration.

[0061] The level shift circuit generates an output signal O corresponding to the input signals Ia and Ib by switching the transistors M19 and M20, which constitute the transmission circuit, on and off. Therefore, transistors M19 and M20, being thin-film transistors, are configured to have a relatively rapid transition to conduction. Consequently, for nodes C and OUT, the falling transition speed is relatively high, while the rising transition speed is slower than the falling transition.

[0062] The result is, as Figure 6 As shown, even if the input signals Ia and Ib are signals with a 50% duty cycle, the L level period is longer than the H level period for the signals displayed at the C and OUT nodes. That is, the duty cycle of the output signal O is not 50%.

[0063] Thus, since the performance of switching to conduction is improved by thinning the transistors M19 and M20 that constitute the transmission circuit, and the transistors M7 and M10 that constitute the protection circuit are stacked on the transistors M19 and M20 respectively for fault-tolerant construction, there is a problem that the period of the output signal is not constant, the duty cycle is not 50%, and it is difficult to achieve high-speed signal transmission.

[0064] (constitute)

[0065] Therefore, in this embodiment, a circuit is added to keep the intermediate nodes (G, H nodes) constant. This allows for the generation of an output signal O with a stable period and a duty cycle of approximately 50%. Furthermore, by utilizing the circuits at nodes C and D (… Figure 4 The output signal O is generated by using the signal displayed by the OUT node in the comparison example. Thus, an output signal O with a duty cycle of 50% can be reliably obtained.

[0066] right Figure 4 The level shifting circuit is constructed by adding transistors M5, M8, M11~M18, M21, and M22. Figure 1 The level shifting circuit. The transfer circuit 20 is constructed of LVMOS. The transfer circuit 20 and... Figure 4 The difference in the transmission circuit 21 is that transistors M21 and M22, which function as switching circuits, are added.

[0067] The drain of PMOS transistor M21, a thin-film transistor, is connected to the drains of transistors M19 and M7 at the intermediate node (G node). For transistor M21, a signal Ob is supplied to the gate from node B, and a power supply voltage VDDA is supplied to the source from the power supply line. Therefore, transistor M21 is off when transistor M19 is on and on when transistor M19 is off. When transistor M21 is on, the power supply voltage VDDA is supplied to node G via transistor M21, and node G becomes the voltage VDDA. Furthermore, since transistor M21 is off when transistor M19 is on, node G becomes the voltage V1 on the low-level side.

[0068] Furthermore, the drain of PMOS transistor M22, which is a thin-film transistor, is connected to the drain of transistors M20 and M10 at the intermediate node (H node). For transistor M22, a signal Oa is supplied to the gate from node A, and a power supply voltage VDDA is supplied to the source from the power supply line. Thus, transistor M22 is off when transistor M20 is on and on when transistor M20 is off. When transistor M22 is on, the power supply voltage VDDA is supplied to node H via transistor M22, and node H becomes the voltage VDDA. In addition, since transistor M22 is off when transistor M20 is on, node H becomes the voltage V1 on the L-level side.

[0069] Thus, in this embodiment, the intermediate node transitions between a fixed voltage VDDA and a voltage V1, and the delay time required for this transition remains constant regardless of changes in the input signals Ia and Ib. Therefore, at nodes C and D, signals synchronized with the input signals Ia and Ib can be obtained from the initial operation immediately after power-on. When the duty cycle of the input signals Ia and Ib is 50%, the duty cycle of the signals displayed at nodes C and D is also 50%.

[0070] In addition, Figure 1 The example shown illustrates applying a power supply voltage VDDA to the gates of transistors M21 and M22, but an appropriate voltage below the withstand voltage of transistors M19 and M20, such as a voltage below VDDA, can also be applied.

[0071] The level shifter 30 is constructed from thick-film transistors. In the level shifter 30, the drain (C node) of transistor M6 is also connected to the gates of PMOS transistor M11 and NMOS transistor M12. Transistors M11 and M12 form an inverter. That is, for transistor M11, a power supply voltage VDDB is applied from the power supply line to its source, and its drain is connected to the drain of transistor M12. The source of transistor M12 is connected to a reference potential. The connection point between the drains of transistors M11 and M12 (hereinafter referred to as the E node) displays the inverted signal of the signal displayed at the C node.

[0072] In this embodiment, to reliably maintain a 50% duty cycle regardless of the time difference between the rise and fall transitions, the signal appearing at node E and the signal appearing at node D are combined. Transistors M13 and M14 are used for this combination. For transistor M13, a power supply voltage VDDB is supplied from the power line to its source, the gate is input with the signal appearing at node E, and its drain is connected to the drain of transistor M14. The source of transistor M14 is connected to a reference potential point, and its gate is input with the signal appearing at node D.

[0073] For transistor M13, by making the signal displayed at node E level low (L), the connection point between the drains of transistor M13 and M14 (hereinafter referred to as node F) shifts to high (H). Conversely, for transistor M14, by making the signal displayed at node D level high (H), node F shifts to low (L). The signal displayed at node E is the inverse of the signal displayed at node C. Therefore, the signal displayed at node F shifts to high (H) if node C is high (H) and to low (L) if node D is high (H).

[0074] It can be assumed that the delay time required for the rising transition of node C when transistor M19 is turned off is the same as the delay time required for the rising transition of node D when transistor M20 is turned off. Therefore, the delay time for the signal appearing at node F to transition to level H due to the turn-off of transistor M19 is the same as the delay time for transitioning to level L due to the turn-off of transistor M20. Therefore, when transistors M19 and M20 are turned on and off based on input signals Ia and Ib with a duty cycle of 50%, the signal appearing at node F becomes a signal with a duty cycle of 50% where the period from rising to falling and the period from falling to rising are the same.

[0075] Furthermore, for transistors M13 and M14, there are sometimes periods when they are simultaneously turned off due to temperature, process, or voltage deviations. Therefore, if the output of node F is used directly as the output signal O, there is a possibility that node F becomes unpredictable and a through current flows during the periods when transistors M13 and M14 are simultaneously turned off. In view of this, in this embodiment, a latching circuit is connected to node F.

[0076] exist Figure 1 In the example, the latch circuit is composed of inverters based on transistors M15 and M16, and inverters based on transistors M17 and M18. For PMOS transistor M15, a power supply voltage VDDB is applied from the power supply line to its source, the gate is supplied with the signal of node F, and its drain is connected to the drain of NMOS transistor M16. For transistor M16, its source is connected to the reference potential point, and its gate is supplied with the signal of node F. The inverted signal of node F is displayed at the junction of the drains of transistors M15 and M16 (output terminal OUT). This signal becomes the output signal O.

[0077] The connection point between the drains of transistors M15 and M16, the output terminal OUT, and the gates of transistors M17 and M18 are connected. The gates of transistors M17 and M18 are supplied with the inverted signal of the signal at node F. For PMOS transistor M17, a power supply voltage VDDB is applied from the power supply line to its source, and its drain is connected to the drain of NMOS transistor M18. For transistor M18, its source is connected to a reference potential. The connection point between the drains of transistors M17 and M18 displays the inverted signal of output signal O. The connection point between the drains of transistors M17 and M18 is connected to node F, and node F is supplied with the inverted signal of output signal O. The signal at node F is inverted by a latching circuit based on transistors M15 to M18 and output as output signal O from the output terminal OUT.

[0078] Furthermore, if the rise delay time ΔT2 is too large, it can sometimes cause the pulse width of the signal appearing at node D to be too narrow and disappear. Therefore, in this embodiment, transistors M5 and M8 are provided to suppress the rise transition delay time. For PMOS transistor M5, a power supply voltage VDDB is supplied from the power supply line to its source, a signal Ob is applied to its gate, and its drain is connected to the source of transistor M6. For PMOS transistor M8, a power supply voltage VDDB is supplied from the power supply line to its source, a signal Oa is applied to its gate, and its drain is connected to the source of transistor M9.

[0079] If signal Ob is at level L, transistor M5 is turned on; if signal Oa is at level L, transistor M8 is turned on. By turning on transistor M5, the transition time from level L to level H at node C can be shortened. Furthermore, by turning on transistor M8, the transition time from level L to level H at node D can be shortened. Therefore, in nodes C and D, excessively narrow widths during the level H period can be prevented.

[0080] (action)

[0081] Next, refer to Figure 7 The operation of this implementation method will be explained. Figure 7 This is a timeline used to explain the actions of the implementation method. Figure 7 This represents the input signals Ia and Ib, and the signals that appear at nodes A, B, C, G, H, and OUT. Furthermore, for simplicity, an example is shown where the input signals Ia and Ib are periodic signals; however, various signals can be used as input signals Ia and Ib.

[0082] Assume that after the power supply voltages VDDA and VDDB are turned on, the input signal Ia is at low level (input signal Ib is at high level), signal Oa is at high level, and signal Ob is at low level. In this state, transistor M20 is turned on, and transistor M19 is turned off. Because transistor M20 is turned on, node H becomes the voltage V1 on the low level side.

[0083] Since node H becomes voltage V1 on the low-level side when transistor M20 is on, node D is at the low-level. Therefore, because transistor M6 is on, transistor M5 is also on, so node C is at the high-level. When transistor M9 is off, node D remains at the low-level.

[0084] In this embodiment, transistor M21 is turned on when transistor M19 is turned off. Therefore, in this case, node G becomes a fixed voltage VDDA.

[0085] Next, let's assume the transition from a state where input signal Ia is at level L to a state where input signal Ia is at level H (input signal Ib is at level L). Input signals Ia and Ib are inverted by inverters INV1 and INV2, respectively. Signals Oa and Ob, which are the inverted signals of input signals Ia and Ib, are displayed at nodes A and B, respectively. That is, node A transitions from level H to level L, and node B transitions from level L to level H. Consequently, transistor M19 switches from off to on, and transistor M20 switches from on to off.

[0086] Furthermore, transistor M21 switches from on to off, and transistor M22 switches from off to on. Therefore, node G changes from a fixed voltage VDDA to a fixed voltage V1. Similarly, node H changes from a fixed voltage V1 to a fixed voltage VDDA. Subsequently, whenever the input signals Ia and Ib invert, nodes G and H change from voltage V1 to voltage VDDA, or vice versa. Therefore, the delay time from the inversion of input signals Ia and Ib until the inversion of nodes C and D is always constant. Therefore, even when transistors M19 and M20 are stacked to form transistors M7 and M10 constituting a protection circuit, the duty cycle of the output signal O will not change due to the influence of transistors M7 and M10.

[0087] Therefore, the level shifting circuit involved in this embodiment can achieve high-speed transmission. However, in Figure 1 In a level shift circuit, the delay time during the fall transition is different from the delay time during the rise transition, which can be considered to affect the duty cycle to some extent.

[0088] Figure 7 This indicates the time delay involved in the impact. For example... Figure 7 As shown, the down-transition delays of node C due to the conduction of transistor M19 and node D due to the conduction of transistor M20 are relatively short. Conversely, the up-transition delays of node C due to the cutoff of transistor M19 and node D due to the cutoff of transistor M20 are relatively long. Figure 7 The diagram illustrates the case where the difference in these delay times is ΔT². The result is as follows: Figure 7 As shown, the L-level period of nodes C and D is 2ΔT2 longer than the H-level period.

[0089] That is, the rise of node D is delayed by ΔT2 compared to the fall of node C, and the rise of node C is delayed by ΔT2 compared to the fall of node D. Therefore, the period from the rise of node D to the rise of node C is the same as the period from the rise of node C to the rise of node D, which is half the period of the input signals Ia and Ib.

[0090] The inverters based on transistors M11 and M12 invert the signal at node C. Thus, the inverted signal from node C is displayed at node E. Therefore, the period from the rise of node D to the fall of node E is the same as the period from the fall of node E to the rise of node D, which is half the period of the input signals Ia and Ib.

[0091] Transistor M13 turns on with a falling turn at node E, making node F a high level (H). Conversely, transistor M14 turns on with a rising turn at node D, making node F a low level (L). The result is as follows: Figure 7 As shown, at node F, a signal with a duty cycle of 50% is displayed with the same period as the input signals Ia and Ib.

[0092] The signal at node F is inverted by an inverter based on transistors M15 and M16. The inverted signal at node F is then inverted by an inverter based on transistors M17 and M18 and supplied to node F. After being inverted by the latching circuit composed of transistors M15 and M18, the signal at node F is output as output signal O from the output terminal OUT. Output signal O is a signal that changes from 0V to VDDB.

[0093] like Figure 7 As shown, the output signal O is a signal with the same period as the input signals Ia and Ib and a duty cycle of 50%.

[0094] Thus, in this embodiment, a level shifting circuit is obtained that stabilizes the output node delay time and improves the duty cycle even when fault tolerance is provided by stacked MOS transistors, by fixing the potential of the intermediate node using a switching circuit. Furthermore, in this embodiment, a level shifting circuit is obtained that further improves the duty cycle by synthesizing differential outputs. Through the improvement of the duty cycle, the semiconductor integrated circuit in this embodiment can achieve high-speed signal transmission.

[0095] (Second Implementation)

[0096] Figure 8 This is a circuit diagram illustrating the second embodiment of the present invention. Figure 8 China and Figure 1 The same constituent elements are given the same reference numerals and their descriptions are omitted.

[0097] exist Figure 4 In the comparative example, the bias voltage VBIAS was set such that no voltage exceeding the withstand voltage of transistors M19 and M20 was applied to nodes G and H. In this embodiment, the setting of the bias voltage VBIAS can be automated so that the voltages of nodes G and H are the desired voltages.

[0098] Figure 8The level shifting circuit and Figure 4 The difference in the level shifting circuit is that transistors M92, M102, M202 and comparator 38 are added, and the output of comparator 38 is applied to the gates of transistors M7 and M10.

[0099] For PMOS transistor M92, a power supply voltage VDDB is supplied from the power supply line to its source, an enable signal ENB is applied to its gate, and its drain is connected to the drain of NMOS transistor M102. For transistor M102, the gate is supplied with the output of comparator 38, and its source is connected to the drain of NMOS transistor M202. For transistor M202, an enable signal EN is applied to its gate, and its source is connected to the reference potential.

[0100] Transistors M92, M102, and M202 have the same configuration as transistors M6, M7, and M19, and also the same configuration as transistors M9, M10, and M20. The enable signals ENB and EN are signals with opposite polarities. Therefore, transistors M202 and M92 are simultaneously turned on and simultaneously turned off.

[0101] The junction of the source of transistor M102 and the drain of transistor M202 (hereinafter referred to as node H2) is connected to the negative input of comparator 38. A voltage VBIAS2 is applied to the positive input of comparator 38. Voltage VBIAS2 is set to a voltage not exceeding the withstand voltage of transistors M19, M20, and M202, for example, a voltage below voltage VDDA. Comparator 38 compares the two inputs and applies an output voltage level corresponding to the comparison result to the gates of transistors M7, M10, and M102. Comparator 38 changes the output voltage to make the voltage at node H2 match voltage VBIAS2.

[0102] In this configuration, the setting operation of the bias voltage applied to the gates of transistors M7 and M10 is related to... Figure 4 The comparison example differs. After power is switched on, transistors M202 and M92 are turned on via enable signals EN and ENB. The voltage at node H2 is applied to the negative input of comparator 38. Comparator 38 compares node H2 with the voltage VBIAS2 supplied to the positive input, applying a voltage corresponding to the differential to the gate of transistor M102. As a result, comparator 38 operates in a manner that makes the voltage at node H2 match the voltage VBIAS2.

[0103] That is, when the voltage at node H2 is lower than voltage VBIAS2, the output level of comparator 38 becomes higher, the drain-source voltage Vds of transistor M102 decreases, and the voltage at node H2 increases. Conversely, if the voltage at node H2 becomes higher than voltage VBIAS2, the output level of comparator 38 becomes lower, the drain-source voltage Vds of transistor M102 increases, and the voltage at node H2 decreases. As a result, the voltage at node H2 matches the voltage VBIAS2.

[0104] Transistors M92, M102, and M202 have the same configuration as transistors M6, M7, and M19, and also the same configuration as transistors M9, M10, and M20. For transistors M7 and M10, the gate is supplied with a voltage from comparator 38. Therefore, the voltages at the G and H nodes of transistors M19 and M20 when they are turned on are consistent with voltage VBIAS2. By setting voltage VBIAS2 to a value not exceeding the withstand voltage of transistors M19 and M20, the appropriate bias voltage for transistors M7 and M10 can be automatically determined.

[0105] Thus, in this embodiment, the optimal bias voltage of the MOS transistor constituting the protection circuit can be automatically determined.

[0106] Furthermore, this embodiment describes a circuit that does not take countermeasures for the intermediate node becoming Hi-Z and the variation in duty cycle caused by the difference in delay time in the rise and fall transitions. However, countermeasures can also be taken for this point in the same way as in the first embodiment. For example, it is also possible to... Figure 1 The circuit is supplemented with transistors M92, M102, M202 and comparator 38 of this embodiment to determine the bias voltage of transistors M7 and M10.

[0107] Furthermore, the present invention is not limited to the embodiments described above, and various modifications can be made during the implementation phase without departing from its spirit. Additionally, the above embodiments include inventions at various stages, and various inventions can be extracted through appropriate combinations of the disclosed constituent elements. For example, if even if several constituent elements are deleted from all the constituent elements shown in the embodiments, the problem described in the "Problem to be Solved by the Invention" column can be solved, and the effects described in the "Invention Effects" column can be obtained, then the configuration with those constituent elements deleted can be extracted as an invention.

[0108] Explanation of reference numerals in the attached figures:

[0109] 10…Input buffer, 20…Pass circuit, 30…Level shifter, 38…Comparator, INV1, INV2…Inverter, M1~M22…Transistor.

Claims

1. A semiconductor integrated circuit, characterized in that, have: The first MOS transistor has its gate supplied with an input signal of a signal level corresponding to the voltage range of the first voltage, which controls the conduction and non-conduction between the reference potential point and the first intermediate node. The second MOS transistor forms a differential pair with the first MOS transistor. Its gate is given an inverted signal of the input signal to control the conduction and non-conduction between the reference potential point and the second intermediate node. The third MOS transistor is connected to the first MOS transistor via the first intermediate node and forms a stack together with the first MOS transistor. The gate is supplied with a bias voltage, and a voltage below the breakdown voltage of the first MOS transistor is applied to the first intermediate node. The fourth MOS transistor is connected to the second MOS transistor via the second intermediate node and forms a stack together with the second MOS transistor. The gate is supplied with a bias voltage, and a voltage below the breakdown voltage of the second MOS transistor is applied to the second intermediate node. The fifth MOS transistor is supplied with a second voltage corresponding to a third voltage that is higher than the first voltage, and its gate is given a signal at a level corresponding to the operation of the first MOS transistor, and outputs an output signal at a signal level corresponding to the voltage range of the third voltage. The sixth MOS transistor is supplied with a fourth voltage corresponding to the third voltage, and together with the fifth MOS transistor, forms a cross-coupled circuit. Its gate is given a signal at a level corresponding to the operation of the second MOS transistor, and it outputs an output signal at a signal level corresponding to the voltage range of the third voltage. The first switching circuit sets a fixed voltage at the first intermediate node when the first MOS transistor is turned off. The second switching circuit sets a fixed voltage at the second intermediate node when the second MOS transistor is turned off. as well as The first circuit combines the signal obtained by inverting one of the output signals of the fifth and sixth MOS transistors constituting the cross-coupled circuit with the signal of the other transistor and outputs the result. The first circuit generates a signal whose edge timing logic level changes when one of the output signals is inverted and the other of the output signals is inverted.

2. The semiconductor integrated circuit according to claim 1, characterized in that, The first circuit includes a latching circuit that latches and outputs signals whose logic levels change.

3. The semiconductor integrated circuit according to claim 1, characterized in that, The first switching circuit is composed of a seventh MOS transistor, whose gate is supplied with the input signal, and a fixed voltage below the withstand voltage of the first MOS transistor supplied with the first terminal is supplied from the second terminal to the first intermediate node. The second switching circuit is composed of an eighth MOS transistor, whose gate is given the inversion signal, and a fixed voltage below the withstand voltage of the second MOS transistor given the first terminal is supplied from the second terminal to the second intermediate node.

4. The semiconductor integrated circuit according to claim 1, characterized in that, It also has: The seventh MOS transistor, whose gate is supplied with the input signal to turn on or off, controls the supply or de-supply of the third voltage to the sixth MOS transistor; and The eighth MOS transistor has its gate given the inverting signal to turn on or off, and controls the supply or cessation of the third voltage to the fifth MOS transistor.

5. The semiconductor integrated circuit according to claim 1, characterized in that, The first circuit includes: The seventh MOS transistor of the first conductivity type has its gate supplied with an input of the inverted signal of the output signal from the sixth MOS transistor, and has a first terminal to which the third voltage is applied, and a second terminal connected to the third intermediate node. as well as The eighth MOS transistor of the second conductivity type has its gate supplied with the input of the output signal from the fifth MOS transistor, and has a first terminal connected to the third intermediate node and a second terminal connected to the reference potential point.

6. The semiconductor integrated circuit according to claim 2, characterized in that, The first circuit includes: The seventh MOS transistor of the first conductivity type has its gate supplied with an input of the inverted signal of the output signal from the sixth MOS transistor, and has a first terminal to which the third voltage is applied, and a second terminal connected to the third intermediate node. as well as The eighth MOS transistor of the second conductivity type has its gate supplied with the input of the output signal from the fifth MOS transistor, and has a first terminal connected to the third intermediate node and a second terminal connected to the reference potential point. The latch circuit includes: The ninth MOS transistor has a gate connected to the third intermediate node, a first terminal to which the third voltage is applied, and a second terminal connected to the output terminal; The tenth MOS transistor has a gate connected to the third intermediate node, a first terminal connected to the output terminal, and a second terminal connected to the reference potential point; The eleventh MOS transistor has a gate connected to the output terminal, a first terminal to which the third voltage is applied, and a second terminal connected to the third intermediate node; as well as The twelfth MOS transistor has a gate connected to the output terminal, a first terminal connected to the third intermediate node, and a second terminal connected to the reference potential point.

7. A semiconductor integrated circuit, characterized in that, have: The first MOS transistor has its gate supplied with an input signal of a signal level corresponding to the voltage range of the first voltage, which controls the conduction and non-conduction between the reference potential point and the intermediate node. The second MOS transistor is connected to the first MOS transistor via the intermediate node and forms a stack together with the first MOS transistor. The gate is supplied with a bias voltage, and a voltage below the breakdown voltage of the first MOS transistor is applied to the intermediate node. The third MOS transistor is supplied with a second voltage that is higher than the first voltage, and its gate is given a signal at a level corresponding to the operation of the first MOS transistor, and it outputs an output signal at a level corresponding to the voltage range of the second voltage. The signal path is formed by a fourth MOS transistor, a fifth MOS transistor, and a sixth MOS transistor connected in series between the power supply line supplying the second voltage and the reference potential point; as well as The comparator circuit compares the voltage at the junction of the fifth MOS transistor and the sixth MOS transistor with a reference voltage and supplies voltages based on the comparison result to the gates of the second MOS transistor and the fifth MOS transistor.

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