Cxl memory module, data checking method, controller chip and system

Abstract

The present disclosure relates to the field of computers, and discloses a CXL memory module, a data verification method, a decoder, a controller chip and a system. The CXL memory module comprises a memory chip and a controller chip connected with the memory chip. The controller chip is configured to read first data from the memory chip, calculate an adjoint based on the first data to obtain a first adjoint, correct errors of the first data based on the first adjoint to obtain second data, calculate an adjoint based on the second data to obtain a second adjoint, and verify the second data based on the second adjoint.

Description

Technical Field

[0001] This disclosure relates to the field of computers, specifically to a CXL memory module, a data verification method, a controller chip, and a system. Background Technology

[0002] With the rapid development of computers, satellite communications, and high-speed data transmission, data exchange, processing, and storage technologies have been widely applied. In the fields of communication and computer memory, increasingly higher demands are being placed on the reliability of data transmission and storage systems. BCH codes are widely used in digital communication and storage systems to improve data transmission reliability. Their powerful error correction capabilities and coding efficiency make them an important tool for improving the reliability and performance of communication systems. For example, in various types of memory, BCH codes can be used to correct bit errors in read operations, improve the reliability of data reads, and extend the lifespan of flash memory.

[0003] BCH code is an important encoding method used to correct bit errors that occur during data reading, thereby improving the reliability of the read data. It can detect and correct one or more errors and has advantages such as simple encoding and decoding, compact system structure, and low complexity.

[0004] CXL (Compute Express Link) is a new memory interface protocol based on the PCIe physical layer. The CXL protocol allows for memory expansion in computers using CXL memory modules; using CXL memory modules can increase memory bandwidth and improve overall system performance. BCH codes are also used in CXL memory modules; however, due to limitations in error correction capabilities, there is still room for improvement in data verification within CXL memory modules. Summary of the Invention

[0005] In view of this, the present disclosure provides a CXL memory module, a data verification method, a controller chip, and a system that can promptly detect unsuccessful error correction and avoid outputting erroneous data due to data errors exceeding the error correction capability of the BCH code.

[0006] The technical solution of this disclosure embodiment is implemented as follows:

[0007] This disclosure provides a CXL memory module, including: a memory chip and a controller chip connected to the memory chip; the controller chip is configured to read first data from the memory chip; calculate a first syndrome based on the first data; correct errors in the first data based on the first syndrome to obtain second data; calculate a second syndrome based on the second data to obtain a second syndrome; and verify the second data based on the second syndrome.

[0008] In some embodiments of this disclosure, the controller chip is further configured to multiply the vectorized first data or the second data with the transpose of a preset parity-check matrix to obtain the first or the second syntactic expression.

[0009] In some embodiments of this disclosure, the controller chip is further configured to output the second data as correct data in response to the second syndrome being zero; or to determine the first data as an uncorrectable error state in response to the second syndrome being non-zero.

[0010] In some embodiments of this disclosure, the controller chip is further configured to correct the first data in response to the first symptom being non-zero, thereby obtaining the second data.

[0011] In some embodiments of this disclosure, the controller chip is further configured to output the first data as correct data in response to the first symptom being zero.

[0012] In some embodiments of this disclosure, the controller chip is further configured to calculate an error location polynomial based on the first syntactic polynomial; determine the error location based on the error location polynomial; and correct the value of the error location in the first data to obtain the second data.

[0013] In some embodiments of this disclosure, the controller chip is further configured to compute an error pattern based on each component of the first syntactic; and to compute the error location polynomial based on the error pattern.

[0014] In some embodiments of this disclosure, the controller chip is further configured to find a solution to the error location polynomial using a search algorithm; and to determine the error location based on the exponent in the solution of the error location polynomial.

[0015] In some embodiments of this disclosure, the controller chip is further configured to invert the value of the error location in the first data to obtain the second data.

[0016] In some embodiments of this disclosure, the controller chip is further configured to acquire initial data; encode a check bit based on the initial data to obtain the first data; and write the first data into the memory chip.

[0017] This disclosure provides a data verification method, the data verification method including: reading first data;

[0018] The first companion equation is obtained by calculating the first companion equation based on the first data; the first data is corrected based on the first companion equation to obtain the second data; the second companion equation is obtained by calculating the second companion equation based on the second data; and the second data is verified based on the second companion equation.

[0019] In some embodiments of this disclosure, the calculation of the syndrome is performed by a check matrix module.

[0020] In some embodiments of this disclosure, the step of calculating the adjoint includes multiplying the vectorized first data or the second data by the transpose of a preset parity matrix.

[0021] In some embodiments of this disclosure, verifying the second data based on the second syndrome includes: outputting the second data as correct data in response to the second syndrome being zero; or, determining the first data as an uncorrectable error state in response to the second syndrome being non-zero.

[0022] In some embodiments of this disclosure, correcting the first data based on the first syndrome to obtain the second data includes: correcting the first data in response to the first syndrome being non-zero to obtain the second data.

[0023] In some embodiments of this disclosure, after calculating the first syndrome based on the first data and obtaining the first syndrome, the data verification method further includes: in response to the first syndrome being zero, outputting the first data as correct data.

[0024] In some embodiments of this disclosure, correcting the first data to obtain the second data includes: calculating an error position polynomial based on the first syntactic expression; determining the error position based on the error position polynomial; and correcting the value of the error position in the first data to obtain the second data.

[0025] In some embodiments of this disclosure, calculating the error location polynomial based on the first syndrome includes: calculating an error pattern based on each component of the first syndrome; and calculating the error location polynomial based on the error pattern.

[0026] In some embodiments of this disclosure, determining the error location based on the error location polynomial includes: finding a solution to the error location polynomial using a search algorithm; and determining the error location based on the exponent in the solution of the error location polynomial.

[0027] In some embodiments of this disclosure, correcting the error position in the first data includes: inverting the value of the error position in the first data.

[0028] In some embodiments of this disclosure, the data verification method further includes: acquiring initial data; parsing the initial data to obtain parsed data, encoding it, and obtaining a check bit, wherein the parsed data and the check bit serve as the first data.

[0029] This disclosure also provides a controller chip for a CXL memory module, the controller chip comprising: a data verification module; the data verification module comprising: an encoder and a decoder; the decoder comprising: a check matrix module and an error correction module; wherein, the check matrix module is configured to read first data; and calculate a syndrome based on the first data to obtain a first syndrome; the error correction module is configured to correct errors in the first data based on the first syndrome to obtain second data; the check matrix module is further configured to calculate a syndrome based on the second data to obtain a second syndrome; and verify the second data based on the second syndrome.

[0030] In some embodiments of this disclosure, the error correction module includes: a key equation solving module, a search module, and a modulo 2 calculation module; the key equation solving module is configured to calculate the error location polynomial based on the first adjoint; the search module is configured to find the error location based on the error location polynomial; and the modulo 2 calculation module is configured to correct the value of the error location in the first data to obtain the second data.

[0031] This disclosure also provides a computer system, characterized in that it includes a host and the CXL memory module described above, wherein the host communicates with the CXL memory module through a CXL interface to realize the discovery, configuration and data transmission of the CXL memory module.

[0032] It is understood that in the BCH decoding process of this embodiment, after correcting the first data, the second data obtained after error correction is subjected to a second verification to verify whether the second data is correct. In this way, unsuccessful error correction can be detected in a timely manner, avoiding output error data caused by data errors exceeding the error correction capability range of the BCH code. Attached Figure Description

[0033] Figure 1 Schematic diagram of the implementation process of the data verification method provided in the embodiments of this disclosure Figure 1 ;

[0034] Figure 2Schematic diagram of the implementation process of the data verification method provided in the embodiments of this disclosure Figure 2 ;

[0035] Figure 3 Schematic diagram of the implementation process of the data verification method provided in the embodiments of this disclosure Figure 3 ;

[0036] Figure 4 Schematic diagram of the implementation process of the data verification method provided in the embodiments of this disclosure Figure 4 ;

[0037] Figure 5 Schematic diagram of the implementation process of the data verification method provided in the embodiments of this disclosure Figure 5 ;

[0038] Figure 6 Schematic diagram of the implementation process of the data verification method provided in the embodiments of this disclosure Figure 6 ;

[0039] Figure 7 Schematic diagram of the implementation process of the data verification method provided in the embodiments of this disclosure Figure 7 ;

[0040] Figure 8 Schematic diagram of the implementation process of the data verification method provided in the embodiments of this disclosure Figure 8 ;

[0041] Figure 9 This is a schematic diagram of the CXL memory module structure provided in an embodiment of this disclosure;

[0042] Figure 10 A schematic diagram of the structure of a computer system provided in an embodiment of this disclosure;

[0043] Figure 11 Schematic diagram of the decoder provided in the embodiments of this disclosure Figure 1 ;

[0044] Figure 12 Schematic diagram of the decoder provided in the embodiments of this disclosure Figure 2 . Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this disclosure clearer, the technical solutions of this disclosure are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this disclosure. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0046] In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. The terms "first / second / third" are used merely to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in orders other than those illustrated or described herein.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. The terminology used herein is for descriptive purposes only and is not intended to limit the scope of this disclosure.

[0048] Figure 1 This is a schematic diagram of an optional implementation flow of the data verification method provided in the embodiments of this disclosure, such as... Figure 1 As shown, the method includes steps S101 to S105.

[0049] S101, Read the first data.

[0050] In this embodiment of the disclosure, the first step in BCH decoding is to receive the first data to be decoded. This first data includes data bits and a parity bit. The parity bit is obtained by BCH encoding based on the data bits and is used to check and correct errors in the data bits.

[0051] In this embodiment of the disclosure, the length of the first data is the sum of the lengths of the data bits and the parity bits; for example, if the data bits are 8 bits and the parity bits are 3 bits, then the length of the first data is 11 bits.

[0052] In some embodiments of this disclosure, the check bit in the first data may be an ECC code (Error Correcting Code).

[0053] S102. Calculate the syndrome based on the first data to obtain the first syndrome.

[0054] In this embodiment of the disclosure, the first data can be received as a vector. For example, the vector of the first data is r = (r0, r1, ..., r...). n-1 ), where each element in the vector is the value of each bit in the first data, and n is the length of the first data.

[0055] In this embodiment of the disclosure, the parity check matrix module of the BCH decoder pre-stores a parity check matrix H, which can be simplified as follows:

[0056]

[0057] Where t represents the error correction capability of the parity check matrix H, that is, it can correct t erroneous positions in the first data; n represents the bit length of the first data; and a represents the root of the polynomial.

[0058] In this embodiment of the disclosure, for decoding a primitive BCH code with error correction capability t, the syndrome is a 2t-dimensional vector. The first syndrome S can be obtained from the following equation (2):

[0059] S = (S1,S2,...,S) 2t )=r·H T (2);

[0060] In other words, the parity matrix H shown in equation (1) above, after being transposed, can be multiplied by the vector r of the first data to obtain the first adjoint equation S.

[0061] S103. Based on the first syntactic expression, the first data is corrected to obtain the second data.

[0062] In this embodiment of the disclosure, if the first syndrome S is not zero, it indicates that there is an error in the first data, and the first data can be corrected.

[0063] From equation (2) above, it can be seen that for 1≤i≤2t, the i-th component S of the first adjoint equation S i for:

[0064] S i =r(a i )=r0+r1a i +r2a 2i +…+r n-1 a (n-1)i (3).

[0065] It should be noted that if h represents the correct part of the first data and e represents the incorrect part of the first data, then the binomial r(X) of the first data satisfies:

[0066] r(X) = r0 + r1X + r2X 2 +…+r n-1 X n-1 =h(X)+e(X) (4).

[0067] Furthermore, in the first adjoint S, the correct part of the first data is zero after calculation. Therefore, from equations (3) and (4) above, we can obtain the following relationship between the first adjoint S and the erroneous pattern for 1≤i≤2t:

[0068] S i =r(a i)=h(a i )+e(a i ) = e(a i (5);

[0069] In other words, the first companion S depends only on the error pattern e(X).

[0070] Furthermore, the error location polynomial can be computed based on the error pattern e(X). Assume the error pattern e(X) has v errors, with error locations j1, j2, ..., j... v Then we have:

[0071]

[0072] In equation (6) above, 0≤j1≤j2≤…≤j v Since ≤n, we can obtain the following system of equations:

[0073]

[0074] By iterating using Peterson's algorithm, we can obtain:

[0075]

[0076] Therefore, we can obtain:

[0077]

[0078] It should be noted that in the iterative algorithm for solving the polynomial σ(X) at the error location, the solution of the (2μ-1)th iteration... It is also the solution of the 2μth iteration. Right now In other words, the (2μ-1)th iteration and the 2μth iteration can be combined. Therefore, based on equations (8) and (9) above, the iterative algorithm for finding σ(X) can be simplified to:

[0079]

[0080] Let v be the number of errors and t be the error correction capability. The error location polynomial σ(X) can be obtained as follows:

[0081] σ(X)=σ0+σ1X+σ2X 2 +…+σ v X v (11).

[0082] After obtaining the polynomial σ(X) at the error position, the coefficients σ of each term are calculated. i Using the Chien search algorithm, the solution to the polynomial σ(X) at the error location can be obtained:

[0083] σ(X)=(a i X+1)(a j X+1)…(a k X+1) (12);

[0084] Furthermore, based on the exponent of prime element a in equation (12), the error position in the received first data can be obtained.

[0085] In some embodiments of this disclosure, for binary BCH code, the position of the exponent of the polynomial factor can be directly located based on the error position, thereby correcting the vector of the first data. Inverting the values ​​at the error positions in the first data completes the error correction, yielding the second data.

[0086] S104. Calculate the second syndrome based on the second data to obtain the second syndrome.

[0087] In this embodiment of the disclosure, the second data obtained after error correction can be vectorized as r′=(r0′,r1′,...,r n ′ -1 The vectorized second data r′ can be multiplied by the transpose of the parity-check matrix H to obtain the second adjoint S′:

[0088] S′=(S1′,S2′,...,S2′ t )=r′·H T (13);

[0089] The second adjoint S′ can be calculated using the parity check matrix H shown in equation (1) above; that is, the same parity check matrix can be used in the process of calculating the first adjoint and the second adjoint.

[0090] S105. Based on the second synergy, verify the second data.

[0091] In this embodiment of the disclosure, the correctness of the second data obtained after error correction can be verified based on the second syndrome. Referring to the above equation (13), if the second syndrome S′ is zero, the second data is correct and the error correction is successful; if the second syndrome S′ is not zero, the second data still contains errors and the error correction is unsuccessful.

[0092] It is understood that in the BCH decoding process of this embodiment, after correcting the first data, the second data obtained after error correction is subjected to a second verification to verify whether the second data is correct. In this way, unsuccessful error correction can be detected in a timely manner, avoiding output error data caused by data errors exceeding the error correction capability range of the BCH code.

[0093] In some embodiments of this disclosure, the process of calculating the adjoint (including the first adjoint and the second adjoint) can be completed by the verification matrix module. That is, the verification matrix module used in the error correction process of the first data can be reused in the process of verifying the second data.

[0094] Accordingly, referring to equations (2) and (13) above, the check matrix module can multiply the vectorized first data or second data with the transpose of the preset check matrix to complete the process of calculating the adjoint equation.

[0095] It is understood that in the BCH decoding process of this embodiment, the second data obtained after error correction can be directly input into the check matrix module for verification again to ensure the correctness of the error correction result. In this way, on the one hand, the reliability of the error correction result is improved, and the verification efficiency is also improved; on the other hand, since the check matrix module is reused, a lot of hardware resources can be saved.

[0096] In some embodiments of this disclosure, it is possible to... Figure 2 The steps S1051 or S1052 shown are used to achieve the following: Figure 1 Step S105 is shown. The explanation will follow each step.

[0097] S1051. In response to the second syndrome being zero, output the second data as the correct data.

[0098] S1052. In response to the second syntactic being non-zero, determine that the first data is an uncorrectable error state.

[0099] In this embodiment of the disclosure, on the one hand, if the second syntactic S′ in the above formula (13) is zero, it indicates that the error correction is successful, and the second data obtained after error correction can be output as the correct data.

[0100] On the other hand, if the second syntactic S′ in equation (13) above is not zero, it indicates that the error correction was unsuccessful, and the first data initially received can be determined to be in an uncorrectable error state. Then, the error state can be reported.

[0101] It is understood that, in the BCH decoding process of this disclosure embodiment, on the one hand, it can accurately determine whether a data bit error has occurred. When the error correction capability is within the range, the number and location of the error can be determined, and error correction can be performed in a timely manner. On the other hand, when the error correction capability is exceeded, the error can be reported in a timely manner, avoiding the output error data caused by the data error exceeding the error correction capability of the BCH code, and improving the reliability of the error correction result.

[0102] In some embodiments of this disclosure, it is possible to... Figure 3 The shown step S1031 is to achieve Figure 1 Step S103 is shown. The explanation will be provided in conjunction with each step.

[0103] S1031. In response to the first syntactic expression being non-zero, the first data is corrected to obtain the second data.

[0104] In this embodiment of the disclosure, if the first adjoint S in equation (2) above is not zero, it indicates that there is an error in the first data, and thus the first data can be corrected. After the error correction is completed, the second data can be obtained.

[0105] In some embodiments of this disclosure, Figure 1 Following step S102, the data verification method further includes... Figure 3 Step S106 is shown. The explanation will be based on each step.

[0106] S106. In response to the first syndrome being zero, output the first data as the correct data.

[0107] In this embodiment of the disclosure, if the first syntactic S in the above formula (2) is zero, it indicates that there is no error in the first data, so the first data can be directly output as correct data.

[0108] In some embodiments of this disclosure, it is possible to... Figure 4 The steps S201 to S203 shown are used to achieve the following: Figure 1 Step S103 is shown. The explanation will be provided in conjunction with each step.

[0109] S201. Calculate the error position polynomial based on the first adjoint.

[0110] In this embodiment of the disclosure, if h represents the correct part of the first data and e represents the incorrect part of the first data, then the binomial r(X) of the first data satisfies the above equation (4).

[0111] Furthermore, in the first adjoint S, the correct part of the first data is zero after calculation. Therefore, for 1≤i≤2t, the first adjoint S depends only on the erroneous pattern e(X), and the first adjoint S and the erroneous pattern e(X) satisfy the above equation (5).

[0112] Furthermore, the error position polynomial can be calculated based on the error pattern e(X) to obtain the above equation (11).

[0113] S202. Based on the error location polynomial, find the error location.

[0114] In this embodiment of the disclosure, after obtaining the error position polynomial σ(X), that is, after obtaining the above equation (11), the above equation (12) can be solved. Furthermore, based on the exponent of the prime element a, the error position in the received first data can be obtained.

[0115] S203. In the first data, the values ​​at the wrong positions are corrected to obtain the second data.

[0116] In some embodiments of this disclosure, for binary BCH code, the values ​​at the error positions in the first data can be inverted, thus completing the error correction of the first data and obtaining the second data.

[0117] In some embodiments of this disclosure, it is possible to... Figure 5 The steps S2011 to S2012 shown are used to achieve the following: Figure 4 Step S201 is shown. Each step will be explained in detail.

[0118] S2011. Calculate the error pattern based on each component of the first synergy.

[0119] In this embodiment of the disclosure, in the first adjoint S, the correct part of the first data is zero after calculation. Therefore, from the above equations (3) and (4), it can be obtained that for 1≤i≤2t, each component S in the first adjoint S is zero. i The above equation (5) is satisfied between the first association S and the error pattern. That is, the first association S depends only on the error pattern e(X).

[0120] S2012. Based on the error pattern, calculate the error location polynomial using the Peterson algorithm.

[0121] In this embodiment of the disclosure, it is assumed that the error pattern e(X) has v errors, with error positions j1, j2, ..., jn. v Then we have equation (6); furthermore, we can obtain the above system of equations (7).

[0122] Furthermore, by iterating according to the Peterson algorithm, we can obtain the above equation (8), and then we can obtain the above equation (9).

[0123] Furthermore, in the iterative algorithm for solving the polynomial σ(X) at the error location, the solution of the (2μ-1)th iteration... It is also the solution of the 2μth iteration. Right now In other words, the (2μ-1)th iteration and the 2μth iteration can be combined. Therefore, based on equations (8) and (9) above, the iterative algorithm for finding σ(X) can be simplified to equation (10) above. Furthermore, equation (11) above can be obtained, that is, the error position polynomial σ(X) can be obtained.

[0124] In some embodiments of this disclosure, it is possible to... Figure 6 The steps S2021 to S2022 shown are used to achieve the following: Figure 4 Step S202 is shown. The explanation will be based on each step.

[0125] S2021. Solve the polynomial at the error position using the Chien search algorithm.

[0126] S2022. Determine the error location based on the exponent in the solution of the error location polynomial.

[0127] In this embodiment of the disclosure, after obtaining the error position polynomial σ(X), the coefficients σ of each term are calculated. i Using the Chien search algorithm, we can obtain the solution of the error position polynomial σ(X), which is the above equation (12).

[0128] Furthermore, based on the exponent of prime element a in equation (12), the error position in the received first data can be obtained.

[0129] Figure 7 The following is a schematic diagram of another optional implementation flow of the data verification method provided in the embodiments of this disclosure, such as... Figure 7 As shown, the method includes steps S301 to S309.

[0130] S301, Read the first data.

[0131] In this embodiment of the disclosure, the first step in BCH decoding requires receiving the first data to be decoded. This first data includes data bits and a parity bit. The parity bit is obtained by BCH encoding based on the data bits and is used to verify and correct errors in the data bits.

[0132] S302, Calculate the syndrome.

[0133] In this embodiment of the disclosure, the first adjoint S is obtained by transposing the parity check matrix H and multiplying it by the vector r of the first data, which is also the above equation (2). The first adjoint S is a 2t-dimensional vector, where t is the error correction capability of the parity check matrix H.

[0134] S303, Output the first data.

[0135] In this embodiment of the disclosure, if the first syndrome S is zero, it indicates that there is no error in the first data, and the first data can be directly output as correct data.

[0136] S304. Calculate the polynomial at the error location.

[0137] In this embodiment of the disclosure, if the first syndrome S is not zero, it indicates that there is an error in the first data, and the first data can be corrected.

[0138] First, the error location polynomial can be calculated based on the error pattern e(X). By iterating and simplifying according to the Peterson algorithm, the error location polynomial σ(X) can be obtained, which is the above equation (11).

[0139] The S305 and Chien search algorithms are used to find error locations.

[0140] In this embodiment of the disclosure, after obtaining the error position polynomial σ(X), the coefficients σ of each term are calculated. i Using the Chien search algorithm, the solution to the error position polynomial σ(X) can be obtained, which is the above equation (12). Furthermore, based on the exponent of the prime element a in the above equation (12), the error position in the received first data can be obtained.

[0141] S306. Based on the erroneous pattern, obtain the corrected second data.

[0142] In this embodiment of the disclosure, for binary BCH code, the values ​​at the erroneous positions in the first data can be inverted to correct the error in the first data and obtain the second data.

[0143] S307. Calculate the syndrome again.

[0144] In this embodiment of the disclosure, the vectorized second data r′ is multiplied by the transpose of the parity matrix H to obtain the second adjoint S′, which is the above equation (13).

[0145] S308, Output the second data.

[0146] In this embodiment of the disclosure, if the second syndrome S′ is zero, it indicates that the error correction is successful, and the second data obtained after error correction can be output as the correct data.

[0147] S309. Output an uncorrectable error status.

[0148] In this embodiment of the disclosure, if the second syndrome S′ is not zero, it indicates that the error correction has failed, and the initially received first data can be determined to be in an uncorrectable error state. Furthermore, the error state can be reported.

[0149] It is understood that, in the BCH decoding process of this disclosure embodiment, on the one hand, it can accurately determine whether a data bit error has occurred. When the error correction capability is within the range, the number and location of the error can be determined, and error correction can be performed in a timely manner. On the other hand, when the error correction capability is exceeded, the error can be reported in a timely manner, avoiding the output error data caused by the data error exceeding the error correction capability of the BCH code, and improving the reliability of the error correction result.

[0150] In some embodiments of this disclosure, such as Figure 8 As shown, the data verification method also includes steps S401 to S402, which will be explained in conjunction with each step.

[0151] S401, Obtain initial data.

[0152] S402. Based on the initial data parsing, obtain the parsed data, encode it, and obtain the check bit. The parsed data and the check bit are used as the first data.

[0153] In this embodiment of the disclosure, during the process of writing data to the memory chip, the controller chip of the CXL memory module can obtain initial data (e.g., 512 data bits) by parsing the message, and obtain parsed data based on the initial data. An ECC encoder based on BCH code can encode the parsed data to obtain ECC check bits (e.g., 20 bits). Furthermore, the CXL memory module can simultaneously write the data bits (i.e., the initial data) and the check bits to the memory chip.

[0154] This disclosure also provides a CXL memory module, such as Figure 9 As shown, the CXL memory module 30 includes a memory chip 20 and a controller chip 10 connected to the memory chip 20. The memory chip 20 includes a memory cell array and peripheral circuitry coupled to the memory cell array. The controller chip 10 is coupled to the memory chip 20 and controls the memory chip 20.

[0155] In this embodiment of the disclosure, reference is made to Figure 9 The host can be configured to send data to or receive data from the CXL memory module 30. The controller chip 10 is coupled to the memory chip 20 and the host, and is configured to control the memory chip 20. The controller chip 10 can manage the data stored in the memory chip 20 and communicate with the host. The host can be a processor of a computer system, such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU).

[0156] Continue to refer to Figure 9 The controller chip 10 can be configured to control the operation of the memory chip 20, such as read, erase, write, and refresh operations. In some embodiments, the controller chip 10 is also configured to process checksums for data read from or written to the memory chip 20. The controller chip 10 can also perform any other suitable function, such as formatting the memory chip 20.

[0157] Continue to refer to Figure 9 Data transmission between the host and controller chip 10 uses the CXL protocol. (Refer to...) Figure 2 The CXL controller module in controller chip 10 serves as the CXL interface.

[0158] It should be noted that CXL is a new high-speed interconnect technology based on open standards, designed to address memory bottlenecks in modern computing and storage systems. Built on the physical and electrical interfaces of the PCIe 5.0 standard, CXL technology provides higher bandwidth and better memory consistency. CXL technology allows for fast and reliable data transfer between different components within a computer system and supports memory expansion and sharing, making collaboration between devices more seamless and efficient.

[0159] For the application of the ECC verification module in the design of CXL controller chip modules, the data verification method provided in the embodiments of this disclosure can be used to design the algorithm of the ECC verification module. Similarly, for the application of the ECC verification module in the design of CXL memory chips, the data verification method provided in the embodiments of this disclosure can also be used to design the algorithm of the ECC verification module.

[0160] In this embodiment of the present disclosure, the controller chip 10 is configured to read first data from the memory chip 20; calculate a first syndrome based on the first data to obtain a first syndrome; correct errors in the first data based on the first syndrome to obtain second data; calculate a second syndrome based on the second data to obtain a second syndrome; and verify the second data based on the second syndrome.

[0161] In some embodiments of this disclosure, the controller chip 10 is further configured to multiply the vectorized first data or second data with the transpose of a preset parity matrix to obtain a first or second syntactic expression.

[0162] In some embodiments of this disclosure, the controller chip 10 is further configured to output the second data as correct data in response to the second syndrome being zero; or to determine the first data as an uncorrectable error state in response to the second syndrome being non-zero.

[0163] In some embodiments of this disclosure, the controller chip 10 is also configured to correct the first data in response to the first symptom being non-zero, thereby obtaining the second data.

[0164] In some embodiments of this disclosure, the controller chip 10 is also configured to output the first data as correct data in response to the first symptom being zero.

[0165] In some embodiments of this disclosure, the controller chip 10 is further configured to calculate an error location polynomial based on a first syntactic polynomial; determine the error location based on the error location polynomial; and correct the value of the error location in the first data to obtain the second data.

[0166] In some embodiments of this disclosure, the controller chip 10 is further configured to compute an error pattern based on each component of the first synod; and to compute an error location polynomial based on the error pattern.

[0167] In some embodiments of this disclosure, the controller chip 10 is further configured to find a solution to the error location polynomial using a search algorithm; and to determine the error location based on the exponent in the solution of the error location polynomial.

[0168] In some embodiments of this disclosure, the controller chip 10 is also configured to invert the value at the erroneous position in the first data to obtain the second data.

[0169] In some embodiments of this disclosure, the controller chip 10 is further configured to acquire initial data; encode a check bit based on the initial data to obtain first data; and write the first data into a memory chip.

[0170] This disclosure also provides a controller chip for a CXL memory module, such as... Figure 10 As shown, the controller chip 10 includes a data verification module 110. The data verification module 110 includes an encoder 130 and a decoder 120.

[0171] like Figure 11 As shown, the decoder 120 includes a parity check matrix module 1201 and an error correction module 1202. The parity check matrix module 1201 is configured to read first data and calculate a first syndrome based on the first data. The error correction module 1202 is configured to correct errors in the first data based on the first syndrome to obtain second data. The parity check matrix module 1201 is also configured to calculate a second syndrome based on the second data and verify the second data based on the second syndrome.

[0172] It is understood that in the decoder 120 of this embodiment, after the error correction module 1202 corrects the first data, it directly inputs the corrected second data into the check matrix module 1201. The check matrix module 1201 then performs a secondary check on the second data to verify its correctness. This allows for timely detection of unsuccessful error correction, avoiding erroneous output data due to data errors exceeding the error correction capability of the BCH code. On one hand, this improves the reliability of the error correction result and increases the verification efficiency; on the other hand, since the check matrix module is reused, it saves significant hardware resources.

[0173] In some embodiments of this disclosure, reference is made to Figure 11 The verification matrix module 1201 is also configured to multiply the vectorized first data or second data with the transpose of the preset verification matrix to complete the process of calculating the adjoint expression.

[0174] In some embodiments of this disclosure, reference is made to Figure 11 The verification matrix module 1201 is also configured to output the second data as correct data in response to the second syndrome being zero; or to determine the first data as an uncorrectable error state in response to the second syndrome being non-zero.

[0175] In some embodiments of this disclosure, reference is made to Figure 11 The error correction module 1202 is also configured to correct the first data in response to the first syntactic being non-zero, and obtain the second data.

[0176] In some embodiments of this disclosure, reference is made to Figure 11 The verification matrix module 1201 is also configured to output the first data as the correct data in response to the first syndrome being zero.

[0177] In some embodiments of this disclosure, such as Figure 12 As shown, the error correction module 1202 includes: a key equation solving module 1203, a search module 1204, and a modular second calculation module 1205.

[0178] In this embodiment of the disclosure, the critical equation solving module 1203 is configured to calculate the error location polynomial based on the first adjoint. The critical equation solving module 1203 can calculate the error location polynomial based on the first adjoint S and the error pattern e(X) in equations (2) and (5) above, to obtain equation (11).

[0179] In this embodiment of the disclosure, the search module 1204 is configured to determine the error position based on the error position polynomial. The search module 1204 can solve for the error position in the above equation (11) to obtain the above equation (12), thereby obtaining the error position in the received first data.

[0180] In this embodiment of the disclosure, the modulo-2 calculation module 1205 is configured to correct errors in the values ​​at incorrect positions in the first data to obtain the second data. The modulo-2 calculation module 1205 can perform binary operations (e.g., modulo-2 addition) on the first data to correct errors in the values ​​at incorrect positions and obtain the second data.

[0181] In some embodiments of this disclosure, reference is made to Figure 12 The key equation solving module 1203 is also configured to compute an error pattern based on each component of the first adjoint; and, based on the error pattern, compute the error location polynomial using the Peterson algorithm.

[0182] In some embodiments of this disclosure, reference is made to Figure 12 The search module 1204 is also configured to find the solution of the error position polynomial using the Chien search algorithm; and to determine the error position based on the exponent in the solution of the error position polynomial.

[0183] In some embodiments of this disclosure, reference is made to Figure 12 The modulo-2 calculation module 1205 is also configured to invert the values ​​at the erroneous positions in the first data.

[0184] In some embodiments of this disclosure, such as Figure 10 As shown, memory chip 20 can be DDR Memory (Double Data Rate, Double Data Rate Synchronous Dynamic Random Access Memory).

[0185] In this embodiment of the disclosure, reference is made to Figure 10 When CXL writes data to DDR memory, controller chip 10 obtains 512 data bits by parsing the message and inputs the parsed data into data verification module 110 based on BCH code design. Encoder 130 performs encoding operation to obtain 20 ECC check bits, and then simultaneously writes the data bits and ECC check bits into DDR memory.

[0186] In this embodiment of the disclosure, reference is made to Figure 10When CXL reads data from DDR memory, the controller chip 10 reads 512 data bits and 20 ECC check bits, and inputs the read data into the decoder 120 based on BCH code for decoding. Decoder 120 first calculates the syndrome to determine if there is an error. If the syndrome calculation is error-free, it directly outputs the data bits. If the syndrome calculation shows an error, decoder 120 performs error polynomial calculation and Qian search algorithm to obtain the error pattern, corrects the data bits, and performs a second syndrome calculation to verify the corrected result. If the correction result is correct, decoder 120 outputs the corrected result; if the correction result is incorrect, i.e., multiple errors exceed the error correction capability, decoder 120 outputs an error status of "uncorrectable".

[0187] This disclosure also provides a computer system, such as... Figure 10 As shown, the computer system includes a host and a CXL memory module 30. The host communicates with the CXL memory module 30 through the CXL interface to discover, configure, and transfer data to the CXL memory module 30.

[0188] In this embodiment of the disclosure, the computer system may be located in a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein.

[0189] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0190] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0191] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A CXL memory module, characterized in that, include: A memory chip and a controller chip connected to the memory chip; The controller chip is configured to read first data from the memory chip; The first syndrome is obtained by calculating the syndrome based on the first data; Based on the first syntactic expression, the first data is corrected to obtain the second data; The second syndrome is obtained by calculating the syndrome based on the second data; The second data is verified based on the second syndrome.

2. The CXL memory module according to claim 1, characterized in that, The controller chip is further configured to multiply the vectorized first data or the second data with the transpose of a preset check matrix to obtain the first or the second syndrome.

3. The CXL memory module according to claim 1, characterized in that, The controller chip is further configured to output the second data as correct data in response to the second syndrome being zero; or to determine the first data as an uncorrectable error state in response to the second syndrome being non-zero.

4. The CXL memory module according to claim 1, characterized in that, The controller chip is also configured to correct the first data in response to the first symptom being non-zero, and obtain the second data.

5. The CXL memory module according to claim 1, characterized in that, The controller chip is also configured to output the first data as correct data in response to the first symptom being zero.

6. The CXL memory module according to claim 1, characterized in that, The controller chip is further configured to calculate an error location polynomial based on the first syntactic equation; determine the error location based on the error location polynomial; and correct the value of the error location in the first data to obtain the second data.

7. The CXL memory module according to claim 6, characterized in that, The controller chip is also configured to calculate an error pattern based on each component of the first syndrome; Based on the error pattern, the error location polynomial is calculated.

8. The CXL memory module according to claim 6, characterized in that, The controller chip is further configured to find the solution of the error location polynomial using a search algorithm; and to determine the error location based on the exponent in the solution of the error location polynomial.

9. The CXL memory module according to claim 6, characterized in that, The controller chip is also configured to invert the value at the error location in the first data to obtain the second data.

10. The CXL memory module according to any one of claims 1 to 9, characterized in that, The controller chip is further configured to acquire initial data; encode a check bit based on the initial data to obtain the first data; and write the first data into the memory chip.

11. A data verification method, characterized in that, The data verification method includes: Read the first data; The first syndrome is obtained by calculating the syndrome based on the first data; Based on the first syntactic expression, the first data is corrected to obtain the second data; The second syndrome is obtained by calculating the syndrome based on the second data; The second data is verified based on the second syndrome.

12. The data verification method according to claim 11, characterized in that, The steps for calculating the adjoint include: The vectorized first or second data is multiplied by the transpose of the preset check matrix.

13. The data verification method according to claim 11, characterized in that, Based on the second syndrome, the second data is verified, including: In response to the second syndrome being zero, the second data is output as the correct data; or, In response to the second syndrome being non-zero, the first data is determined to be in an uncorrectable error state.

14. The data verification method according to claim 11, characterized in that, Based on the first syndrome, the first data is corrected to obtain the second data, including: In response to the first syntactic expression being non-zero, the first data is corrected to obtain the second data.

15. The data verification method according to claim 11, characterized in that, Based on the first data, the association formula is calculated. After obtaining the first association formula, the data verification method further includes: In response to the first symptom being zero, the first data is output as the correct data.

16. The data verification method according to claim 11, characterized in that, The first data is corrected to obtain the second data, including: Based on the first syndrome, calculate the error location polynomial; The error location is determined based on the aforementioned error location polynomial; In the first data, the values ​​at the erroneous positions are corrected to obtain the second data.

17. The data verification method according to claim 16, characterized in that, Based on the first syndrome, the error position polynomial is calculated, including: Calculate the error pattern based on each component of the first synergy; Based on the error pattern, the error location polynomial is calculated.

18. The data verification method according to claim 16, characterized in that, The error location is determined based on the error location polynomial, including: The solution to the polynomial at the error location is obtained by using a search algorithm; The error location is determined based on the exponent in the solution of the error location polynomial.

19. The data verification method according to claim 16, characterized in that, In the first data, error correction at the erroneous location includes: In the first data, the values ​​at the error locations are inverted.

20. The data verification method according to any one of claims 11 to 19, characterized in that, The data verification method further includes: Get initial data; Based on the initial data, parsed data is obtained, encoded, and a check bit is obtained. The parsed data and the check bit are used as the first data.

21. A controller chip for a CXL memory module, characterized in that, The controller chip includes: a data verification module; the data verification module includes: an encoder and a decoder; The decoder includes: a parity check matrix module and an error correction module; wherein... The verification matrix module is configured to read first data; and to calculate the first syndrome based on the first data. The error correction module is configured to correct the first data based on the first symptom to obtain the second data; The verification matrix module is further configured to calculate the second syndrome based on the second data to obtain the second syndrome; and to verify the second data based on the second syndrome.

22. The controller chip for the CXL memory module according to claim 21, characterized in that, The error correction module includes: a key equation solving module, a search module, and a modulo 2 calculation module; The key equation solving module is configured to calculate the error location polynomial based on the first adjoint equation; The search module is configured to find the error location based on the error location polynomial; The modulo-2 calculation module is configured to correct the values ​​at the erroneous positions in the first data to obtain the second data.

23. A computer system, characterized in that, The device includes a host and a CXL memory module as described in any one of claims 1 to 10, wherein the host communicates with the CXL memory module through a CXL interface to realize the discovery, configuration and data transmission of the CXL memory module.

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