High-speed serial interface and data transmission method thereof, electronic device

Abstract

This application discloses a high-speed serial interface and its data transmission method and electronic device, belonging to the field of communication technology. The high-speed serial interface includes: a transmitting port, which includes a request input module, an arbitration module, and a first processing module connected in sequence; the request input module is used to receive frame transmission requests; the arbitration module is used to respond to frame transmission requests; the first processing module is used to encrypt the frame transmission requests, obtain transmission data, and output the transmission data; and a receiving port, which includes a second processing module and a buffer module connected in sequence; the second processing module is connected to the first processing module, and is used to receive the transmission data, decrypt the transmission data to obtain the frame transmission request, and transmit the frame transmission request to the buffer module; the buffer module is used to temporarily store the frame transmission request according to a deterministic delay. The high-speed serial interface provided by this application can meet the requirements of deterministic delay.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to high-speed serial interfaces and their data transmission methods and electronic devices. Background Technology

[0002] The DigRF v4 protocol provides a frame-based transmission protocol, but it is described based on the LTE (Long Term Evolution) product form. LTE has low latency requirements, but with the rapid evolution of communication protocols to 5G (5th Generation Mobile Communication Technology), latency requirements are becoming increasingly stringent. However, the DigRF v4 protocol does not have deterministic latency-related descriptions, resulting in latency uncertainty issues for high-speed serial interfaces using the DigRF v4 protocol. Summary of the Invention

[0003] The main objective of this application is to provide a high-speed serial interface and its data transmission method and electronic device, which aims to at least solve the problem of delay uncertainty in high-speed serial interfaces.

[0004] To achieve the above objectives, embodiments of this application provide a high-speed serial interface, the high-speed serial interface comprising:

[0005] The sending port includes a request input module, an arbitration module, and a first processing module connected in sequence; the request input module is used to receive frame transmission requests; the arbitration module is used to respond to the frame transmission requests; the first processing module is used to encrypt the frame transmission requests, obtain transmission data, and output the transmission data.

[0006] The receiving port includes a second processing module and a cache module connected in sequence; the second processing module is connected to the first processing module, and the second processing module is used to receive the transmitted data, decrypt the transmitted data to obtain the frame transmission request, and transmit the frame transmission request to the cache module; the cache module is used to temporarily store the frame transmission request according to a deterministic delay.

[0007] Furthermore, to achieve the above objectives, embodiments of this application also provide a data transmission method for a high-speed serial interface, the method comprising:

[0008] The system receives a frame transmission request through the sending port, responds to the frame transmission request, encrypts the frame transmission request, and obtains the transmission data.

[0009] The transmission data is received through the receiving port, the transmission data is decrypted to obtain the frame transmission request, and the frame transmission request is temporarily stored according to the deterministic delay.

[0010] Furthermore, to achieve the above objectives, embodiments of this application also provide an electronic device, the electronic device comprising:

[0011] The high-speed serial interface described above;

[0012] Alternatively, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the data transmission method of the high-speed serial interface as described above.

[0013] This application proposes a high-speed serial interface and its data transmission method and electronic device, which at least solves the problem of latency uncertainty in high-speed serial interfaces in related technologies. The high-speed serial interface includes: a transmitting port, which includes a request input module, an arbitration module, and a first processing module connected in sequence; the request input module is used to receive frame transmission requests; the arbitration module is used to respond to frame transmission requests; the first processing module is used to encrypt the frame transmission requests, obtain transmission data, and output the transmission data; and a receiving port, which includes a second processing module and a buffer module connected in sequence; the second processing module is connected to the first processing module, and is used to receive transmission data, decrypt the transmission data to obtain frame transmission requests, and transmit the frame transmission requests to the buffer module; the buffer module is used to temporarily store frame transmission requests according to a deterministic delay. This application embodiment enables the high-speed serial interface to meet the deterministic latency requirements in some scenarios by configuring a deterministic delay for the buffer module. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of the structure of a high-speed serial interface provided in one embodiment of this application;

[0016] Figure 2 A schematic diagram illustrating an application example of a high-speed serial interface provided in an embodiment of this application;

[0017] Figure 3 A schematic diagram of the structure of an 8-bit message header of a frame request related to a high-speed serial interface provided in an embodiment of this application;

[0018] Figure 4 A schematic diagram illustrating the phase relationship before and after business data transmission, provided as an embodiment of this application;

[0019] Figure 5 A schematic diagram illustrating another phase relationship before and after business data transmission, provided as an embodiment of this application;

[0020] Figure 6 This is a schematic diagram illustrating another phase relationship before and after business data transmission, provided as an embodiment of this application.

[0021] Figure 7 This is a schematic diagram of another high-speed serial interface provided in an embodiment of this application;

[0022] Figure 8 A schematic diagram of another high-speed serial interface provided in an embodiment of this application;

[0023] Figure 9 A schematic flowchart illustrating a data transmission method for a high-speed serial interface provided in an embodiment of this application;

[0024] Figure 10 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application.

[0025] The realization of the objectives, functional features and advantages of the embodiments of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings.

[0026] Explanation of icon numbers:

[0027] 10. Sending port; 11. Request input module; 12. Arbitration module; 13. First processing module;

[0028] 20. Receive port; 21. Second processing module; 22. Buffer module; 14. First timing module;

[0029] 23. Second timing module. Detailed Implementation

[0030] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of the embodiments of this application.

[0031] Currently, high-speed interface protocols are broadly divided into two categories: streaming protocols, such as CPRI, Aurora, and J204; and frame protocols, such as the DigRF series. Streaming protocols, through continuous iteration, have achieved increasingly higher line rates and support more and more features; for example, J204B supports deterministic latency. However, streaming protocols also have their own drawbacks: firstly, they do not support low-power features, and with increasingly stringent power requirements across various product forms, the adoption of power-saving high-speed interface designs for terminal chips is particularly important; secondly, in multi-standard concurrent scenarios, a framer must use the same sampling rate, leading to oversampling of low-sampling-rate data and wasting bandwidth; and thirdly, CPRI, Aurora, and J204 do not support sharing bandwidth between standard service data and control port messages. The DigRF v4 protocol provides a frame-based transmission protocol, but it is described based on the LTE product form. LTE has low latency requirements, but with the rapid evolution of communication protocols to 5G, latency requirements are becoming increasingly stringent. However, the DigRF v4 protocol does not have deterministic latency-related descriptions, resulting in latency uncertainty issues for high-speed serial interfaces using the DigRF v4 protocol.

[0032] Based on this, embodiments of this application provide a high-speed serial interface and its data transmission method and electronic device. For various service standards, this high-speed serial interface can ensure that service data and control ports share bandwidth for transmission. By sharing the high-speed serial differential interface with the control port, low-speed interface devices can be saved, reducing the number of chip IO (input / output) pins and lowering chip costs. The high-speed serial differential interface has a large bandwidth, enabling fast transmission of multiple control port messages with low latency and more precise control. Service data of different standards are transmitted according to their true sampling rate, avoiding bandwidth waste due to oversampling of low sampling rate data. For increasingly stringent latency requirements in high-level scenarios, embodiments of this application can meet the requirements of low latency and deterministic latency based on this high-speed serial interface.

[0033] The high-speed serial interface, data transmission method, and electronic device provided in this application are specifically described through the following embodiments. First, the high-speed serial interface in this application embodiment is described.

[0034] This application provides a high-speed serial interface, see embodiments thereof. Figure 1 , Figure 1 This is a schematic diagram of a high-speed serial interface according to an embodiment of this application. The high-speed serial interface includes:

[0035] Sending port 10 includes a request input module 11, an arbitration module 12, and a first processing module 13 connected in sequence; the request input module 11 is used to receive frame transmission requests; the arbitration module 12 is used to respond to frame transmission requests; the first processing module 13 is used to encrypt the frame transmission requests, obtain the transmission data, and output the transmission data.

[0036] The receiving port 20 includes a second processing module 21 and a buffer module 22 connected in sequence. The second processing module 21 is connected to the first processing module 13. The second processing module 21 is used to receive transmission data, decrypt the transmission data to obtain a frame transmission request, and transmit the frame transmission request to the buffer module 22. The buffer module 22 is used to temporarily store the frame transmission request according to the deterministic delay.

[0037] The high-speed serial interface provided in this embodiment can be used in mobile terminal products. For example, radio frequency chips and terminal chips can use this interface to perform uplink and downlink data interaction. This interface can also be applied to baseband processing units or active antenna processing units. Taking the baseband processing unit as an example, two boards can perform cell data scheduling processing through the high-speed serial interface provided in this embodiment.

[0038] In this embodiment, the input of the transmitting port 10 is connected to a forward external circuit or device capable of generating a frame transmission request, and the output of the receiving port 20 is connected to a backward external circuit or device that needs to receive the information carried by the frame transmission request.

[0039] As an example, refer to Figure 2 Transmit port 10 can be implemented using a BBIC (baseband integrated circuit), and receive port 20 can be implemented using an RFIC (radio frequency front-end integrated circuit).

[0040] In this embodiment, the request input module 11 may include a data frame request input unit, a control frame request input unit, and a retransmission frame request input unit, enabling the control port to share high-speed differential bandwidth with service data without the need to open an additional low-speed interface, thus taking into account the advantages of fast transmission speed, low latency, precise control, and cost savings; similarly, the frame transmission request may be one or more of the data frame request, control frame request, and / or retransmission frame request from outside the high-speed serial interface.

[0041] As an example, in this embodiment, the request input module 11 may also include multiple data logic channels, each of which is independent of each other and has a different sampling rate (for example, each sampling rate is divided into 7 levels, or other numbers of levels, which are not limited in this embodiment). In this way, when multiple service data are transmitted concurrently, they can be transmitted according to the actual sampling rate without oversampling small sample data. On the one hand, this can save bandwidth, reduce chip area and size, thereby reducing costs. On the other hand, it can also avoid transmitting redundant data and reduce chip power consumption.

[0042] As an example, data frames and control frames can be distinguished by an 8-bit header (8-bit message header), and the meaning of each bit is as follows: Figure 3 As shown.

[0043] Furthermore, in this embodiment, the arbitration module 12 may include an arbitrator. Since the high-speed serial interface provided in this embodiment is serially transmitted, the arbitration module 12 will only respond to one of the data frame request, control frame request, and / or retransmission frame request at the same time. Different types of frame requests cannot be responded to simultaneously. The specific response order can be determined according to the access timing of the frame transmission request. This embodiment does not impose any restrictions on this.

[0044] In this embodiment, the first processing module 13 may include a processor and any electronic device with encryption function, and the second processing module 21 may include a processor and any electronic device with decryption function. The processor in the first processing module 13 and the processor in the second processing module 21 are independent of each other.

[0045] As an example, in this embodiment, the process of encrypting the frame transmission request by the first processing module 13 may include framing, encoding, and parallel-to-serial conversion. That is, after the frame transmission request is processed by the first processing module 13 through framing, encoding, and parallel-to-serial conversion, the transmission data carrying the frame transmission request can be obtained. After receiving the transmission data from the sending port 10, the process of decrypting the transmission data by the second processing module 21 may include serial-to-parallel conversion, decoding, and deframing. That is, after the transmission data is processed by the second processing module 21 through serial-to-parallel conversion, decoding, and deframing, the frame transmission request can be restored to avoid leakage during data transmission.

[0046] As an example, to further understand the technical effects achievable in this embodiment, this embodiment uses NR2CC (New Radio; Carrier Aggregation) as an example, referring to... Figure 4 , Figure 5 and Figure 6The three phase relationship diagrams shown illustrate the delay uncertainty problem in the DigRF v4 protocol of related technologies: such as Figure 4 As shown, the initial phase relationship between service a and service b is basically the same. Both services require transmission simultaneously. Since the RF interface transmits serially, the arbitrator responds to service a first, then service b. After the service data arrives at the RF chip, the phase difference between the two services is t1. Figure 4 As can be seen, the phase relationship changes after the service data passes through the RF interface; for example... Figure 5 As shown, the initial phase of service a and service b is t. Since the RF interface transmits serially, the arbitrator responds to service a first, then to service b. After service b collects one frame of data, service a has not yet finished transmitting. After the service data arrives at the RF chip, the phase difference between the two service data is still t1. Figure 6 As shown, the initial phase of service a and service b is t'. Since the RF interface transmits serially, the arbitrator responds to service a first, then to service b. After service b collects one frame of data, service a has already finished transmitting, so it will immediately respond to service b. After the service data arrives at the RF chip, the phase difference between the two service data is still t'. Figure 4 , Figure 5 and Figure 6 As can be seen, since the DigRF v4 protocol uses shared bandwidth, it can only respond to one type of service data request at a time. The different order in which the arbitrators respond will lead to differences in group latency.

[0047] In this embodiment, the cache module 22 may include a buffer (buffer register). In order to meet the requirements of deterministic latency, by configuring deterministic latency at the cache module 22, the cache module 22 can temporarily store the frame transmission request and allow the external device connected to the receiving port 20 to read the frame transmission request only after the deterministic latency is reached. This ensures that different service data will no longer have different group delays due to different response orders of the arbitrator.

[0048] Considering that the sources of latency jitter are mainly from the following aspects: 1) Different order in which the arbitrator responds to multiple requests will lead to differences in group latency; 2) Asynchronous cross-clock paths between different blocks will cause latency jitter; 3) Differences in board-level trace latency will also lead to differences in group latency.

[0049] Therefore, this embodiment proposes the following specific implementation methods for configuring deterministic latency.

[0050] In some feasible embodiments, the first processing module 13 is further configured to record the difference value of the response frame transmission request of the arbitration module 12 and integrate the difference value into the transmission data; the second processing module 21 is further configured to extract the difference value from the transmission data and adjust the actual cache value of the cache module 22 according to the difference value, wherein the difference value is negatively correlated with the actual cache value, and the deterministic delay is determined according to the difference value and the actual cache value.

[0051] In this embodiment, the problem of different group delays caused by different order of arbitrator responses to multiple requests is overcome by compensating the receiving port 20.

[0052] In this embodiment, after the service data is sent to the arbitration module 12 via the request input module 11, the arbitrator starts to respond to the request. At this time, the first processing module 13 can record the difference value of the arbitrator's response and transmit the difference value to the cache module 22 via the second processing module 21 through a control message. This allows the cache module 22 to adjust its actual cache value according to the difference value, so that there is no longer a group delay difference after different service data arrive at the receiving port 20.

[0053] As an example, the negative correlation between the difference value and the actual cache value means that the larger the difference value, the smaller the actual cache value; and the smaller the difference value, the larger the actual cache value. The cache module 22 can use its own maximum cache value as a reference for deterministic latency, ensuring that the sum of the difference value and the actual cache value is always the maximum cache value, thereby achieving the purpose of configuring deterministic latency.

[0054] In some feasible embodiments, refer to Figure 7 The transmitting port 10 also includes a first timing module 14, which is connected to the request input module 11. The first timing module 14 is used to control the request input module 11 to access the frame transmission request at the first moment. The receiving port 20 also includes a second timing module 23, which is connected to the buffer module 22. The second timing module 23 is used to control the buffer module 22 to output the frame transmission request at the second moment. The deterministic delay is determined based on the difference between the second moment and the first moment.

[0055] In this embodiment, by adding a first timing module 14 to the transmitting port 10 to achieve timed transmission and adding a second timing module 23 to the receiving port 20 to achieve timed reception, the problem of delay jitter that occurs between different blocks in asynchronous cross-clock paths is overcome.

[0056] In this embodiment, the timing of service data transmission is determined by the first timing module 14. Under the control of the first timing module 14, assuming that the sending port 10 starts service data transmission at time t1, the service data passes through the arbitrator, and then through the first processing module 13 for framing, encoding, and parallel-to-serial conversion before reaching the receiving port 20. The receiving port 20 performs serial-to-parallel conversion, decoding, and deframing through the second processing module 21. Under the control of the second timing module 23, the service data is read from the buffer module 22 at time t1+T. Then, T can be regarded as the value of deterministic delay.

[0057] As an example, the first timing module 14 and the second timing module 23 can be any type of timer, as long as they can meet the timing control logic of this embodiment. This embodiment does not impose any restrictions on them.

[0058] In some feasible embodiments, refer to Figure 8 The first timing module 14 and the second timing module 23 are connected. The first timing module 14 or the second timing module 23 is used to output a synchronization pulse so that the first timing module 14 and the second timing module 23 can synchronize the time reference based on the synchronization pulse.

[0059] In this embodiment, the problem of group delay differences caused by board-level trace delay differences is overcome by connecting the first timing module 14 and the second timing module 23 to synchronize the time base.

[0060] In this embodiment, the first timing module 14 and the second timing module 23 can be connected by hardware pins. Either of the two timing modules can be used as a synchronization pulse output terminal to achieve synchronization control. That is, when synchronization is required, a pulse or periodic pulse is output by the first timing module 14 or the second timing module 23, so that the two timing modules are aligned to a time reference under the control of the pulse, thereby performing high-precision time delay control.

[0061] This embodiment provides a high-speed serial interface that can meet the requirements of deterministic latency by recording delay jitter values, setting timed transmission at the transmitting port, timed reading at the receiving port, and synchronizing timers at the transmitting and receiving ports. Simultaneously, it ensures that service data and control ports share bandwidth for transmission. By sharing the high-speed serial differential interface with the control port, low-speed interface devices can be saved, reducing the number of chip I / O (input / output) pins and lowering chip costs. Due to the large bandwidth of the high-speed serial differential interface, multiple control port messages can be transmitted quickly with low latency, resulting in more precise control. Service data of different standards are transmitted according to their true sampling rate, preventing bandwidth waste caused by oversampling of low-sampling-rate data.

[0062] Furthermore, this application also provides a data transmission method for a high-speed serial interface, applied to the high-speed serial interface provided in the above embodiments, with reference to... Figure 9 The data transmission method includes steps S10 and S20.

[0063] Step S10: Access frame transmission request through the sending port, respond to frame transmission request, encrypt frame transmission request, and obtain transmission data;

[0064] Step S20: Receive transmission data through the receiving port, decrypt the transmission data to obtain a frame transmission request, and temporarily store the frame transmission request according to the deterministic delay.

[0065] In some feasible embodiments, the data transmission method may further include:

[0066] The first processing module records the difference value of the arbitration module's response frame transmission request and integrates the difference value into the transmitted data;

[0067] The second processing module extracts the difference value from the transmitted data and adjusts the actual cache value of the cache module according to the difference value. The difference value and the actual cache value are negatively correlated, and the deterministic delay is determined based on the difference value and the actual cache value.

[0068] In some feasible embodiments, the data transmission method may further include:

[0069] The first timing module controls the request input module to receive the frame transmission request at the first moment.

[0070] The second timing module controls the buffer module to output a frame transmission request at the second moment, and the deterministic delay is determined based on the difference between the second moment and the first moment.

[0071] In some feasible embodiments, the data transmission method may further include:

[0072] The first timing module or the second timing module outputs a synchronization pulse so that the first timing module and the second timing module can synchronize their time references based on the synchronization pulse.

[0073] The data transmission method of the high-speed serial interface proposed in this embodiment belongs to the same technical concept as the high-speed serial interface proposed in the above embodiments. Technical details not described in detail in this embodiment can be found in any of the above embodiments. Furthermore, this embodiment has the same beneficial effects as the above embodiments of the high-speed serial interface.

[0074] Furthermore, this application also provides an electronic device, which includes: the high-speed serial interface provided in the above embodiments; or, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the data transmission method of the high-speed serial interface provided in the above embodiments.

[0075] Reference Figure 10 , Figure 10 This is a schematic diagram of the hardware structure of an electronic device provided in an embodiment of this application. Figure 10 As shown, the electronic device may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to enable communication between these components. The user interface 1003 may include a display screen or an input unit such as a keyboard; optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wi-Fi interface). The memory 1005 may be high-speed random access memory (RAM) or stable non-volatile memory (NVM), such as a disk drive. The memory 1005 may also optionally be a storage device independent of the aforementioned processor 1001.

[0076] Those skilled in the art will understand that Figure 10 The structures shown do not constitute a limitation on the electronic device and may include more or fewer components than illustrated, or combine certain components, or have different component arrangements. Figure 10 As shown, the memory 1005, which serves as a storage medium, may include an operating system, a data storage module, a network communication module, a user interface module, and computer programs.

[0077] exist Figure 10 In the electronic device shown, the network interface 1004 is mainly used for data communication with other devices; the user interface 1003 is mainly used for data interaction with the user; the processor 1001 and the memory 1005 in this embodiment can be set in the electronic device. The electronic device calls the computer program stored in the memory 1005 through the processor 1001 and executes the data transmission method of the high-speed serial interface provided in any of the above embodiments.

[0078] The electronic device proposed in this embodiment belongs to the same technical concept as the high-speed serial interface and its data transmission method proposed in the above embodiments. Technical details not described in detail in this embodiment can be found in any of the above embodiments. Furthermore, this embodiment has the same beneficial effects as the above embodiments of the high-speed serial interface.

[0079] It should be noted that all directional indicators (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationship and movement of each component in a certain specific posture (as shown in the figure). If the specific posture changes, the directional indicator will also change accordingly.

[0080] Furthermore, in the embodiments of this application, descriptions involving "first," "second," etc., are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of the embodiments of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. Additionally, the meaning of "and / or" throughout the text includes three parallel solutions; for example, "A and / or B" includes solution A, solution B, or a solution that simultaneously satisfies A and B.

[0081] In the embodiments of this application, unless otherwise expressly specified and limited, the terms "connection" and "fixed" should be interpreted broadly. For example, "fixed" can mean a fixed connection, a detachable connection, or an integral part; it can mean a mechanical connection or an electrical connection; it can mean a direct connection or an indirect connection through an intermediate medium; it can mean the internal communication of two components or the interaction between two components, unless otherwise expressly limited. Those skilled in the art can understand the specific meaning of the above terms in the embodiments of this application according to the specific circumstances.

[0082] It should also be understood that references to "one embodiment" or "some embodiments" in the specification of embodiments of this application mean that one or more embodiments of this application include the specific features, structures, or characteristics described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof all mean "including but not limited to," unless otherwise specifically emphasized.

[0083] It should be noted that the technical solutions of the various embodiments of this application can be combined with each other, but only if they are implemented by those skilled in the art. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such combination of technical solutions does not exist and is not within the scope of protection claimed by the embodiments of this application.

[0084] The above are merely optional embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the description and drawings of this application, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A high-speed serial interface, characterized in that, The high-speed serial interface includes: The sending port includes a request input module, an arbitration module, and a first processing module connected in sequence; the request input module is used to receive frame transmission requests; the arbitration module is used to respond to the frame transmission requests; the first processing module is used to encrypt the frame transmission requests, obtain transmission data, and output the transmission data. The receiving port includes a second processing module and a cache module connected in sequence; the second processing module is connected to the first processing module, and the second processing module is used to receive the transmitted data, decrypt the transmitted data to obtain the frame transmission request, and transmit the frame transmission request to the cache module; the cache module is used to temporarily store the frame transmission request according to a deterministic delay.

2. The high-speed serial interface as described in claim 1, characterized in that, The first processing module is further configured to record the difference value in the arbitration module's response to the frame transmission request, and integrate the difference value into the transmission data; The second processing module is further configured to extract the difference value from the transmitted data and adjust the actual cache value of the cache module according to the difference value, wherein the difference value is negatively correlated with the actual cache value, and the deterministic delay is determined according to the difference value and the actual cache value.

3. The high-speed serial interface as described in claim 1, characterized in that, The sending port further includes a first timing module, which is connected to the request input module. The first timing module is used to control the request input module to access the frame transmission request at a first moment. The receiving port further includes a second timing module, which is connected to the buffer module. The second timing module is used to control the buffer module to output the frame transmission request at a second time. The deterministic delay is determined based on the difference between the second time and the first time.

4. The high-speed serial interface as described in claim 3, characterized in that, The first timing module and the second timing module are connected. The first timing module or the second timing module is used to output a synchronization pulse so that the first timing module and the second timing module can synchronize their time references based on the synchronization pulse.

5. The high-speed serial interface as described in claim 1, characterized in that, The request input module includes multiple data logic channels, each of which is independent of the others and has a different sampling rate.

6. The high-speed serial interface as described in claim 1, characterized in that, The frame transmission request includes at least one data frame request, control frame request, and / or retransmission frame request.

7. The high-speed serial interface as described in claim 6, characterized in that, The arbitration module responds to only one of the data frame request, control frame request, and / or retransmission frame request at any given time.

8. The high-speed serial interface as described in claim 1, characterized in that, The first processing module encrypts the frame transmission request by framing, encoding, and parallel-to-serial conversion. The second processing module's decryption process for the transmitted data includes serial-to-parallel conversion, decoding, and frame de-framing.

9. A data transmission method for a high-speed serial interface, characterized in that, The method is applied to a high-speed serial interface as described in any one of claims 1 to 8, comprising: The system receives a frame transmission request through the sending port, responds to the frame transmission request, encrypts the frame transmission request, and obtains the transmission data. The transmission data is received through the receiving port, the transmission data is decrypted to obtain the frame transmission request, and the frame transmission request is temporarily stored according to the deterministic delay.

10. An electronic device, characterized in that, The electronic device includes: High-speed serial interface as described in any one of claims 1 to 8; Alternatively, a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the data transmission method of the high-speed serial interface as described in claim 9.

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