Data transmission method, first chip, second chip and data transmission circuit

Abstract

The application relates to a data transmission method, a first chip, a second chip and a data transmission circuit. The method comprises the following steps: in the case that a first target level signal is received through an expansion signal line, determining that the first chip is a slave chip; in the case that a second target level signal is received through a chip selection signal line, receiving a data packet sent by the second chip from an MOSI signal line, the header of the data packet carrying an operation type, a target operation address and a target operation value; converting the data packet into a data format corresponding to an APB interface through an SPI2APB bus IP core, and performing a corresponding operation according to the operation type, the target operation address and the target operation value. The method can avoid establishing a complex chip holding mechanism, does not need to pass through software logic processing, and can effectively improve the data transmission efficiency between chips.

Description

Technical Field

[0001] This application relates to the field of chip technology, and in particular to a data transmission method, a first chip, a second chip, and a data transmission circuit. Background Technology

[0002] In scenarios where multiple chips / chip modules with independent CPUs work together efficiently, it is crucial to determine a method for data transmission between chips, between chips and chip modules, and between chip modules.

[0003] In the prior art, data transmission between chips is carried out through a general-purpose SPI interface. SPI usually adopts a master-slave mode, that is, when a master chip communicates with multiple slave chips, the master chip connects to each slave chip through multiple chip select signal lines, sends a chip select signal (Chip Select, CS) to the designated slave chip, activates the slave chip, and performs data transmission.

[0004] However, in the existing technology, data transmission via the SPI interface requires the establishment of a complex chip handshake mechanism and software logic processing, resulting in low data transmission efficiency. Summary of the Invention

[0005] Therefore, it is necessary to provide a data transmission method, a first chip, a second chip, and a data transmission circuit that can improve the efficiency of data transmission between chips, in order to address the above-mentioned technical problems.

[0006] In a first aspect, this application provides a data transmission method for use in a first chip, the first chip including an SPI2APB bus IP core and an APB interface, the SPI2APB bus IP core being connected to the APB interface, the SPI2APB bus IP core being connected to signal lines, the signal lines including extended signal lines, chip select signal lines, and MOSI signal lines, the method including:

[0007] If a first target level signal is received through the extended signal line, the first chip is determined to be a slave chip;

[0008] When the second target level signal is received through the chip select signal line, the data packet sent by the second chip is received from the MOSI signal line. The header of the data packet carries the operation type, target operation address and target operation value.

[0009] The SPI2APB bus IP core converts data packets into the data format corresponding to the APB interface and executes the corresponding operation based on the operation type, target operation address, and target operation value.

[0010] In one embodiment, the SPI2APB bus IP core includes an SPI interface, a data packet processing module, and a data conversion interface. The data packet processing module is connected to each signal line through the SPI interface, and the data packet processing module is connected to the APB interface through the data conversion interface. The SPI interface includes a receive first-in-first-out queue (RXFIFO).

[0011] The SPI2APB bus IP core converts data packets into the data format corresponding to the APB interface, and performs corresponding operations based on the operation type, target operation address, and target operation value, including:

[0012] Data packets sent by the second chip are received from the MOSI signal line via RXFIFO;

[0013] The packet processing module parses the packet header to obtain the operation type, target operation address, and target operation value.

[0014] The operation type, target operation address, and target operation value are converted into a first data format through the data conversion interface, and the corresponding operation is executed according to the operation type, target operation address, and target operation value. The first data format is the data format corresponding to the APB interface.

[0015] In one embodiment, when the operation type is a read operation, the packet tail includes a padding data segment, which is used to generate a clock signal to trigger the first chip to send target data to the second chip. The SPI interface includes a transmit first-in-first-out queue TXFIFO, and the signal lines also include MISO signal lines.

[0016] Execute the corresponding operation based on the operation type, target operation address, and target operation value, including:

[0017] The target data is obtained from the target operation address in the first data format through the APB interface;

[0018] The target data is converted into a second data format through a data conversion interface. The second data format is the data format corresponding to the SPI interface.

[0019] The target data in the second data format is forwarded to the TXFIFO by the packet processing module, and then sent to the second chip through the MISO signal line under the trigger of the clock signal.

[0020] In one embodiment, when the operation type is a write operation, the corresponding operation is performed according to the operation type, the target operation address, and the target operation value, including:

[0021] The target operation value is written to the target operation address through the APB interface.

[0022] Secondly, this application provides a data transmission method for use in a second chip, the second chip including an SPI2APB bus IP core and an APB interface, the SPI2APB bus IP core being connected to the APB interface and the SPI2APB bus IP core being connected to signal lines, the signal lines including extended signal lines, chip select signal lines, and MOSI signal lines, the method including:

[0023] When the second chip is the main chip, a first target level signal is sent to the first chip through an extended signal line, and a second target level signal is sent to the first chip through a chip select signal line. The second target level signal is used to instruct the first chip to start receiving data.

[0024] Data packets are sent to the first chip via the MOSI signal line. The header of the data packet carries the operation type, the target operation address, and the target operation value.

[0025] In one embodiment, when the operation type is a read operation, the signal line further includes a MISO signal line, and the method further includes:

[0026] Receive target data sent by the first chip from the MISO signal line;

[0027] The target data is converted into a first data format via the SPI2APB bus IP core and then sent to the CPU of the second chip via the APB interface. The first data format is the data format corresponding to the APB interface.

[0028] Thirdly, this application also provides a data transmission device for a first chip. The first chip includes an SPI2APB bus IP core and an APB interface. The SPI2APB bus IP core is connected to the APB interface and is connected to signal lines, which include extended signal lines, chip select signal lines, and MOSI signal lines.

[0029] The determination module is used to determine that the first chip is a slave chip when a first target level signal is received through the extended signal line;

[0030] The receiving module is used to receive data packets sent by the second chip from the MOSI signal line when the second target level signal is received through the chip select signal line. The header of the data packet carries the operation type, target operation address and target operation value.

[0031] The execution module is used to convert data packets into the data format corresponding to the APB interface through the SPI2APB bus IP core, and to execute the corresponding operation according to the operation type, target operation address and target operation value.

[0032] Fourthly, this application also provides a data transmission device for a second chip. The second chip includes an SPI2APB bus IP core and an APB interface. The SPI2APB bus IP core is connected to the APB interface and to signal lines, which include extended signal lines, chip select signal lines, and MOSI signal lines.

[0033] The first transmitting module is configured to transmit a first target level signal to the first chip via an extended signal line and a second target level signal to the first chip via a chip select signal line when the second chip is the main chip. The second target level signal is used to instruct the first chip to start receiving data.

[0034] The second transmitting module is used to send data packets to the first chip via the MOSI signal line. The header of the data packet carries the operation type, the target operation address, and the target operation value.

[0035] Fifthly, this application also provides a first chip, including a processor and a communication interface, wherein the processor is configured to cause the first chip to perform the method described in the first aspect above.

[0036] Sixthly, this application also provides a first chip module, including a communication module, a power module, a storage module, and a first chip, wherein:

[0037] The power module is used to provide power to the first chip module;

[0038] The storage module is used to store data and instructions;

[0039] The communication module is used for internal communication within the first chip module, or for communication between the first chip module and external devices.

[0040] The first chip is used to perform the steps of the method provided in the first aspect above.

[0041] In a seventh aspect, this application also provides a second chip, including a processor and a communication interface, wherein the processor is configured to cause the second chip to perform the method described in the second aspect above.

[0042] Eighthly, this application also provides a second chip module, including a communication module, a power module, a storage module, and a second chip, wherein:

[0043] The power module is used to provide power to the second chip module;

[0044] The storage module is used to store data and instructions;

[0045] The communication module is used for internal communication within the second chip module, or for communication between the second chip module and external devices;

[0046] The second chip is used to perform the steps of the method provided in the second aspect above.

[0047] Ninthly, this application also provides a data transmission circuit, including the first chip described in the fifth aspect, the second chip described in the seventh aspect, and a signal line manager; wherein the chip select signal line and extended signal line of the first chip are connected to the chip select signal line and extended signal line of the second chip through the signal line manager.

[0048] In a tenth aspect, this application also provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the method described in either the first or second aspect above.

[0049] In one aspect, this application also provides a computer program product, including a computer program that, when executed by a processor, implements the method described in either the first or second aspect above.

[0050] The aforementioned data transmission method, the first chip, the second chip, and the data transmission circuit allow the first chip to determine itself as a slave chip upon receiving a first target level signal via an extended signal line. Upon receiving a second target level signal via a chip select signal line, the first chip receives data packets sent by the second chip via the MOSI signal line. The packet header carries the operation type, target operation address, and target operation value. The SPI2APB bus IP core converts the data packets into the data format corresponding to the APB interface and executes the corresponding operation based on the operation type, target operation address, and target operation value. This allows the first chip to freely switch its master / slave role configuration based on the level signal received via the extended signal line, achieving multi-chip coordination. Simultaneously, the first chip begins receiving data packets sent by the second chip based on the second target level signal. Since the packet header carries the operation type, target operation address, and target operation value, the first chip can determine the operation type, target operation address, and target operation value through hardware parsing upon receiving the data packet and execute the corresponding operation. This avoids establishing a complex chip handshake mechanism and eliminates the need for software logic processing, effectively improving the data transmission efficiency between chips. Attached Figure Description

[0051] To more clearly illustrate the technical solutions in the embodiments of this application or related technologies, the drawings used in the description of the embodiments of this application or related technologies will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is an application environment diagram of a data transmission method in one embodiment;

[0053] Figure 2 This is a flowchart illustrating a data transmission method in one embodiment;

[0054] Figure 3 This is a flowchart illustrating the execution of corresponding operation steps based on the operation type in one embodiment.

[0055] Figure 4 This is a schematic diagram of the structure of the first chip or the second chip in one embodiment;

[0056] Figure 5 This is a flowchart illustrating the execution of corresponding operation steps based on the operation type in another embodiment;

[0057] Figure 6 This is a flowchart illustrating the data transmission method in another embodiment.

[0058] Figure 7 This is a flowchart illustrating the data transmission method in another embodiment;

[0059] Figure 8 This is a schematic diagram of the data transmission path when the operation type is read data in one embodiment;

[0060] Figure 9 This is a structural block diagram of a data transmission device in one embodiment;

[0061] Figure 10 This is a structural block diagram of a data transmission device in another embodiment;

[0062] Figure 11 This is an internal structure diagram of a chip module in one embodiment. Detailed Implementation

[0063] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0064] It should be noted that the terms "first," "second," etc., used in this application can be used to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from the second element. The terms "comprising" and "having," and any variations thereof, used in this application, are intended to cover non-exclusive inclusion. The term "multiple" used in this application refers to two or more. The term "and / or" used in this application refers to one of the embodiments, or any combination of multiple embodiments.

[0065] The data transmission method provided in this application embodiment can be applied to, for example... Figure 1 In the data transmission circuit shown, where, Figure 1 The data transmission circuit includes a first chip, a second chip, and a signal line manager. Both the first and second chips include an SPI2APB bus IP core and an APB interface. The SPI2APB bus IP core is connected to the APB interface and to signal lines, which include extended signal lines, chip select signal lines, master output / slave input (MOSI) signal lines, and master input / slave output (MISO) signal lines. During data exchange between chips, only one chip acts as the master, and the other chips act as slaves, with the first chip as the slave chip. Figure 1 Chips 2 to N are slave chips, and the second chip is the master chip. Figure 1 Taking chip 1 as the main chip as an example, the data transmission circuit may include multiple first chips. The second chip is directly connected to the MOSI signal line and MISO signal line of each first chip. The chip select signal line and extended signal line of the second chip are connected to each first chip through a signal line manager. The chip select signal line and extended signal line of the first chip are connected to the chip select signal line and extended signal line of the second chip through a signal line manager.

[0066] refer to Figure 1 The SPI2APB bus IP cores in the first and second chips may include an SPI interface, a data packet processing module, and a data conversion interface. Figure 1 (not shown in the image), where the SPI interface includes a Transmit First-In First-Out (TXFIFO) queue and a Receive First-In First-Out (RXFIFO) queue.

[0067] In one exemplary embodiment, such as Figure 2 As shown, a data transmission method is provided, which is applied to... Figure 1The first chip in, or applied to Figure 1 Taking the first chip / first chip module with data processing capabilities as an example, the explanation includes the following steps 201 to 203. Wherein:

[0068] Step 201: When the first chip receives the first target level signal through the extended signal line, it determines that the first chip is a slave chip.

[0069] Optionally, the first chip can receive the level signal sent by the second chip through the extended signal line connected to the second chip, and determine that the first chip is a slave chip if the level signal is the first target level signal. In other words, the level signal transmitted through the extended signal line (hereinafter referred to as the CS_CD signal) can characterize the master-slave role of the first chip.

[0070] The first target level signal can be a low-level signal or a high-level signal, depending on the actual situation. For example, if the first target level signal is a low-level signal, the first chip acts as a slave chip when it receives the low-level signal through the extended signal line.

[0071] Optionally, when the second chip is the master chip, since only one chip is the master chip when data is exchanged between chips at the same time, the second chip sends a first target level signal to the first chip through the extended signal line and sends a second target level signal to the first chip through the chip select signal line. The second target level signal is used to instruct the first chip to start receiving data.

[0072] The CPU of the second chip can determine the second chip as the master chip based on the scenario and information contained in the transmitted data packets, combined with preset rules. Alternatively, the second chip can determine the second chip as the master chip when it receives a third target level signal through an extended signal line, wherein the third target level signal is opposite to the first target level signal.

[0073] Optionally, when the second chip is the master chip and the first chip is the slave chip, the second chip sends a second target level signal to the first chip via the chip select (CS) signal line to select the first chip and instruct the first chip to start receiving data. The second target level signal can be either a low-level signal or a high-level signal; this embodiment does not limit its usage.

[0074] Both the first chip and the second chip include multiple chip select signal lines. When the second chip is the master chip, the signals of each CS of the second chip are in the output state, and the number of CS that are turned on is determined by the maximum number of chip select signals that can be supported. When the first chip is the slave chip, the signals of the CS of the first chip are in the input state, and only one CS connected to the second chip (such as the first CS) is turned on, while the other CS are turned off.

[0075] Step 202: When the first chip receives the second target level signal through the chip select signal line, it receives the data packet sent by the second chip from the MOSI signal line.

[0076] The data packet header carries the operation type, target operation address, and target operation value. The header may include, but is not limited to, SPI protocol serial data. The operation type indicates the action the second chip intends to take on the first chip; the operation type may include a read operation or a write operation. The target operation address indicates the address of the first chip that the second chip intends to operate on. The target operation value may be the data that the second chip intends to write to the target operation address of the first chip.

[0077] The second chip's MOSI signal line is connected to the first chip's MOSI signal line. The second chip can send data packets to the first chip through the MOSI signal line. At the same time, the second chip interacts with the first chip through the SPI protocol. The corresponding data packets are encapsulated based on the SPI protocol and are sent serially.

[0078] Step 203: The first chip converts the data packet into the data format corresponding to the APB interface through the SPI2APB bus IP core, and performs the corresponding operation according to the operation type, target operation address and target operation value.

[0079] Among them, the SPI2APB bus IP core is an on-chip protocol conversion bridge. Its core function is to convert external SPI serial instructions / data packets into address mapping transactions of the APB bus inside the first chip, so that the external SPI second chip can access the registers of the APB peripheral in the first chip like a CPU. It also supports the reverse transmission of APB side data back to the second chip via SPI.

[0080] Optionally, after the first chip receives the data packet through the MOSI signal line, since the data packet is encapsulated based on the SPI protocol, and the modules within the first chip communicate with each other through the APB protocol, it is necessary to convert the data packet based on the SPI protocol into the data format corresponding to the APB interface in the first chip, that is, the data format corresponding to the APB protocol.

[0081] After the data packet format is converted to the corresponding data format of the APB interface through the SPI2APB bus IP core, the data sent by the second chip can be directly written to the on-chip register of the first chip through APB, or the second chip can read data from the on-chip register of the first chip through APB, without the need for the CPU intervention of the first chip or simplifying the CPU interrupt handling.

[0082] For example, taking a write operation as an example, the first chip can write the target operation value into the target operation address through the APB interface to complete the writing of the target operation value.

[0083] Taking a read operation as an example, the first chip can read the target data from the target operation address through the APB interface, and then send the target data to the SPI2APB bus IP core through the APB interface, so that the SPI2APB bus IP core can convert the target data into the data format corresponding to the SPI interface and send the target data to the second chip to complete the reading of the target data.

[0084] In the aforementioned data transmission method, when the first chip receives a first target level signal via the extended signal line, it determines itself as a slave chip. When it receives a second target level signal via the chip select signal line, it receives data packets sent by the second chip via the MOSI signal line. The packet header carries the operation type, target operation address, and target operation value. The SPI2APB bus IP core converts the data packets into the data format corresponding to the APB interface and executes the corresponding operation based on the operation type, target operation address, and target operation value. In this way, the first chip can freely switch its master / slave role configuration based on the level signal received via the extended signal line, achieving multi-chip coordination. Simultaneously, the first chip begins receiving data packets sent by the second chip based on the second target level signal. Since the packet header carries the operation type, target operation address, and target operation value, the first chip can determine the operation type, target operation address, and target operation value through hardware parsing after receiving the data packet and execute the corresponding operation. This avoids establishing a complex chip handshake mechanism and eliminates the need for software logic processing, effectively improving the data transmission efficiency between chips.

[0085] In one exemplary embodiment, such as Figure 3 As shown, the SPI2APB bus IP core includes an SPI interface, a data packet processing module, and a data conversion interface. The data packet processing module is connected to each signal line through the SPI interface, and the data packet processing module is connected to the APB interface through the data conversion interface. The SPI interface includes a receive first-in-first-out queue (RXFIFO); optionally, as... Figure 4As shown, the data packet is converted into the data format corresponding to the APB interface through the SPI2APB bus IP core, and the corresponding operation is executed according to the operation type, target operation address, and target operation value, including the following steps 401 to 403:

[0086] Step 401: The first chip receives the data packet sent by the second chip from the MOSI signal line through the RXFIFO.

[0087] Among them, reference Figure 4 The SPI2APB bus IP core can be connected to the following signal lines: CLK, MISO, MOSI, CS0, CS1, ..., CSN and CS_CD.

[0088] Optionally, the first chip receives serially transmitted data packets from the MOSI signal line through the RXFIFO in the SPI interface. The SPI interface is used to transmit data from the second chip based on the SPI general protocol. At the same time, the SPI interface can be divided into an SPI Master module and an SPI Slave module, as well as a configuration and management method for the CS signal. The SPI Master and SPISlave multiplex the CLK / MOSI / MISO / CS signal lines, and the input and output states of their signals are determined by the master and slave roles of the first chip, which will not be elaborated here.

[0089] For example, when the first chip receives data, it does so through the SPI Slave module in the SPI interface; when the first chip sends data, it does so through the SPI Master module in the SPI interface.

[0090] In other words, the first chip can receive data packets sent by the second chip from the MOSI signal line through the RXFIFO in the SPI Slave module.

[0091] Step 402: The first chip parses the header of the data packet through the data packet processing module to obtain the operation type, target operation address and target operation value.

[0092] Optionally, the data packet processing module, as a key module of the SPI2APB bus IP core, is used to parse and process data packets, providing data and signal sources for the data conversion interface, SPI interface, and SPI2APB bus IP core status variables.

[0093] The data packet can adopt a fixed-length frame structure, which includes, from the high bit to the low bit, the operation type (occupying the first preset number of bits), the target operation address (occupying the second preset number of bits), and the target operation value (occupying the third preset number of bits).

[0094] It is understandable that different operation types correspond to different preset values. For example, 0X02 indicates that the operation type is a write operation, and 0X03 indicates that the operation type is a read operation.

[0095] For example, the first chip receives the serial bit stream on the MOSI line bit by bit under the drive of the clock signal. After receiving the first preset number of bits, the data packet processing module determines the operation type and then continues to receive the next preset number of bits. The data packet processing module concatenates the second preset number of bits into a parallel address data and temporarily stores it in the address register. Then it continues to receive the next preset number of bits. The data packet processing module concatenates the third preset number of bits into a parallel write data and temporarily stores it in the write data register.

[0096] It is understandable that in the above process, if the operation type is a read operation, there is no need to execute the step of continuing to receive the next three preset bits.

[0097] Step 403: The first chip converts the operation type, target operation address, and target operation value into a first data format through the data conversion interface, and performs the corresponding operation according to the operation type, target operation address, and target operation value.

[0098] The first data format is the data format corresponding to the APB interface.

[0099] Optionally, the data format corresponding to the APB protocol is parallel data of "address + data". The data conversion interface obtains the operation type from the data packet processing module and determines whether to enable write or read based on the operation type. The data conversion interface obtains the target address data and the target operation value from the data packet processing module.

[0100] Then, the APB Slave module in the APB interface of the first chip reads the target address data and target operation value, and generates a standard APB write transaction or APB read transaction, and executes the corresponding operation according to the APB write transaction or APB read transaction.

[0101] The above-mentioned method receives data packets sent by the second chip from the MOSI signal line via the RXFIFO. The data packet processing module parses the packet header to obtain the operation type, target operation address, and target operation value. The data conversion interface converts the operation type, target operation address, and target operation value into a first data format, and executes the corresponding operation based on these parameters. The first data format is the data format corresponding to the APB interface. After receiving the data packet, the first chip can determine the operation type, target operation address, and target operation value through hardware parsing and execute the corresponding operation. This avoids establishing a complex chip handshake mechanism and eliminates the need for software logic processing, effectively improving the data transmission efficiency between chips.

[0102] In an exemplary embodiment, when the operation type is a read operation, the packet tail includes a padding data segment. This padding data segment is used to generate a clock signal to trigger the first chip to send target data to the second chip. The SPI interface includes a transmit first-in-first-out queue (TXFIFO), and the signal lines also include a MISO signal line. Figure 5 As shown, optionally, the corresponding operation is performed according to the operation type, target operation address, and target operation value, including the following steps 501 to 503. Wherein:

[0103] Step 501: The first chip obtains the target data from the target operation address in the first data format through the APB interface.

[0104] Optionally, the APB interface initiates an APB read transaction based on the target operation address, triggered by a clock signal, to read the target data from the target operation address.

[0105] Step 502: The first chip converts the target data into a second data format through a data conversion interface. The second data format is the data format corresponding to the SPI interface.

[0106] Optionally, the target data obtained through the APB interface is 32-bit parallel data, while the SPI interface can only transmit data bit by bit on the MISO signal line. Therefore, it is necessary to convert the target data from parallel to serial through a data conversion interface.

[0107] The order of the target data can also be converted. For example, on the APB interface side, the target data follows little-endian or natural alignment, meaning the least significant byte is stored at the lowest address. On the SPI interface side, the SPI protocol itself does not specify the byte order, but in practical applications, the master chip usually expects the target data to be transmitted in big-endian order, meaning the most significant byte comes first. Therefore, to conform to the reading habits of the master chip, the data conversion interface can adjust the order of the bytes to ensure that the order of the data stream received by the master chip is consistent with the expectation and to avoid data misalignment.

[0108] Step 503: The first chip forwards the target data in the second data format to the TXFIFO through the data packet processing module, and sends the target data to the second chip through the MISO signal line under the trigger of the clock signal.

[0109] Optionally, after the target data is converted to the desired format via the data conversion interface, the target data in the second data format is forwarded to the TXFIFO in the SPI interface via the data packet processing module.

[0110] In this process, when the second chip sends a data packet to the first chip, the packet tail includes a dummy data segment. Since the clock signal is generated by the second chip, and the target data is sent out by the first chip along with the clock signal, the first chip, after reading the target data from the target operation address, has no control over the clock line and cannot send out the target data. Therefore, the second chip can generate a clock signal on the clock signal line by sending dummy data to the first chip. When the clock signal reaches the first chip, the first chip, triggered by the clock signal, sends the target data in the TXFIFO bit by bit to the second chip through the MISO signal line.

[0111] Understandably, the length of the padding data segment in the data packet can be determined based on the target data size, so that the first chip can send the target data completely to the second chip.

[0112] Optionally, when sending target data to the second chip via the MISO signal line, the frame structure can be filled using the SPI read frame length.

[0113] For example, taking an SPI read frame length of 9 bytes (1 byte command + 4 bytes address + 4 bytes data) as an example, during the first 5 bytes of SPI transmission, the MISO line may be in high configuration or send invalid data. When the transmission is in the 6th byte, the data in the TXFIFO can be sent bit by bit.

[0114] The first chip obtains target data from the target operation address in the first data format via the APB interface, converts the target data into a second data format (the data format corresponding to the SPI interface) via a data conversion interface, and forwards the target data in the second data format to the TXFIFO via the data packet processing module. Then, triggered by a clock signal, the target data is sent to the second chip via the MISO signal line. This data conversion interface allows for rapid matching of the SPI interface, improving data reading efficiency.

[0115] In one exemplary embodiment, such as Figure 6 As shown, a data transmission method is provided, which is applied to... Figure 1 The second chip in, or applied to Figure 1 Taking a second chip / second chip module with data processing capabilities as an example, the second chip includes an SPI2APB bus IP core and an APB interface. The SPI2APB bus IP core is connected to the APB interface and to signal lines, including extended signal lines, chip select signal lines, and MOSI signal lines. The process includes steps 601 to 602. Wherein:

[0116] Step 601: When the second chip is the main chip, a first target level signal is sent to the first chip through the extended signal line, and a second target level signal is sent to the first chip through the chip select signal line.

[0117] The second target level signal is used to indicate that the first chip has started receiving data.

[0118] Step 602: Send a data packet to the first chip via the MOSI signal line. The header of the data packet carries the operation type, target operation address, and target operation value.

[0119] In an exemplary embodiment, optionally, when the operation type is a read operation, the signal line further includes a MISO signal line, and the method further includes:

[0120] Receive target data sent by the first chip from the MISO signal line.

[0121] The target data is converted into a first data format through the SPI2APB bus IP core, and then sent to the CPU of the second chip through the APB interface. The first data format is the data format corresponding to the APB interface.

[0122] The specific implementation methods and beneficial effects of the embodiments in this application have been described in detail in the above-described method embodiments on the first chip side, and will not be repeated here.

[0123] As an optional implementation method, such as Figure 7 As shown, the data transmission method provided in this application embodiment may include the following specific steps:

[0124] Step 701: When the second chip is the main chip, a first target level signal is sent to the first chip through the extended signal line, and a second target level signal is sent to the first chip through the chip select signal line;

[0125] The second target level signal is used to indicate that the first chip has started receiving data;

[0126] Step 702: When the first chip receives the first target level signal through the extended signal line, it determines that the first chip is a slave chip;

[0127] Step 703: The second chip sends a data packet to the first chip through the MOSI signal line. The header of the data packet carries the operation type, target operation address and target operation value.

[0128] Step 704: When the first chip receives the second target level signal through the chip select signal line, it receives the data packet sent by the second chip from the MOSI signal line through the RXFIFO;

[0129] Step 705: The first chip parses the packet header of the data packet through the data packet processing module to obtain the operation type, target operation address, and target operation value;

[0130] Step 706: The first chip converts the operation type, target operation address, and target operation value into a first data format through a data conversion interface;

[0131] The first data format is the data format corresponding to the APB interface;

[0132] Step 707: When the operation type is a read operation, the first chip obtains the target data from the target operation address in the first data format through the APB interface;

[0133] Step 708: The first chip converts the target data into the second data format through the data conversion interface;

[0134] The second data format is the data format corresponding to the SPI interface;

[0135] Step 709: The first chip forwards the target data in the second data format to the TXFIFO through the data packet processing module;

[0136] Step 710: The first chip sends the target data to the second chip via the MISO signal line under the trigger of the clock signal;

[0137] Step 711: The second chip converts the target data into the first data format through the SPI2APB bus IP core, and sends the target data to the CPU of the second chip through the APB interface;

[0138] The first data format is the data format corresponding to the APB interface;

[0139] Step 712: When the operation type is a write operation, the first chip writes the target operation value into the target operation address through the APB interface.

[0140] Combination Figure 1 Taking a read operation as an example, the data transmission path is illustrated below. Figure 8As shown, chip 1 is the master chip, and chips 2 and 3 are slave chips. When chip 1 reads data from chip 2, the CPU of chip 1 initiates a read data request. The header of the corresponding data packet includes the operation type, target operation address, and target operation value, while the footer includes a padding data segment. The data packet is then sent by the CPU of chip 1 to the APB Master module in the APB interface of chip 1. The APB Master module then sends it to the TXFIFO in the SPI interface of chip 1, and then transmits it via the SPI2APB bus to the RXFIFO, data packet processing module, and data conversion interface in the SPI interface of chip 2. The APB Slave module in the APB interface of chip 2 then retrieves the target data from the target operation address. Chip 2 sends the retrieved target data to its data conversion interface for format conversion, then sends it to the TXFIFO in the SPI interface of chip 2 via data packet processing. The data is then transmitted via the SPI2APB bus to the RXFIFO in the SPI interface of chip 1, and finally sent to the APB Master module in the APB interface of chip 1, before being returned to the CPU of chip 1, thus completing the data reading process.

[0141] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages in other steps. It is understood that the steps in different embodiments can be freely combined as needed, and all non-contradictory solutions formed by such combinations are within the scope of protection of this application.

[0142] Based on the same inventive concept, this application also provides a data transmission apparatus for implementing the data transmission method described above. This apparatus can be applied to or integrated into a chip or chip module, for example. The solution provided by this apparatus is similar to the implementation scheme described in the above method; therefore, the specific limitations in one or more data transmission apparatus embodiments provided below can be found in the limitations of the data transmission method described above, and will not be repeated here.

[0143] In one exemplary embodiment, such as Figure 9As shown, a data transmission device 900 is provided for a first chip. The first chip includes an SPI2APB bus IP core and an APB interface. The SPI2APB bus IP core is connected to the APB interface and to signal lines, including extended signal lines, chip select signal lines, and MOSI signal lines. The device includes a determination module 901, a receiving module 902, and an execution module 903.

[0144] The determination module 901 is used to determine that the first chip is a slave chip when a first target level signal is received through the extended signal line;

[0145] The receiving module 902 is used to receive data packets sent by the second chip from the MOSI signal line when the second target level signal is received through the chip select signal line. The header of the data packet carries the operation type, target operation address and target operation value.

[0146] The execution module 903 is used to convert data packets into the data format corresponding to the APB interface through the SPI2APB bus IP core, and to perform the corresponding operation according to the operation type, target operation address and target operation value.

[0147] In one embodiment, the SPI2APB bus IP core includes an SPI interface, a data packet processing module, and a data conversion interface. The data packet processing module is connected to each signal line through the SPI interface and to the APB interface through the data conversion interface. The SPI interface includes a receive first-in-first-out queue (RXFIFO); an execution module 903, specifically used to receive data packets sent by the second chip from the MOSI signal line through the RXFIFO; to parse the packet header of the data packet through the data packet processing module to obtain the operation type, target operation address, and target operation value; to convert the operation type, target operation address, and target operation value into a first data format through the data conversion interface, and to execute the corresponding operation according to the operation type, target operation address, and target operation value. The first data format is the data format corresponding to the APB interface.

[0148] In one embodiment, when the operation type is a read operation, the packet tail includes a padding data segment, which is used to generate a clock signal to trigger the first chip to send target data to the second chip. The SPI interface includes a transmit first-in-first-out queue TXFIFO, and the signal lines also include MISO signal lines. The execution module 903 is specifically used to obtain target data from the target operation address in the first data format through the APB interface; convert the target data into a second data format through a data conversion interface, the second data format being the data format corresponding to the SPI interface; forward the target data in the second data format to the TXFIFO through the packet processing module, and send the target data to the second chip through the MISO signal line under the trigger of the clock signal.

[0149] In one embodiment, when the operation type is a write operation, the execution module 903 is specifically used to write the target operation value into the target operation address through the APB interface.

[0150] In one exemplary embodiment, such as Figure 10 As shown, a data transmission device 1000 is provided for a second chip. The second chip includes an SPI2APB bus IP core and an APB interface. The SPI2APB bus IP core is connected to the APB interface and to signal lines, including extended signal lines, chip select signal lines, and MOSI signal lines. The device includes a first transmitting module 1001 and a second transmitting module 1002. Wherein:

[0151] The first transmitting module 1001 is used to transmit a first target level signal to the first chip through an extended signal line and a second target level signal to the first chip through a chip select signal line when the second chip is the main chip. The second target level signal is used to instruct the first chip to start receiving data.

[0152] The second transmitting module 1002 is used to send data packets to the first chip via the MOSI signal line. The header of the data packet carries the operation type, the target operation address, and the target operation value.

[0153] In one embodiment, when the operation type is a read operation, the signal line further includes a MISO signal line, and the data transmission device further includes a receiving module, which is used to receive target data sent by the first chip from the MISO signal line; convert the target data into a first data format through the SPI2APB bus IP core, and send the target data to the CPU of the second chip through the APB interface, wherein the first data format is the data format corresponding to the APB interface.

[0154] Regarding the modules / units included in the various devices and products described in the above embodiments, they can be software modules / units, hardware modules / units, or a combination of both. For example, for various devices and products applied to or integrated into a chip, all of their modules / units can be implemented using hardware methods such as circuits, or at least some modules / units can be implemented using software programs that run on a processor integrated within the chip, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits; for various devices and products applied to or integrated into a chip module, all of their modules / units can be implemented using hardware methods such as circuits, and different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or different components of the chip module, or at least some modules / units can be implemented using hardware methods such as circuits. The components can be implemented using software programs that run on the processor integrated within the chip module. The remaining (if any) modules / units can be implemented using hardware methods such as circuits. For various devices and products applied to or integrated into the terminal, each of its components / units can be implemented using hardware methods such as circuits. Different modules / units can be located in the same component (e.g., chip, circuit module, etc.) or in different components within the terminal. Alternatively, at least some modules / units can be implemented using software programs that run on the processor integrated within the terminal, while the remaining (if any) modules / units can be implemented using hardware methods such as circuits.

[0155] Based on the same inventive concept, embodiments of this application also provide a first chip, including a processor and a communication interface; the communication interface is used to receive or send data; the processor is configured to cause the first chip to perform the steps of any of the methods in the above embodiments.

[0156] Based on the same inventive concept, embodiments of this application also provide a second chip, including a processor and a communication interface; the communication interface is used to receive or send data; the processor is configured to cause the second chip to perform the steps of any of the methods in the above embodiments.

[0157] It is understood that the chip involved in the embodiments of this application may be a field-programmable gate array (FPGA), may be an application-specific integrated circuit (ASIC), may be a system on chip (SoC), may be a central processor unit (CPU), may be a network processor (NP), may be a digital signal processor (DSP), may be a microcontroller unit (MCU), may be a programmable logic device (PLD), or other integrated chips, etc.

[0158] Based on the same inventive concept, this application also provides a first chip module, such as... Figure 11 As shown, the first chip module includes a communication module, a power module, a storage module, and a first chip. Wherein:

[0159] The power module is used to provide power to the first chip module; the storage module is used to store data and instructions; the communication module is used for internal communication within the first chip module, or for communication between the first chip module and external devices; the first chip corresponds to the first chip in the above-described first chip embodiment.

[0160] The implementation method of the first chip module can be found in the relevant content of the first chip embodiment described above, and will not be repeated here.

[0161] Based on the same inventive concept, this application also provides a second chip module, which similarly includes a communication module, a power module, a storage module, and a second chip. Wherein:

[0162] The power module is used to provide power to the second chip module; the storage module is used to store data and instructions; the communication module is used for internal communication within the second chip module, or for communication between the second chip module and external devices; the second chip corresponds to the second chip in the first chip embodiment described above.

[0163] The implementation method of the second chip module can be found in the relevant content of the above-mentioned second chip embodiment, and will not be repeated here.

[0164] In one embodiment, such as Figure 1As shown, a data transmission circuit is provided, including a first chip as described in the above embodiments, a second chip as described in the above embodiments, and a signal line manager; wherein, the chip select signal line and extended signal line of the first chip are connected to the chip select signal line and extended signal line of the second chip through the signal line manager.

[0165] The use of a signal line manager to manage chip select signal lines and expansion signal lines can save wiring space and facilitate the management of chip select signals and expansion signals.

[0166] Optionally, the signal line manager manages the signal through the chip select signal line and extended signal line corresponding to the second chip, and transmits the received signal sent by the second chip to the corresponding first chip.

[0167] As can be seen from the above embodiments, the second chip can send a first target level signal through the extended signal line to configure the first chip as a slave chip. When multiple chips attempt to initiate transmission as the master chip, arbitration can be performed through the signal line manager to ensure that there is only one master chip at the same time.

[0168] For example, the signal line manager can select the second chip that first sends the target level signal as the master chip based on the time when each chip sends the target level signal through the corresponding extended signal line or chip select signal line.

[0169] In one embodiment, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, implements the steps in the above method embodiments.

[0170] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, implements the steps in the above method embodiments.

[0171] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, artificial intelligence (AI) processors, etc., and are not limited to these.

[0172] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0173] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of this patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this application should be determined by the appended claims.

Claims

1. A data transmission method, characterized in that, Used in a first chip, the first chip includes an SPI2APB bus IP core and an APB interface, the SPI2APB bus IP core is connected to the APB interface, the SPI2APB bus IP core is connected to signal lines, the signal lines include extended signal lines, chip select signal lines, and MOSI signal lines, the method includes: If a first target level signal is received through the extended signal line, the first chip is determined to be a slave chip; When a second target level signal is received through the chip select signal line, a data packet sent by the second chip is received from the MOSI signal line. The header of the data packet carries the operation type, target operation address, and target operation value. The SPI2APB bus IP core converts the data packet into the data format corresponding to the APB interface, and performs the corresponding operation according to the operation type, the target operation address, and the target operation value.

2. The method according to claim 1, characterized in that, The SPI2APB bus IP core includes an SPI interface, a data packet processing module, and a data conversion interface. The data packet processing module is connected to each of the signal lines through the SPI interface, and the data packet processing module is connected to the APB interface through the data conversion interface. The SPI interface includes a receive first-in-first-out queue (RXFIFO). The step of converting the data packet into the data format corresponding to the APB interface through the SPI2APB bus IP core, and performing the corresponding operation according to the operation type, the target operation address, and the target operation value, includes: The data packets sent by the second chip are received from the MOSI signal line via the RXFIFO; The packet processing module parses the packet header to obtain the operation type, target operation address, and target operation value. The operation type, target operation address, and target operation value are converted into a first data format through the data conversion interface, and the corresponding operation is performed according to the operation type, the target operation address, and the target operation value. The first data format is the data format corresponding to the APB interface.

3. The method according to claim 2, characterized in that, When the operation type is a read operation, the packet tail of the data packet includes a padding data segment, which is used to generate a clock signal to trigger the first chip to send target data to the second chip. The SPI interface includes a transmit first-in-first-out queue TXFIFO, and the signal line also includes a MISO signal line. The step of performing the corresponding operation based on the operation type, the target operation address, and the target operation value includes: The target data is obtained from the target operation address in the first data format through the APB interface; The target data is converted into a second data format through the data conversion interface, and the second data format is the data format corresponding to the SPI interface. The data packet processing module forwards the target data in the second data format to the TXFIFO, and sends the target data to the second chip through the MISO signal line under the trigger of the clock signal.

4. The method according to claim 1 or 2, characterized in that, When the operation type is a write operation, the step of performing the corresponding operation based on the operation type, the target operation address, and the target operation value includes: The target operation value is written into the target operation address through the APB interface.

5. A data transmission method, characterized in that, Used in a second chip, the second chip includes an SPI2APB bus IP core and an APB interface, the SPI2APB bus IP core is connected to the APB interface, the SPI2APB bus IP core is connected to signal lines, the signal lines include extended signal lines, chip select signal lines, and MOSI signal lines, the method includes: When the second chip is the main chip, a first target level signal is sent to the first chip through the extended signal line, and a second target level signal is sent to the first chip through the chip select signal line, wherein the second target level signal is used to instruct the first chip to start receiving data; Data packets are sent to the first chip via the MOSI signal line. The header of the data packet carries the operation type, the target operation address, and the target operation value.

6. The method according to claim 5, characterized in that, When the operation type is a read operation, the signal line further includes a MISO signal line, and the method further includes: Receive target data sent by the first chip from the MISO signal line; The target data is converted into a first data format through the SPI2APB bus IP core, and then sent to the CPU of the second chip through the APB interface. The first data format is the data format corresponding to the APB interface.

7. A first chip, characterized in that, It includes a processor and a communication interface, the processor being configured to cause the first chip to perform the steps of the method described in any one of claims 1 to 4.

8. A second chip, characterized in that, It includes a processor and a communication interface, the processor being configured to cause the second chip to perform the steps of the method of claim 5 or 6.

9. A data transmission circuit, characterized in that, The device includes the first chip as described in claim 7, the second chip as described in claim 8, and a signal line manager; wherein the chip select signal line and the extended signal line of the first chip are connected to the chip select signal line and the extended signal line of the second chip through the signal line manager.

10. A first chip module, characterized in that, It includes a communication module, a power module, a storage module, and a first chip, wherein: The power module is used to provide power to the first chip module; The storage module is used to store data and instructions; The communication module is used for internal communication within the first chip module, or for communication between the first chip module and external devices. The first chip is used to perform the steps of the method according to any one of claims 1 to 4.

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