Method, system, storage medium and chip for reading a calibrated quantity in a multi-core chip
By introducing a cache access unit into a multi-core chip, the system performance problem caused by large calibrated quantity access latency is solved, achieving data consistency and efficient reading of calibrated quantities across multiple cores, while maintaining no loss in system performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING SEMIDRIVE TECHNOLOGY LTD
- Filing Date
- 2025-05-14
- Publication Date
- 2026-06-16
Smart Images
Figure CN120123287B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip technology, and in particular to a method, system, storage medium, and chip for reading the quantitative data of a multi-core chip. Background Technology
[0002] In applications such as automotive Electronic Control Units (ECUs), it is necessary to measure and calibrate certain parameters of embedded software products running on multi-core chips. This process is called calibration, and these parameters are called calibration values. For multi-core chips, a Universal Measurement and Calibration Protocol (XCP) typically runs in one core. The XCP interacts with the host computer to read and modify the calibration values, and the modified calibration values are shared among multiple cores.
[0003] In a multi-core chip, each core typically contains an independent instruction and data cache. When core A modifies a certain scalar value (VAR1) through XCP, if core B needs to access that VAR1, it is necessary to ensure that core A and core B have cache consistency for VAR1, that is, to ensure that core A and core B read the same VAR1.
[0004] In related technologies, scalar values can be placed in non-cacheable memory areas. In this case, each kernel needs to directly access memory to access any scalar value, which will result in a relatively large access latency. This is especially true when the scalar value is read frequently, which will have a particularly serious impact on system performance. Summary of the Invention
[0005] This application provides a method, system, storage medium, and chip for reading calibration data in a multi-core chip, to solve the problem that when the calibration data is placed in a non-cacheable memory area, each core needs to directly access memory to access the calibration data, resulting in large access latency and affecting system performance. The technical solution is as follows:
[0006] According to a first aspect of this application, a method for reading the quantity of a multi-core chip is provided, which is used in a multi-core chip, wherein the multi-core chip includes at least a first CPU, a second CPU and a memory, and the first CPU includes a first core, a first cache access unit and a first cache line;
[0007] The first kernel obtains the cache address of the target calibrator in the first cache line and sends the cache address to the first cache access unit. The target calibrator is written into the memory by the second CPU and cached from the memory into the calibrator in the first cache line. The first cache line includes multiple cache entries, and each cache entry includes a valid flag bit, the cache address of the target calibrator, and cache data.
[0008] The first cache access unit selects the corresponding target cache item in the first cache line according to the cache address;
[0009] The first cache access unit reads the value of the valid flag bit from the target cache item. The value indicates whether the cached data of the target calibrated quantity is valid. Invalid cached data means that the cached data is inconsistent with the stored data in the memory. Valid cached data means that the cached data is consistent with the stored data in the memory.
[0010] If the value indicates that the cached data of the target calibrated quantity is invalid, the first cache access unit reads the stored data of the target calibrated quantity from the memory and sends the stored data to the first kernel;
[0011] The first kernel receives the target calibrated amount of stored data.
[0012] In one possible implementation, the method further includes:
[0013] The first cache access unit updates the cached data of the target calibrated quantity in the first cache line using the read stored data;
[0014] The first cache access unit modifies the value of the valid flag bit in the target cache item so that the modified value indicates that the cached data is valid.
[0015] In one possible implementation, the method further includes:
[0016] The second CPU sends a cache invalidation request to the first cache access unit, the cache invalidation request including the cache address of the target calibrated quantity;
[0017] The first cache access unit selects the corresponding target cache item in the first cache line according to the cache address;
[0018] The first cache access unit modifies the value of the valid flag bit in the target cache item so that the modified value indicates that the cached data is invalid.
[0019] In one possible implementation, the first cache access unit modifies the value of the valid flag bit in the target cache entry so that the modified value indicates that the cached data is invalid, including:
[0020] The first cache access unit reads the value of the valid flag bit in the target cache item;
[0021] If the value of the valid flag indicates that the cached data is invalid, the first cache access unit does not modify the value of the valid flag.
[0022] If the value of the valid flag indicates that the cached data is valid, the first cache access unit modifies the value of the valid flag in the target cache item so that the modified value indicates that the cached data is invalid.
[0023] In one possible implementation, the second CPU includes a second core, a second cache access unit, and a second cache line; the method further includes:
[0024] The second kernel receives a calibration request from the calibration application for the target calibration value;
[0025] The second kernel calibrates the target calibration value according to the calibration request;
[0026] If the second cache line contains the target calibration value, the second kernel updates the cached data of the target calibration value cached in the second cache line using the calibration content;
[0027] The second kernel uses the cached data to update the stored data of the target calibrated quantity stored in the memory.
[0028] In one possible implementation, the second kernel updates the cached data of the target calibrated value cached in the second cache line using the calibration content, including:
[0029] The second kernel sends the calibration content to the second cache access unit;
[0030] The second cache access unit selects the corresponding target cache item in the second cache line according to the cache address of the target calibrated quantity;
[0031] The second cache access unit updates the cache data in the target cache item using the calibration content.
[0032] In one possible implementation, the method further includes:
[0033] If the value indicates that the cached data of the target calibrated quantity is valid, then the first cache access unit sends the cached data of the target calibrated quantity to the first kernel;
[0034] The first kernel receives the cached data.
[0035] According to a second aspect of this application, a reading system for a multi-core chip is provided, which is used in a multi-core chip, the multi-core chip including at least a first CPU, a second CPU and a memory, wherein the first CPU includes a first core, a first cache access unit and a first cache line;
[0036] The first kernel is used to obtain the cache address of the target calibrator in the first cache line and send the cache address to the first cache access unit. The target calibrator is written into the memory by the second CPU and cached from the memory into the calibrator in the first cache line. The first cache line includes multiple cache entries, and each cache entry includes a valid flag bit, the cache address of the target calibrator, and cache data.
[0037] The first cache access unit is configured to select a corresponding target cache item in the first cache line based on the cache address;
[0038] The first cache access unit is further configured to read the value of the valid flag bit from the target cache item, the value indicating whether the cached data of the target calibrated quantity is valid, the cached data being invalid means that the cached data is inconsistent with the stored data in the memory, and the cached data being valid means that the cached data is consistent with the stored data in the memory;
[0039] If the value indicates that the cached data of the target calibrated quantity is invalid, the first cache access unit is further configured to read the stored data of the target calibrated quantity from the memory and send the stored data to the first kernel;
[0040] The first kernel is also used to receive the stored data of the target calibrated quantity.
[0041] According to a third aspect of this application, a computer-readable storage medium is provided, the storage medium storing at least one instruction, the at least one instruction being loaded and executed by a processor to implement the multi-core chip scalar reading method as described above.
[0042] According to a fourth aspect of this application, a chip is provided, the chip comprising the above-described multi-core chip quantitative reading system.
[0043] The beneficial effects of the technical solution provided in this application include at least the following:
[0044] By introducing a first cache access unit into a multi-core chip, the first core can read the value of the valid flag bit in the first cache line through the first cache access unit. Based on this value, it can determine whether the cached data is valid. If the cached data is valid, it can be read directly from the first cache line, improving read efficiency. If the cached data is invalid, it can be read from the memory to obtain the target calibrated value. This allows the latest data to be read even when the cached data and the stored data are inconsistent after the target calibrated value is updated. Without increasing the complexity and cost of the multi-core chip, the consistency problem of calibrated value between multiple cores is solved without sacrificing system performance, and the cache lines in the CPU can be fully utilized to maximize system performance. Attached Figure Description
[0045] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0046] Figure 1 This is a schematic diagram of the structure of a multi-core chip according to some exemplary embodiments;
[0047] Figure 2 This is a schematic diagram illustrating the structure of a cache access unit according to some exemplary embodiments;
[0048] Figure 3 This is a flowchart of a method for reading the quantitative data of a multi-core chip according to an embodiment of this application;
[0049] Figure 4 This is a flowchart of a calibration method for multi-core chip calibration quantity provided in one embodiment of this application;
[0050] Figure 5 This is a flowchart of a method for reading the quantitative data of a multi-core chip according to an embodiment of this application;
[0051] Figure 6 This is a structural block diagram of a multi-core chip calibration reading system provided in one embodiment of this application. Detailed Implementation
[0052] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.
[0053] A multi-core chip can be a microcontroller unit (MCU), which includes multiple central processing units (CPUs), memory, and a routing arbitrator (Fabric). Each CPU accesses memory through the routing arbitrator. The memory is system memory, which can be random access memory (RAM), flash memory, etc. The routing arbitrator is the bus routing and arbitration unit within the system.
[0054] Each CPU consists of a core, a cache access unit, and cache lines. The core and other CPUs can access cache lines through the cache access unit. For example... Figure 1 As illustrated, this application uses two CPUs as an example. One CPU is referred to as the first CPU, which includes a first core, a first cache access unit, and a first cache line; the other CPU is referred to as the second CPU, which includes a second core, a second cache access unit, and a second cache line. The first core in the first CPU accesses the cache line for the first time through the first cache access unit, and accesses memory through Bus1_1 and the routing arbitrator. The first cache access unit in the first CPU accesses the second cache access unit in the second CPU through Bus1_2, the routing arbitrator, and Bus2_2. Similarly, the second core in the second CPU accesses the cache line for the second time through the second cache access unit, and accesses memory through Bus2_1 and the routing arbitrator. The second cache access unit in the second CPU accesses the first cache access unit in the first CPU through Bus2_2, the routing arbitrator, and Bus1_2.
[0055] The cache line in this application includes multiple cache entries, each representing a scalar cache content. Each cache entry includes at least a validity flag (V), a cache address (Addr), and cache data (Data). Other flags irrelevant to this application are not shown. The scalar value in this application is a value that can only be written to by one CPU but can be read by multiple CPUs, thus preventing dirty data.
[0056] (1) The valid flag V indicates whether the calibrated cached data is valid. We can set two different values for the valid flag V to distinguish whether the cached data is valid. For example, V=0 indicates that the calibrated cached data is invalid, and V=1 indicates that the calibrated cached data is valid.
[0057] (2) The cache address Addr represents the address of the calibrated value in the cache line. Only the high-order bits of the address are needed, and the low-order bits can be ignored. The number of high-order bits is related to the cache size and structure, such as the number of sets in a set-associative cache. Taking a 32KB 4-set associative cache as an example, the number of bits in Addr is 4G / (32KB / 4) = 19 bits.
[0058] (3) Cached data Data represents a calibrated amount of data. Generally, each Data can store a fixed size of data, such as 32 / 64 bytes.
[0059] like Figure 2 As shown, the cache access unit includes a local kernel interface, a remote access interface, a mapping and selection module, and an access control module. The local kernel interface provides an access interface for the local kernel, enabling the kernel to write the calibration content of a local calibrated value into the cache data in the cache line, or to flush the cache data of a local calibrated value from the cache line to memory, or to write the calibration content of an external calibrated value from memory into the cache data in the cache line. The remote access interface provides an access interface for an external CPU, enabling the external CPU to instruct the cache access unit to invalidate the cache data of that calibrated value after calibrating it. The mapping and selection module calculates the intra-group offset based on the cache address sent by the external CPU, and then selects the corresponding cache entry from the cache line based on the intra-group offset. The access control module performs mutual exclusion and necessary synchronization when the kernel and the external CPU access the same cache entry simultaneously.
[0060] like Figure 3 The diagram illustrates a flowchart of a method for reading the calibration quantity of a multi-core chip according to an embodiment of this application. This method for reading the calibration quantity of a multi-core chip can be applied to... Figure 1 In the multi-core chip shown, the method for reading the calibration values of this multi-core chip may include:
[0061] Step 301: The first kernel obtains the cache address of the target scalar in the first cache line and sends the cache address to the first cache access unit. The target scalar is written into memory by the second CPU and cached from memory into the scalar in the first cache line. The first cache line includes multiple cache entries, each of which includes a valid flag bit, the cache address of the target scalar, and cache data.
[0062] The first cache line contains multiple scalar values, including local scalar values and external scalar values. Local scalar values are those that can be calibrated by the first kernel, while external scalar values are those that can be calibrated by the second CPU. In this embodiment, the application scenario is that the first kernel reads the external scalar value from the first cache line, which we refer to as the target scalar value.
[0063] The first kernel sends the cache address of the target scalar value to the first memory access unit through the local kernel interface.
[0064] Step 302: The first cache access unit selects the corresponding target cache item in the first cache line according to the cache address.
[0065] Step 303: The first cache access unit reads the value of the valid flag bit from the target cache entry. This value indicates whether the cached data of the target calibrated quantity is valid. Invalid cached data means that the cached data is inconsistent with the stored data in the memory, and valid cached data means that the cached data is consistent with the stored data in the memory.
[0066] After the second CPU calibrates the target calibration value, it writes the calibration content into memory. However, it doesn't update the cached data of the target calibration value in the first cache access unit, leading to inconsistencies between the cached data and the stored data in memory. To solve this problem, the second CPU can modify the value of the valid flag bit of the target calibration value in the first cache line after writing the calibration content into memory. This value indicates that the cached data of the target calibration value is invalid, causing the first kernel to read the stored data of the target calibration value from memory when it determines that the cached data is invalid.
[0067] The first cache access unit can read the value of the validity flag bit and determine whether the cached data is valid based on the value. For example, when the read value is 0, the first cache access unit determines that the cached data is invalid and executes step 304; when the read value is 1, the first cache access unit determines that the cached data is valid, reads the cached data and feeds it back to the first kernel.
[0068] Step 304: If the value indicates that the cached data of the target calibrated quantity is invalid, the first cache access unit reads the stored data of the target calibrated quantity from the memory and sends the stored data to the first kernel.
[0069] The first cache access unit can obtain the storage address of the target calibrator in the memory, read the stored data from the memory according to the storage address, and feed the stored data back to the first kernel.
[0070] Step 305: The first kernel receives the target calibrated amount of stored data.
[0071] In summary, the method for reading the calibrated quantity in a multi-core chip provided in this application introduces a first cache access unit into the multi-core chip. This allows the first core to read the value of the valid flag bit in the first cache line using the first cache access unit. Based on this value, it determines whether the cached data is valid. If the cached data is valid, it is read directly from the first cache line, improving read efficiency. If the cached data is invalid, it is read from the memory. This allows the latest data to be read even when the cached data and the stored data are inconsistent after updating the target calibrated quantity. Without significantly increasing the complexity and cost of the multi-core chip, this method solves the consistency problem of the calibrated quantity across multiple cores without sacrificing system performance, and fully utilizes the cache lines in the CPU to maximize system performance.
[0072] like Figure 4 The diagram illustrates a flowchart of a calibration method for multi-core chip calibration quantization according to an embodiment of this application. This calibration method can be applied to multi-core chips. The multi-core chip calibration method may include:
[0073] Step 401: The second kernel receives the calibration request from the calibration application for the target calibration quantity.
[0074] The calibration application can send a calibration request to the second kernel via XCP. The calibration request includes the identifier of the target calibration quantity and the calibration content; the second kernel can receive the calibration request.
[0075] Step 402: The second kernel calibrates the target calibration quantity according to the calibration request.
[0076] The second kernel locates the target calibration quantity based on the identifier and updates the original data of the target calibration quantity using the calibration content.
[0077] For example, if the target calibration value is VAR1, the original data is A, and the calibration content is B, then the second kernel will update VAR1=A to VAR1=B.
[0078] If the second cache line contains the target calibrator value, the second kernel needs to update the cache data of the target calibrator value according to the calibration content, that is, execute step 403; if the second cache line does not contain the target calibrator value, the second kernel can use the calibration content to update the stored data of the target calibrator value stored in memory.
[0079] Step 403: If the second cache line contains the target calibrator, the second kernel updates the cached data of the target calibrator in the cache using the calibrator content.
[0080] Specifically, the second kernel updates the cached data of the target calibrated quantity in the second cache line using the calibration content, which may include: the second kernel sending the calibration content to the second cache access unit; the second cache access unit selecting the corresponding target cache entry in the second cache line according to the cache address of the target calibrated quantity; and the second cache access unit updating the cached data in the target cache entry using the calibration content.
[0081] For example, if the target calibration value is VAR1, the original data is A, and the calibration content is B, then the second kernel will change the Data in the target cache item from A to B.
[0082] Step 404: The second kernel uses cached data to update the stored data of the target calibrated quantity in memory.
[0083] The second kernel needs to perform cache flushing to update the target calibrated cache data into memory.
[0084] Step 405: The second CPU sends a cache invalidation request to the first cache access unit. The cache invalidation request includes the cache address of the target scalar value.
[0085] Step 406: The first cache access unit selects the corresponding target cache item in the first cache line based on the cache address.
[0086] The first cache access unit calculates the offset within the group based on the cache address, and then selects the corresponding target cache item from the cache line based on the offset within the group.
[0087] Step 407: The first cache access unit modifies the value of the valid flag bit in the target cache entry so that the modified value indicates that the cached data is invalid.
[0088] Specifically, the first cache access unit modifies the value of the valid flag bit in the target cache entry so that the modified value indicates that the cached data is invalid. This can include: the first cache access unit reading the value of the valid flag bit in the target cache entry; if the value of the valid flag bit indicates that the cached data is invalid, then the first cache access unit does not modify the value of the valid flag bit; if the value of the valid flag bit indicates that the cached data is valid, then the first cache access unit modifies the value of the valid flag bit in the target cache entry so that the modified value indicates that the cached data is invalid.
[0089] For example, the first cache access unit reads the value of the valid flag. If the value is 0, no modification is needed; if the value is 1, the value is modified to 0 to indicate that the cached data is invalid.
[0090] In summary, the calibration method for calibrated values in a multi-core chip provided in this application introduces a first cache access unit into the multi-core chip. This allows the second core to modify the value of the valid flag bit through the first cache access unit after updating the target calibrated value. Based on this value, the cached data is invalidated, enabling the first core to read the stored data of the target calibrated value from memory when the cached data is determined to be invalid. Without significantly increasing the complexity and cost of the multi-core chip, this method solves the consistency problem of calibrated values across multiple cores, without sacrificing system performance, and fully utilizes the cache lines in the CPU to maximize system performance.
[0091] like Figure 5 The diagram illustrates a flowchart of a method for reading the calibration quantity of a multi-core chip according to an embodiment of this application. This method can be applied to multi-core chips. The method for reading the calibration quantity of a multi-core chip may include:
[0092] Step 501: The first kernel obtains the cache address of the target scalar in the first cache line and sends the cache address to the first cache access unit. The target scalar is written into memory by the second CPU and cached from memory into the scalar in the first cache line. The first cache line includes multiple cache entries, each of which includes a valid flag bit, the cache address of the target scalar, and cache data.
[0093] The application scenario of this embodiment is that the first kernel reads the external scalar value in the first cache line, and we refer to this external scalar value as the target scalar value.
[0094] The first kernel sends the cache address of the target scalar value to the first memory access unit through the local kernel interface.
[0095] Step 502: The first cache access unit selects the corresponding target cache item in the first cache line according to the cache address.
[0096] Step 503: The first cache access unit reads the value of the valid flag bit from the target cache entry. This value indicates whether the cached data of the target calibrated quantity is valid. Invalid cached data means that the cached data is inconsistent with the stored data in the memory, and valid cached data means that the cached data is consistent with the stored data in the memory.
[0097] The first cache access unit can read the value of the validity flag bit and determine whether the cached data is valid based on the value. For example, when the read value is 0, the first cache access unit determines that the cached data is invalid and executes step 504; when the read value is 1, the first cache access unit determines that the cached data is valid, reads the cached data and feeds it back to the first kernel.
[0098] Step 504: If the value indicates that the cached data of the target calibrated quantity is invalid, the first cache access unit reads the stored data of the target calibrated quantity from the memory and sends the stored data to the first kernel.
[0099] The first cache access unit can obtain the storage address of the target calibrator in the memory, read the stored data from the memory according to the storage address, and feed the stored data back to the first kernel.
[0100] Step 505: The first cache access unit updates the cached data of the target scalar quantity in the first cache line using the read storage data, and modifies the value of the valid flag bit in the target cache item so that the modified value indicates that the cached data is valid.
[0101] The first cache access unit can update the cached data in the first cache line using the stored data, so that the target scalar amount of data can be read directly from the first cache line next time. In addition, the first cache access unit also needs to modify the value of the validity flag in the target cache entry so that the modified value indicates that the cached data is valid.
[0102] For example, the first cache access unit changes the value of the valid flag from 0 to 1 to indicate that the cached data is valid.
[0103] Step 506: The first kernel receives the target calibrated amount of stored data.
[0104] Step 507: If the value indicates that the cached data of the target calibrated quantity is valid, the first cache access unit sends the cached data of the target calibrated quantity to the first kernel.
[0105] The first cache access unit can directly read the cached data of the target calibrated quantity and send the cached data to the first kernel.
[0106] Step 508: The first kernel receives cached data.
[0107] In summary, the method for reading the calibrated quantity in a multi-core chip provided in this application introduces a first cache access unit into the multi-core chip. This allows the first core to read the value of the valid flag bit in the first cache line using the first cache access unit. Based on this value, it determines whether the cached data is valid. If the cached data is valid, it is read directly from the first cache line, improving read efficiency. If the cached data is invalid, it is read from the memory. This allows the latest data to be read even when the cached data and the stored data are inconsistent after updating the target calibrated quantity. Without significantly increasing the complexity and cost of the multi-core chip, this method solves the consistency problem of the calibrated quantity across multiple cores without sacrificing system performance, and fully utilizes the cache lines in the CPU to maximize system performance.
[0108] like Figure 6 The diagram illustrates a structural block diagram of a multi-core chip calibration quantitative reading system according to an embodiment of this application. This multi-core chip calibration quantitative reading system can be applied to... Figure 1 The multi-core chip shown includes at least a first CPU 610, a second CPU 620, and a memory. The first CPU 610 includes a first core 611, a first cache access unit 612, and a first cache line 613.
[0109] The first core 611 is used to obtain the cache address of the target calibrator in the first cache line 613 and send the cache address to the first cache access unit 612. The target calibrator is written into the memory by the second CPU 620 and cached from the memory into the calibrator in the first cache line 613. The first cache line 613 includes multiple cache entries, each cache entry including a valid flag bit, the cache address of the target calibrator, and cache data.
[0110] The first cache access unit 612 is used to select the corresponding target cache item in the first cache line 613 according to the cache address;
[0111] The first cache access unit 612 is also used to read the value of the valid flag bit from the target cache entry. The value indicates whether the cached data of the target calibrated quantity is valid. Invalid cached data means that the cached data is inconsistent with the stored data in the memory, and valid cached data means that the cached data is consistent with the stored data in the memory.
[0112] If the value indicates that the cached data of the target calibrated quantity is invalid, the first cache access unit 612 is also used to read the stored data of the target calibrated quantity from the memory and send the stored data to the first kernel 611;
[0113] The first core, 611, is also used to receive the target calibrated amount of stored data.
[0114] In an optional embodiment, the first cache access unit 612 is further configured to:
[0115] Update the cached data of the target scalar value in the first cache line 613 using the read stored data;
[0116] Modify the value of the validity flag in the target cache entry so that the modified value indicates that the cached data is valid.
[0117] In an optional embodiment, the second CPU 620 is further configured to send a cache invalidation request to the first cache access unit 612, the cache invalidation request including the cache address of the target scalar value;
[0118] The first cache access unit 612 is also used to select the corresponding target cache item in the first cache line 613 according to the cache address;
[0119] The first cache access unit 612 is also used to modify the value of the valid flag bit in the target cache entry so that the modified value indicates that the cached data is invalid.
[0120] In an optional embodiment, the first cache access unit 612 is further configured to:
[0121] Read the value of the valid flag bit in the target cache entry;
[0122] If the value of the valid flag indicates that the cached data is invalid, then the value of the valid flag will not be modified.
[0123] If the value of the valid flag indicates that the cached data is valid, then modify the value of the valid flag in the target cache entry so that the modified value indicates that the cached data is invalid.
[0124] In an optional embodiment, the second CPU 620 includes a second core 621, a second cache access unit 622, and a second cache line 623. The second core 621 is further configured to:
[0125] Receive calibration requests from calibration applications for the target calibration quantity;
[0126] The target calibration quantity is calibrated according to the calibration request;
[0127] If the second cache line 623 contains the target calibration value, then the cached data of the target calibration value cached in the second cache line 623 is updated using the calibration content;
[0128] Update the stored data of the target calibrated quantity in memory using cached data.
[0129] In an optional embodiment, the second kernel 621 is further configured to send the calibration content to the second cache access unit 622;
[0130] The second cache access unit 622 is also used to select the corresponding target cache item in the second cache line 623 according to the cache address of the target scalar quantity;
[0131] The second cache access unit 622 is also used to update the cache data in the target cache item using the calibrated content.
[0132] In an optional embodiment, if the numerical value indicates that the cached data of the target calibrated quantity is valid, the first cache access unit 612 is further configured to send the cached data of the target calibrated quantity to the first kernel 611.
[0133] The first kernel, 611, was also used to receive cached data.
[0134] In summary, the multi-core chip calibration reading system provided in this application introduces a first cache access unit into the multi-core chip. This allows the first core to read the value of the valid flag bit in the first cache line using the first cache access unit. Based on this value, it determines whether the cached data is valid. If the cached data is valid, it is read directly from the first cache line, improving reading efficiency. If the cached data is invalid, it is read from the memory. This allows the system to read the latest data even when the cached data and the stored data are inconsistent after updating the target calibration. Without significantly increasing the complexity and cost of the multi-core chip, it solves the consistency problem of calibration across multiple cores without sacrificing system performance, and fully utilizes the cache lines in the CPU to maximize system performance.
[0135] One embodiment of this application provides a computer-readable storage medium storing at least one instruction, which is loaded and executed by a processor to implement the method for reading calibrated quantities in a multi-core chip as described above.
[0136] One embodiment of this application provides a chip, which includes the quantitative reading system described above for any multi-core chip.
[0137] It should be noted that the multi-core chip calibration quantity reading system provided in the above embodiments is only illustrated by the division of the functional modules described above. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the multi-core chip calibration quantity reading system can be divided into different functional modules to complete all or part of the functions described above. Furthermore, the multi-core chip calibration quantity reading system and the multi-core chip calibration quantity reading method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, which will not be repeated here.
[0138] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.
[0139] The above description is not intended to limit the embodiments of this application. Any adjustments, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of the embodiments of this application.
Claims
1. A method for reading the quantitative data of a multi-core chip, characterized in that, Used in a multi-core chip, the multi-core chip is a microcontroller unit (MCU), the multi-core chip includes at least a first CPU, a second CPU and a memory, the first CPU includes a first core, a first cache access unit and a first cache line, the first cache access unit includes a local kernel interface, a remote access interface, a mapping and selection module; The first kernel obtains the cache address of the target calibrator in the first cache line and sends the cache address to the first cache access unit through the local kernel interface. The target calibrator is written into the memory by the second CPU and cached from the memory into the calibrator in the first cache line. The first cache line includes multiple cache entries, each cache entry representing the cache content of a calibrator, including a valid flag, the cache address of the target calibrator, and cache data. The first cache access unit selects the corresponding target cache item in the first cache line according to the cache address; The first cache access unit reads the value of the valid flag bit from the target cache item. The value indicates whether the cached data of the target calibrated quantity is valid. Invalid cached data means that the cached data is inconsistent with the stored data in the memory. Valid cached data means that the cached data is consistent with the stored data in the memory. If the value indicates that the cached data of the target calibrated quantity is invalid, the first cache access unit reads the stored data of the target calibrated quantity from the memory and sends the stored data to the first kernel through the local kernel interface; The first kernel receives the stored data of the target calibrated quantity; The method further includes: after the second kernel updates the storage data of the target scalar quantity stored in the memory, the second CPU sends a cache invalidation request to the first cache access unit through the remote access interface, the cache invalidation request including the cache address of the target scalar quantity; the first cache access unit, through the mapping and selection module, ignores the low bits in the cache address, calculates the intra-group offset based on the high bits in the cache address, and then selects the corresponding target cache entry in the first cache line based on the intra-group offset, the number of high bits being related to the cache size and structure; The first cache access unit modifies the value of the valid flag bit in the target cache item so that the modified value indicates that the cached data is invalid.
2. The method for reading the quantitative data of a multi-core chip according to claim 1, characterized in that, The method further includes: The first cache access unit updates the cached data of the target calibrated quantity in the first cache line using the read stored data; The first cache access unit modifies the value of the valid flag bit in the target cache item so that the modified value indicates that the cached data is valid.
3. The method for reading the quantitative data of a multi-core chip according to claim 1, characterized in that, The first cache access unit modifies the value of the valid flag bit in the target cache entry so that the modified value indicates that the cached data is invalid, including: The first cache access unit reads the value of the valid flag bit in the target cache item; If the value of the valid flag indicates that the cached data is invalid, the first cache access unit does not modify the value of the valid flag. If the value of the valid flag indicates that the cached data is valid, the first cache access unit modifies the value of the valid flag in the target cache item so that the modified value indicates that the cached data is invalid.
4. The method for reading the quantitative data of a multi-core chip according to claim 1, characterized in that, The second CPU includes a second core, a second cache access unit, and a second cache line. The method further includes: The second kernel receives a calibration request from the calibration application for the target calibration value; The second kernel calibrates the target calibration value according to the calibration request; If the second cache line contains the target calibration value, the second kernel updates the cached data of the target calibration value cached in the second cache line using the calibration content; The second kernel uses the cached data to update the stored data of the target calibrated quantity stored in the memory.
5. The method for reading the quantitative data of a multi-core chip according to claim 4, characterized in that, The second kernel updates the cached data of the target calibrated quantity cached in the second cache line using the calibrated content, including: The second kernel sends the calibration content to the second cache access unit; The second cache access unit selects the corresponding target cache item in the second cache line according to the cache address of the target calibrated quantity; The second cache access unit updates the cache data in the target cache item using the calibration content.
6. The method for reading the quantitative data of a multi-core chip according to any one of claims 1 to 5, characterized in that, The method further includes: If the value indicates that the cached data of the target calibrated quantity is valid, then the first cache access unit sends the cached data of the target calibrated quantity to the first kernel; The first kernel receives the cached data.
7. A system for reading the quantity of data from a multi-core chip, characterized in that, Used in a multi-core chip, the multi-core chip is a microcontroller unit (MCU), the multi-core chip includes at least a first CPU, a second CPU and a memory, the first CPU includes a first core, a first cache access unit and a first cache line, the first cache access unit includes a local kernel interface, a remote access interface, a mapping and selection module; The first kernel is used to obtain the cache address of the target calibrator in the first cache line and send the cache address to the first cache access unit through the local kernel interface. The target calibrator is written into the memory by the second CPU and cached from the memory into the calibrator in the first cache line. The first cache line includes multiple cache entries, each cache entry representing the cache content of a calibrator, including a valid flag, the cache address of the target calibrator, and cache data. The first cache access unit is configured to select a corresponding target cache item in the first cache line based on the cache address; The first cache access unit is further configured to read the value of the valid flag bit from the target cache item, the value indicating whether the cached data of the target calibrated quantity is valid, the cached data being invalid means that the cached data is inconsistent with the stored data in the memory, and the cached data being valid means that the cached data is consistent with the stored data in the memory; If the value indicates that the cached data of the target calibrated quantity is invalid, the first cache access unit is further configured to read the stored data of the target calibrated quantity from the memory and send the stored data to the first kernel through the local kernel interface; The first kernel is also configured to receive the stored data of the target calibrated quantity; The second CPU is further configured to, after the second core updates the storage data of the target calibrated quantity stored in the memory, send a cache invalidation request to the first cache access unit through the remote access interface, the cache invalidation request including the cache address of the target calibrated quantity; the first cache access unit is further configured to, through the mapping and selection module, ignore the low-order bits in the cache address, calculate the intra-group offset based on the high-order bits in the cache address, and then select the corresponding target cache item in the first cache line based on the intra-group offset, the number of high-order bits being related to the cache size and structure; The first cache access unit is further configured to modify the value of the valid flag bit in the target cache item so that the modified value indicates that the cached data is invalid.
8. A computer-readable storage medium, characterized in that, The storage medium stores at least one instruction, which is loaded and executed by a processor to implement the method for reading the calibrated quantity of a multi-core chip as described in any one of claims 1 to 6.
9. A chip, characterized in that, The chip includes the quantitative reading system for multi-core chips as described in claim 7.