Machine learning enhanced compiler

Abstract

One method includes: generating a netlist for a circuit design; and predicting a first compilation time for the circuit design by applying a first machine learning model to the netlist. The method further includes predicting a first placement and routing strategy based on the first compilation time by applying a second machine learning model to the netlist. The method also includes adjusting the logic of the circuit design according to the first placement and routing strategy.

Description

Technical Field

[0001] This disclosure relates to compilers used in the design of circuits or electrical components. Background Technology

[0002] Designs for circuits or electrical components are programmed and compiled (e.g., for verification purposes). Program code for the design can be written and compiled to create virtual circuits or electronic components. For example, code for the design can be compiled to simulate one or more field-programmable gate arrays (FPGAs) performing the design's operations. Test signals can then be sent through the virtual circuit or electrical component to test the design. Summary of the Invention

[0003] In one embodiment, a method includes: generating a netlist for a circuit design, and predicting a first compilation time for the circuit design by applying a first machine learning model to the netlist. The method further includes predicting a first placement and routing strategy based on the first compilation time by applying a second machine learning model to the netlist. The method also includes adjusting the logic of the circuit design according to the first placement and routing strategy.

[0004] The method may include: predicting a second compile time for circuit design by applying a third machine learning model to the adjusted logic, and predicting a second placement and routing strategy based on the second compile time by applying a fourth machine learning model to the adjusted logic. The method may also include placing components of the circuit design according to the second placement and routing strategy.

[0005] The method may include: predicting a third compilation time for circuit design by applying a fifth machine learning model to the components of the layout, and predicting a third placement and routing strategy based on the third compilation time by applying a sixth machine learning model to the components of the layout. The method may also include routing components according to the third placement and routing strategy.

[0006] This method may include generating a bitstream based on the wiring of the components.

[0007] In some cases, the first and second machine learning models are part of a base model generated using the base data, and the base model is selected from a group including the base model, a tuned model generated using training data generated by compiling multiple circuit designs, and a hybrid model generated using both training data and base data.

[0008] The method may include selecting a base model in response to determining that a first distance between the netlist and the circuit design is less than a second distance between the netlist and the training data used to generate the tuned model, and a third distance between the netlist and the training data used to generate the hybrid model, as well as the base data.

[0009] The method may include: determining a first distance by applying a first weight to the distance between a first feature in a netlist and a first feature in basic data to generate a first weighted distance; applying a second weight to the distance between a second feature in a netlist and a second feature in basic data to generate a second weighted distance; and adding the first weighted distance to the second weighted distance.

[0010] This method may include a separate compilation of the initial circuit design. In this separate compilation, the logic of the circuit design is adjusted based on a first layout and routing strategy.

[0011] In another embodiment, a method includes: storing a base model generated using basic data, receiving training data generated by compiling multiple circuit designs, and generating a tuned model using the training data. The method also includes generating a hybrid model using the training data and the base data, receiving a selected cost function, and biasing the base model, the tuned model, and the hybrid model using the selected cost function.

[0012] In some cases, a cost function is selected from multiple cost functions, including a first cost function that is biased towards reducing compilation time, a second cost function that is biased towards reducing resource consumption during compilation, and a third cost function that is biased towards reducing both compilation time and resource consumption during compilation.

[0013] The method may include generating a netlist for a circuit design and predicting a first compilation time for the circuit design by applying a first machine learning model to the netlist. The method may also include predicting a first placement and routing strategy based on the first compilation time by applying a second machine learning model to the netlist. The method may further include adjusting the logic of the circuit design according to the first placement and routing strategy.

[0014] The method may include predicting a second compile time for circuit design by applying a third machine learning model to the adjusted logic, and predicting a second placement and routing strategy based on the second compile time by applying a fourth machine learning model to the adjusted logic. The method may also include placing components of the circuit design according to the second placement and routing strategy.

[0015] The method may include predicting a third compilation time for circuit design by applying a fifth machine learning model to the components of the layout, and predicting a third placement and routing strategy based on the third compilation time by applying a sixth machine learning model to the components of the layout. The method may also include routing the components according to the third placement and routing strategy.

[0016] This method may include generating a bitstream based on the wiring of the components.

[0017] The method may include selecting a base model in response to determining that a first distance between the netlist and the circuit design is less than a second distance between the netlist and the training data used to generate the tuned model, and a third distance between the netlist and the training data used to generate the hybrid model, as well as the base data.

[0018] In another embodiment, an apparatus includes a memory and a hardware processor communicatively coupled to the memory. The hardware processor receives instructions to compile a circuit design and, in response to the instructions, generates a netlist for the circuit design. The hardware processor also predicts a first compilation time for the circuit design by applying a first machine learning model to the netlist. The hardware processor further predicts a first placement and routing strategy based on the first compilation time by applying a second machine learning model to the netlist, and adjusts the logic of the circuit design according to the first placement and routing strategy.

[0019] The hardware processor can predict the second compile time of the circuit design by applying a third machine learning model to the adjusted logic, and predict a second placement and routing strategy based on the second compile time by applying a fourth machine learning model to the adjusted logic. The hardware processor can also place components of the circuit design according to the second placement and routing strategy.

[0020] The hardware processor can predict the third compilation time for circuit design by applying a fifth machine learning model to the placed components, and predict a third placement and routing strategy based on the third compilation time by applying a sixth machine learning model to the placed components. The hardware processor can also route components according to the third placement and routing strategy.

[0021] Hardware processors can generate bitstreams based on the wiring of components.

[0022] In some cases, the first and second machine learning models are part of a base model generated using the base data, and the base model is selected from a group that includes the base model, a tuned model generated using training data generated by compiling multiple circuit designs, and a hybrid model generated using both training data and base data. Attached Figure Description

[0023] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings illustrating embodiments of this disclosure. These drawings are intended to provide knowledge and understanding of embodiments of this disclosure and are not intended to limit the scope of this disclosure to these particular embodiments. Furthermore, these drawings are not necessarily drawn to scale.

[0024] Figure 1A An example system for compiling designs of circuits and / or electrical components is shown;

[0025] Figure 1B It shows Figure 1A The compiler device of the example system;

[0026] Figure 1C It shows Figure 1A The compiler device of the example system;

[0027] Figure 2 It shows Figure 1A A flowchart of the process used for compiling the design in an example system;

[0028] Figure 3 It shows the use of Figure 1A Model training for compiler devices in example systems;

[0029] Figure 4 It shows Figure 1A A flowchart of the process used to train a model in an example system;

[0030] Figure 5 It shows the use of Figure 1A The model selection of compiler devices for example systems;

[0031] Figure 6 It shows Figure 1A A flowchart of the process for selecting a model in the example system;

[0032] Figure 7 Flowcharts depict various processes used during the design and manufacture of integrated circuits and / or FPGAs according to some embodiments of this disclosure;

[0033] Figure 8 An abstract diagram of an example simulation system according to some embodiments of the present disclosure is depicted; and

[0034] Figure 9 An abstract diagram of an example computer system in which embodiments of the present disclosure may operate is depicted. Detailed Implementation

[0035] Various aspects of this disclosure relate to a machine learning-enhanced compiler. As previously described, a design of a circuit or electronic component is programmed and compiled to create a virtual circuit or electronic component (e.g., for verification purposes). For example, code for the design can be compiled to simulate one or more FPGAs performing the design operations. The design can then be tested using test signals.

[0036] Compilation can be a very time-consuming and / or resource-intensive task. Compiling program code for complex designs can take a long time and may consume significant computing resources (e.g., processor, memory, and / or network resources). When a project includes code for many different components, compilation can take a very long time (e.g., more than ten hours). In some cases, the compiler may not even have enough resources to perform the compilation, leading to failures.

[0037] For example, a verification team might use a field-FPGA-based prototyping and simulation platform (FPEP) to simulate their ASIC design and build prototypes. In the prototyping flow, they provide a working model of their design for firmware / library development; in the simulation flow, they probe / force data on wires / registers and troubleshoot / debug the "real-time" design. Various compilers on the market help map these designs onto the FPEP.

[0038] These compilers perform numerous steps, such as front-end synthesis, technology mapping, instruction insertion, partitioning, system-level placement and routing, FPGA compilation, and debug database generation. Users recompile their designs using these compilers when register-transfer-level (RTL) / gate-level inputs change or are repaired. Reducing compilation time is crucial for faster turnaround times to achieve design repair and verification signatures.

[0039] One of the most common causes of long compilation times is netlist congestion within FPGA devices. Upstream partitioning tools partition logic into FPGAs based on the logic capacity of the FPGA device on the FPEP. They do not consider the routerbility of the logic within the FPGA, which is affected by various factors such as resource layout on the FPGA device, netlist connectivity, I / O locations, and placement forces acting on cells within the FPGA device. This oversight can lead to post-placement congestion within the FPGA, slowing down vendor routing tools (sometimes exceeding 12 hours) and even resulting in designs that cannot be routed.

[0040] This disclosure provides a compiler that applies machine learning techniques to reduce compilation time and resource consumption. Typically, the compiler applies machine learning models at different stages of compilation to predict whether changes should be made to reduce compilation time or resource consumption. For example, the model may be applied first in the stage of predicting compilation time. If the compilation time exceeds a threshold (e.g., the predicted compilation time can be compared to a threshold, or the predicted compilation time falls within a time range or category defined by certain thresholds), the model can be applied to predict placement and routing strategies to reduce compilation time and / or resource consumption. The predicted placement and routing strategies can then be applied to subsequent stages. In some embodiments, the compiler reduces the duration and resource consumption of the compilation process in this way. In practical applications, the compiler applies machine learning techniques to reduce the time spent on compilation design and / or the resources consumed by the compilation design.

[0041] Furthermore, in some embodiments, the compiler also trains additional machine learning models that can be selectively used. For example, the compiler can train three models: (1) a base model generated using the base data; (2) a tuned model generated using training data from the client site; and (3) a hybrid model generated using both the base data and the training data. The compiler selects the model best suited for compiling a specific design at runtime. (Using Figures 1 to...) Figure 9 Describe the compiler in more detail.

[0042] Figure 1A An example system 100 for testing circuits and / or electronic components is shown. Figure 1A As shown, system 100 includes one or more devices 104, a network 106, and a compiler device 108. Typically, system 100 applies one or more machine learning models to enhance the compilation of a specific design. In some embodiments, system 100 reduces the compilation time and / or resources consumed when compiling the design.

[0043] User 102 uses one or more devices 104 to interact with other components of system 100. For example, user 102 can use device 104 to create designs 110 for circuits or electronic components. Figure 1A In the example, user 102A uses one or more devices 104A to create design 110. User 102 can then use device 104A to communicate design 110 to compiler device 108 for compilation. Figure 1AIn the example, user 102A can use device 104A to communicate design 110 to compiler device 108. Device 104 can receive updates for compilation from compiler device 108. For example, device 104 can be reported by compiler device 108 whether the compilation was successful or unsuccessful. Furthermore, device 104 can receive messages from compiler device 108 indicating how long the compilation took and the amount of resources consumed during compilation.

[0044] Design 110 can be used with any suitable circuit or electrical component. For example, design 110 can be used with integrated circuits, FPGAs, hardware processors, memory arrays, and systems-on-a-chip. Compiler device 108 can be configured to compile each of these designs 110.

[0045] Device 104 includes any suitable device for communicating with components of system 100 via network 106. By way of example and not limitation, device 104 may be a computer, laptop computer, wireless or cellular phone, e-notebook, personal digital assistant, tablet computer, or any other device capable of receiving, processing, storing, and / or communicating information with other components of system 100. Device 104 may also include a user interface, such as a display, microphone, keypad, or other suitable terminal device usable by user 102. Device 104 may include hardware processors, memory, and / or circuitry configured to perform any of the functions or actions of device 104 described herein. For example, a software application designed using software code may be stored in memory and executed by a processor to perform the functions of device 104.

[0046] Network 106 allows communication between various components of system 100. For example, user 102 can communicate via network 106 using device 104. This disclosure contemplates network 106 as any suitable network operable to facilitate communication between components of system 100. Network 106 may include any interconnected system capable of transmitting audio, video, signals, data, messages, or any combination thereof. Network 106 may include all or part of a public switched telephone network (PSTN), public or private data network, local area network (LAN), metropolitan area network (MAN), wide area network (WAN), local, regional, or global communications or computer network, such as the Internet, wired or wireless networks, corporate intranets, or any other suitable communication link operable to facilitate communication between components, including combinations thereof.

[0047] Compiler device 108 applies machine learning techniques to enhance the compilation of the design. In a particular embodiment, by applying machine learning techniques during certain stages of compilation to predict appropriate placement and routing strategies, compiler device 108 reduces the amount of time spent compiling the design and / or the amount of resources consumed during compilation. Figure 1A In the example, compiler device 108 includes processor 112 and memory 114, which can be configured to perform any of the functions or actions of compiler device 108 described herein. Compiler device 108 can be embodied in any suitable number of physical devices. For example, compiler device 108 can be contained in a single computer or server. To expand the computing resources available to compiler device 108, compiler device 108 can be distributed across multiple computers or servers containing multiple processors 112 and memory 114.

[0048] Processor 112 is any electronic circuit communicatively coupled to memory 114 and controlling the operation of compiler device 108, including but not limited to microprocessors, application-specific integrated circuits (ASICs), application-specific instruction set processors (ASIPs), and / or state machines. Processor 112 may be 8-bit, 16-bit, 32-bit, 64-bit, or any other suitable architecture. Processor 112 may include an arithmetic logic unit (ALU) for performing arithmetic and logical operations, processor registers for providing operands to the ALU and storing the results of ALU operations, and a control unit for fetching instructions from memory and executing instructions by directing the coordinated operation of the ALU, registers, and other components. Processor 112 may include other hardware running software to control and process information. Processor 112 executes software stored in memory to perform any of the functions described herein. Processor 112 controls the operation and management of compiler device 108 by processing information received from device 104, network 106, and memory 114. Processor 112 may be a programmable logic device, microcontroller, microprocessor, any suitable processing device, or any suitable combination of the foregoing. Processor 112 is not limited to a single processing device and may include multiple processing devices.

[0049] Memory 114 may permanently or temporarily store data, operating software, or other information of processor 112. Memory 114 may include any or a combination of volatile or non-volatile local or remote devices suitable for storing information. For example, memory 114 may include random access memory (RAM), read-only memory (ROM), magnetic storage devices, optical storage devices, or any other suitable information storage devices or combinations thereof. The software refers to any suitable set of instructions, logic, or code contained in a computer-readable storage medium. For example, the software may be contained in memory 114, a disk, CD, or flash drive. In a particular embodiment, the software may include an application executable by processor 112 to perform one or more of the functions described herein.

[0050] As previously mentioned, compiler device 108 compiles design 110, which communicates with device 104, and applies machine learning techniques during compilation to improve the compilation process. Typically, the compilation process includes... Figure 1A , Figure 1B and Figure 2 The several stages described in [the document]. Using [the document / method / approach]... Figure 7 Describe further details of the compilation process.

[0051] The compilation process begins when compiler device 108 receives design 110 and instructions 116 to compile design 110. Design 110 and instructions 116 may have already been communicated by user 102 and / or device 104. Design 110 can be used with any suitable circuit or electronic component (e.g., integrated circuit, FPGA, hardware processor, memory array, system-on-a-chip, etc.). In response to receiving design 110 and / or instructions 116, compiler device 108 selects a machine learning model 118 to apply to the compilation of design 110. Compiler device 108 can select different(multiple) machine learning models 118 to apply to different stages of compilation. Figure 3 and Figure 4 To describe the training of the selected(multiple) models(118). This will use... Figure 5 and Figure 6 The selection of model 118 is described below. In some embodiments, by applying the selected model 118 to the compilation of design 110, compiler device 108 reduces compilation time and resources consumed during compilation.

[0052] In one embodiment, compilation is a process comprising several distinct phases. At each phase, a selected model 118 can be applied to determine whether changes should be made to improve compilation time and / or resource consumption. Different models 118 can be selected and applied during different phases of compilation. Typically, compilation phases include generating a netlist 120, logic tuning 122, placement 124, and routing 126. In one embodiment, these phases occur sequentially. The compiler device 108 can apply the selected model 118 during one or more of these phases.

[0053] Netlist 120 includes a list of components in the design and a list of connections between those components. Netlist 120 typically includes a list of components in design 110 and a list of connections between those components. Therefore, netlist 120 provides a picture of the structure of design 110. During logic tuning 122, the logic in the design is tuned to optimize its structure and flow. During placement 124, compiler device 108 places virtual components into a virtual design to simulate the design described in netlist 120. During routing 126, the placed components are connected to each other to simulate the design described in netlist 120. After routing 126 is complete, test signals can be sent through the virtual design to generate bitstream 128. User 102 or verification software can then verify bitstream 128 to determine if the design functions as expected.

[0054] During certain stages of compilation, compiler device 108 applies a selected model 118 to determine whether tweaks should be made to improve certain aspects of compilation (e.g., compilation time, resource consumption, power consumption, efficiency, heat generation, and timing). For example, the selected model 118 can be applied to features in netlist 120 to determine whether model 118 should be applied during logic tweaking 122. If model 118 should be applied during logic tweaking 122, model 118 is applied to determine the placement and routing strategy to be applied during logic tweaking 112. Logic tweaking 122 is then performed according to this placement and routing strategy.

[0055] Similarly, the selected model 118 can be applied to the adjusted logic to determine whether model 118 should be applied during layout 124. If model 118 should be applied during layout 124, then model 118 is applied to determine the layout and routing strategy to be applied during layout 124. Layout 124 is then performed according to this layout and routing strategy.

[0056] Similarly, the selected model 118 can be applied to the components of the layout to determine whether model 118 should be applied during routing 126. If model 118 should be applied during routing 126, then model 118 is applied to determine the layout and routing strategy to be applied during routing 126. Routing 126 is then performed according to this layout and routing strategy.

[0057] Figure 1B Further details are provided on how compiler device 108 applies model 118 during compilation. During certain stages of compilation, compiler device 108 applies the selected model 118 to determine whether adjustments should be made to improve certain aspects of compilation (e.g., compilation time, resource consumption, power consumption, efficiency, heat generation, and timing). Figure 1BAs shown, the selected model 118 may include several different models (models A1 130, A2 140, A3 150, B1 136, B2 146 and B3 156) that can be applied during different stages of compilation.

[0058] As an example, after generating netlist 120, compiler device 108 can select model 118 to apply to features of netlist 120. Then, compiler device 108 applies model A1 130 of the selected model 118 to netlist 120. Model A1 130 may be part of the selected model 118, which, upon application, predicts compilation time 132 based on features in netlist 120 (e.g., the number of lookup tables, the number of registers, the number of flip-flops, the number of input / output connections, the number of memories, estimated wiring congestion). Compiler device 108 analyzes the predicted compilation time 132 to determine whether a change should be made to improve compilation. Compiler device 108 may compare compilation time 132 to a threshold 134 to determine whether a change should be made. In some embodiments, compiler device 108 may determine whether compilation time 132 exceeds threshold 134. In some embodiments, compiler device 108 may determine that compilation time 132 falls within a time range or category defined by threshold 134. If the compilation time 132 exceeds the threshold 134, or if the compilation time 132 falls within a time range considered too high, the compiler device 108 can determine that a change should be made. In response, the compiler device 108 applies model B1136 of the selected model 118 to the netlist 120 to predict a placement and routing strategy 138. Model B1136 may be part of the selected model 118, which analyzes characteristics of the netlist 120 (e.g., the number of lookup tables, the number of registers, the number of flip-flops, the number of input / output connections, the number of memories, estimated routing congestion) to predict a placement and routing strategy 138 for tuning the logic of design 110. The placement and routing strategy 138 can reduce the amount of time spent tuning the logic and / or the resources consumed. The compiler device 108 can apply the placement and routing strategy 138 to logic tuning 122.

[0059] If the compilation time 132 does not exceed the threshold 134, or if the compilation time 132 falls within a time range or category considered not too high, then the compiler device 108 can continue with the logic adjustment 122 without applying model B1 136 to the netlist 120. In other words, if the compilation time 132 is not too high, the compiler device 108 can proceed with the logic adjustment 122 without changing the compilation process.

[0060] Then, compiler device 108 applies the selected model 118 during logic tuning 122. As previously mentioned, the model 118 selected during logic tuning 122 may not be the same model 118 selected for netlist 120. Differences in model selection can be attributed to features in netlist 120 changing during logic tuning 122 and / or new features introduced during logic tuning 122. After selecting model 118, compiler device 108 applies model A2 140 of the selected model 118 during logic tuning 122 to predict compile time 142. Compile time 142 may differ from compile time 132 because the logic in the design is tuned during logic tuning 122, and / or because model A2 140 analyzes features of the tuned logic (e.g., the number of lookup tables, the number of registers, the number of flip-flops, the number of input / output connections, the number of memories, estimated wiring congestion) instead of the features of netlist 120. Some of these features may have changed during logic tuning 122. Furthermore, some of these features may be introduced during logic tuning 122 but are not visible in the original netlist 120. Compiler device 108 compares compilation time 142 to a threshold 144 to determine if changes should be made at this point in the compilation process. If compilation time 142 exceeds the threshold 144, or if compilation time 142 falls within a time range or category considered too high, compiler device 108 applies model B2 146 of selected model 118 to the tuned logic to predict placement and routing strategy 148. Model B2 146 may be part of selected model 118 that analyzes characteristics of the tuned logic (e.g., the number of lookup tables, the number of registers, the number of flip-flops, the number of input / output connections, the number of memories, estimated routing congestion) to predict placement and routing strategy 148 for laying out components of the tuned logic. For example, model B2 146 may predict placement and routing strategy 148 that optimally reduces compilation time and / or resources consumed when laying out parts of the virtual design. The compiler device 108 applies layout and routing strategies 148 during layout 124 to adjust the layout of components in the virtual design.

[0061] If the compilation time 142 does not exceed the threshold 144, or if the compilation time 142 falls within a time range or category considered not too high, then the compiler device 108 can continue the compilation process without applying model B2 146. In other words, if the compiler device 108 determines that the compilation time 142 is not too high, then the compiler device 108 can proceed to layout 124 without changing the compilation process.

[0062] During layout 124, compiler device 108 lays out components of the virtual design. Then, compiler device 108 applies a selected model 118 during layout 124. As previously mentioned, the model selected during layout 124 may differ from the model selected during logic adjustment 122 or used for netlist 120. Differences in model selection can be attributed to features that change during layout 124 and / or new features introduced during layout 124. Compiler device 108 applies model A3 150 of the selected model 118 to the components laid out in the virtual design to predict compilation time 152. Model A3 150 may be part of the selected model 118, which analyzes the characteristics of the laid-out components (e.g., the number of lookup tables, the number of registers, the number of flip-flops, the number of input / output connections, the number of memories, estimated wiring congestion) to predict compilation time 152. Some of these characteristics may have changed during layout 124. Furthermore, some of these characteristics may have been introduced during layout 124 but are not available in the original netlist 120 or during logic adjustment 122. Compiler device 108 compares compilation time 152 with threshold 154 to determine whether additional changes should be made to the routing of components in design 110. If compilation time 152 exceeds threshold 154, compiler device 108 applies model B3 156 of selected model 118 to the components laid out in the virtual design. In some embodiments, compiler device 108 determines that compilation time 152 exceeds threshold 154 by determining that compilation time 152 falls within a time range or category considered excessively high as defined by threshold 154. Model B3 156 may be part of selected model 118, which analyzes the characteristics of the laid-out components (e.g., the number of lookup tables, the number of registers, the number of flip-flops, the number of input / output connections, the number of memories, estimated routing congestion) to predict layout and routing strategy 158. Layout and routing strategy 158 may be a strategy for routing the components that reduces compilation time and / or resource consumption during routing 126. Compiler device 108 may apply layout and routing strategy 158 to routing 126.

[0063] If the compilation time 152 does not exceed the threshold 154, the compiler device 108 proceeds to wiring 126 without applying model B3 156. In other words, if the compiler device 108 determines that the predicted compilation time 152 is not too high, the compiler device 108 proceeds to wiring 126 without adjusting the compilation process.

[0064] The compiler device 108 performs routing 126 to route the components laid out in the virtual design. If model B3156 is applied, the compiler device 108 can perform routing 126 based on the placement and routing strategy 158. After the compiler device 108 completes routing 126, it sends test signals through the virtual design to generate a bitstream 128. The user 102 and / or the verification program then verify the bitstream 128 to determine if the virtual design is functioning as expected.

[0065] In some embodiments, when compiler time 132, 142, or 152 is determined to exceed threshold 134, 144, or 154, compiler device 108 initiates a separate compilation process from the original compilation process. For example, if compiler device 108 determines that compilation time 132 exceeds threshold 134, compiler device 108 may initiate a separate compilation process that performs logic adjustment 122 based on placement and routing strategy 138. The original compilation process may proceed to logic adjustment 122 without applying placement and routing strategy 138. Therefore, two separate compilation processes can be performed in parallel. Later in this process, if compilation time 142 exceeds threshold 144, compiler device 108 may again initiate a separate compilation process that applies placement and routing strategy 148 during placement 124. The original compilation process may continue to placement 124 without applying placement and routing strategy 148. Therefore, three independent compilation processes may be performed in parallel. In other words, if compilation time 132 exceeds threshold 134, or if compilation time 142 exceeds threshold 144, or if compilation time 152 exceeds threshold 154, then compiler device 108 may initiate a separate compilation process at the point where compilation time 132, 142, or 152 exceeds threshold 134, 144, or 154. Then, compiler device 108 may apply the appropriate placement and routing strategies 138, 148, or 158 during the separately initiated compilation process.

[0066] In some embodiments, if the compilation time 142 does not exceed a threshold 144 during the original compilation process or a separately initiated compilation process, the separately initiated compilation process is stopped or terminated. As a result, if the compilation time 142 does not exceed the threshold 144, the compiler device 108 can consider the separately initiated compilation processes unnecessary and stop those processes. The initial compilation process can then continue. In some embodiments, when a separately initiated compilation process completes, all remaining compilation processes can be stopped or terminated. In this way, the compiler device 108 considers many different compilation strategies in parallel and uses the result from the fastest completed compilation.

[0067] Figure 1CThis demonstrates how compiler device 108 can be used to improve the compilation process in any general electronic design automation (EDA) process. For example... Figure 1C As shown, the compilation process during EDA can include several stages 120C, 122C, 124C, and 126C. These stages 120C, 122C, 124C, and 126C occur sequentially. Figure 1B In the example, these stages are netlist 120, logic adjustment 122, placement 124, and routing 126. The compiler device 108 can select the model 118 to be applied during one or more stages 120C, 122C, 124C, and 126C of the compilation process. Figure 1B Similarly, the selected model 118 includes models A1130C, A2 140C, A3 150C, B1 136C, B2 146C, and B3 156C. Model 118 can include even more models to accommodate compilation processes with more stages.

[0068] Similar to Figure 1B For example, compiler device 118 may select model 118 during a first phase 120C, and during the first phase 120C, model A1 130C of the selected model 118 is applied to features to predict a specific cost function 132C that indicates user preferences (e.g., compilation time, resource consumption, efficiency, power consumption, heat generation, etc.). This predicted cost function 132C can then be compared with a threshold 134C to determine whether model B1 136C of the selected model 118 should be applied to predict an implementation strategy 138C. If model B1 136C is applied, the implementation strategy 138C is predicted and applied to a second phase 122C. If not, the compilation process proceeds to the second phase 122C.

[0069] This process is repeated for stages 122C, 124C, and so on, as needed. For example, during each of these stages, model 118 can be selected based on the characteristics of those stages. Model A (e.g., model A2 140C or A3 150C) can be applied to predict a cost function (e.g., cost function 142C or 152C). This cost function is compared with a threshold (e.g., threshold 144c or 154c) to determine whether model B (e.g., model B2 146C or 156C) should be applied to predict an implementation strategy (e.g., implementation strategy 148C or 158C). If model B is applied, the implementation strategy is predicted and applied to subsequent stages. If not, the compilation process proceeds to the next stage.

[0070] Figure 2 It shows the compilation Figure 1A , Figure 1B and / or Figure 1C The flowchart illustrates the design process 200 in the example system 100. Typically, the compiler device 108 executes process 200. In a particular embodiment, the compiler device 108 reduces compilation time and / or resources consumed during compilation by executing process 200.

[0071] The compiler device 108 begins by generating a netlist 120 for design 110 in step 202. This design can be for circuits or electronic components, such as an FPGA design. Netlist 120 lists the components of the design and the connections between them. The compiler device 108 can analyze netlist 120 to determine if adjustments should be made during the compilation process.

[0072] In step 204, compiler device 108 predicts compilation times 132, 142, or 152 by applying a first machine learning model 130. The first machine learning model (e.g., Figure 1B Models A1 130, A2 140, or A3 150 in the design can be designed to predict compile time based on features in netlist 120, features of the adjusted logic of design 110, or features of the layout components of design 110.

[0073] In step 206, compiler device 108 determines whether compilation times 132, 142, or 152 exceed thresholds 134, 144, or 154. Compiler device 108 may make this determination by comparing compilation times 132, 142, or 152 with thresholds 134, 144, or 154. In some embodiments, compiler device 108 determines whether compilation times 132, 142, or 152 fall within a time range or category considered too high as defined by thresholds 134, 144, or 154. If compilation times 132, 142, or 152 do not exceed thresholds 134, 144, or 154, compiler device 108 proceeds according to the original compilation process in step 214. In other words, if compilation times 132, 142, or 152 are considered not too high, compiler device 108 proceeds to logic tweaking 122, placement 124, or routing 126 without tweaking the compilation process.

[0074] If the compilation time 132, 142, or 152 exceeds the threshold 134, 144, or 154, compiler device 108 initiates a separate compilation process in 208. In some embodiments, compiler device 108 does not execute 208. In 210, compiler device 108 applies a second machine learning model (e.g., Figure 1BThe second machine learning model (B1 136, B2 146, or B3 156) is used to predict placement and routing strategies 138, 148, or 158. The second machine learning model 136, 146, or 156 can be designed to predict placement and routing strategies 138, 148, or 158, which reduces compilation time and / or resource consumption when applied. Typically, the second machine learning model analyzes features of netlist 120, features of the adjusted design logic 110, or features of the layout components of design 110 to predict placement and routing strategies 138, 148, or 158. In 212, compiler device 108 makes adjustments based on placement and routing strategies 138, 148, or 158 (e.g., adjusting the logic of design 110, adjusting the layout of components of design 110, or adjusting the routing of components of design 110). In other words, compiler device 108 performs logic adjustments 122, layout 124, or routing 126 based on placement and routing strategies 138, 148, or 158.

[0075] Figure 3 A compiler device 108 for training machine learning models in system 100 is illustrated. In one embodiment, compiler device 108 uses... Figure 3 The techniques described in the text are used to generate in Figure 1A , Figure 1B , Figure 1C and Figure 2 The machine learning models used are typically trained by the compiler device 108 to form a set of models that can be applied during the compilation process. These models can be configured to take into account different types of designs. Therefore, in some embodiments, the compiler device 108 can enhance the compilation process for several different types of designs by selecting different models to apply.

[0076] Compiler device 108 stores a base model 304 and base data 306 (e.g., in memory 114). Base model 304 includes one or more machine learning models trained using base data 306. Base data 306 can be generated by compiling common or more common designs of circuits and / or electrical components. Base model 304 can be generated by analyzing base data 306 using machine learning techniques. The manufacturer of compiler device 108 or the developer of software running on compiler device 108 can generate base model 304 and / or base data 306 by compiling common designs. Therefore, when compiler device 108 is initially set up, compiler device 108 can apply base model 304 and / or base data 306 to enhance the compilation of common or more common designs.

[0077] Although the basic model 304 can Figure 1B and Figure 2The process described herein is used, but because the base model 304 and base data 306 are generated using a general or more common design, the base model 304 and / or base data 306 may not be well-suited to the design created by user 102. For example, the base model 304 may be one or more default machine learning models provided to the user, but the base model 304 may not meet the user's expectations. Compiler device 108 can generate additional models that can be selected during compilation and are more suitable for the specific design of user 102. Compiler device 108 may receive one or more designs 302 that can be used (e.g., from users 102A and 102B) to generate these additional models. These designs 302 can be used for any suitable circuit or electronic component (e.g., integrated circuit, FPGA, hardware processor, memory array, system-on-a-chip, etc.). These designs 302 may be created by users 102A and 102B. Compiler device 108 can compile and / or analyze these designs 302 to train additional machine learning models, which can be used to enhance the compilation of subsequent designs generated by users 102A and 102B. In other words, design 302 can be used as a reference design for users 102A and 102B, and compiler device 108 can use these reference designs to design models customized for users 102A and 102B.

[0078] Compiler device 108 compiles and / or analyzes design 302 to generate training data 308. Training data 308 may include information related to the structure of design 302 and information related to the compilation and / or analysis of design 302. For example, training data 308 may identify structural elements in design 302, such as the layout and routing of components. Furthermore, training data 308 may indicate compilation time and / or resources consumed during the compilation of a specific structure in design 302. Compiler device 108 may analyze training data 308 to generate additional machine learning models that can be applied to subsequent compilations. Figure 3 In the example, compiler device 108 analyzes training data 308 to generate a tuned model 310. Compiler device 108 also analyzes both base data 306 and training data 308 to generate a hybrid model 312. As a result, tuned model 310 can be specifically tailored to designs created by users 102A and 102B, while hybrid model 312 can take into account designs created by users 102A and 102B, as well as general or more common designs that compiler device 108 was initially set to handle. These models can be used to enhance subsequent compilation work.

[0079] The compiler device 108 can bias the base model 304, the tuned model 310, and / or the hybrid model 312 based on the preferences of users 102A and 102B. For example, users 102A and 102B can select one or more cost functions 314 that the compiler device 108 uses to bias the base model 304, the tuned model 310, and / or the hybrid model 312. These selected cost functions 314 represent the specific preferences of users 102A and 102B. For example, if users 102A and 102B prefer to reduce compilation time, they can select a cost function 314 that is biased towards reducing compilation time (e.g., possibly at the cost of increased resource consumption). As another example, if users 102A and 102B prefer to reduce resource consumption, they can select a cost function 314 that is biased towards reducing resource consumption (e.g., possibly at the cost of increased compilation time). As another example, if users 102A and 102B prefer reduced compilation time and resource consumption, they can choose a cost function 314 to balance compilation time reduction and resource consumption. Using the selected cost function 314, compiler device 108 can adjust the base model 304, tuned model 310, and / or hybrid model 312 to introduce deviations. In this way, the base model 304, tuned model 310, and / or hybrid model 312 can be adjusted and / or customized according to the preferences of users 102A and 102B. Users 102A and 102B can choose the cost function 314 for any appropriate preferences. For example, users 102A and 102B can choose the cost function 314 to favor power consumption, timing, efficiency, heat generation, etc.

[0080] As an example, if the user selects a cost function 314 that favors aggressively reducing compilation time, compiler device 108 can bias the base model 304, tuned model 310, and hybrid model 312 towards reducing compilation time. Compiler device 108 can modify models B1 136, B2 146, and B3 156 among these models to predict placement and routing strategies 138, 148, and 158. When these strategies are implemented, several different tuning, placement, or routing attempts are made to see which minimizes compilation time. These types of strategies may reduce compilation time but may result in increased resource consumption during compilation. Compiler device 108 can also lower thresholds 134, 144, and 154 to apply models B1 136, B2 146, and B3 156 more frequently to reduce compilation time.

[0081] On the other hand, if the user selects a cost function 314 that indicates a preference for aggressively reducing resource consumption, the compiler device 108 can bias the base model 304, the tuned model 310, and the hybrid model 312 towards reducing resource consumption. The compiler device 108 can modify models B1 136, B2 146, and B3 156 in these models to predict placement and routing strategies 138, 148, and 158, which make minimal adjustments to placement and routing at implementation time. These types of strategies may reduce resource consumption during compilation but may increase compilation time.

[0082] Figure 4 It shows Figure 1A The flowchart illustrates the process 400 for training a model in the example system 100. Typically, the compiler device 108 can execute process 400 to train the model. Figure 1A , Figure 1B , Figure 1C , Figure 2 and Figure 3 The model used. In a particular embodiment, by executing process 400, compiler device 108 reduces the compilation time and / or resource consumption associated with the compilation design.

[0083] The compiler device 108 begins at 402 by compiling multiple designs 302 to generate training data 308. Designs 302 may be created by users 102A and 102B and communicated to the compiler device 108. Designs 302 can be used with any suitable circuit or electronic component (e.g., integrated circuits, FPGAs, hardware processors, memory arrays, etc.). The compiler device 108 can compile and / or analyze designs 302 to generate training data 308. Training data 308 may include information about the structures within designs 302 and the compilation time and / or resources consumed when compiling these structures.

[0084] In step 404, compiler device 108 uses training data 308 to generate tuning model 310. As a result, tuning model 310 is designed to handle the specific designs created by users 102A and 102B. However, this does not mean that tuning model 310 is always the optimal model for the designs of users 102A and 102B.

[0085] In 406, compiler device 108 uses training data 308 and basic data 306 to generate a hybrid model 312. Compiler device 108 can be one or more models among basic model 304, tuned model 310, and / or hybrid model 312 to enhance the compilation of designs from users 102A and 102B. Basic model 304 can be designed to handle general or more common designs. Tuned model 310 can be designed to handle specific designs created by users 102A and 102B. Hybrid model 312 can be designed to consider both general or more common designs and specific designs created by users 102A and 102B.

[0086] In 408, compiler device 108 receives a selected cost function 314. Cost function 314 can be selected by user 102A or 102B based on their compilation preferences. For example, if users 102A and 102B prefer to reduce compilation time, they can choose a cost function 314 that favors reducing compilation time. As another example, if users 102A and 102B prefer to reduce resource consumption during compilation, they can choose a cost function 314 that favors reducing resource consumption. Users 102A and 102B can also choose a cost function 314 that balances compilation time reduction and resource consumption. This disclosure considers users 102A and 102B choosing a cost function 314 that focuses on any suitable preferences of users 102A and 102B. For example, users 102A and 102B can choose a cost function 314 that addresses power consumption, efficiency, and / or heat generation, to name just a few.

[0087] In 410, compiler device 108 uses a selected cost function 314 to bias the base model 304, tuned model 310, and / or hybrid model 312. Compiler device 108 can use the selected cost function 314 to adjust one or more of these models to favor the preferences of users 102A and 102B. As a result, in a particular embodiment, when these models are applied, they will address the preferences and expectations of users 102A and 102B.

[0088] Figure 5 It shows Figure 1A The example system 100 is selected to be the compiler device 108 for the model of the compilation process. In one embodiment, the compiler device 108 uses... Figure 5 The technology described in the text is used to select in Figure 1A , Figure 1B , Figure 1C , Figure 2 , Figure 3 and Figure 4The machine learning models used, particularly the machine learning models selected during different stages of the compilation process. Typically, compiler device 108 selects an appropriate machine learning model based on the characteristics of the design and applies it to the design. In a particular embodiment, by selecting an appropriate model and applying it to the design, compiler device 108 reduces the compilation time and / or resources consumed during compilation.

[0089] As previously described, the compilation process begins when compiler device 108 receives instruction 116. Instruction 116 may include instructions for compiling a specific design. Compiler device 108 receives design 110, which may be an integrated circuit, FPGA, or other design. Instruction 116 may include instructions for compiling design 110. In response to instruction 116, compiler device 108 initiates the complication of design 110. The compilation process includes one or more stages 501. During each stage 501, compiler device 108 may, according to... Figure 5 Example selection: model 118 to be applied.

[0090] For example, during the first stage 501, compiler device 108 generates a netlist 120 for design 110. Netlist 120 includes a list of components in design 110 and a list of connections between these components. Therefore, netlist 120 provides a picture of the structure of design 110. In a particular embodiment, compiler device 108 identifies one or more features 502 of design 110 from netlist 120. For example, netlist 120 may include a list 502 of these features. As another example, compiler device 108 may determine these features 502 by analyzing the list of components and connections in netlist 120. Figure 5 In the example, netlist 120 includes features 502A and 502B. This disclosure considers netlist 120 to include any appropriate number of features 502.

[0091] Then, compiler device 108 selects a machine learning model to be applied to the compilation of design 110 during the first phase 501. To determine which model should be selected, compiler device 108 compares features 502 in netlist 120 with the features listed in those models. Figure 5 In the example, compiler device 108 selects one of the base model 304, tuned model 310, and hybrid model 312 to apply. Compiler device 108 determines which model should be selected by calculating the distance between feature 502 in netlist 120 and the features identified in base model 304, tuned model 310, and hybrid model 312. Figure 5In the example, compiler device 108 determines the distance 510A between feature 502A and feature 504A in base model 304, and the distance 510B between feature 502B and feature 504B in base model 304. Compiler device 108 also determines the distance 512A between feature 502A and feature 506A in tuned model 310, and the distance 512B between feature 502B and feature 506B in tuned model 310. Compiler device 108 also determines the distance 514A between feature 502A and feature 508A in hybrid model 312, and the distance 514B between feature 502B and feature 508B in hybrid model 312. Compiler device 108 can use any suitable processing to determine these distances. For example, compiler device 108 can count multiple differences between features to determine the distance. As another example, compiler device 108 can cluster features and determine the distance between the centroids of the clusters. By analyzing these distances 510, 512, and 514, compiler device 108 can determine which of the basic model 304, tuned model 310, and hybrid model 312 is closest to netlist 120 and / or design 110.

[0092] In some embodiments, compiler device 108 weights distances 510, 512, and 514 based on the importance of certain features 502. Compiler device 108 may apply weights 516 to distances 510, 512, and 514 to create weighted distances 518, 520, and 524. Weights 516 may indicate the relative importance of feature 502 in netlist 120. Figure 5 In the example, weight 516A can correspond to feature 502A, and weight 516B can correspond to feature 502B. As a result, weights 516A and 516B indicate the relative importance of features 502A and 502B. For example, if weight 516A is greater than weight 516B, then feature 502A can be considered more important than feature 502B. On the other hand, if weight 516B is greater than weight 516A, then feature 502B can be considered more important than feature 502A.

[0093] The compiler device 108 applies weights 516 to distances 510, 512, and 514 to generate weighted distances 518, 520, and 524. For example, the compiler device 108 can multiply distance 510A by weight 516A and distance 510B by weight 516B. The compiler device 108 can then add the results of these two multiplications to produce a weighted distance 518. The compiler device 108 can also multiply distance 512A by weight 516A and distance 512B by weight 516B. The compiler device 108 can then sum the results of these multiplications to produce a weighted distance 520. The compiler device 108 can also multiply distance 514A by weight 516A and distance 514B by weight 516B. The compiler device 108 can then sum the results of these multiplications to produce a weighted distance 524. The compiler device 108 can apply any appropriate number of weights 516 to any appropriate number of distances. For example, if netlist 120 includes ten different features 502, then ten different weights 516 can be applied.

[0094] The compiler device 108 selects one of the base model 304, the tuned model 310, and the hybrid model 312 based on weighted distances 518, 520, and 524. For example, the compiler device 108 can select the model with the shortest weighted distance among 518, 520, and 524. If the weighted distance 518 is shorter than the weighted distances 520 and 524, the compiler device 108 selects the base model 304. If the weighted distance 520 is shorter than the weighted distances 518 and 524, the compiler device 108 selects the tuned model 310. If the weighted distance 524 is shorter than the weighted distances 518 and 520, the compiler device 108 selects the hybrid model 312. The compiler device 108 then applies the selected model to the compilation of design 110.

[0095] During a subsequent stage 501 of the compilation process, the compiler process may repeat the procedure to select one of the base model 304, the tuned model 310, and the hybrid model 312. For example, the compiler device 108 may repeat the procedure during logic adjustment 122 and layout 124. Different models may be selected during different stages 501 because feature 502 may change at different stages. For example, even if the base model 304 is selected during the first stage 501, feature 502 may be changed during the second stage so that the tuned model 310 is selected during the second stage 501.

[0096] Figure 6 It shows Figure 1A The flowchart illustrates the process 600 for selecting a model in the example system 100. Typically, the compiler device 108 can execute process 600 to select from... Figure 1A , Figure 1B , Figure 2 , Figure 3 , Figure 4 and Figure 5 The model used in the example. In a particular embodiment, by executing process 600, compiler device 108 reduces the compilation time and / or resources consumed during compilation design.

[0097] The compiler device 108 begins by receiving instruction 116 in 602 to compile design 110. In some embodiments, design 110 is an FPGA design. In response to receiving instruction 116, the compiler device 108 initiates compilation of design 110.

[0098] In step 604, compiler device 108 generates a netlist 120 for design 110. Netlist 120 may include a list of components of design 110 and a list of connections between components. Compiler device 108 may analyze netlist 120 to determine the appropriate model for compilation applied to design 110.

[0099] In step 606, compiler device 108 calculates the distance 518 between netlist 120 and base model 304. In some embodiments, compiler device 108 calculates the distance 518 by determining the distance 510 between features 502 in netlist 120 and features 504 in base model 304. Compiler device 108 may apply weights 516 to these distances 510 to produce the distance 518.

[0100] In step 608, compiler device 108 calculates the distance 520 between netlist 120 and tuning model 310. In some embodiments, compiler device 108 calculates the distance 520 by determining the distance 512 between feature 502 in netlist 120 and feature 506 in tuning model 310. Compiler device 108 may apply weights 516 to these distances 512 to determine the distance 520.

[0101] In step 610, compiler device 108 calculates the distance 524 between netlist 120 and hybrid model 312. In some embodiments, compiler device 108 calculates the distance 524 by determining the distance 514 between features 502 in netlist 120 and features 508 in hybrid model 312. Compiler device 108 then applies weights 516 to these distances 514 to determine the distance 524.

[0102] In step 612, compiler device 108 selects one of the base model 304, tuned model 310, or hybrid model 312 based on calculated distances 518, 520, and 524. In some embodiments, compiler device 108 selects the model with the shortest association distance 518, 520, or 524.

[0103] In 614, compiler device 108 uses the selected model to compile the design. In a particular embodiment, by applying the selected model to the compilation of the design, compiler device 108 reduces compilation time and / or resources consumed during compilation.

[0104] Although examples of compiling FPGA designs have been used, this disclosure contemplates the use of compiler device 108 during the compilation of any suitable device, such as any suitable circuitry and / or any suitable electronic components. For example, compiler device 108 can be used in the design of integrated circuits. Furthermore, although examples of reducing compile-time resource consumption have been described, this disclosure contemplates that compiler device 108 is configured to address any concerns of user 102. For example, user 102 can select any suitable cost function 314 that addresses any user concerns. User 102 can select cost function 314 that focuses on improving factors other than compilation time and resource consumption, such as efficiency, power consumption, etc. Compiler device 108 can bias machine learning models toward the selected cost function 314 such that when these machine learning models are applied during compilation, the machine learning models will predict placement and routing strategies that optimize these other factors.

[0105] Figure 7 A set of example processes 700 used during the design, verification, and manufacturing of artifacts such as integrated circuits or FPGAs are illustrated to transform and verify design data and instructions representing integrated circuits. Each of these processes can be organized and enabled as multiple modules or operations. The term 'EDA' refers to 'Electronic Design Automation'. These processes begin by creating a product concept 710 using information provided by the designer, which is then transformed to create a manufactured article using a set of EDA processes 712. When the design is complete, the design is tape-out 734, which occurs when the original pattern (e.g., geometric pattern) of the integrated circuit is sent to a manufacturing facility to create a mask set, which is then used to manufacture the integrated circuit. After tape-out, a semiconductor die is manufactured 736, and a packaging and assembly process 738 is performed to produce a finished integrated circuit 740.

[0106] Specifications for circuits or electronic structures can range from low-level transistor material placement to high-level description languages. High-level abstractions are used to design circuits and systems using hardware description languages ​​('HDL') such as VHDL, Verilog, System Verilog, SystemC, MyHDL, or OpenVera. This hardware description can be translated into logic-level register-transfer-level ('RTL') descriptions, gate-level descriptions, placement-level descriptions, or mask-level descriptions. Each lower level of abstraction is a less abstract description, adding more useful details to the design description, such as more details about the modules included in the description. Lower levels of abstraction are less abstract descriptions and can be computer-generated, derived from design libraries, or created by another design automation process. An example of a lower-level specification language used to specify a more detailed abstraction language is SPICE, used for detailed descriptions of circuits with many analog components. Descriptions at each level of abstraction can be used by the corresponding tools at that layer (e.g., formal verification tools). The design process can use... Figure 7 The sequence described herein. The described process is enabled by an EDA product (or tool).

[0107] During the system design phase 714, the functionality of the integrated circuit to be manufactured is specified. The design can be optimized for desired characteristics such as power consumption, performance, area (physical and / or lines of code), and cost reduction. At this stage, the design can be divided into different types of modules or components.

[0108] During logic design and functional verification 716, modules or components in a circuit are specified in one or more description languages, and the functional accuracy of that specification is checked. For example, components of a circuit can be verified to produce output that matches the specification requirements of the circuit or system being designed. Functional verification can be performed using simulators and other programs, such as test bench generators, static HDL validators, and formal validators. In some embodiments, a special component system referred to as a 'simulator' or 'prototype system' is used to accelerate functional verification.

[0109] During test synthesis and design 718, HDL code is converted into a netlist. In some embodiments, the netlist can be a graph structure, where edges represent components of the circuit and nodes represent how the components are interconnected. Both HDL code and netlist are tiered manufacturing products that EDA products can use to verify that an integrated circuit performs as specified during manufacturing. The netlist can be optimized for a target semiconductor manufacturing technology. Furthermore, the completed integrated circuit can be tested to verify that it meets specification requirements.

[0110] During netlist verification (720), the netlist is checked to ensure it meets timing constraints and is consistent with the HDL code. During design planning (722), the overall planar diagram of the integrated circuit is built and analyzed for timing and top-level routing.

[0111] During layout or physical implementation 724, physical layout (e.g., the positioning of circuit components such as transistors or capacitors) and wiring (connecting circuit components through multiple conductors) occur, and cells can be selected from a library to implement a specific logic function. As used herein, the term 'cell' can specify a set of transistors, other components, and interconnections that provide Boolean logic functions (e.g., AND, OR, NOT, XOR) or storage functions (e.g., flip-flops or latches). As used herein, a circuit 'block' can refer to two or more cells. Both cells and circuit blocks can be referred to as modules or components and can be enabled as physical structures and in simulation. Parameters (based on "standard cells") are specified for the selected cells, such as size, and they are made accessible in a database for use in EDA products.

[0112] During Analysis and Extraction 726, circuit functionality is verified at the layout level, allowing for improvements to the layout design. During Physical Verification 728, the layout design is checked to ensure that manufacturing constraints are correct, such as DRC constraints, electrical constraints, and lithographic constraints, and that the circuit functionality matches the HDL-type design specification. During Resolution Enhancement 730, the geometry of the layout is transformed to improve how the circuit design is manufactured.

[0113] During the tape-out process, data is created for the production of a photomask (if appropriate, after the application of photolithography enhancement). During mask data preparation 732, the photomask is used to produce the final integrated circuit.

[0114] Computer systems (e.g., Figure 9 Computer system 900 or Figure 8 The storage subsystem of the host system (807) can be used to store programs and data structures used by some or all of the EDA products described herein, as well as units for developing libraries and products for physical and logical designs for using libraries.

[0115] Figure 8An abstract diagram of an example simulation environment 800 is depicted. The simulation environment 800 can be configured to verify the functionality of a circuit design. The simulation environment 800 may include a host system 807 (e.g., a computer as part of an EDA system) and a simulation system 802 (e.g., a set of programmable devices such as a field-programmable gate array (FPGA) or processor). The host system generates data and information by using a compiler 810 to construct the simulation system to simulate the circuit design. The circuit design to be simulated is also referred to as a design under test (DUT), where data and information from the simulation are used to verify the functionality of the DUT.

[0116] The host system 807 may include one or more processors. In embodiments where the host system includes multiple processors, the functions performed by the host system described herein may be distributed across multiple processors. The host system 807 may include a compiler 810 to transform a specification written in a description language to represent the DUT and to generate data (e.g., binary data) and information for constructing the simulation system 802 to simulate the DUT. The compiler 810 may transform, modify, refactor, add new functions to the DUT, and / or control the timing of the DUT.

[0117] The host system 807 and the emulation system 802 exchange data and information using signals carried by an emulation connection. This connection can be, but is not limited to, one or more cables, such as cables with pin configurations compatible with recommended standard RS232 or Universal Serial Bus (USB) protocols. The connection can be a wired communication medium or network, such as a local area network (LAN) or a wide area network (WAN), such as the Internet. The connection can also be a wireless communication medium or a network with one or more access points using wireless protocols such as Bluetooth or IEEE 802.11. The host system 807 and the emulation system 802 can exchange data and information via a third device, such as a network server.

[0118] The simulation system 802 includes multiple FPGAs (or other modules), such as FPGAs 8041 and 8042, as well as additional FPGAs up to 804. N Each FPGA may include one or more FPGA interfaces through which it connects to other FPGAs (and potentially other emulation components) to exchange signals. FPGA interfaces may be referred to as input / output pins or FPGA pads. While an emulator may include an FPGA, embodiments of the emulator may include alternative FPGAs used to emulate the DUT or other types of logic blocks used in conjunction with the FPGA used to emulate the DUT. For example, emulation system 802 may include a custom FPGA, a dedicated ASIC for emulation or prototyping, memory, and input / output devices.

[0119] Programmable devices may include an array of programmable logic blocks and an interconnection hierarchy that enables the programmable logic blocks to interconnect according to a description in HDL code. Each programmable logic block may enable complex combinational functions or enable logic gates, such as AND logic blocks and XOR logic blocks. In some embodiments, logic blocks may also include memory elements / devices, which may be simple latches, flip-flops, or other memory blocks. Depending on the length of the interconnection between different logic blocks, signals may arrive at the inputs of the logic blocks at different times, thus allowing them to be temporarily stored in the memory elements / devices.

[0120] FPGA 8041-804 N Arranged on one or more plates 8121 and 8122 and additional plate 812 M Above. Multiple boards can be laid out in simulation unit 8141. The boards within the simulation unit can be connected using the simulation unit's baseboard or any other type of connection. Furthermore, multiple simulation units (e.g., 8141 and 8142 to 814) can be configured. K They can be connected to each other by cables or any other means to form a multi-simulation unit system.

[0121] For a DUT to be simulated, the host system 807 sends one or more bit files to the simulation system 802. The bit files can specify a description of the DUT and can further specify partitions of the DUT created by the host system 807 using trace and injection logic, the mapping of partitions to the simulator's FPGA, and design constraints. The simulator uses the bit files to construct the FPGA to perform the functionality of the DUT. In some embodiments, one or more FPGAs of the simulator can have the trace and injection logic built into the silicon of the FPGA. In such embodiments, the host system may not build the FPGA to simulate the trace and injection logic.

[0122] The host system 807 receives a description of the DUT to be simulated. In some embodiments, the DUT description uses a description language (e.g., Register Transfer Language (RTL)). In some embodiments, the DUT description is a netlist-level file or a mixture of a netlist-level file and an HDL file. If part or all of the DUT description is in HDL, the host system can synthesize the DUT description to create a gate-level netlist using the DUT description. The host system can use the DUT's netlist to partition the DUT into multiple partitions, where one or more partitions include tracing and injection logic. The tracing and injection logic tracks interface signals exchanged through the FPGA's interface. Furthermore, the tracing and injection logic can inject the tracked interface signals into the FPGA's logic. The host system maps each partition to the emulator's FPGA. In some embodiments, the tracing and injection logic is included in selected partitions for a set of FPGAs. The tracing and injection logic can be built into one or more FPGAs of the emulator. The host system can synthesize multiplexers to map into the FPGA. The tracing and injection logic can use multiplexers to inject interface signals into the DUT logic.

[0123] The host system creates a bit file describing each partition of the DUT and its mapping to the FPGAs. For partitions containing tracing and injection logic, the bit file also describes the contained logic. The bit file may include placement and routing information as well as design constraints. The host system stores the bit file and information describing which FPGAs will emulate each component of the DUT (e.g., which FPGA each component maps to).

[0124] Upon request, the host system transfers the bit file to the emulator. The host system signals the emulator to begin DUT simulation. During or at the end of DUT simulation, the host system receives simulation results from the emulator via the simulation connection. The simulation results are data and information generated by the emulator during DUT simulation, including interface signals and their states, which have been traced and injected by the tracing logic of each FPGA. The host system can store the simulation results and / or send them to another processing system.

[0125] After simulating the DUT, the circuit designer can request to debug components of the DUT. If such a request is made, the circuit designer can specify the time period for the simulation to be debugged. The host system uses stored information to identify which FPGAs are simulating the component. The host system retrieves stored interface signals associated with that time period and traced by the trace and injection logic of each identified FPGA. The host system signals the emulator to re-simulate the identified FPGA. The host system sends the retrieved interface signals to the emulator to re-simulate the component within the specified time period. The trace and injection logic of each identified FPGA injects its respective interface signals received from the host system into the logic of the DUT mapped to that FPGA. In the case of multiple FPGA re-simulations, the combined results produce a complete debug view.

[0126] During component re-simulation, the host system receives signals traced by the logic of the identified FPGA from the simulation system. The host system stores the signals received from the simulator. Signals traced during re-simulation can have a higher sampling rate than those during the initial simulation. For example, in the initial simulation, the traced signals might include component states saved every X milliseconds. However, in the re-simulation, the traced signals might include states saved every Y milliseconds, where Y is less than X. If the circuit designer requests to view the waveform of the signals traced during re-simulation, the host system can retrieve the stored signals and display a graph of those signals. For example, the host system can generate the waveform of the signals. Afterward, the circuit designer can request to re-simulate the same component or another component at different time periods.

[0127] The host system 807 and / or compiler 810 may include subsystems, such as, but not limited to, a design synthesizer subsystem, a mapping subsystem, a runtime subsystem, a results subsystem, a debugging subsystem, a waveform subsystem, and a storage subsystem. Subsystems can be built and enabled as single or multiple modules, or two or more modules can be built as a module. These subsystems together constitute the simulator and monitor simulation results.

[0128] The design synthesizer subsystem translates the hardware description language representing the DUT 805 into gate-level logic. For a DUT to be simulated, the design synthesizer subsystem receives the description of that DUT. If the DUT's description is entirely or partially in HDL (e.g., RTL or other levels of abstraction), the design synthesizer subsystem synthesizes the DUT's HDL to create a gate-level netlist that contains a description of the DUT based on the gate-level logic.

[0129] The mapping subsystem partitions the DUT and maps the partitions to the simulator FPGA. The mapping subsystem uses the DUT's netlist to divide the gate-level DUT into multiple partitions. For each partition, the mapping subsystem retrieves the gate-level description of the tracing and injection logic and adds that logic to the partition. As described above, the tracing and injection logic included in the partition is used to trace signals exchanged via the interface of the FPGA mapped to that partition (tracing interface signals). The tracing and injection logic can be added to the DUT before partitioning. For example, the tracing and injection logic can be added by the design synthesizer subsystem before or after synthesizing the HDL language of the DUT.

[0130] In addition to including tracing and injection logic, the mapping subsystem can also include additional tracing logic within partitions to track the state of certain DUT components that are not traced or injected. The mapping subsystem can include this additional tracing logic in the DUT before partitioning or in partitions after partitioning. The design synthesizer subsystem can include this additional tracing logic in the DUT's HDL description before synthesizing the HDL description.

[0131] The mapping subsystem maps each partition of the DUT to an FPGA of the simulator. For partitioning and mapping, the mapping subsystem uses design rules, design constraints (e.g., timing or logic constraints), and information about the simulator. For components of the DUT, the mapping subsystem stores information in the storage subsystem describing which FPGAs will be simulated for each component.

[0132] Using partitioning and mapping, the mapping subsystem generates one or more bit files that describe the created partitions and the mapping of logic to each FPGA in the simulator. The bit files may include additional information such as constraints of the DUT and wiring information for connections between FPGAs and connections within each FPGA. The mapping subsystem can generate a bit file for each partition of the DUT and can store this bit file in the storage subsystem. Upon request from the circuit designer, the mapping subsystem transfers the bit file to the simulator, and the simulator can use the bit file to construct the FPGA to simulate the DUT.

[0133] If the simulator includes a dedicated ASIC that includes tracking and injection logic, the mapping subsystem can generate a specific structure for connecting the dedicated ASIC to the DUT. In some embodiments, the mapping subsystem can store information about the tracking / injection signals and the location on the dedicated ASIC where that information is stored.

[0134] The runtime subsystem controls the simulation performed by the emulator. It can start or stop the emulator from performing the simulation. Furthermore, the runtime subsystem can provide input signals and data to the emulator. Input signals can be provided directly to the emulator via a connection or indirectly via other input signal devices. For example, the host system can control input signal devices to provide input signals to the emulator. Input signal devices can be, for example, test boards (directly or via cable), signal generators, another emulator, or another host system.

[0135] The results subsystem processes the simulation results generated by the simulator. During and / or after simulation, the results subsystem receives the simulation results generated during simulation from the simulator. The simulation results include signals traced during simulation. Specifically, the simulation results include interface signals traced by the trace and injected logic traced by each FPGA, and may include signals traced by additional logic traced in the DUT. Each trace signal may span multiple simulation cycles. The trace signal includes multiple states, and each state is associated with a time interval of the simulation. The results subsystem stores the trace signals in the storage subsystem. For each stored signal, the results subsystem may store information indicating which FPGA generated the trace signal.

[0136] The debug subsystem allows circuit designers to debug DUT components. After the simulator has simulated the DUT and the results subsystem has received interface signals traced by the tracking and injection logic during simulation, the circuit designer can request to debug a component of the DUT by resimulating the component for a specific time period. In the request to debug a component, the circuit designer identifies the component and indicates the simulation period to be debugged. The circuit designer's request may include a sampling rate, which indicates how frequently the logic tracing the signals should save the state of the component being debugged.

[0137] The debug subsystem uses information stored in the storage subsystem by the mapping subsystem to identify one or more FPGAs of the simulator of the component being simulated. For each identified FPGA, the debug subsystem retrieves from the storage subsystem the interface signals traced by the FPGA's trace and injected logic during a time period indicated by the circuit designer. For example, the debug subsystem retrieves the state of the trace and injected logic traces associated with the time period.

[0138] The debug subsystem sends the retrieved interface signals to the simulator. The debug subsystem instructs the tracing and injection logic of each identified FPGA to inject its respective tracing signals into the FPGA's logic to re-emulate the component within the requested time period. The debug subsystem can also transmit a sampling rate provided by the circuit designer to the simulator, allowing the tracing logic to track the state at appropriate intervals.

[0139] To debug components, the simulator can use the FPGA to which the component is mapped. Furthermore, component re-simulation can be performed at any point specified by the circuit designer.

[0140] For the identified FPGA, the debug subsystem can send instructions to the emulator to load multiple emulator FPGAs with the same configuration as the identified FPGA. The debug subsystem also signals to the emulator to use multiple FPGAs in parallel. Each of the multiple FPGAs is used with different time windows of the interface signals to generate a larger time window within a shorter time frame. For example, the identified FPGA might require an hour or more to use a certain number of cycles. However, if the multiple FPGAs have the same data and the structure of the identified FPGA, and each FPGA represents a subset of the running cycles, the emulator might require several minutes to get all the cycles shared by the FPGAs.

[0141] Circuit designers can identify the hierarchy or list of DUT signals to be re-emulated. To achieve this, the debug subsystem determines the FPGA required to simulate the signal hierarchy or list, retrieves the necessary interface signals, and sends the retrieved interface signals to the emulator for re-emulation. Therefore, circuit designers can identify any element (e.g., component, device, or signal) of the DUT to be debugged / re-emulated.

[0142] The waveform subsystem generates waveforms using the tracked signal. If the circuit designer requests to view the waveform of a signal tracked during simulation execution, the host system retrieves the signal from the storage subsystem. The waveform subsystem displays a graph of the signal. For one or more signals, the waveform subsystem can automatically generate a graph of the signal when it is received from the simulator.

[0143] Figure 9 An example machine of computer system 900 is shown, in which a set of instructions can be executed to cause the machine to perform any or more of the methods discussed herein. In alternative implementations, the machine can be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0144] The machine can be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network equipment, server, network cabling, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) specifying the actions to be taken by the machine. Furthermore, while a single machine is shown, the term "machine" should also be considered as any collection of machines that individually or jointly execute a set (or more) of instructions to perform any one or more of the methods discussed herein.

[0145] Example computer system 900 includes processing device 902, main memory 904 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 906 (e.g., flash memory, static random access memory (SRAM) and the like), and data storage device 918, which communicate with each other via bus 930.

[0146] Processing device 902 represents one or more processors, such as microprocessors, central processing units, etc. More specifically, processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing combinations of instruction sets. Processing device 902 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 902 may be configured to execute instructions 926 to perform the operations and steps described herein.

[0147] The computer system 900 may also include a network interface device 908 for communication via a network 920. The computer system 900 may also include a video display unit 910 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 912 (e.g., a keyboard), a cursor control device 914 (e.g., a mouse), a graphics processing unit 922, a signal generation device 916 (e.g., a speaker), a graphics processing unit 922, a video processing unit 928, and an audio processing unit 932.

[0148] Data storage device 918 may include machine-readable storage medium 924 (also known as non-transitory computer-readable medium) on which one or more sets of instructions 926 or software embodying any one or more methods or functions described herein are stored. During execution of instructions 926 by computer system 900, instructions 926 may also reside wholly or at least partially in main memory 904 and / or processing device 902, which also constitute machine-readable storage media.

[0149] In some implementations, instruction 926 includes instructions that implement the functions corresponding to this disclosure. While machine-readable storage medium 924 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be considered to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine and processing device 902 to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memories, optical media, and magnetic media.

[0150] Based on the algorithms and symbolic representations of operations on data bits within computer memory, some parts have been described in detail above. These algorithmic descriptions and representations are the methods used by those skilled in the art of data processing to most effectively convey the essence of their work to those skilled in the art. An algorithm can be a sequence of operations that leads to a desired result. Operations are those that require physical manipulation of physical quantities. These quantities can take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Such signals can be referred to as bits, values, elements, symbols, characters, items, numbers, etc.

[0151] However, it should be remembered that all these and similar terms will be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise specifically stated, it will be understood that throughout this specification, certain terms refer to the actions and processes of a computer system or similar electronic computing device, which will manipulate data representing physical (electronic) quantities within the registers and memories of the computer system and convert them into other data representing physical quantities similarly represented within the computer system's memory or registers or other such information storage devices.

[0152] This disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specifically constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0153] The algorithms and displays presented herein are not associated with any particular computer or other device. Various other systems may be used with the programs taught herein, or it may be demonstrated that constructing more specialized devices to perform the methods is convenient. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0154] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media include any mechanism for storing information in a machine-readable (e.g., computer-readable) form. For example, machine-readable (e.g., computer-readable) media include machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory devices, etc.

[0155] In the foregoing disclosure, embodiments of the present disclosure have been described with reference to specific exemplary embodiments thereof. It will be apparent that various modifications may be made thereto without departing from the broader spirit and scope of the implementation of the present disclosure as set forth in the following claims. Where the present invention relates to elements in the singular tense, more than one element may be depicted in the drawings, and similar elements are labeled with similar numbers. Therefore, this disclosure and the drawings should be considered illustrative rather than restrictive.

Claims

1. A method comprising: Generate a netlist for the circuit design; By applying a first machine learning model to the netlist, a first amount of time is predicted to complete the compilation of the circuit design. By applying a second machine learning model to the netlist, a first layout and routing strategy is predicted based on the first time quantity exceeding a first threshold. as well as The logic of the circuit design is adjusted according to the first layout and routing strategy; The first machine learning model and the second machine learning model are part of the selection model; as well as The selected model is chosen from the group consisting of: a base model generated using base data, a tuned model generated using training data generated by compiling multiple circuit designs, and a hybrid model generated using the training data and the base data.

2. The method according to claim 1, further comprising: By applying a third machine learning model to the adjusted logic, a second time amount for completing the circuit design is predicted; By applying a fourth machine learning model to the adjusted logic, a second layout and routing strategy is predicted based on the second time quantity exceeding a second threshold; as well as The components of the circuit design are laid out according to the second layout and routing strategy.

3. The method according to claim 2, further comprising: By applying a fifth machine learning model to the laid-out components, a third time amount is predicted to complete the circuit design; By applying a sixth machine learning model to the laid-out components, a third layout and routing strategy is predicted based on the third time quantity exceeding a third threshold; and The components are routed according to the third layout and routing strategy.

4. The method of claim 3, further comprising: A bit stream is generated based on the wiring of the component.

5. The method of claim 1, further comprising: In response to determining that a first distance between the netlist and the circuit design is less than a second distance between the netlist and the training data used to generate the tuning model, and a third distance between the netlist and the training data and the base data used to generate the hybrid model, the selected model is selected; and One of the following: (a) Wherein determining the first distance includes: counting the number of differences between the features of the netlist and the features of the circuit design; Determining the second distance includes: counting the number of differences between the features of the netlist and the features of the training data used to generate the tuning model; and Determining the third distance includes: counting the number of differences between the features of the netlist and the training data and the features of the base data used to generate the hybrid model; or (b) Wherein determining the first distance includes: clustering the features of the netlist and the features of the circuit design and determining the distance between the centroids of the clusters; Determining the second distance includes: clustering the features of the netlist with the features of the training data used to generate the tuning model and determining the distance between the centroids of the clusters; and Determining the third distance includes: clustering the features of the netlist and the training data with the features of the base data used to generate the hybrid model and determining the distance between the centroids of the clusters.

6. The method according to claim 5, further comprising: The first distance is further determined by the following: The first weight is applied to the distance between the first feature in the netlist and the first feature in the basic data to generate a first weighted distance; The second weight is applied to the distance between the second feature in the netlist and the second feature in the basic data to generate a second weighted distance; and Add the first weighted distance and the second weighted distance together.

7. The method according to claim 1, further comprising: Initiate a separate compilation of the circuit design, wherein the logic of the circuit design is adjusted according to the first layout and routing strategy in the separately initiated compilation.

8. A method comprising: Store the basic model generated using basic data; as well as Receive training data generated through compiler circuit design; The training data is used to generate a tuned model; A hybrid model is generated using the training data and the base data; Receive the selected cost function; as well as The base model, the tuned model, and the hybrid model are biased using a selected cost function; The cost function is selected from a plurality of cost functions, including: a first cost function that is biased towards reducing compilation time, a second cost function that is biased towards reducing resource consumption during compilation, and a third cost function that is biased towards reducing both compilation time and resource consumption during compilation.

9. The method according to claim 8, further comprising: Generate a netlist for the circuit design; By applying a first machine learning model to the netlist, a first compilation time for the circuit design is predicted. By applying a second machine learning model to the netlist, a first layout and routing strategy is predicted based on the first compilation time; as well as The logic of the circuit design is adjusted according to the first layout and routing strategy.

10. The method of claim 9, further comprising: By applying a third machine learning model to the adjusted logic, a second compilation time for the circuit design is predicted; By applying a fourth machine learning model to the adjusted logic, a second layout and routing strategy is predicted based on the second compile time; as well as The components of the circuit design are laid out according to the second layout and routing strategy.

11. The method of claim 10, further comprising: By applying a fifth machine learning model to the laid-out components, a third compilation time is predicted for the circuit design; By applying a sixth machine learning model to the laid-out components, a third placement and routing strategy is predicted based on the third compile time; and The components are routed according to the third layout and routing strategy.

12. The method of claim 11, further comprising: A bit stream is generated based on the wiring of the component.

13. The method of claim 9, further comprising: In response to determining that a first distance between the netlist and the circuit design is less than a second distance between the netlist and the training data used to generate the tuning model, and a third distance between the netlist and the training data and the base data used to generate the hybrid model, the base model is selected; as well as One of the following: (a) Wherein determining the first distance includes: counting the number of differences between the features of the netlist and the features of the circuit design; Determining the second distance includes counting the number of differences between the features of the netlist and the features of the training data used to generate the tuning model; and Determining the third distance includes counting the number of differences between the features of the netlist and the training data and the features of the base data used to generate the hybrid model; or (b) Wherein determining the first distance includes: clustering the features of the netlist and the features of the circuit design and determining the distance between the centroids of the clusters; Determining the second distance includes: clustering the features of the netlist with the features of the training data used to generate the tuning model and determining the distance between the centroids of the clusters; and Determining the third distance includes: clustering the features of the netlist and the training data with the features of the base data used to generate the hybrid model and determining the distance between the centroids of the clusters.

14. An apparatus comprising: Memory; as well as A hardware processor, communicatively coupled to the memory, is configured to: Receive instructions for compiling and editing circuit designs; In response to the instruction, a netlist for the circuit design is generated; By applying a first machine learning model to the netlist, a first time amount is predicted to complete the circuit design; as well as By applying a second machine learning model to the netlist, a first layout and routing strategy is predicted based on the first time quantity exceeding a first threshold. as well as The logic of the circuit design is adjusted according to the first layout and routing strategy; The first machine learning model and the second machine learning model are part of the selection model; as well as The selected model is chosen from the group consisting of: a base model generated using base data, a tuned model generated using training data generated by compiling multiple circuit designs, and a hybrid model generated using the training data and the base data.

15. The apparatus of claim 14, wherein the hardware processor is further configured to: By applying a third machine learning model to the adjusted logic, a second time amount is predicted to complete the circuit design; By applying a fourth machine learning model to the adjusted logic, a second layout and routing strategy is predicted based on the second time quantity exceeding a second threshold; and The components of the circuit design are laid out according to the second layout and routing strategy.

16. The apparatus of claim 15, wherein the hardware processor is further configured to: By applying a fifth machine learning model to the laid-out components, a third time amount is predicted to complete the circuit design; By applying a sixth machine learning model to the laid-out components, a third layout and routing strategy is predicted based on the third time quantity exceeding a third threshold; and The components are routed according to the third layout and routing strategy.

17. The apparatus of claim 16, wherein the hardware processor is further configured to generate a bit stream based on the wiring of the components.

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