A method for implementing reliable transmission of Ethernet messages based on FPGA

Abstract

The present invention relates to a method for implementing reliable transmission of Ethernet messages based on FPGA, and belongs to the field of network communication technology. The present invention proposes a method for implementing reliable transmission of Ethernet messages based on FPGA, which redefines the message frame format, including a reliable header field; in the data communication process, by parsing the reliable header, reliable transmission of messages is implemented in FPGA according to the packet sequence number, packet response number, sending status and receiving status of the packet. When the network is abnormally out of step, the communication between the two parties can be initialized again through a handshake packet on the premise that the data packets received on the FPGA side will not be lost, and the communication efficiency is improved while quickly recovering from the abnormality to normal communication. When the network is abnormal, the terminal can quickly locate the problem by parsing the reliable header field of the message, so as to facilitate rapid recovery to a normal network. The present invention improves the performance of reliable transmission, consumes less logic resources, and reduces complexity.

Description

Technical Field

[0001] The invention belongs to the technical field of network communication, and in particular relates to a method for realizing reliable transmission of Ethernet messages based on FPGA. Background Art

[0002] At present, the technology for reliable transmission and communication in the network is the mature TCP protocol. The TCP protocol is connection-oriented and implements reliable transmission at the transport layer. In a point-to-point network environment, it is relatively complicated to use the TCP protocol to implement reliable transmission of messages. Due to the objective existence of limited resources of FPGA, it is difficult to implement a reliable transmission mechanism of the TCP protocol in FPGA. In addition, it is also difficult to restore normal communication when communication is abnormal. Summary of the invention

[0003] 1. Technical issues to be resolved

[0004] The technical problem to be solved by the present invention is to propose a reliable transmission method which is relatively easy to implement on FPGA, consumes less resources, has high transmission efficiency, can quickly locate the problem when communication is abnormal, and can also quickly restore normal communication.

[0005] (II) Technical solution

[0006] In order to solve the above technical problems, the present invention proposes a method for implementing reliable transmission of Ethernet messages based on FPGA, and the technical solution is as follows:

[0007] A method for implementing reliable transmission of Ethernet messages based on FPGA, characterized in that the message frame format of reliable transmission is redefined to include a reliable header field, wherein the reliable header field contains a packet sequence number; the specific communication process is as follows: S1 initialization stage: Ethernet terminal 1 sends a handshake packet to FPGA end, the handshake packet carries the packet sequence number of the message to be sent by Ethernet terminal 1, and after receiving the handshake packet, the FPGA end sends a handshake packet to Ethernet terminal 1, the handshake packet carries the packet sequence number of the message to be sent by the FPGA side; S2 data communication stage: Ethernet terminal 1 sends the message to the receiving module of the reliable module 1 of FPGA; the receiving module of the reliable module 1 of FPGA parses the reliable header field of the message, and sends the message to the sending module of the reliable module 2 of FPGA; the sending module of the reliable module 2 of FPGA sends the message to Ethernet terminal 2, and waits for Ethernet terminal 2 to reply with a corresponding response packet; S3 end of communication stage: when the FPGA side sends a certain number of timeout retransmission data packets and does not receive any packets, it is considered that the link is disconnected and the communication is ended.

[0008] Furthermore, the reliable header field also includes: message type, packet response number, receiving status and sending status.

[0009] Furthermore, the receiving module of the reliable module 1 of the FPGA parses the reliable header field of the message, including:

[0010] Determine whether it is a data packet. If it is a data packet, determine whether the packet sequence number of the packet is the expected packet sequence number. If it is, cache the packet and wait for it to be taken away. If n normal data packets are received consecutively, inform the sending module on this side to send a normal response packet to Ethernet terminal 1. The packet response number of the response packet is the packet sequence number of the nth normal data packet + 1.

[0011] Furthermore, if the packet sequence number of the packet is less than the expected packet sequence number, it is considered to be a retransmitted data packet, and the FPGA side discards the packet and notifies the sending module on this side to immediately send a normal response packet to Ethernet terminal 1; if the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is less than the window value, the data packet is considered to be lost, all data packets with a packet sequence number greater than the expected packet sequence number are discarded, and the sending module on this side is notified to immediately send a retransmission response packet to Ethernet terminal 1; if the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is not less than the window value, it is considered to be out of step, and the sending module on this side is notified to immediately send a response packet containing out-of-step information to Ethernet terminal 1.

[0012] Furthermore, after receiving the response packet containing the out-of-sync status sent by the FPGA side, the Ethernet terminal 1 will send a handshake packet to the FPGA side. When the FPGA side receives the handshake packet, it will return a handshake packet to re-establish communication.

[0013] Furthermore, the sending module of the reliable module 2 uses a sliding window to send a data packet to the Ethernet terminal 2, starts a timer to wait for the Ethernet terminal 2 to reply with a corresponding response packet, and if the timer times out and the receiving module of the reliable module 2 has not received the expected response packet, the sending module of the reliable module 2 will retransmit the corresponding data packet; if the timer has not timed out, the receiving module of the reliable module 2 receives the expected response packet and updates the sliding window; if the receiving module of the reliable module 2 receives a retransmitted response packet, the sending module of the reliable module 2 is informed to retransmit the corresponding data packet.

[0014] Furthermore, the S2 data communication stage can also perform two-way communication: Ethernet terminal 1 sends message 1 to the receiving module of the reliable module 1 of the FPGA, and Ethernet terminal 2 sends message 2 to the receiving module of the reliable module 2 of the FPGA; the receiving module of the reliable module 1 of the FPGA performs reliable header field analysis on the message 1 sent by the Ethernet terminal 1, and sends the message 1 to the sending module of the reliable module 2 of the FPGA; the receiving module of the reliable module 2 of the FPGA performs reliable header field analysis on the message 2 sent by the Ethernet terminal 2, and sends the message 2 to the sending module of the reliable module 1 of the FPGA; the sending module of the reliable module 2 of the FPGA sends the message 1 to the Ethernet terminal 2, and the receiving module of the reliable module 2 of the FPGA waits for the Ethernet terminal 2 to reply to the corresponding response packet 1, and the sending module of the reliable module 1 of the FPGA sends the message 2 to the Ethernet terminal 1, and the receiving module of the reliable module 1 of the FPGA waits for the Ethernet terminal 1 to reply to the corresponding response packet 2.

[0015] (III) Beneficial effects

[0016] The present invention improves the performance of reliable transmission, consumes less logical resources, and reduces complexity. When the network is abnormally out of sync, the received data packets are not lost, which greatly reduces the retransmission rate when the network is abnormal. When the network is abnormal, the terminal can quickly locate the problem by parsing the reliable header field of the message, which is convenient for quickly recovering to a normal network. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is the overall framework diagram of the present invention.

[0018] Figure 2 The frame format of the transmitted message.

[0019] Figure 3 This is a one-way communication block diagram for messages.

[0020] Figure 4 This is the retransmission process.

[0021] Figure 5 This is a block diagram of bidirectional message communication.

[0022] Figure 6 Implement bidirectional reliable message transmission process on the FPGA side.

[0023] Figure 7 It is a sliding window mechanism. DETAILED DESCRIPTION

[0024] In order to make the purpose, content and advantages of the present invention more clear, the specific implementation methods of the present invention are further described in detail below in conjunction with the drawings and examples.

[0025] Figure 1 It is the overall framework diagram of the present invention. Figure 1 As shown, full-duplex communication is implemented between Ethernet terminal 1 and Ethernet terminal 2. The solid line represents the processing process of application data packets from Ethernet terminal 1 through FPGA to Ethernet terminal 2, and the dotted line represents the processing process of application data packets from Ethernet terminal 2 through FPGA to Ethernet terminal 1. Reliable transmission is required between Ethernet terminal 1 and FPGA, and between Ethernet terminal 2 and FPGA to ensure that the packets transmitted between Ethernet terminals are not lost or repeated, and the flow is controllable.

[0026] In order to achieve reliable transmission between Ethernet terminals and FPGA, the transmission message frame format is redefined. Figure 2 The definition of the reliable header field is as follows:

[0027] Message type: Four message types are defined, namely handshake packet, data packet, response packet, and data + response packet.

[0028] The handshake packet is used to initialize the packet sequence number of the Ethernet terminal and FPGA, and to re-update the packet sequence number of the Ethernet terminal and FPGA when the communication between the Ethernet terminal and FPGA is out of sync. When the message type is a handshake packet, you need to pay attention to the packet sequence number field.

[0029] Data packets are packets that contain only application data, including retransmitted data packets. When the message type is data packets, you only need to pay attention to the packet sequence number and sending status.

[0030] The reply packet is a reply packet sent to the sender to indicate the receipt of a normal packet containing application data. The reply packet is a reply packet sent to the sender to indicate the need for retransmission when a packet containing application data is lost. When the message type is a reply packet, you need to pay attention to the packet reply number and receiving status.

[0031] Data+Response Packet refers to a packet that carries information that needs to be responded to in a data packet. When the message type is Data+Response Packet, you need to pay attention to the packet sequence number, packet response number, receiving status, and sending status.

[0032] Packet sequence number: the number of a data packet (including data + response packet) or a handshake packet. The Ethernet terminal and FPGA each maintain their own packet sequence number. If it is a normal data packet (including data + response packet), the packet sequence number is incremented by 1; if it is a retransmitted data packet (including data + response packet), the packet sequence number is the response number of the retransmitted response packet (including data + response packet); if it is a handshake packet, during the initialization phase, the Ethernet terminal starts with an arbitrary value, and the FPGA starts with 0. When out of step, this field in the handshake packet indicates the packet sequence number of the next data packet (including data + response packet) expected to be received.

[0033] Packet Response Number: The number of the response packet (including data + response packet), indicating the packet sequence number of the next data packet (including data + response packet) expected to be received. When the Ethernet terminal receives a normal data packet (including data + response packet), this field is the packet sequence number of the data packet (including data + response packet) plus 1; when the FPGA receives n (n value can be obtained through register configuration, 1 <= n < window value) normal data packets (including data + response packets) in succession, this field is the packet sequence number of the nth data packet (including data + response packet) plus 1. When a lost data packet (including data + response packet) is received, this field is the packet sequence number of the first lost data packet (including data + response packet).

[0034] Receiving status: indicates the status of receiving data packets (including data + response packets), including whether there is packet loss, whether the cache is full, and whether the message type is normal. This status is updated in the response packet (including data + response packet). Under normal circumstances, this status is normal, the cache is not full, and the message type is normal. If there is packet loss, the normal status is updated to the packet loss status. If the cache is full, the not full status is updated to the full status. If the message type is abnormal, the normal message type is updated to abnormal.

[0035] Sending status: indicates the current sending status of the sender, including whether it is a retransmission data packet (including data + response packet), whether the window is full, and whether it is out of step. Under normal circumstances, this status is normal, the window is not full, and there is no out of step. If the sent data packet (including data + response packet) waits for the corresponding response packet for a timeout or receives a retransmission response packet to retransmit the data packet (including data + response packet), it will be updated to retransmission normally; if there is no extra window to send data packets (including data + response packets), the window is not full and is updated to full; if the packet response number of the received response packet (including data + response packet) exceeds the maximum window value, no out of step will be updated to out of step.

[0036] There are three stages: s1, s2, and s3 to achieve reliable transmission between the Ethernet terminal and the FPGA.

[0037] s1. Initialization phase.

[0038] First, Ethernet terminal 1 sends a handshake packet to FPGA. The handshake packet carries the packet sequence number of the message that Ethernet terminal 1 is about to send. After receiving the handshake packet, FPGA initializes the expected received packet sequence number maintained by the receiving module. Then it sends a handshake packet to Ethernet terminal 1. The handshake packet carries the packet sequence number of the message that the FPGA side is about to send. After receiving the handshake packet, Ethernet terminal 1 initializes the expected received packet sequence number maintained.

[0039] The packet sequence numbers of the Ethernet terminal and the FPGA side are initialized through a send-receive handshake packet mechanism before communication begins, which simplifies the process of establishing communication.

[0040] s2.Data communication phase.

[0041] It is divided into one-way communication and two-way communication. In one-way communication, either Ethernet terminal 1 sends a data packet to Ethernet terminal 2 through FPGA, or Ethernet terminal 2 sends a data packet to Ethernet terminal 1 through FPGA. Figure 1 In the solid line process or dotted line process, when the receiver replies to the sender, no data packet will be sent, so there will be no data + reply packet. Figure 1 The solid line process and the dotted line process are processed at the same time. Ethernet terminal 1 and Ethernet terminal 2 send data packets to the other end through FPGA at the same time. At this time, the receiver will send data packets while replying the response packet to the sender, so data + response packet will appear.

[0042] Figure 3 This is a block diagram for implementing one-way message communication, taking Ethernet terminal 1 sending a data packet to Ethernet terminal 2 as an example.

[0043] S11: Ethernet terminal 1 sends the message to the receiving module of reliable module 1 of FPGA;

[0044] S12: The receiving module of the reliable module 1 of the FPGA parses the reliable header of the message, and on the one hand informs the sending module on the local side to send a corresponding response packet to the Ethernet terminal 1, and on the other hand, the receiving module of the reliable module 1 of the FPGA sends the message to the sending module of the reliable module 2 of the FPGA;

[0045] S13: The reliable module 2 of the FPGA sends the message to the Ethernet terminal 2 through the sending module, while the receiving module on the local side waits for the Ethernet terminal 2 to reply with a corresponding response packet.

[0046] The specific implementation process on the FPGA side is as follows: The receiving module of the reliable module 1 parses the reliable header field in the received message frame format. Determine whether it is a data packet. If it is a data packet, determine whether the packet sequence number of the packet is the expected packet sequence number. If it is, on the one hand, cache the packet and wait for it to be taken away. On the other hand, if n normal data packets are received continuously, inform the sending module on this side to send a normal response packet to Ethernet terminal 1. The packet response number of the response packet is the packet sequence number of the nth normal data packet + 1;

[0047] If the packet sequence number of the packet is less than the expected packet sequence number, it is considered to be a retransmitted data packet. To prevent the Ethernet terminal from continuously retransmitting the data packet, the FPGA side discards the packet and informs the sending module on this side to immediately send a normal response packet to Ethernet terminal 1.

[0048] If the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is less than the window value, the data packet is considered lost, all data packets with a sequence number greater than the expected packet sequence number are discarded, and the sending module on this side is notified to immediately send a retransmission response packet to Ethernet terminal 1;

[0049] If the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is not less than the window value, it is considered out of step, and the sending module on this side is notified to immediately send a response packet containing out-of-step information to Ethernet terminal 1. After the Ethernet terminal receives the response packet containing the out-of-step status sent by the FPGA side, it will send a handshake packet to the FPGA side. When the FPGA side receives the handshake packet, it will return a handshake packet to indicate that the communication has been re-established and update the packet response number of the response packet that the receiving module on this side expects to receive. The handshake packet will only change the packet sequence number of the expected data packet or the packet response number of the expected response packet, and the data packets that have been cached normally will not be lost.

[0050] If it is not a data packet but a handshake packet, the packet sequence number of the expected data packet is updated and the sending module on this side is informed to send a handshake packet. If it is other messages, the packets are discarded.

[0051] If it is a data packet, its reliable header information will be trimmed. After the trimmed data packet reaches the sending module of the reliable module 2, the sending module of the reliable module 2 will add the reliable header information to the packet containing the application data according to the packet sequence number on this side, turn it into a new data packet and send it to the Ethernet terminal 2. The data packet is sent using a sliding window. If the sliding window is not full and there are data packets to be sent, the data packet will continue to be sent to the Ethernet terminal 2. If the sliding window is full and there are data packets to be sent, the data packet will not continue to be sent to the Ethernet terminal 2 at this time, and the data packet will not continue to be sent until the sliding window is not full. The sending module of the reliable module 2 starts the timer to wait for the response packet sent by the Ethernet terminal 2. If the timer times out and the receiving module of the reliable module 2 has not received the expected response packet, the sending module of the reliable module 2 will retransmit the corresponding data packet; if the timer does not time out, if the receiving module on this side receives the expected response packet, it will update the sliding window; if the reliable module 2 receives a retransmitted response packet, it will inform the sending module on this side to retransmit the corresponding data packet. See the retransmitted data packet processing process. Figure 4 If the packet response number of the received response packet exceeds the sum of the expected packet response number and the window value, it is considered out of step, and the sending module on this side is notified to send a response packet containing the out of step information.

[0052] Figure 5 The block diagram of the bidirectional communication of messages is shown in FIG. 2. In the bidirectional communication, the Ethernet terminal 1 sends a data packet to the Ethernet terminal 2, and the Ethernet terminal 2 also sends a data packet to the Ethernet terminal 1.

[0053] S21: Ethernet terminal 1 sends the side data packet (including data + response packet) to the receiving module of the reliable module 1 of the FPGA, while Ethernet terminal 2 sends the side data packet (including data + response packet) to the receiving module of the reliable module 2 of the FPGA;

[0054] S22: The receiving module of the reliable module 1 of the FPGA parses the reliable header field of the message sent by the Ethernet terminal 1. On the one hand, it informs the sending module on this side to send the corresponding response packet to the Ethernet terminal 1. On the other hand, the receiving module of the reliable module 1 of the FPGA will send the data packet to the sending module of the reliable module 2 of the FPGA; the receiving module of the reliable module 2 of the FPGA parses the reliable header field sent by the Ethernet terminal 2. On the one hand, it informs the sending module on this side to send the corresponding response packet to the Ethernet terminal 2. On the other hand, the reliable module 2 of the FPGA will send the data packet to the sending module of the reliable module 1 of the FPGA.

[0055] S23: The reliable module 2 of FPGA sends the data packet (including data + response packet) to Ethernet terminal 2 through the sending module, while the receiving module on this side waits for Ethernet terminal 2 to reply with the corresponding response packet (including data + response packet); the reliable module 1 of FPGA sends the data packet (including data + response packet) to Ethernet terminal 1 through the sending module, while the receiving module on this side waits for Ethernet terminal 1 to reply with the corresponding response packet (including data + response packet).

[0056] Ethernet terminal 1 corresponds to reliable module 1 of FPGA, and Ethernet terminal 2 corresponds to reliable module 2 of FPGA. The opposite side of reliable module 1 is reliable module 2, and the opposite side of reliable module 2 is reliable module 1.

[0057] For the specific implementation process on the FPGA side, see Figure 6 , the implementation process of reliable module 1 and reliable module 2 is the same. Take reliable module 1 as an example.

[0058] The receiving module of the reliable module 1 performs reliable header parsing and judgment on the received message frame format. If it is a data packet, it is judged whether the packet sequence number of the packet is the expected packet sequence number. If it is, on the one hand, the packet is cached and waits to be taken away. On the other hand, if n normal data packets are received continuously, the sending module on this side is informed to send a normal response packet to the corresponding Ethernet terminal. The packet response number of the response packet is the packet sequence number of the nth normal data packet + 1; if it is less than the expected packet sequence number, it is considered to be a retransmitted data packet. In order to avoid the Ethernet terminal from retransmitting the data packet all the time, this packet is discarded and the sending module on this side is informed to immediately send a normal response packet to the corresponding Ethernet terminal; if it is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is less than the window value, it is considered that the data packet is lost, all data packets greater than the expected packet sequence number are discarded, and the sending module on this side is informed to immediately send a retransmission response packet to the corresponding Ethernet terminal; if it is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is not less than the window value, it is considered to be out of step, and the sending module on this side is informed to immediately send a response packet containing out-of-step information to the corresponding Ethernet terminal. At this time, if there is a data packet sent from the opposite side that needs to be sent to the corresponding Ethernet terminal on this side, the data packet carries the response packet information and is sent to the corresponding Ethernet terminal. If there is no data packet from the opposite side that needs to be sent, the response packet is sent to the corresponding Ethernet terminal.

[0059] If it is an expected response packet, update the sliding window of the sending module on this side; if it is a retransmission response packet, inform the sending module on this side to retransmit the corresponding data packet. At this time, if there is a response packet that needs to be sent, the retransmission data packet carries the response information; if the packet response number of the received response packet exceeds the sum of the expected packet response number and the window value, it is considered out of step, and inform the sending module on this side to send a response packet containing the out-of-step information. If it is a data + response packet, analyze it according to the data packet and the response packet.

[0060] If it is a handshake packet, update the packet sequence number of the data packet expected to be received, and inform the sending module on this side to send a handshake packet. If it is other messages, discard them. If the receiving module does not receive any packets, and the data packets sent by the opposite side need to be sent to the corresponding Ethernet terminal on this side, only normal data packets are sent without carrying response information.

[0061] The rules for sending packets with and without acknowledgment information in two-way communication are the same as the rules for sending packets without acknowledgment information in one-way communication.

[0062] The FPGA side sliding window control flow mechanism is shown in Figure 7. The sliding window is only used when sending data packets, and the size of the sliding window value is obtained by the Ethernet terminal through register configuration. The FPGA needs to maintain the leftmost, rightmost and currently sent pointers of the sliding window. The leftmost side of the sliding window is the minimum packet sequence number a of the data packet that has been sent but has not received the corresponding response packet. The rightmost side is the maximum packet sequence number of the data packet that can be sent, which is recorded as b, and b is equal to a + sliding window value. If the packet sequence number of the data packet is between a and b, it is recorded as d, which means that the sliding window is not full and the data packet can be sent. If the packet sequence number of the data packet is b+1, it means that the sliding window is full and the data packet cannot be sent out temporarily. It can only be sent out when the sliding window is not full. The packet response number of the received normal response packet is recorded as c. If a is less than or equal to c-1 and less than or equal to b, it is considered that the receiver of all data packets from a to c-1 (including c-1) has received it. At this time, the leftmost value of the sliding window is updated to c, and the rightmost value is updated to c+sliding window value.

[0063] s3. End the communication phase.

[0064] When the FPGA side sends a certain number m (configured by registers) of retransmitted data packets due to timeout and does not receive any packets, it considers the link disconnected and the communication is over.

[0065] The present invention first simplifies the process of establishing communication. The packet sequence numbers of the Ethernet terminal and the FPGA side are initialized through a one-to-one handshake packet mechanism, and then communication is started. When the FPGA receiving side detects that a data packet is lost, all data packets after the packet loss are discarded, saving FPGA cache resources and reducing the complexity of disorder processing due to packet loss inside the FPGA. In the data communication process, reliable message transmission is realized in the FPGA according to the packet sequence number, packet response number, sending state and receiving state of the packet, which is simple and easy to implement. On the other hand, the Ethernet terminal can also quickly judge the ability of the FPGA to send data packets and analyze the state of the FPGA sending side. If the synchronization is lost, the communication between the two parties can be initialized again through the handshake packet on the premise that the data packets received by the FPGA side will not be lost, and the communication efficiency is improved while recovering from abnormality to normal communication quickly. When the FPGA receives a data packet with a sequence number less than the expected packet, it discards the packet and immediately replies to the corresponding Ethernet terminal with a reply packet, avoiding the Ethernet terminal from retransmitting all the time, reducing communication congestion. In addition, when the FPGA side receives a normal data packet, a method of merging multiple packets to reply to the reply packet is adopted, which greatly improves the transmission efficiency. The use of sliding windows to control the flow through the Ethernet terminal and the FPGA is more efficient than other mechanisms such as interruption. When the communication ends, if the FPGA side sends a certain number of retransmitted data packets and does not receive any packets, it considers that the communication between the two parties is over, thereby reducing the use of heartbeat packets and reducing processing complexity.

[0066] Compared with the reliable transmission of TCP protocol, the present invention improves the performance of reliable transmission, consumes less logical resources and reduces complexity. When the network is abnormally out of step, the received data packets are not lost, which greatly reduces the retransmission rate when the network is abnormal. When the network is abnormal, the terminal can quickly locate the problem by parsing the reliable header field of the message, which is convenient for rapid recovery to the normal network.

[0067] The above is only a preferred embodiment of the present invention. It should be noted that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered as the protection scope of the present invention. The specific embodiments of the invention are further described in detail.

Claims

1. A method for implementing reliable transmission of Ethernet messages based on FPGA, characterized in that: Redefine the message frame format of reliable transmission, including a reliable header field, wherein the reliable header field contains a packet sequence number; the specific communication process is as follows: S1 initialization phase: Ethernet terminal 1 sends a handshake packet to the FPGA end, the handshake packet carries the packet sequence number of the message to be sent by Ethernet terminal 1, and after receiving the handshake packet, the FPGA end sends a handshake packet to Ethernet terminal 1, the handshake packet carries the packet sequence number of the message to be sent by the FPGA side; S2 data communication phase: Ethernet terminal 1 sends the message to the receiving module of the reliable module 1 of the FPGA; the receiving module of the reliable module 1 of the FPGA parses the reliable header field of the message, and sends the message to the sending module of the reliable module 2 of the FPGA; the sending module of the reliable module 2 of the FPGA sends the message to Ethernet terminal 2, and waits for Ethernet terminal 2 to reply with a corresponding response packet; S3 end of communication phase: when the FPGA side sends a certain number of timeout retransmission data packets and does not receive any packets, it is considered that the link is disconnected and the communication is over; in, The receiving module of the reliable module 1 of the FPGA parses the reliable header field of the message, including: Determine whether it is a data packet. If it is a data packet, determine whether the packet sequence number of the packet is the expected packet sequence number. If it is, cache the packet and wait for it to be taken away. If n normal data packets are received continuously, inform the sending module on this side to send a normal response packet to Ethernet terminal 1. The packet response number of the response packet is the packet sequence number of the nth normal data packet + 1; If the packet sequence number of the packet is less than the expected packet sequence number, it is considered to be a retransmitted data packet, and the FPGA side discards the packet and notifies the sending module on this side to immediately send a normal response packet to Ethernet terminal 1; if the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is less than the window value, the data packet is considered to be lost, all data packets greater than the expected packet sequence number are discarded, and the sending module on this side is notified to immediately send a retransmission response packet to Ethernet terminal 1; if the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is not less than the window value, it is considered to be out of step, and the sending module on this side is notified to immediately send a response packet containing out-of-step information to Ethernet terminal 1; After Ethernet terminal 1 receives the response packet containing the out-of-sync status sent by the FPGA side, it will send a handshake packet to the FPGA side. After the FPGA side receives the handshake packet, it will return a handshake packet to re-establish communication, specifically including: After Ethernet terminal 1 receives the response packet containing the out-of-sync status sent by the FPGA side, it will send a handshake packet to the FPGA side. After the FPGA side receives the handshake packet, it will return a handshake packet to indicate that communication has been re-established and the packet response number of the response packet that the receiving module on this side expects to receive is updated. The handshake packet will only change the packet sequence number of the expected data packet or the packet response number of the expected response packet, and the data packets that have been cached normally will not be lost.

2. The method for implementing reliable transmission of Ethernet messages based on FPGA as claimed in claim 1, characterized in that: The reliable header field also includes: message type, packet response number, receiving status and sending status.

3. The method for implementing reliable transmission of Ethernet messages based on FPGA as claimed in claim 1, characterized in that: The sending module of the reliable module 2 uses a sliding window to send a data packet to the Ethernet terminal 2, starts a timer and waits for the Ethernet terminal 2 to reply with a corresponding response packet. If the timer times out and the receiving module of the reliable module 2 has not received the expected response packet, the sending module of the reliable module 2 will retransmit the corresponding data packet; if the timer does not time out, the receiving module of the reliable module 2 receives the expected response packet and updates the sliding window; if the receiving module of the reliable module 2 receives a retransmission response packet, the sending module of the reliable module 2 is informed to retransmit the corresponding data packet.

4. A method for implementing reliable transmission of Ethernet messages based on FPGA, characterized in that: Redefine the message frame format of reliable transmission, including a reliable header field, wherein the reliable header field contains a packet sequence number; the specific communication process is as follows: S1 initialization phase: Ethernet terminal 1 and Ethernet terminal 2 send handshake packets to the FPGA end respectively, the handshake packets carry the packet sequence numbers of the messages to be sent by Ethernet terminal 1 and Ethernet terminal 2, and after receiving the handshake packets, the FPGA end sends handshake packets to Ethernet terminal 1 and Ethernet terminal 2 respectively, and the handshake packets carry the packet sequence numbers of the messages to be sent by the FPGA side; S2 data communication phase: Ethernet terminal 1 sends message 1 to the receiving module of the reliable module 1 of the FPGA, and Ethernet terminal 2 sends message 2 to the receiving module of the reliable module 2 of the FPGA; the receiving module of the reliable module 1 of the FPGA performs a reliable header field check on the message 1 sent by the Ethernet terminal 1 Parse and send the message 1 to the sending module of the reliable module 2 of the FPGA; the receiving module of the reliable module 2 of the FPGA performs reliable header field parsing on the message 2 sent by the Ethernet terminal 2, and sends the message 2 to the sending module of the reliable module 1 of the FPGA; the sending module of the reliable module 2 of the FPGA sends the message 1 to the Ethernet terminal 2, the receiving module of the reliable module 2 of the FPGA waits for the Ethernet terminal 2 to reply with the corresponding response packet 1, the sending module of the reliable module 1 of the FPGA sends the message 2 to the Ethernet terminal 1, and the receiving module of the reliable module 1 of the FPGA waits for the Ethernet terminal 1 to reply with the corresponding response packet 2; s3 ends the communication stage: when the FPGA side sends a certain number of timeout retransmission data packets and does not receive any packets, it is considered that the link is disconnected and the communication is ended.

5. The method for implementing reliable transmission of Ethernet messages based on FPGA as claimed in claim 4, characterized in that: The reliable header field also includes: message type, packet response number, receiving status and sending status.

6. The method for implementing reliable transmission of Ethernet messages based on FPGA as claimed in claim 4, characterized in that: The receiving module of the reliable module 1 of the FPGA performs reliable header field parsing on the message 1 sent by the Ethernet terminal 1, including: Determine whether it is a data packet. If it is a data packet, determine whether the packet sequence number of the packet is the expected packet sequence number. If it is, cache the packet and wait for it to be taken away. If n normal data packets are received continuously, inform the sending module on this side to send a normal response packet to Ethernet terminal 1. The packet response number of the response packet is the packet sequence number of the nth normal data packet + 1; If the packet sequence number of the packet is less than the expected packet sequence number, it is considered to be a retransmitted data packet. The FPGA side discards the packet and notifies the sending module on this side to immediately send a normal response packet to Ethernet terminal 1; if the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is less than the window value, the data packet is considered to be lost, all data packets with a packet sequence number greater than the expected packet sequence number are discarded, and the sending module on this side is notified to immediately send a retransmission response packet to Ethernet terminal 1; if the packet sequence number of the packet is greater than the expected packet sequence number and the difference between the received packet sequence number and the expected packet sequence number is not less than the window value, it is considered to be out of step, and the sending module on this side is notified to immediately send a response packet containing out-of-step information to Ethernet terminal 1.

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