Current characteristic interference of integrated circuits

Abstract

The embodiments provide a current characteristic disruptor for an integrated circuit. This specification relates to an integrated circuit that includes a load, circuitry, and a current output digital-to-analog converter between a first terminal and a second terminal, a first voltage being applied between the first and second terminals, the load being configured to execute instructions, the circuitry being configured to deliver a digital signal having at least two bits based on a binary signal, and the current output digital-to-analog converter being controlled by the digital signal and coupled in parallel with the load between the first and second terminals.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to French patent application No. FR2012873, filed on December 8, 2020, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This disclosure generally relates to integrated circuits, and in certain embodiments to protecting algorithms or digital data manipulated by integrated circuits from potential attacks by analyzing circuit power consumption. Background Technology

[0004] The power consumption of electronic circuits (especially data processing circuits) varies depending on the circuit's activity, and more specifically, on the calculations performed. When circuits perform activities that must be kept confidential or manipulate data or secret quantities, it is generally desirable to prevent third-party hacking by analyzing the circuit's power consumption. Such hacking uses attacks known as Simple Power Analysis (SPA) or Differential Power Analysis (DPA), which examine the circuit's current characteristics to discover operations or its secret data.

[0005] Methods exist to prevent hacking by analyzing circuit power consumption. One type of these methods involves disrupting the current characteristics of the circuit to make it more difficult to inspect.

[0006] One example of a method involves smoothing the current consumed by the circuit.

[0007] One example of a method involves adding a randomly varying current to the current consumed by the circuit.

[0008] However, in some cases, such methods may not provide sufficient protection against hackers who analyze circuit power consumption. Summary of the Invention

[0009] Therefore, one objective of the embodiments is to overcome all or part of the disadvantages of the previously described integrated circuits.

[0010] Another objective of the embodiments is to configure the integrated circuit to prevent hacking by analyzing the circuit's power consumption.

[0011] To this end, one embodiment provides an integrated circuit that includes a load, circuitry, and a current-output digital-to-analog converter between a first terminal and a second terminal, wherein a first voltage is applied between the first and second terminals, the load is configured to execute instructions, the circuitry is configured to supply a digital signal having at least two bits based on a binary signal, and the current-output digital-to-analog converter is controlled by the digital signal.

[0012] According to one embodiment, the digital-to-analog converter is coupled in parallel with the load between the first terminal and the second terminal.

[0013] According to one embodiment, the integrated circuit further includes a regulator between the first terminal and the second terminal, the regulator being configured to deliver a second voltage from the first voltage for supplying power to a load, and the digital-to-analog converter is coupled in parallel with the load and the regulator between the first terminal and the second terminal.

[0014] According to one embodiment, the digital signal includes at least three bits.

[0015] According to one embodiment, the load is configured to deliver binary signals.

[0016] According to one embodiment, the binary signal is a random signal.

[0017] According to one embodiment, the circuit for delivering digital signals includes a series of flip-flops whose rate is set by a clock signal, wherein the input of the first flip-flop in the series receives a binary signal, and the output of the flip-flops in the series delivers bits of the digital signal.

[0018] According to one embodiment, the number of flip-flops included in the series is greater than the number of bits of the digital signal.

[0019] According to one embodiment, the integrated circuit also includes circuitry configured to smooth the current consumed by the load.

[0020] One embodiment also provides a chip card with or without contacts, the chip card including an integrated circuit as previously defined.

[0021] One embodiment also provides a method for interfering with the current characteristics of a load that executes digital instructions, the load being located between a first terminal and a second terminal, a first voltage being applied between the first and second terminals, the method comprising delivering a digital signal having at least two bits according to a binary signal, and delivering current to the first terminal via a current output digital-to-analog converter controlled by the digital signal. Attached Figure Description

[0022] To gain a more complete understanding of this disclosure and its advantages, the following description is now taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 This is an electrical diagram of the electronic chip in the embodiment;

[0024] Figure 2 yes Figure 1 The signal timing diagram of the electronic chip for the first voltage Vcc in the embodiment;

[0025] Figure 3 yes Figure 1The signal timing diagram of the electronic chip for the second voltage Vcc in the embodiment;

[0026] Figure 4 yes Figure 2 and Figure 3 The signal variation distribution of the timer;

[0027] Figure 5 This is a diagram of the electronic chip in the embodiment;

[0028] Figure 6 yes Figure 5 A diagram of a portion of an electronic chip in an embodiment;

[0029] Figure 7 yes Figure 5 The signal timing diagram of the electronic chip for the first voltage Vcc in the embodiment;

[0030] Figure 8 yes Figure 5 The signal timing diagram of the electronic chip for the second voltage Vcc in the embodiment;

[0031] Figure 9 yes Figure 7 and Figure 8 The signal variation distribution of the timer;

[0032] Figure 10 This is a schematic diagram of an embodiment of a chip card with contact portions; and

[0033] Figure 11 This is a schematic diagram of a contactless chip card in an embodiment. Detailed Implementation

[0034] In the various figures, the same features are designated by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with identical structures, dimensions, and material properties. For clarity, only steps and elements useful for understanding the embodiments described herein are illustrated and described in detail. In particular, voltage regulation circuits and current smoothing circuits are well known to those skilled in the art and will not be described in detail below.

[0035] Unless otherwise indicated, when referring to two elements connected together, it means that there is no direct connection between them except for the conductor, and when referring to two elements coupled together, it means that the two elements can be connected or they can be coupled via one or more other elements.

[0036] Unless otherwise stated, the expressions "about," "approximately," "substantially," and "around" indicate within 10%, preferably within 5%. Furthermore, a signal that alternates between a first constant state (e.g., a low state labeled "0") and a second constant state (e.g., a high state labeled "1") is called a "binary signal." Different binary signals of the same electronic circuit can have different high and low states. In practice, a binary signal can correspond to a voltage or current that may not be completely constant in either the high or low state. Additionally, the term "digital signal" refers to a signal that comprises at least two binary signals.

[0037] An example of the application of this disclosure is in the field of chip cards and other electronic tags, with or without contact parts.

[0038] Figure 1 An electrical diagram of an embodiment of integrated circuit 10 (also referred to as an electronic chip) is shown. Integrated circuit 10 may correspond to a chip of a chip card with contacts or a chip of a contactless chip card.

[0039] Integrated circuit 10 includes terminals 12 and 14, with a voltage Vcc applied between terminals 12 and 14. The voltage Vcc is delivered by a system coupled to the integrated circuit (e.g., a card reader). The voltage Vcc can be a voltage directly delivered by a system connected to terminals 12 and 14.

[0040] In one embodiment, the integrated circuit 10 may be part of an electronic device (e.g., a contactless chip card), and the voltage Vcc may be delivered from a signal received by the electronic device when it is coupled to the system.

[0041] For example, the voltage Vcc can be a substantially constant voltage derived from an oscillation signal. Typically, the voltage Vcc can vary depending on the type of system coupled to the integrated circuit. As an example, the voltage Vcc can vary from 1V to 5V.

[0042] The integrated circuit 10 includes a load 16 between terminals 12 and 14. For example, the load 16 includes a processor, microprocessor, or microcontroller.

[0043] The integrated circuit also includes a regulation circuit 18 for delivering a power supply voltage Vdd suitable for the operation of the load 16 from the voltage Vcc. The regulation circuit 18 can be a linear regulation circuit, particularly a series regulation circuit or a shunt regulation circuit.

[0044] In order to disrupt the current characteristics of integrated circuit 10, integrated circuit 10 may include a smoothing circuit 20, which is configured to smooth the current Idd consumed by load 16.

[0045] exist Figure 1In this diagram, the load 16, regulating circuit 18, and smoothing circuit 20 are shown assembled in series between terminals 12 and 14. However, it should be understood that the assembly of the load 16, regulating circuit 18, and smoothing circuit 20 between terminals 12 and 14 depends on the structure of the regulating circuit 18 and the smoothing circuit 20. Examples of the regulating circuit 18 and the smoothing circuit 20 are described in patent US9678525, which is incorporated herein by reference in its entirety.

[0046] To interfere with the current characteristics of integrated circuit 10, integrated circuit 10 may also include interference circuit 22. Interference circuit 22 may be coupled in parallel with load 16, regulation circuit 18 and smoothing circuit 20 between terminals 12 and 14.

[0047] As an example, interference circuit 22 corresponds to a current source controlled by the signal Jam_binary delivered by load 16. The current Icc flowing between terminals 12 and 14 is the sum of the current Idd supplying power to load 16 and the current Ijam delivered by interference circuit 22.

[0048] The Jam_binary signal can be a binary signal that controls the interference circuit 22 in a way that is either entirely or entirely absent. For example, when the Jam_binary signal is "0", the current Ijam delivered by the interference circuit 22 is zero. When the Jam_binary signal is "1", the current Ijam is equal to a substantially constant maximum value Imax. According to one embodiment, new values ​​of the binary signal Jam_bit are delivered at a clock signal rate. Figure 1 Not shown in the diagram. Preferably, the signal Jam_binary is a random or pseudo-random signal.

[0049] Figure 2 and Figure 3 Timing diagrams of the signals of integrated circuit 10 obtained through simulation are shown, namely Ch_Jam_binary, Ch_Icc_0_A, Ch_Icc_1_A, Ch_Icc_2_A, Ch_Icc_3_A, Ch_Icc_0'_A, Ch_Icc_0"_A, Ch_Icc_1'_A, Ch_Icc_2'_A, and Ch_Icc_3'_A. Load 16 is active between times t1 and t2.

[0050] for Figure 2 The voltage Vcc equals 2.2V, while for Figure 3 The voltage Vcc is equal to 5V.

[0051] exist Figure 2 and Figure 3In the diagram, Ch_Jam_binary is the timing diagram for the Jam_binary signal used in all simulations. The other timing diagrams are timing diagrams for the current Icc at terminal 12.

[0052] for Figure 2 For timing diagram Ch_Icc_0_A, there is a smoothing circuit 20, but no interference circuit 22. For timing diagrams Ch_Icc_1_A, Ch_Icc_2_A, and Ch_Icc_3_A, there is a smoothing circuit 20, and interference circuit 22 delivers currents Imax equal to 0.75mA, 1.5mA, and 2.5mA, respectively.

[0053] for Figure 3 For timing diagram Ch_Icc_0"_A, there is no smoothing circuit 20 and no interference circuit 22. For timing diagram Ch_Icc_0'_A, there is smoothing circuit 20, but no interference circuit 22. For timing diagrams Ch_Icc_1'_A, Ch_Icc_2'_A, and Ch_Icc_3'_A, there is smoothing circuit 20, and interference circuit 22 delivers currents Imax equal to 0.75mA, 1.5mA, and 2.5mA, respectively.

[0054] Figure 4 The distributions of the intensity of current Icc relative to the change in average current consumption ΔI, obtained for timing diagrams Ch_Icc_0_A, Ch_Icc_1_A, Ch_Icc_2_A, Ch_Icc_3_A, Ch_Icc_0'_A, Ch_Icc_1'_A, Ch_Icc_2'_A, and Ch_Icc_3'_A, are shown, respectively. The essentially constant distribution of current Icc reflects efficient interference, making it difficult to extract information from circuit power consumption analysis.

[0055] like Figure 2 As shown, when the voltage Vcc equals 2.2V, the current Imax of 0.75mA is too low, causing the timing diagram Ch_Icc_1_A of the current Icc obtained when the interference circuit 22 is active to still be close to the timing diagram Ch_Icc_0_A of the current Icc without the interference circuit 22. However, for Figure 2 The timing diagrams Ch_Icc_2_A and Ch_Icc_3_A are obtained by using currents Imax of 1.5mA and 2.5mA respectively to obtain appropriate interference.

[0056] However, as Figure 3As shown, when the voltage Vcc equals 5V, the currents Imax of 1.5mA and 2.5mA are too high, causing interference introduced by interference circuit 22 to appear in timing diagrams Ch_Icc_1'_A, Ch_Icc_2'_A, and Ch_Icc_3'_A, and processing will allow this interference to be subtracted effortlessly. This also appears Figure 4 In the above, because distributions D_Icc_1'_A, D_Icc_2'_A, and D_Icc_3'_A have two distinct parts with a zero value in the middle region, this is not the case for distributions D_Icc_2_A and D_Icc_3_A. Therefore, for an extended range of voltage Vcc, it may be difficult to determine the value of current Imax to obtain efficient interference.

[0057] Figure 5 This is an electrical diagram of one embodiment of integrated circuit 30. The integrated circuit includes... Figure 1 All components of the integrated circuit 10 shown are different except that the interference circuit 22 is replaced by circuit 32 and current output from digital-to-analog converter 34. Circuit 32 receives binary signal Jam_binary and delivers digital signal Jam_bit. Digital-to-analog converter 34 is controlled by digital signal Jam_bit.

[0058] The digital signal Jam_bit comprises N bits, where N is a natural integer greater than or equal to 2, preferably a natural integer greater than or equal to 3. According to one embodiment, each bit of the digital signal Jam_bit is timed by a clock signal (…). Figure 5 The rate (not shown in the figure) varies randomly.

[0059] According to one embodiment, a digital-to-analog converter 34 is connected between terminals 12 and 14 and delivers a current Ijam. The digital-to-analog converter 34 is configured to deliver 2 ohms for the current Ijam. N There are two different values. Therefore, the current Ijam takes 2 values ​​in time. N There are 10 distinct values, where the probability of each value depends on the digital signal Jam_bit.

[0060] According to one embodiment, each bit of the digital signal Jam_bit varies randomly or pseudo-randomly at the rate of a clock signal. Therefore, the current Ijam takes values ​​of 2 over time. N There are several different values, each advantageously having a uniform probability. This improves the interference function. According to one embodiment, circuit 32 and digital-to-analog converter 34 are activated once load 16 is active.

[0061] Figure 6 This is an electrical diagram of one embodiment of circuit 32 when N equals 3. In this embodiment, circuit 32 includes a series of D-type flip-flops 36 (FF). Figure 6 The example shown is 7 D-type flip-flops 36.

[0062] The first flip-flop 36 in the series receives the binary signal Jam_binary at its data input. For each other flip-flop 36 in the series, the input of the flip-flop is coupled to the output of the previous flip-flop in the series.

[0063] Each flip-flop 36 is rate-set by the clock signal CLK. As an example, for each flip-flop 36, the value at the input of flip-flop 36 is copied to the output of flip-flop 36 at each rising edge of the clock signal CLK.

[0064] Each bit of the digital signal Jam_bit corresponds to the output of one of the flip-flops 36. As an example, in... Figure 6 In, the least significant bit Jam_bit <0> The second Jam_bit corresponds to the output of the first flip-flop. <1> The output corresponds to the third flip-flop, and the most significant bit is Jam_bit. <2> This corresponds to the output of the final trigger.

[0065] In this embodiment, the number of triggers 36 in the series of triggers is equal to or greater than N.

[0066] use Figure 5 The integrated circuit 30 shown is used for simulation. Figure 7 and Figure 8 Timing diagrams of the signals of integrated circuit 30 obtained through simulation are shown, namely Ch_max_1, Ch_max_2, Ch_max_3, Ch_max_4, Ch_Icc_0_B, Ch_Icc_0'_B, Ch_Icc_1_B, Ch_Icc_2_B, Ch_Icc_3_B, Ch_Icc_4_B, Ch_Icc_1'_B, Ch_Icc_2'_B, Ch_Icc_3'_B, and Ch_Icc_4'_B. Load 16 is active between times t1 and t2.

[0067] for Figure 7 The voltage Vcc equals 2.2V, while for Figure 8 The voltage Vcc equals 5V. Figure 7 and Figure 8 In the simulation, timing diagrams Ch_max_1, Ch_max_2, Ch_max_3, and Ch_max_4 are timing diagrams for the current Ijam obtained by four increments of the maximum current that can be supplied by the digital-to-analog converter 34, and are used in all simulations. The other timing diagram is the timing diagram for the current Icc at terminal 12. For... Figure 7 and Figure 8For the timing diagram Ch_Icc_0"_B, there are no smoothing circuits 20 and 32.

[0068] for Figure 7 For timing diagram Ch_Icc_0_B, there is a smoothing circuit 20, but no circuit 32. For timing diagrams Ch_Icc_1_B, Ch_Icc_2_B, Ch_Icc_3_B, and Ch_Icc_4_B, there is a smoothing circuit 20, and the interference circuit 22 delivers a maximum current Imax of 0.805mA, 1.330mA, 2.030mA, and 3.045mA, respectively.

[0069] for Figure 8 For timing diagram Ch_Icc_0'_B, there is a smoothing circuit 20, but no circuit 32. For timing diagrams Ch_Icc_1'_B, Ch_Icc_2'_B, Ch_Icc_3'_B, and Ch_Icc_4'_B, there is a smoothing circuit 20, and circuit 32 delivers a maximum current Imax of 0.805mA, 1.330mA, 2.030mA, and 3.045mA, respectively.

[0070] Figure 9 The distributions of current Icc obtained for timing diagrams Ch_Icc_0_B, Ch_Icc_1_B, Ch_Icc_2_B, Ch_Icc_3_B, Ch_Icc_4_B, Ch_Icc_0'_B, Ch_Icc_1'_B, Ch_Icc_2'_B, Ch_Icc_3'_B, and Ch_Icc_4'_B are shown.

[0071] like Figures 7 to 9 As shown, for a voltage Vcc equal to 2.2V or 5V, efficient interference is obtained regardless of the value of the maximum current Imax. This facilitates the selection of the value of the current Imax during the calibration of integrated circuit 30.

[0072] Over a wide range of voltage Vcc, the interference signal delivered by interference circuit 22 is difficult to distinguish from the characteristics of the current in load 16. This reduces the risk of identifying the characteristics of the current in load 16 by analyzing circuit power consumption. Therefore, this improves the safety of integrated circuit 30.

[0073] Interference circuit 22 provides additional flexibility and simplifies the selection of the strength of the maximum current Imax because it reduces the need to maintain smooth performance independently of supply voltage Vcc, processing conditions and temperature variations.

[0074] The interference circuit 30 has a simple structure and requires virtually no additional silicon area compared to the integrated circuit 10.

[0075] Figure 10 A card 40 having a chip 42 is shown schematically. The chip 42 has contacts, and the chip 42 may include the previously described integrated circuit 30. The card 40 is formed of a plate, typically made of plastic material, on which the chip 42 is placed. The chip 42 is externally accessible through electrical contacts, at least two of which, 44 and 46, are used to apply a power supply voltage when the card is introduced into a reader.

[0076] Figure 11 A second example of a card 50 with a chip 52 is shown, wherein the chip 52 may include the previously mentioned integrated circuit 30. It is a contactless card commonly referred to as an electromagnetic transponder. The card 50 includes a chip 52 having two input terminals 54 and 56 coupled to two corresponding ends of a conductive track 58 supported by the card 50 and forming an antenna. When the card is near the terminal generating the electromagnetic field, this antenna forms part of the resonant circuit of the transponder 50 to capture not only information but also remotely supplied energy.

[0077] Two systems, one with contacts and one without, can exist on the same card, or even on the same chip.

[0078] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will conceive of by those skilled in the art. Finally, based on the functional indications given above, actual implementations of the described embodiments and variations are within the capabilities of those skilled in the art.

[0079] While the description has been detailed, it should be understood that various changes, substitutions, and alterations can be made without departing from the spirit and scope of this disclosure as defined by the appended claims. In the various figures, the same elements are indicated by the same reference numerals. Furthermore, the scope of this disclosure is not intended to be limited to the specific embodiments described herein, as it will be readily understood from this disclosure by those skilled in the art that currently existing or later developed processes, machines, manufactures, compositions of matter, means, methods, or steps can perform substantially the same functions or achieve substantially the same results as the corresponding embodiments described herein. Therefore, the appended claims are intended to include such processes, machines, manufactures, compositions of matter, means, methods, or steps within their scope.

[0080] Therefore, the specification and drawings should be regarded merely as a description of the disclosure as defined by the appended claims, and are intended to cover any and all modifications, variations, combinations or equivalents falling within the scope of the disclosure.

Claims

1. An integrated circuit, comprising: a first terminal and a second terminal, wherein a first voltage is applied between the first terminal and the second terminal; a processor coupled between the first terminal and the second terminal, the processor configured to execute instructions and generate a first control signal of a binary species; a disturbance circuit, the disturbance circuit configured to: receive the first control signal, and generate a second control signal based on the first control signal, the second control signal being a digital signal having N bits, where N is an integer equal to or greater than two; and a digital-to-analog converter, the digital-to-analog converter configured to: receive the second control signal, and generating an interference current based on the second control signal, the interference current being a value between zero and a constant maximum current value and having 2 N possible values, and a current flowing from the first terminal to the second terminal being equal to a sum of a current drawn from the processor and the interference current.

2. The integrated circuit of claim 1, wherein the digital-to-analog converter is also coupled between the first terminal and the second terminal, and the digital-to-analog converter is arranged in parallel with the processor.

3. The integrated circuit of claim 1, wherein the processor includes a power supply, the integrated circuit further comprising: a regulator coupled between the first terminal and the second terminal, the regulator configured to deliver a second voltage to the power supply based on the first voltage, and wherein the digital-to-analog converter is also coupled between the first terminal and the second terminal, and the digital-to-analog converter is coupled in parallel with the processor and the regulator.

4. The integrated circuit of claim 1, wherein N is equal to three.

5. The integrated circuit of claim 1, wherein the first control signal is a random signal.

6. The integrated circuit of claim 1, wherein the disturbance circuit comprises: a plurality of flip-flops arranged in series, each flip-flop's operation controlled by a clock signal, wherein a first flip-flop in the series is configured to receive the first control signal, and a last flip-flop in the series is configured to output the second control signal.

7. The integrated circuit of claim 6, wherein the plurality of flip-flops is greater in number than N.

8. The integrated circuit of claim 1, further comprising a smoothing circuit configured to smooth current consumed by the processor.

9. A method implemented by a circuit, comprising: having a processor for executing instructions, the processor coupled between a first terminal and a second terminal; applying a first voltage between the first terminal and the second terminal; generating, by the processor, a first control signal of a binary species; generating, by a disturbance circuit, a second control signal based on the first control signal, the second control signal being a digital signal having N bits, where N is an integer equal to or greater than two; and generating, by a digital-to-analog converter, a disturbance current based on the second control signal, the disturbance current being a value between zero and a constant maximum current value and having 2 N possible values, and a current flowing from the first terminal to the second terminal being equal to a sum of a current drawn from the processor and the disturbance current.

10. The method of claim 9, wherein the digital-to-analog converter is coupled between the first terminal and the second terminal, and the digital-to-analog converter is arranged in parallel with the processor.

11. The method of claim 9, further comprising: having a regulator coupled between the first terminal and the second terminal; and generating, by the regulator, a second voltage to a power supply of the processor, the second voltage based on the first voltage. ​ 12. The method of claim 9, wherein N is equal to three.

13. The method of claim 9, wherein the first control signal is a random signal.

14. The method of claim 9, wherein the interference circuit comprises: a plurality of flip-flops arranged in series, operation of each flip-flop being controlled by a clock signal, wherein a first flip-flop in the series is configured to receive the first control signal, and a last flip-flop in the series is configured to output the second control signal.

15. A system comprising an integrated circuit, the integrated circuit comprising: a first terminal and a second terminal, wherein a first voltage is applied between the first terminal and the second terminal; a processor coupled between the first terminal and the second terminal, the processor configured to execute instructions and generate a first control signal of a binary species; an interference circuit, the interference circuit configured to: receive the first control signal, and generate a second control signal based on the first control signal, the second control signal being a digital signal having N bits, where N is an integer equal to or greater than two; and a digital-to-analog converter, the digital-to-analog converter configured to: receive the second control signal, and generating an interference current based on the second control signal, the interference current being a value between zero and a constant maximum current value and having 2 N possible values, and a current flowing from the first terminal to the second terminal being equal to a sum of a current drawn from the processor and the interference current.

16. The system of claim 15, wherein the digital-to-analog converter is also coupled between the first terminal and the second terminal, and the digital-to-analog converter is arranged in parallel with the processor.

17. The system of claim 15, wherein the processor comprises a power supply, the integrated circuit further comprising: a regulator coupled between the first terminal and the second terminal, the regulator configured to deliver a second voltage to the power supply based on the first voltage, and wherein the digital-to-analog converter is also coupled between the first terminal and the second terminal, and the digital-to-analog converter is coupled in parallel with the processor and the regulator.

18. The system of claim 15, wherein N is equal to three.

19. The system of claim 15, wherein the first control signal is a random signal.

20. The system of claim 15, wherein the interference circuit comprises: a plurality of flip-flops arranged in series, operation of each flip-flop being controlled by a clock signal, wherein a first flip-flop in the series is configured to receive the first control signal, and a last flip-flop in the series is configured to output the second control signal.

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