Using chip enable pins for status checking

Abstract

This application relates to using a chip enable pin for status checking. An apparatus can include a memory device, a pin coupled with the memory device, and a driver coupled with the pin and configured to bias the pin to a first voltage or a second voltage based on a status of the memory device. The status can indicate, for example, whether the memory device is available to receive a command. The driver can bias the pin to the first voltage based on a first status of the memory device indicating that the memory device is busy. Additionally or alternatively, the driver can bias the pin to the second voltage based on a second status of the memory device indicating that the memory device is available to receive the command. In some cases, the pin can be an instance of a chip enable pin.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 117,933, filed December 10, 2020, entitled “STATUS CHECK USING CHIP ENABLE PIN”, which is assigned to the assignee and is expressly incorporated herein by reference in its entirety. Technical Field

[0003] The technical field involves using chip enable pins for status checks. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed to support one of two states, often corresponding to logic 1 or logic 0. In some instances, a single memory cell can support more than two possible states, and any one of those two possible states can be stored by the memory cell. To access the information stored by the memory device, a component can read or sense the state of one or more memory cells within the memory device. To store information, a component can write or program one or more memory cells within the memory device into corresponding states.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), 3D crosspoint memory, NOR (Non-OR), and NAND (NAND) memory devices. Memory devices can be volatile or non-volatile. Volatile memory cells (e.g., DRAM cells) can lose their programmed state over time unless periodically updated by an external power supply. Non-volatile memory cells (e.g., NAND memory cells) can maintain their programmed state for a long period of time even in the absence of an external power supply. Summary of the Invention

[0006] Describe a device. The device may include: a memory device; a pin coupled to the memory device and configured to receive a chip enable signal for the memory device; and a driver coupled to the pin and configured to bias the pin to a first voltage or a second voltage at least in part based on a state of the memory device, the state indicating whether the memory device is available to receive commands.

[0007] Describe another device. The device may include: a memory device; a pin coupled to the memory device and configured to receive a chip enable signal for the memory device; and a controller coupled to the memory device and the pin, wherein the controller is operable to cause the device to: determine the state of the memory device at least in part based on the received chip enable signal, the state indicating whether the memory device is available to receive commands; and bias the pin to a voltage at least in part based on the determined state of the memory device.

[0008] A method performed by a memory device is described. The method may include: receiving a chip enable signal via a pin configured to receive a chip enable signal; determining a state of the memory device, at least in part, based on the received chip enable signal, the state indicating whether the memory device is available to receive a command; and biasing the pin to a voltage indicating the state, at least in part, based on the determined state of the memory device.

[0009] Another device is described. The device may include: a memory device; a pin coupled to the memory device; and a driver coupled to the pin and configured to bias the pin to a first voltage or a second voltage, at least in part, based on the state of the memory device, the state indicating whether the memory device is available to receive commands. Attached Figure Description

[0010] Figure 1 This document describes examples of systems that support status checks using chip enable pins, based on the examples disclosed herein.

[0011] Figure 2 This document describes examples of systems that support status checks using chip enable pins, based on the examples disclosed herein.

[0012] Figure 3 This document describes an example of the process flow for supporting status checks using the chip enable pin, based on the examples disclosed herein.

[0013] Figure 4 A block diagram illustrating a memory device that supports status checks using a chip enable pin, based on examples disclosed herein.

[0014] Figure 5 The flowchart illustrates one or more methods for performing status checks using the chip enable pin, based on the examples disclosed herein. Detailed Implementation

[0015] A memory device can provide one or more states indicating information about itself. For example, a state (e.g., Ready / Busy (R / B) state, Pass / Fail state, or some other state) can indicate whether the memory device is available to receive commands (e.g., from a host device). In some cases, a device coupled to a memory device (e.g., a host device, controller, or some other device) can poll the memory device (e.g., via a polling command) to determine its state. In some cases, the device can periodically and blindly poll the memory device until a state (e.g., a Ready state) indicates that the memory device is ready (i.e., available to receive commands). However, due to periodic polling, a delay can exist between when the memory device becomes ready and when the device knows that the memory device is ready, thereby increasing the latency for communicating with the memory device. Furthermore, polling the memory device can increase the overhead and latency for communicating with the memory device and reduce bus utilization efficiency due to sending, processing, and responding to polling commands. In some other cases, the memory device may include additional pins dedicated to transmitting the R / B status of the memory device, but these additional pins may increase the cost of the memory device, and in some cases, it may not be possible to indicate the R / B status of individual memory dies of the memory device without polling commands.

[0016] This document describes techniques, systems, and apparatus for determining the state of a memory device by signaling a status using pins, said pins being configured to also transmit other information (e.g., a chip enable pin). In some cases, circuitry can determine the state of a memory device without using polling commands or adding pins to the memory device. For example, the memory device may be coupled to a pin configured to receive a chip enable (CE) signal for the memory device. A driver may be coupled to the pin and configured to bias the pin to a voltage based on the state of the memory device. For example, if the memory device is busy (i.e., unavailable for receiving commands), the driver may bias the pin to a first voltage indicating that the memory device is busy. If the memory device is ready, the driver may bias the pin to a second voltage indicating that the memory device is ready. Circuitry coupled to the pin (e.g., included in a host device, controller, or some other component) may be configured to monitor the pin (e.g., the voltage of the pin, the current of the pin) to determine the state of the memory device. Thus, when the memory device becomes ready, the driver may bias the pin to the second voltage, and the circuitry may determine the ready state of the memory device. This method allows circuits to detect when a memory device transitions from busy to ready with less latency than some configurations that use polling to determine the state of the memory device. This technology, system, and apparatus can improve latency, overhead, cost, and other benefits associated with status signaling.

[0017] First, as referenced Figures 1 to 2 Features of this disclosure are described in the context of the systems, apparatus, and circuits described herein. (See references...) Figure 3 The features of this disclosure are described in the context of the process flow described herein. (See references...) Figure 4 and 5 The device diagrams and flowcharts described herein, which further illustrate and illustrate these and other features of this disclosure, are further explained with reference to the device diagrams and flowcharts.

[0018] Figure 1 This document provides an example of a system 100 that supports status checks using a chip enable pin, based on the examples disclosed herein. System 100 includes a host system 105 coupled to a memory system 110.

[0019] The memory system 110 may be or include any device or collection of devices, wherein the device or collection of devices includes at least one memory array. For example, the memory system 110 may be or include a Universal Flash Storage (UFS) device, an Embedded Multimedia Controller (eMMC) device, a flash device, a Universal Serial Bus (USB) flash device, a Secure Digital (SD) card, a Solid State Drive (SSD), a Hard Disk Drive (HDD), a Dual In-line Memory Module (DIMM), a Small Form Factor DIMM (SO-DIMM), or a Non-Volatile DIMM (NVDIMM), and other possibilities.

[0020] System 100 may be included in a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), device with Internet of Things (IoT) capabilities, embedded computer (e.g., embedded computer included in a vehicle, industrial equipment or networked business device), or any other computing device that includes memory and processing devices.

[0021] System 100 may include a host system 105 that can be coupled to a memory system 110. In some instances, this coupling may include an interface to a host system controller 106, which may be an example of a control component configured to cause the host system 105 to perform various operations as described herein. The host system 105 may include one or more devices, and in some cases, may include a processor chipset and software stacking performed by the processor chipset. For example, the host system 105 may include an application configured to communicate with the memory system 110 or devices therein. The processor chipset may include one or more cores, one or more caches (e.g., memory local to the host system 105 or included in the host system), a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a Serial Advanced Technology Attachment (SATA) controller). The host system 105 may use the memory system 110, for example, to write data to and read data from the memory system 110. Although in Figure 1 The diagram shows a memory system 110, but the host system 105 can be coupled to any number of memory systems 110.

[0022] Host system 105 may be coupled to memory system 110 via at least one physical host interface. In some cases, host system 105 and memory system 110 may be configured to communicate via the physical host interface using associated protocols (e.g., to exchange or otherwise transmit control, address, data, and other signals between memory system 110 and host system 105). Examples of physical host interfaces may include, but are not limited to, SATA interfaces, UFS interfaces, eMMC interfaces, PCIe interfaces, USB interfaces, Fibre Channel interfaces, Small Computer System Interface (SCSI), Serial Attached SCSI (SAS), Dual Data Rate (DDR) interfaces, DIMM interfaces (e.g., DDR-enabled DIMM sockets), Open NAND Flash Interface (ONFI), and Low Power Dual Data Rate (LPDDR) interfaces. In some instances, one or more of these interfaces may be included in or otherwise supported between host system controller 106 of host system 105 and memory system controller 115 of memory system 110. In some instances, host system 105 may be coupled to memory system 110 via a corresponding physical host interface for each memory device 130 included in memory system 110, or via a corresponding physical host interface for each type of memory device 130 included in memory system 110 (e.g., host system controller 106 may be coupled to memory system controller 115).

[0023] Memory system 110 may include memory system controller 115 and one or more memory devices 130. Memory device 130 may include one or more memory arrays of any type of memory cells (e.g., non-volatile memory cells, volatile memory cells, or any combination thereof). Although in Figure 1 The example shows two memory devices 130-a and 130-b, but the memory system 110 may contain any number of memory devices 130. Furthermore, the memory system 110 may contain more than one memory device 130, and different memory devices 130 within the memory system 110 may contain the same or different types of memory cells.

[0024] The memory system controller 115 may be coupled to and communicate with the host system 105 (e.g., via a physical host interface) and may be an example of a control component configured to cause the memory system 110 to perform various operations as described herein. The memory system controller 115 may also be coupled to and communicate with the memory device 130 to perform operations generally referred to as access operations at the memory device 130, such as reading data, writing data, erasing data, or updating data, and other such operations. In some cases, the memory system controller 115 may receive commands from the host system 105 and communicate with one or more memory devices 130 to execute such commands (e.g., at a memory array within one or more memory devices 130). For example, the memory system controller 115 may receive commands or operations from the host system 105 and may translate these commands or operations into instructions or appropriate commands to implement the desired access to the memory device 130. In some cases, the memory system controller 115 may exchange data with the host system 105 and with one or more memory devices 130 (e.g., in response to or otherwise in conjunction with commands from the host system 105). For example, the memory system controller 115 may translate responses (e.g., data packets or other signals) associated with the memory device 130 into corresponding signals for the host system 105.

[0025] The memory system controller 115 may be configured for other operations associated with the memory device 130. For example, the memory system controller 115 may perform or manage operations such as wear leveling, garbage collection, error control operations such as error detection or error correction, encryption, caching, media management, background updates, health monitoring, and address translation between logical addresses (e.g., logical block addresses (LBAs)) associated with commands from the host system 105 and physical addresses (e.g., physical block addresses) associated with memory cells within the same memory device 130.

[0026] The memory system controller 115 may include hardware such as one or more integrated circuits or discrete components, buffer memories, or combinations thereof. The hardware may include circuitry with dedicated (e.g., hard-decoded) logic for performing the operations described herein that pertain to the memory system controller 115. The memory system controller 115 may be or include a microcontroller, dedicated logic circuitry (e.g., a field-programmable gate array (FPGA), application-specific integrated circuit (ASIC), digital signal processor (DSP)), or any other suitable processor or processing circuitry.

[0027] The memory system controller 115 may also include local memory 120. In some cases, local memory 120 may include read-only memory (ROM) or other memory that can store operational code (e.g., executable instructions) that can be executed by the memory system controller 115 to perform the functions belonging to the memory system controller 115 herein. In some cases, local memory 120 may additionally or alternatively include static random access memory (SRAM) or other memory that can be used by the memory system controller 115 for, for example, internal storage or operations related to the functions belonging to the memory system controller 115 herein. Additionally or alternatively, local memory 120 may act as a cache for the memory system controller 115. For example, when data is read from or written to memory device 130, data may be stored in local memory 120, and said data may be available within local memory 120 for subsequent retrieval or manipulation (e.g., updating) by the host system 105 according to a caching strategy (e.g., with reduced latency relative to memory device 130).

[0028] although Figure 1 The example of memory system 110 described herein includes memory system controller 115; however, in some cases, memory system 110 may not include memory system controller 115. For example, memory system 110 may additionally or alternatively rely on an external controller (e.g., implemented by host system 105) or one or more local controllers 135, each located within memory device 130, to perform the functions belonging to memory system controller 115 herein. Generally, one or more functions belonging to memory system controller 115 herein may, in some cases, be performed by host system 105, local controller 135, or any combination thereof. In some cases, memory device 130, at least partially managed by memory system controller 115, may be referred to as a managed memory device. An example of a managed memory device is a managed NAND (MNAND) device.

[0029] Memory device 130 may include one or more arrays of non-volatile memory cells. For example, memory device 130 may include NAND (e.g., NAND flash) memory, ROM, phase-change memory (PCM), auto-select memory, other chalcogenide-based memories, ferroelectric RAM (FeRAM), magnetic RAM (MRAM), NOR (e.g., NOR flash) memory, spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), and electrically erasable programmable ROM (EEPROM). Alternatively, memory device 130 may include one or more arrays of volatile memory cells. For example, memory device 130 may include random access memory (RAM) cells, such as dynamic RAM (DRAM) cells and synchronous DRAM (SDRAM) cells.

[0030] In some instances, memory device 130 may include local controllers 135 (e.g., on the same die or within the same package), which may operate on one or more memory cells of memory device 130. Local controllers 135 may operate in conjunction with memory system controller 115, or may perform one or more functions belonging to memory system controller 115 herein.

[0031] In some cases, memory device 130 may be or include a NAND device (e.g., a NAND flash device). Memory device 130 may be or include a memory die 160. For example, in some cases, memory device 130 may be a package including one or more dies 160. In some instances, die 160 may be a block of electronic-grade semiconductor diced from a wafer (e.g., a silicon die diced from a silicon wafer). Each die 160 may include one or more planes 165, and each plane 165 may include a set of corresponding blocks 170, wherein each block 170 may include a set of corresponding pages 175, and each page 175 may include a set of memory cells.

[0032] In some cases, the NAND memory device 130 may include memory cells configured to each store one bit of information, which may be referred to as a single-level cell (SLC). Alternatively, the NAND memory device 130 may include memory cells configured to each store multiple bits of information. If configured to store two bits of information, it may be referred to as a multi-level cell (MLC); if configured to store three bits of information, it may be referred to as a three-level cell (TLC); if configured to store four bits of information, it may be referred to as a four-level cell (QLC), or more generally, a multi-level memory cell. Multi-level memory cells can provide greater storage density compared to SLC memory cells, but in some cases, this may involve narrower read or write tolerances or greater complexity for supporting circuitry.

[0033] In some cases, plane 165 may refer to a group of blocks 170, and in some cases, parallel operations may occur within different planes 165. For example, memory cells within different blocks 170 can be operated on in parallel, as long as the different blocks 170 are in different planes 165. In some cases, parallel operations in different planes 165 may be subject to one or more restrictions, such as performing the same operation on memory cells within different pages 175, which have the same page address within their respective planes 165 (e.g., regarding command decoding, page address decoding circuitry, and other circuitry shared across planes 165).

[0034] In some cases, block 170 may contain memory cells organized into rows (page 175) and columns (e.g., strings, not shown). For example, memory cells in the same page 175 may share a common word line (e.g., coupled thereto), and memory cells in the same string may share a common digital line (which may alternatively be called a bit line) (e.g., coupled thereto).

[0035] For some NAND architectures, memory cells can be read and programmed (e.g., written) at a first-level granularity (e.g., at the page level), but can be erased at a second-level granularity (e.g., at the block level). That is, page 175 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently programmed or read (e.g., programmed or read simultaneously as part of a single programming or reading operation), and block 170 can be the smallest unit of memory (e.g., a set of memory cells) that can be independently erased (e.g., erased simultaneously as part of a single erase operation). Furthermore, in some cases, NAND memory cells can be erased before they can be rewritten with new data. Therefore, for example, in some cases, a used page 175 may not be updated until the entire block 170 containing page 175 has been erased.

[0036] Memory device 130 can provide a status indicating information about memory device 130 (e.g., R / B status, pass / fail status, normal status, or some other status). In some instances, to indicate the status of memory device 130, memory device 130 may be coupled to a pin configured to receive a CE signal for memory device 130 (e.g., indicating whether memory device 130 is available for access). The pin of memory device 130 may be coupled to a driver configured to bias the pin to a voltage based on the status of memory device 130. For example, if memory device 130 has a first state, the driver may bias the pin to a first voltage, and if memory device 130 has a second state, the driver may bias the pin to a second voltage. In some instances, status communication may be configured to avoid conflict with a chip enable signal transmitted via the same pin, thereby enabling the pin to transmit both the chip enable signal to the memory device and the status to the circuitry. Circuitry coupled to the pin (e.g., included in some other component of host system controller 106, memory system controller 115, or host system 105 or memory system 110) can be configured to monitor the pin (e.g., the voltage or current of the pin) to determine the state of memory device 130. When memory device 130 transitions from a first state to a second state or vice versa, a driver can bias the pin, and thus the circuitry can determine the new state of memory device 130. As described herein, this method enables precise timing detection of when memory device 130 transitions to a new state, thereby providing advantages in latency, overhead, cost, and other aspects.

[0037] System 100 may include any number of non-transitory computer-readable media that support status checks using chip enable pins. For example, host system 105, memory system controller 115, or memory device 130 may include or otherwise access one or more non-transitory computer-readable media that store instructions (e.g., firmware) to perform functions belonging to host system 105, memory system controller 115, or memory device 130 herein. For example, when executed by host system 105 (e.g., by host system controller 106), memory system controller 115, or memory device 130 (e.g., by local controller 135), such instructions may cause host system 105, memory system controller 115, or memory device 130 to perform one or more associated functions as described herein.

[0038] Figure 2 This document describes an example of a system 200 that supports status checks using a chip enable pin, based on the examples disclosed herein. System 200 may be as described in the references. Figure 1Examples of system 100 as described in the description of the present invention. For example, system 200 may include circuitry 205 and memory devices 210-a, 210-b, which may be an example of memory system controller 115 or host system controller 106 or both and memory device 130, as referred to in detail below. Figure 1 As described. For illustrative purposes, Figure 2 Two memory devices 210 are depicted; however, the principles disclosed below are also suitable for and applicable to any number of memory devices.

[0039] Circuit 205 may be coupled to and communicate with memory device 210 to perform operations such as access operations. In some cases, circuit 205 may be an example of an ASIC coupled to memory device 210 (e.g., memory system controller 115, host system controller 106, or some other controller). Memory device 210 may transmit status information to circuit 205, such as whether memory device 210 is available to receive commands. In some cases, circuit 205 may periodically poll memory device 210 to check its status; however, polling memory device 210 may introduce a delay between when memory device 210 becomes available to receive commands and when circuit 205 becomes aware that memory device 210 is available to receive commands. Additionally, in some cases, circuit 205 may be a CE driver and pin 215 may be a CE pin. Here, the memory device 210 can be polled using pins other than pin 215 (e.g., address enable latch pin, command latch enable pin, data pin, or some other pin), and pin 215 can be kept low during polling (e.g., biased to a voltage lower than that indicating whether the memory device 210 is available for access). Therefore, polling the memory device 210 to transmit status information increases the throughput on other pins of the memory device 210, thereby increasing latency.

[0040] To transmit status information without polling commands, memory device 210 may bias pin 215, coupled to memory device 210 and circuit 205, to a voltage based on the state of memory device 210. For example, memory device 210-a may bias pin 215 to a first voltage when memory device 210-a is busy (i.e., unavailable for receiving commands) and bias pin 215 to a second voltage when memory device 210-a is ready (i.e., available for receiving commands). Circuit 205 may determine the state of memory device 210 based on the voltage of pin 215.

[0041] In some instances, pin 215 may have one or more specific functions. For example, pin 215 may be a CE pin configured to receive a CE signal indicating whether memory device 210 is available for access. Memory device 210 may include buffers 225 (e.g., buffers 225-a, buffers 225-b) that receive the CE signal and generate an internal CE signal for use by memory device 210. By biasing pin 215 to a voltage based on the state of memory device 210, memory device 210 may transmit information beyond its original function. In some memory systems, the CE pin may be configured to transmit the CE signal in a unidirectional (one-way communication) manner. In this case, the CE pin of circuit 205 may include a driver, and the CE pin of memory device 210 may include a receiver (e.g., buffers 225-a, buffers 225-b). In the memory system described herein, the CE pin of circuit 205 may include both a driver and a receiver, and the CE pin of memory device 210 may include both a driver and a receiver.

[0042] To bias pin 215 to a voltage, memory device 210 may include a driver 220. Driver 220 may be coupled to pin 215 (e.g., via conductive line 235) and to a voltage source 240. For example, memory device 210-a may include a driver 220-a coupled to voltage source 240-a and coupled to pin 215 via conductive line 235-a. Memory device 210-a may use driver 220-a to couple voltage source 240-a to pin 215. For example, driver 220-a may include one or more transistors that can be activated or deactivated to couple pin 215 to or decouple it from voltage source 240-a, respectively. In some cases, voltage source 240-a may be ground or dummy ground. Here, driver 220-a can act as a "pull-down" driver, such that coupling pin 215 to voltage source 240-a reduces the voltage across pin 215. In some other cases, voltage source 240-a can be a voltage supply. Here, driver 220-a can act as a "pull-up" driver, such that coupling pin 215 to voltage source 240-a increases the voltage across pin 215. In some cases, driver 220 can include any number of devices or "pins" to pull the signal on the pin to the desired level.

[0043] Memory device 210-a can use driver 220-a to couple pin 215 to voltage source 240-a based on the state of memory device 210-a. For example, if memory device 210-a is busy, it can use driver 220-a to couple pin 215 to voltage source 240-a, thereby biasing pin 215 to a first voltage. If memory device 210-a is ready, it can use driver 220-a to decouple pin 215 from voltage source 240-a, thus biasing pin 215 to a second voltage. In some cases, if memory device 210-a is busy, it can decouple pin 215 from voltage source 240-a, and if it is ready, it can couple pin 215 to voltage source 240-a.

[0044] Circuit 205 can determine the state of memory device 210-a based on the voltage biased to pin 215. For example, circuit 205 may include a receiver 230 for monitoring the voltage at pin 215. Receiver 230 may be coupled to pin 215 via conductive line 235-c and may be coupled to other components of circuit 205 via conductive line 235-c. In some instances, receiver 230 can determine the state of memory device 210-a by comparing the voltage at pin 215 to a set of voltages. For example, each voltage in the voltage set may be associated with the state of memory device 210-a. Receiver 230 can compare the voltage at pin 215 to the voltage set to determine the voltage of the voltage set. Receiver 230 can determine the state of memory device 210-a based on the state associated with the determined voltage. In some instances, receiver 230 may be a series of analog comparators, where each analog comparator is associated with a voltage in the voltage set. In some other instances, receiver 230 may be a digital comparator that identifies the value of the voltage at pin 215 and compares it to a set of voltages. In some cases, receiver 230 may determine the state of memory device 210-a by comparing the current at pin 215 to a set of currents, where each current in the set is associated with a state of memory device 210-a.

[0045] In some instances, pin 215 can be biased according to timing diagram 265. For example, before time t1, circuit 205 can bias pin 215 to voltage V. ssQ 270. To bias pin 215 to V ssQ270. Circuit 205 may include one or more voltage sources 240 and one or more transistors, as well as other components. For example, circuit 205 may include voltage source 240-c, voltage source 240-d, transistor 250, and transistor 255. Circuit 205 can bias pin 215 to a voltage by activating transistors 250 and 255. Circuit 205 can activate transistors 250 and 255 by applying a voltage supplied by voltage source 240-d to the gates of transistors 250 and 255, thereby connecting voltage source 240-c to conductor 235-c. Based on the voltage supplied by voltage sources 240-c and 240-d, circuit 205 can bias pin 215 to a voltage including V. ssQ Voltage range of 270.

[0046] In some instances, biasing pin 215 to VssQ 270 can indicate access to memory device 210-a (e.g., the CE signal indicates that memory device 210-a is enabled). That is, biasing pin 215 to V ssQ 270 allows memory device 210-a to receive commands from circuit 205 or from another component coupled to memory device 210-a (e.g., a controller, a host device). Pin 215 is biased to voltage V. ccQ 280 may indicate that memory device 210-a is not accessed (e.g., the CE signal indicates that memory device 210 is not enabled).

[0047] At t1, circuit 205 can begin to bias pin 215 to V. ccQ 280. For example, memory device 210-a may receive a command before t1 and may begin executing the command. The voltage at pin 215 may be increased above the breakpoint 285 indicating that memory device 210-a is not available for access (e.g., less than 45mV of VccQ 280 or some other voltage). That is, if the voltage at pin 215 is higher than the breakpoint 285, then memory device 210-a may not be available for access. In response to receiving a command before t1, memory device 210-a may enter a busy state and use driver 220 to couple pin 215 to voltage source 240-a.

[0048] At t2, memory device 210-a can bias pin 215 to voltage V. Busy 275, this is because memory device 210-a executes commands and may not be used to receive other commands. For example, circuit 205 can convert voltage V ccQ A voltage of 280 is applied to pin 215; however, using driver 220-a to couple pin 215 to voltage source 240-a reduces the voltage drop from pin 215 to V. BusyA voltage of 275. For example, driver 220-a can act as a pull-down driver, causing the voltage at pin 215 to decrease when driver 220-a couples pin 215 to voltage source 240-a. Receiver 230 can be biased to V Busy Pin 215 of 275 defines memory device 210-a. V Busy The 275 level can be configured to be lower than V. ccQ 280 (which indicates the presence of a CE signal) and above the breakpoint 285 (which is a reference level used by the receiver of the memory device 210 to distinguish whether the CE signal is on or off).

[0049] At t3, memory device 210-a can enter a ready state. In response to entering the ready state, memory device 210-a can use driver 220-a to decouple pin 215 from voltage source 240-a. Because pin 215 is decoupled from voltage source 240-a, memory device 210-a can bias pin 215 to V... ccQ 280. Receiver 230 can be based on bias to V ccQ Pin 215 of 280 determines that memory device 210-a is ready. In some cases, biasing (via driver 220) to a level indicating that memory device 210 is ready to receive another signal involves turning off driver 220 and allowing the signal to be biased to V. ccQ 280 or some other voltage.

[0050] In the example of timing diagram 265, pin 215 may be referred to as a "low-active" pin. That is, when pin 215 is biased to a voltage below the breakpoint 285, memory device 210-a is available for access. In some cases, pin 215 may be a "high-active" pin, such that when pin 215 is biased to a voltage above the breakpoint 285, memory device 210-a is available for access. Here, V Busy 275 can be lower than the breakout point 285, and circuit 205 can bias pin 215 to V before t1. ccQ 280 and after t1, bias pin 215 to V. ssQ 270. In addition, in this case, driver 220-a can act as a pull-up circuit, such that when driver 220-a couples pin 215 to voltage source 240-a, the voltage of pin 215 increases.

[0051] In some instances, memory device 210-a may include multiple drivers 220 (not shown) to transmit information about multiple states of memory device 210-a via multiple pins 215. For example, memory device 210-a may include a first driver 220 that biases a first pin 215 based on a first state of memory device 210-a, and a second driver 220 that biases a second pin 215 based on a second state of memory device 210-a. For example, the first state may indicate whether memory device 210-a is busy or ready, and the second state may indicate whether memory device 210-a has successfully operated. Memory device 210-a may use the first driver 220 to bias the first pin 215 to a first voltage or a second voltage based on the first state, and may use the second driver 220 to bias the second pin 215 to a third voltage or a fourth voltage based on the second state. Receiver 230 may determine a first state based on comparing the voltage of the first pin 215 with a voltage set, and may determine a second state based on comparing the voltage of the second pin 215 with a voltage set. In some instances, an additional driver 220 may be included in memory device 210-a to transmit additional state information using the additional pin 215.

[0052] In some instances, pin 215 may be biased to a voltage to transmit status information for more than one memory device 210. For example, pin 215 may be coupled to memory device 210-a via conductor 235-a and to memory device 210-b via conductor 235-b. Driver 220-a may be configured to bias pin 215 to a first voltage or a second voltage based on the status of memory device 210-a, and driver 220-b may be configured to bias pin 215 to a third voltage or a fourth voltage based on the status of memory device 210-b. For example, if memory devices 210-a and 210-b are ready, then driver 220 may not be coupled to pin 215, and the voltage of pin 215 may be V. ccQ 280. Receiver 230 can be based on bias to V ccQ The voltage at pin 215 of 280 determines whether both memory devices 210 are ready. However, if one or both memory devices 210 are busy, the corresponding driver 220 can couple pin 215 to the corresponding voltage source 240, thereby reducing the voltage at pin 215 when the driver 220 acts as a pull-down driver. Based on the reduced voltage at pin 215, the receiver 230 can determine which memory devices 210 are busy. In some instances, if pin 215 is a low-level active pin, then the first, second, third, and fourth voltages are greater than the breakpoint 285, or if pin 215 is a high-level active pin, then these voltages are less than the breakpoint 285.

[0053] Drivers 220-a and 220-b may bias pin 215 based on corresponding resistors of driver 220. For example, driver 220-a may have a first resistor, and driver 220-b may have a second resistor different from the first resistor. In some cases, the first and second resistors may be inherent resistors of the respective drivers 220. In some cases, driver 220-a may include a resistor with the first resistor, and driver 220-b may include a resistor with the second resistor. Because the first and second resistors are different, coupling pin 215 to voltage source 240-a will reduce the voltage at pin 215 by a different amount than coupling pin 215 to voltage source 240-b. For example, if the first resistor is greater than the second resistor, then coupling pin 215 to voltage source 240-a will reduce the voltage at pin 215 by a greater amount than coupling pin 215 to voltage source 240-b. In this way, receiver 230 can determine state information for each memory device 210. The resistor of each driver 220 of each memory device 210 can be configured such that circuitry 205 can determine whether any combination of memory devices 210 is available to receive commands based on the voltage level or impedance of pin 215. For example, if a single memory device 210 is ready, pin 215 can be driven to a first level; if the first memory device 210-a and the second memory device 210-b are ready, pin 215 can be driven to a second level; or if the first memory device 210-a and a third memory device (not shown) are ready, pin 215 can be driven to a third level. Thus, multiple memory devices 210 can use the same pin 215 and / or channel to transmit a ready signal, and circuitry 205 can uniquely identify which memory device 210 is ready. In effect, the status signal on pin 215 can be multiplexed in such a way as to encode which memory device 210 is ready.

[0054] In some instances, memory devices 210-a and 210-b may be dies (e.g., die 160) included within a single memory device 210. In some cases, additional dies may be included within a single memory device 210. Circuit 205 may determine the state information of each die of the single memory device 210 based on the voltage biased to pin 215.

[0055] Figure 3 This document describes an example of process flow 300 that supports status checks using a chip enable pin, based on the examples disclosed herein. Aspects of process flow 300 can be implemented through system components, for example, by referring to... Figure 1 and 2Systems 100 and 200 are described. For example, process flow 300 can be implemented via circuit 305 and memory device 310, which can be instances of circuit 205 and memory devices 130 and 210, as referred to respectively. Figure 1 and 2 As described. Process flow 300 can be implemented to reduce latency, overhead, and cost of memory device 310, and other advantages. Aspects of process flow 300 can be implemented by a controller and other components. Alternatively, aspects of process flow 300 can be implemented as instructions stored in memory (e.g., firmware stored in memory coupled to memory device 310). For example, the instructions, when executed by a controller (e.g., circuitry 305), can cause the controller to perform the operation of process flow 300.

[0056] In the following description of process flow 300, operations may be performed in different orders or at different times. Some operations may also be omitted from process flow 300, and other operations may be added to process flow 300.

[0057] At 315, a pin coupled to memory device 310 can be driven low. For example, circuitry 305 can be coupled to the pin and drive it low. In some instances, driving the pin low indicates that memory device 310 is available for access. For example, the pin can be the CE pin, and driving the CE pin low enables memory device 310 to receive write commands, read commands, or other access commands from circuitry 305 or another component coupled to memory device 310.

[0058] At 320, memory device 310 is operable. For example, when the pin drive is low, circuit 305 or another component coupled to memory device 310 can send one or more access commands to memory device 310.

[0059] At 325, the pin can be driven high. For example, circuit 305 can drive the pin high. In some instances, driving the pin high indicates that the memory device is unavailable for access. For example, the pin could be the CE pin, and driving the CE pin high can prevent memory device 310 from receiving write commands, read commands, or other access commands from circuit 305 or another component coupled to memory device 310. In some cases, circuit 305 can drive the pin high in response to memory device 310 receiving an access command. For example, memory device 310 can receive an access command and begin processing it. Memory device 310 can be busy processing an access command, and circuit 305 can drive the pin high to prevent memory device 310 from receiving additional access commands.

[0060] At 330, the pin can be coupled to a voltage source. For example, in response to entering a busy state, memory device 310 can use a driver to couple the pin to a voltage source. In some cases, the voltage source can be ground or a virtual ground. In some instances, the driver can include one or more transistors, and memory device 310 can couple the pin to the voltage source by activating one or more transistors.

[0061] At point 335, the pin can be biased to a first voltage. For example, memory device 310 can bias the pin to the first voltage by coupling the pin to a voltage source. Although process flow 300 specifies that 335 occurs after 330, in some instances, 335 can occur simultaneously with 330. In some instances, the driver may include a resistor. In some cases, the resistor may be the inherent resistance of the driver. In some other cases, the driver may include a resistor with resistance. In some instances, the pin can be biased to the first voltage based on the resistance of the driver.

[0062] At 340, a first voltage can be compared to a voltage set. For example, circuit 305 can use a receiver coupled to a pin of circuit 305 to compare the first voltage to the voltage set. In some cases, a voltage set can be defined such that each voltage in the voltage set is associated with the state of memory device 310. In some instances, biasing a pin to the first voltage can generate a first current across the pin, and circuit 305 can compare the first current to a current set. In some cases, a current set can be defined such that each current in the current set is associated with the state of memory device 310.

[0063] At 345, the busy state of memory device 310 can be determined. For example, a first voltage can be associated with the busy state, and based on comparing the first voltage with a voltage set, circuit 305 can determine that memory device 310 is busy. In some instances, circuit 305 can determine that memory device 310 is busy based on comparing a first current with a current set.

[0064] At position 350, a ready state can be entered. For example, memory device 310 can finish processing a previously received access command and enter a ready state, making memory device 310 available to receive another access command.

[0065] At 355, the pin can be decoupled from the voltage source (e.g., one or more means of the driver at memory device 310 can be deactivated to disconnect the pin from the voltage source). For example, in response to entering a ready state, memory device 310 can use the driver to decouple the pin from the voltage source. In some instances, memory device 310 can decouple the pin from the voltage source by deactivating one or more transistors contained in the driver.

[0066] At 360, the pin can be biased to a second voltage. For example, memory device 310 can bias the pin to a second voltage by using a driver to decouple the pin from the voltage source. Although process flow 300 describes 360 as occurring after 350 and 355, in some instances, 360 can occur simultaneously with 350 and 355.

[0067] At 365, the second voltage can be compared with a set of voltages. For example, circuit 305 can compare the second voltage with a set of voltages. In some instances, biasing a pin to the second voltage can generate a second current across the pin, and circuit 305 can compare the second current with a set of currents.

[0068] At 370, the ready state of the memory device can be determined. For example, a second voltage can be associated with the ready state, and based on comparing the second voltage with a voltage set, circuit 305 can determine that memory device 310 is ready. In some instances, circuit 305 can determine that memory device 310 is ready based on comparing a second current with a current set. Therefore, the state of the memory device can be determined without polling commands.

[0069] Figure 4 A block diagram 400 illustrates a system 405 that supports status checks using a chip enable pin, based on examples disclosed herein. System 405 may be as described in the references... Figures 1 to 2 Examples of aspects of the described system. System 405 or its various components may be examples of various aspects of constructs for performing status checks using the chip enable pins described herein. For example, system 405 may include communication component 410, status component 415, bias component 420, comparator 425, or any combination thereof. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0070] Communication component 410 may be configured or otherwise support means for receiving a chip enable signal by the memory device via a pin configured to receive a chip enable signal. Status component 415 may be configured or otherwise support means for determining the status of the memory device based on the received chip enable signal, the status indicating whether the memory device is available to receive commands. Bias component 420 may be configured or otherwise support means for biasing pins to a voltage indicating the status based on the determined status of the memory device.

[0071] In some instances, to support pin biasing to a voltage, biasing component 420 may be configured or otherwise support means for biasing the pin to a first voltage based on a first state of the memory device, indicating that the memory device is busy. In some instances, to support pin biasing to a voltage, biasing component 420 may be configured or otherwise support means for biasing the pin to a second voltage based on a second state of the memory device, indicating that the memory device is available to receive commands. In some cases, the first voltage is lower than the second voltage. In some other cases, the second voltage is lower than the first voltage.

[0072] In some instances, to support pin biasing to a voltage, biasing component 420 may be configured or otherwise support a component for coupling the pin to a voltage source using a driver configured to bias the pin to a voltage based on a defined state. In some instances, the pin is biased to a voltage based on the resistance of the driver.

[0073] In some instances, the state component 415 may be configured or otherwise support means for determining the state of the second memory device based on a received chip enable signal. In some instances, the bias component 420 may be configured or otherwise support means for biasing pins to a second voltage based on determining the state of the second memory device.

[0074] In some cases, to support the determination of the state of a memory device, comparator 425 may be configured or otherwise supported to support means for comparing a voltage with a set of voltages associated with the state of the memory device. In some instances, to support the determination of the state of a memory device, comparator 425 may be configured or otherwise supported to support means for comparing the current of a pin with a set of currents associated with the state of the memory device, wherein the current of the pin is based on biasing the pin to a voltage. In some examples, the voltage may satisfy a threshold voltage indicating that the memory device is not available for access.

[0075] Figure 5 The flowchart illustrates a method 500 for status checking using a chip enable pin, based on the examples disclosed herein. The operation of method 500 can be implemented by a memory device or its components as described herein. For example, it can be implemented by... (See reference...) Figures 1 to 4 The described memory device performs the operation of method 500. In some instances, the memory device may execute an instruction set to control the functional elements of the device to perform the described functions. Alternatively, the memory device may use dedicated hardware to perform aspects of the described functions.

[0076] At point 505, the method may include receiving a chip enable signal by a memory device via a pin configured to receive a chip enable signal. Operation of point 505 may be performed according to examples as disclosed herein. In some examples, aspects of operation of point 505 may be as described in references... Figure 4 The communication component 410 described herein shall be used.

[0077] At 510, the method may include determining the state of the memory device based on a receive chip enable signal, the state indicating whether the memory device is available to receive commands. Operation of 510 may be performed according to examples as disclosed herein. In some examples, aspects of the operation of 510 may be as described in references... Figure 4 The state component 415 described herein shall be used.

[0078] At 515, the method may include biasing a pin to a voltage indicating the state based on determining the state of the memory device. Operation of 515 may be performed according to examples disclosed herein. In some instances, it may be performed by, as referenced... Figure 4 The bias component 420 described performs the operation of 515.

[0079] In some instances, the device as described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for receiving a chip enable signal by a memory device via a pin configured to receive a chip enable signal, determining a state of the memory device based on the received chip enable signal, the state indicating whether the memory device is available to receive commands, and biasing the pin to a voltage indicating the state based on the determined state of the memory device.

[0080] In some examples of the method 500 and device described herein, biasing a pin to a voltage may include operations, features, circuitry, logic, components, or instructions for biasing a pin to a first voltage based on a first state of the memory device, the first state indicating that the memory device may be busy, and biasing a pin to a second voltage based on a second state of the memory device, the second state indicating that the memory device may be available to receive commands.

[0081] In some cases of the method 500 and apparatus described herein, the first voltage may be lower than the second voltage.

[0082] In some instances of the method 500 and device described herein, biasing a pin to a voltage may include operations, features, circuitry, logic, components, or instructions for coupling a pin to a voltage source using a driver configured to bias the pin to a voltage based on a determined state.

[0083] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for biasing pins to voltages that may be based on the resistance of a driver.

[0084] Some examples of the methods 500 and devices described herein may further include operations, features, circuit systems, logic, components, or instructions for determining the state of a second memory device based on a received chip enable signal and biasing pins to a second voltage based on the determined state of the second memory device.

[0085] In some examples of the method 500 and apparatus described herein, determining the state of a memory device may include operations, features, circuitry, logic, components, or instructions for comparing a voltage with a set of voltages associated with the state of the memory device, or comparing the current of a pin with a set of currents associated with the state of the memory device, wherein the current of the pin may be based on biasing the pin to a voltage.

[0086] In some cases of the method 500 and apparatus described herein, the voltage satisfies a threshold voltage indicating that the memory device may not be used for access.

[0087] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are possible. Furthermore, two or more parts from the methods described may be combined.

[0088] Describe a device. The device may include: a memory device; a pin coupled to the memory device and configured to receive a chip enable signal for the memory device; and a driver coupled to the pin and configured to bias the pin to a first voltage or a second voltage based on a state of the memory device, the state indicating whether the memory device is available to receive commands.

[0089] In some instances, the driver may be configured to bias the pin to a first voltage based on a first state of the memory device, the first state indicating that the memory device may be busy, and to bias the pin to a second voltage based on a second state of the memory device, the second state indicating that the memory device may be used to receive commands.

[0090] In some cases, the first voltage may be lower than the second voltage. In other cases with the device, the second voltage may be lower than the first voltage.

[0091] In some cases, the driver may include one or more transistors configured to couple a pin to a voltage source, wherein biasing the pin to a first voltage or a second voltage may be based on using one or more transistors to couple the pin to the voltage source.

[0092] In some instances, the device may include a second memory device coupled to conductive lines associated with pins of the memory device, the second memory device including a second driver configured to bias the conductive lines to a third or fourth voltage based on the state of the second memory device.

[0093] In some cases, the driver includes a first resistor, and the second driver includes a second resistor that is different from the first resistor.

[0094] In some examples, the device may include circuitry coupled to pins and configured to determine the state of a memory device and a second memory device based on biasing the pins to a first voltage, a second voltage, a third voltage, or a fourth voltage.

[0095] In some instances, the device may include circuitry coupled to pins and configured to determine the state of the memory device based on comparing the voltage of the pins to a voltage set or based on comparing the current of the pins to a current set.

[0096] In some cases, the first voltage and the second voltage satisfy the threshold voltage of the chip enable signal, which indicates that the memory device may not be used for access.

[0097] Describe another device. The device may include: a memory device; a pin coupled to the memory device and configured to receive a chip enable signal for the memory device; and a controller coupled to the memory device and the pin, wherein the controller is operable to cause the device to: determine the state of the memory device based on the received chip enable signal, the state indicating whether the memory device is available to receive commands, and bias the pin to a voltage based on the determined state of the memory device.

[0098] In some instances, in order to bias a pin to a voltage, the controller may operate such that the device biases the pin to a first voltage based on a first state of the memory device, the first state indicating that the memory device may be busy, and to a second voltage based on a second state of the memory device, the second state indicating that the memory device may be used to receive commands.

[0099] In some cases, the first voltage may be lower than the second voltage. In some other instances, the second voltage may be lower than the first voltage.

[0100] In some examples, in order to bias a pin to a voltage, the controller can be operated so that the device uses a driver configured to bias the pin to a voltage based on a deterministic state to couple the pin to a voltage source.

[0101] In some instances, pins can be biased to voltage based on the driver's resistance.

[0102] In some cases, the device may include a second memory device coupled to a pin, wherein the controller is operable to cause the device to determine the state of the second memory device based on a received chip enable signal, and to bias the pin to a second voltage based on the determined state of the second memory device.

[0103] In some examples, in order to determine the state of a memory device, the controller may operate such that the device compares a voltage to a set of voltages associated with the state of the memory device or compares the current of a pin to a set of currents associated with the state of the memory device, wherein the current of the pin may be based on biasing the pin to a voltage.

[0104] In some instances, the voltage satisfies a threshold voltage that indicates the memory device may not be used for access.

[0105] Describe another device. The device may include: a memory device; a pin coupled to the memory device; and a driver coupled to the pin and configured to bias the pin to a first voltage or a second voltage based on the state of the memory device, the state indicating whether the memory device is available to receive commands.

[0106] In some instances, the status indicates whether the memory device has operated successfully.

[0107] In some cases, the driver can be configured to bias the pin to a first voltage based on a first state of the memory device, indicating that the memory device has successfully operated, and to bias the pin to a second voltage based on a second state of the memory device, indicating that the memory device has failed to operate.

[0108] In some examples, the device may include: a second pin coupled to a memory device; and a second driver coupled to the second pin and configured to bias the pin to a third or fourth voltage based on the state of the memory device.

[0109] In some instances, the status indicates whether the memory device has operated successfully.

[0110] In some cases, pins can be dedicated to transmitting the status of memory devices.

[0111] The information and signals described herein can be represented using any of a variety of different techniques and skills. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, the signal may represent a bus of signals, which may have various bit widths.

[0112] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enables the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or an indirect conductive path that may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the flow of signals between connected components for a period of time.

[0113] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently not allowed to be transmitted between the components via a conductive path, and in which a signal is allowed to be transmitted between the components via the conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0114] The term "separation" refers to a relationship between components where signals are currently unable to flow between them. If an open circuit exists between components, then the components are separated from each other. For example, components separated by a switch positioned between two components are separated when the switch is open. When the controller separates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0115] The devices comprising memory arrays discussed herein can be formed on semiconductor substrates, such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemicals including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0116] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), then the FET may be called a p-type FET. The channel may be end-capped by an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, makes the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0117] The descriptions herein, illustrated with reference to the accompanying drawings, depict exemplary configurations and do not represent all implementable or claim-scoped instances. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed descriptions include specific details that provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0118] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a hyphen following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any similar component that has the same first reference numeral but is independent of the second reference numeral.

[0119] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions or code on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located in various locations, including distribution such that portions of the functions are implemented in different physical locations.

[0120] For example, the various illustrative blocks and modules described herein can be implemented or performed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. A general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0121] As used herein (included in the claims), "or" as used in a list of items (e.g., a list of items preceded by phrases such as "at least one of" or "one or more of") indicates a list containing endpoints, such that a list of at least one of, for example, A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should also be interpreted as the phrase "at least partially based on".

[0122] Computer-readable media includes both non-transitory computer storage media and communication media, with communication media encompassing any media that facilitates the transfer of a computer program from one place to another. Non-transitory storage media can be any available media accessible by a general-purpose or special-purpose computer. By way of example, and not limitation, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code components in the form of instructions or data structures and is accessible by a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave are included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital versatile discs (DVDs), floppy disks, and Blu-ray discs, where disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of these terms are also included within the scope of computer-readable media.

[0123] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. An apparatus comprising: Memory devices; A pin coupled to the memory device and configured to receive a chip enable signal for the memory device; as well as A driver, coupled to the said pin and configured to: The pin is biased to a first voltage based at least in part on a first state of the memory device, the first state indicating that the memory device is busy; as well as The pin is biased to a second voltage based at least in part on a second state of the memory device, the second state indicating that the memory device is capable of receiving commands.

2. The device according to claim 1, wherein the first voltage is lower than the second voltage.

3. The device of claim 1, wherein the driver comprises: One or more transistors configured to couple the pin to a voltage source, wherein biasing the pin to the first voltage or the second voltage is based at least in part on coupling the pin to the voltage source using the one or more transistors.

4. The device according to claim 1, further comprising: A second memory device coupled to a conductive line associated with the pin of the memory device, the second memory device including a second driver configured to bias the conductive line to a third voltage or a fourth voltage at least in part based on the state of the second memory device.

5. The device according to claim 4, wherein: The driver includes a first resistor; and The second driver includes a second resistor that is different from the first resistor.

6. The device according to claim 4, further comprising: A circuit coupled to the pin and configured to determine the state of the memory device and the state of the second memory device based at least in part on biasing the pin to the first voltage, the second voltage, the third voltage, or the fourth voltage.

7. The device according to claim 1, further comprising: A circuit coupled to the pin and configured to determine the state of the memory device based at least in part on comparing the voltage of the pin to a voltage set or at least in part on comparing the current of the pin to a current set.

8. The device of claim 1, wherein the first voltage and the second voltage satisfy a threshold voltage of the chip enable signal, the threshold voltage indicating that the memory device cannot be used for access.

9. An apparatus comprising: Memory devices; A pin coupled to the memory device and configured to receive a chip enable signal for the memory device; as well as A controller, coupled to the memory device and the pin, wherein the controller is operable to cause the device to perform the following operations: The state of the memory device is determined at least in part based on receiving the chip enable signal, the state indicating whether the memory device can be used to receive commands; The pin is biased to a first voltage based at least in part on a first state of the memory device, the first state indicating that the memory device is busy; as well as The pin is biased to a second voltage at least in part based on a second state of the memory device, the second state indicating that the memory device is capable of receiving the command.

10. The device of claim 9, wherein the first voltage is lower than the second voltage.

11. The device of claim 9, wherein in order to bias the pin to the first voltage and the second voltage, the controller is operable to cause the device to perform the following operations: The pin is coupled to a voltage source using a driver configured to bias the pin to the first voltage and the second voltage, at least in part, based on determining the state.

12. The device of claim 11, wherein biasing the pin to the first voltage and the second voltage is at least partially based on the resistance of the driver.

13. The device according to claim 9, further comprising: A second memory device coupled to the pin, wherein the controller is operable to cause the device to perform the following operations: The state of the second memory device is determined at least in part based on receiving the chip enable signal; and The pin is biased to a second voltage, at least in part, based on determining the state of the second memory device.

14. The device of claim 9, wherein, in order to determine the state of the memory device, the controller is operable to cause the device to perform the following operations: Compare the first voltage and the second voltage with the set of voltages associated with the state of the memory device; or The current of the pin is compared with a set of currents associated with the state of the memory device, wherein the current of the pin is at least partially based on biasing the pin to the first voltage and the second voltage.

15. The device of claim 9, wherein the first voltage and the second voltage satisfy a threshold voltage indicating that the memory device cannot be used for access.

16. A method performed by a memory device, comprising: The chip enable signal is received via a pin configured to receive the chip enable signal; The state of the memory device is determined at least in part based on receiving the chip enable signal, the state indicating whether the memory device can be used to receive commands; The pin is biased to a first voltage based at least in part on a first state of the memory device, the first state indicating that the memory device is busy; as well as The pin is biased to a second voltage at least in part based on a second state of the memory device, the second state indicating that the memory device is capable of receiving the command.

17. The method of claim 16, further comprising: The state of the second memory device is determined at least in part based on receiving the chip enable signal; as well as The pin is biased to a second voltage, at least in part, based on determining the state of the second memory device.

18. An apparatus comprising: Memory devices; A pin, which is coupled to the memory device; as well as A driver, coupled to the said pin and configured to: The pin is biased to a first voltage based at least in part on a first state of the memory device, the first state indicating that the memory device has successfully operated; and The pin is biased to a second voltage at least in part based on a second state of the memory device, the second state indicating that the memory device has failed to perform the operation.

19. The apparatus of claim 18, further comprising: The second pin is coupled to the memory device; as well as A second driver, coupled to the second pin and configured to bias the pin to a third or fourth voltage, at least in part, based on the first and second states of the memory device.

20. The device of claim 18, wherein the pin is dedicated to transmitting the first state and the second state of the memory device.

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