Semiconductor structure and method of forming the same

Abstract

Semiconductor structures and methods of forming the same are provided. According to one embodiment, a semiconductor structure includes: first nanos structures; first gate structures wrapping each of the first nanos structures and disposed over an isolation structure; and a backside gate contact disposed under the first nanos structures and adjacent to the isolation structure. A bottom surface of the first gate structures is in direct contact with the backside gate contact.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor structures and methods for forming the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded multiple generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC evolution, functional density (i.e., the number of interconnect devices per chip area) has generally increased, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) has decreased. This scaling down process typically provides benefits through increased production efficiency and reduced associated costs. However, this scaling down also increases the complexity of handling and manufacturing ICs.

[0003] In IC design, multiple devices can be combined together as cells or standard cells to perform certain circuit functions. Such cells or standard cells can perform logic operations such as NAND, AND, OR, NOR, or inverters, or be used as memory cells, such as static random access memory (SRAM) cells. The number of metal lines in an interconnect cell is a factor determining the cell size, such as cell height. Some existing technologies have included back-side source / drain contacts in an effort to reduce front-side metal lines. While existing contact structures to semiconductor devices are generally sufficient for their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] An embodiment of the present invention provides a semiconductor structure, comprising: a first nanostructure; a first gate structure enclosing each of the first nanostructures and disposed above an isolation structure; and a back-side gate contact disposed below the first nanostructures and adjacent to the isolation structure, wherein the bottom surface of the first gate structure is in direct contact with the back-side gate contact.

[0005] Another embodiment of the present invention provides a semiconductor structure, including: a first plurality of nanostructures; a first gate structure encapsulating each of the first plurality of nanostructures; a first capping layer disposed on the top surface of the first gate structure; a back-side gate contact directly contacting the bottom surface of the first gate structure, the bottom surface being opposite to the top surface; a second plurality of nanostructures; a second gate structure encapsulating each of the second plurality of nanostructures; a second capping layer disposed on the second gate structure; and a front-side gate contact directly contacting the second capping layer.

[0006] Another embodiment of the present invention provides a method for forming a semiconductor structure, comprising: receiving a workpiece, the workpiece comprising: a first nanostructure disposed above a first mesa structure; a second nanostructure disposed above a second mesa structure; a first gate structure enclosing the first nanostructure; a second gate structure enclosing the second nanostructure; a first source / drain component sandwiched between the first nanostructure and the second nanostructure; a second source / drain component spaced apart from the first source / drain component by the second nanostructure; a first pseudo-epicentric plug located below the first source / drain component and between the first mesa structure and the second mesa structure; and a second pseudo-epicentric plug located below the second source / drain component and adjacent to the second mesa structure; replacing the second pseudo-epicentric plug with a back-side source / drain contact; replacing the first mesa structure with a back-side dielectric component; replacing the first pseudo-epicentric plug with a dielectric plug; and replacing the back-side dielectric component with a back-side gate contact that directly contacts the first gate structure. Attached Figure Description

[0007] The various aspects of the invention will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A flowchart of a method for forming a semiconductor device having back-side contacts according to one or more aspects of the present invention is shown.

[0009] Figures 2 to 16 It illustrates one or more aspects of the invention in accordance with Figure 1 A partial three-dimensional view or partial top view of the workpiece during the manufacturing process of the method.

[0010] Figures 17 to 21 The use of one or more aspects of the invention is shown. Figure 1 A partial stereoscopic view of an optional semiconductor structure fabricated using a specific method. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and not intended to be limiting. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, and can also include embodiments where an additional component can be formed between the first and second components, such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the individual embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or component and another, as shown in the figures. In addition to the orientations shown in the figures, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be positioned in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0013] Furthermore, when using terms such as "about," "approximately," etc., to describe numerical values ​​or ranges, the term is intended to encompass values ​​within a reasonable range, taking into account variations inherent during manufacturing as understood by those skilled in the art. For example, based on known manufacturing tolerances associated with manufacturing a component having characteristics associated with that value, a numerical value or range encompasses a reasonable range including the described value, such as within + / - 10% of the described value. For example, a material layer having a thickness of "about 5 nm" can encompass a size range from 4.25 nm to 5.75 nm, where manufacturing tolerances associated with the deposited material layer are known to those skilled in the art to be + / - 15%. Further, the invention may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, prescribe a relationship between the various embodiments and / or configurations discussed.

[0014] As integrated circuit (IC) technology advances towards smaller technology nodes, multi-gate metal-oxide-semiconductor field-effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effects (SCE). Multi-gate devices generally refer to devices with gate structures or portions thereof disposed above more than one side of the channel region. FinFETs and multi-bridge channel (MBC) transistors are examples of multi-gate devices. MBC transistors have gate structures that can extend partially or completely around the channel region to provide access to the channel region on two or more sides. Because their gate structures surround the channel region, MBC transistors can also be called gate-around transistors (SGTs) or gate-all-around (GAA) transistors. However, shrinking the size of multi-gate devices is only one challenge. Reducing the number of conductive components on a substrate of a given size becomes another challenge, as small, densely packaged devices require interconnect structures with densely packed conductive components. Forming densely packaged conductive contacts can be challenging, and the close proximity of adjacent conductive components can affect device performance.

[0015] This invention includes a semiconductor structure comprising back-side contacts to a gate structure and source / drain components to facilitate intra-cell routing and reduce the number of metal lines on the front side of the substrate. The process for forming the back-side contacts to the gate structure and source / drain component regions can be readily integrated. In one embodiment, the semiconductor structure includes a back-side gate contact (BVG) in direct contact with the gate structure and a back-side source contact (VB) electrically coupled to the source components. Back-side conductive components (such as back-side metal lines) may be electrically coupled to one or more of the back-side gate contact and the back-side source contact.

[0016] Various aspects of the invention will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor device according to an embodiment of the present invention. Method 100 is merely an example and is not intended to limit the scope of the invention to what is explicitly described in method 100. Additional steps may be provided before, during, and after method 100, and some steps described may be replaced, eliminated, or rearranged for additional embodiments of the method. For simplicity, not all steps are described in detail herein. The following is in conjunction with... Figures 2 to 16 Description method 100, Figures 2 to 16This is a partial perspective or top view of the workpiece 200 at different manufacturing stages according to an embodiment of method 100. Because the workpiece 200 will be manufactured into a semiconductor device or semiconductor structure at the end of the manufacturing process, it may also be referred to as a semiconductor device or semiconductor structure depending on the context. Furthermore, throughout this application, unless otherwise stated, the same reference numerals denote the same parts. Embodiments of the invention (including method 100) are described with respect to semiconductor structures including MBC transistors. However, the invention is not limited thereto and can be applied to semiconductor structures including other types of multi-gate devices (such as FinFETs).

[0017] refer to Figure 1 and Figure 2 Method 100 includes block 102, wherein a workpiece 200 is received. Figure 2 Workpiece 200 is shown, with its front side (FS) facing upwards and its back side (BS) facing downwards. Workpiece 200 has undergone front-side processing and includes various components. Figure 2 In the illustrated embodiment, workpiece 200 includes a substrate 202. In one embodiment, substrate 202 includes silicon (Si). In other embodiments, substrate 202 may also include other semiconductor materials, such as germanium (Ge), silicon carbide (SiC), silicon germanium (SiGe), III-V semiconductors, or diamond. Workpiece 200 includes various mesa structures, such as a first mesa structure 202-1, a second mesa structure 202-2, or a third mesa structure 202-3, each mesa structure being patterned by substrate 202 and sharing the same composition as substrate 202. Although in Figure 2 Substrate 202 is shown in the figure, but it may be omitted in other figures because substrate 202 can be thinned or ground at the start of the back-side process. Reference Figure 2 The first mesa structure 202-1 and the second mesa structure 202-2 are spaced apart from each other by an isolation member 204. In some embodiments, the isolation member 204 is deposited in a trench formed in the substrate 202. The isolation member 204 may also be referred to as a shallow trench isolation (STI) member 204. The isolation member 204 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric, combinations thereof, and / or other suitable materials.

[0018] refer to Figure 2 The workpiece 200 includes a plurality of vertically stacked channel members 208 (or nanostructures). Each channel member 208 may have a different nanoscale shape or structure, such as nanowires, nanosheets, or nanorods. In the depicted embodiment, as Figure 2As shown, vertically stacked channel members 208 are disposed above each of the first mesa structure 202-1, the second mesa structure 202-2, and the third mesa structure 202-3. At the same vertical level, the spacing between the channel members 208 above the first mesa structure 202-1 and the channel members 208 above the second mesa structure 202-2 can be between approximately 14 nm and approximately 50 nm. This spacing can also be referred to as the spacing between adjacent active regions. Along the Z-direction, each of the channel members 208 can have a thickness between approximately 4 nm and approximately 12 nm. The channel members 208 can be formed of a semiconductor material similar to that of the substrate 202. In one embodiment, the channel member 208 can include silicon (Si). Each channel member 208 is enveloped by a gate structure 240 extending along the Y-direction. Each gate structure 240 can include an interface layer 242, a gate dielectric layer 244 above the interface layer 242, and a gate electrode layer 246 above the gate dielectric layer 244. In some embodiments, interface layer 242 comprises silicon oxide. Gate dielectric layer 244 may also be referred to as a high-k dielectric layer because it is formed of a dielectric material with a dielectric constant greater than that of silicon dioxide (approximately 3.9). In one embodiment, gate dielectric layer 244 may comprise hafnium oxide. Optionally, the gate dielectric layer 244 may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium aluminum oxide (HfAlO), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), yttrium oxide (Y2O3), SrTiO3 (STO), BaTiO3 (BTO), BaZrO, hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), (Ba,Sr)TiO3 (BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. The gate electrode layer 246 may include a single layer or optional multilayer structure, such as a metal layer (work function metal layer) having a selected work function to improve device performance, a pad layer, a wetting layer, a first adhesive layer, a metal alloy, or various combinations of metal silicides. For example, the gate electrode layer 246 may include titanium nitride (TiN), aluminum titanium nitride (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum nitride (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum carbide (TaC), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. Figure 2In this configuration, each gate structure 240 is positioned above the mesa structure and the isolation component 204.

[0019] refer to Figure 2 The workpiece 200 includes a gate spacer 210 disposed along the sidewall of the gate structure 240 above the topmost channel member 208 or above the isolation member 204. The gate spacer 210 may be a single layer or multiple layers. In some embodiments, the gate spacer 210 may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, and / or combinations thereof. Between two adjacent channel members 208, an inner spacer member 220 liner is provided between the sidewalls of the gate structure 240. The inner spacer member 220 may include silicon oxide, silicon nitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, metal nitride, or a suitable dielectric material. Each vertical stack of channel members 208 extends between two source / drain members 230. One end face of each channel member 208 is coupled to one source / drain member 230, and the other end face of each channel member 208 is coupled to the other source / drain member 230. Depending on the conductivity type of the MBC transistor to be formed, the source / drain components 230 can be n-type or p-type. When they are n-type, they can include silicon (Si), phosphorus-doped silicon (Si:P), arsenic-doped silicon (Si:As), antimony-doped silicon (Si:Sb), or other suitable materials, and can be in-situ doped during the epitaxial process by introducing n-type dopants (such as phosphorus (P), arsenic (As), or antimony (Sb)). When they are p-type, they can include germanium (Ge), gallium-doped silicon germanium (SiGe:Ga), boron-doped silicon germanium (SiGe:B), or other suitable materials, and can be in-situ doped during the epitaxial process by introducing p-type dopants (such as boron (B) or gallium (Ga)).

[0020] Workpiece 200 also includes a contact etch stop layer (CESL) 232 disposed above the source / drain component 230 and an interlayer dielectric (ILD) layer (not shown) disposed above the CESL 232. CESL 232 may comprise silicon nitride, silicon oxynitride, and / or other materials known in the art. The ILD layer may comprise materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials). The source / drain component 230 in workpiece 200 may be disposed directly above a pseudo-epicentric plug 218 or a sacrificial plug 218. Each sacrificial plug 218 extends through the substrate 202 and the isolation component 204. Along the X direction, each sacrificial plug 218 is sandwiched between two mesa structures. Along the Y direction, the sacrificial plug 218 is sandwiched between two portions of the isolation component 204 (one shown). In some embodiments, the sacrificial plug 218 may be formed of undoped silicon germanium (SiGe). Along the Z direction, the sacrificial plug 218 may have a height between about 25 nm and about 100 nm. In some embodiments, the composition of the sacrificial plug 218 and the source / drain component 230 is selected such that the sacrificial plug 218 can be selectively removed or etched without substantially damaging the source / drain component 230. For example, when an n-type MBC transistor is desired, the source / drain component 230 is formed of silicon (Si) doped with an n-type dopant, and the sacrificial plug 218 is formed of silicon germanium (SiGe). Due to the reduced germanium (Ge) content, the etching process of etching the sacrificial plug 218 (formed of silicon germanium (SiGe)) when etching the source / drain component can be slowed down. When a p-type MBC transistor is desired, the source / drain component 230 is formed of boron (B)-doped silicon germanium (SiGe). Since the boron (B) dopant can reduce the etching rate, the etching process of etching the sacrificial plug 218 (formed of silicon germanium) can be slowed down when etching the source / drain component 230.

[0021] exist Figure 2In some embodiments shown, workpiece 200 includes a self-aligned cover (SAC) dielectric layer 254 disposed over gate structure 240 and gate spacer 210. SAC layer 254 may be a single layer or multiple layers and may include silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, silicon carbonitride, silicon carbonitride, silicon carbonitride, and / or combinations thereof. Workpiece 200 may also include a front-side source / drain contact 236 located above source / drain component 230. Front-side source / drain contact 236 may include titanium nitride (TiN), tantalum (Ta), titanium (Ti), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), nickel (Ni), copper (Cu), molybdenum (Mo), and may be electrically coupled to source / drain component 230 via a silicide component (not explicitly shown) disposed at the interface between source / drain component 230 and front-side source / drain contact 236. The silicide component may include titanium silicide (TiSi), tungsten silicide (WSi), platinum silicide (PtSi), cobalt silicide (CoSi), nickel silicide (NiSi), or combinations thereof. In some embodiments, the front source / drain contact 236 is formed only above the drain component.

[0022] exist Figure 2 In some embodiments shown, adjacent gate structures 240 or adjacent source / drain components 230 may be spaced apart along the Y direction by dielectric fins 206. The dielectric fins 206 may be single-layered or multi-layered and may have a Y-direction width between approximately 6 nm and approximately 26 nm. When the dielectric fins 206 are as follows... Figures 2 to 17 When the dielectric fin 206 is a single layer as shown, it may comprise silicon nitride, silicon oxide, silicon oxynitride, silicon carbide, silicon carbonitride, silicon, aluminum oxide, hafnium oxide, titanium oxide, zirconium oxide, yttrium oxide, zinc oxide, or a suitable dielectric material. When the dielectric fin 206 is as shown... Figure 20 In the multilayer configuration shown, the dielectric fin 206 may include an outer layer 2062 and an inner layer 2064. In some embodiments, the dielectric constant of the outer layer 2062 is greater than that of the inner layer 2064. In some embodiments, the outer layer is formed of hafnium oxide, zirconium oxide, hafnium aluminum oxide, hafnium silicon oxide, aluminum oxide, or zinc oxide, and the inner layer is formed of silicon oxide, silicon carbonitride, silicon carbide, or silicon carbonitride. The outer layer 2062 serves as an etch-resistant layer to protect the inner layer 2064, and the inner layer 2064 is used to reduce parasitic capacitance. The portion of the gate structure 240 located between the channel member 208 and the adjacent dielectric fin 206 may be referred to as a metal gate cap. According to the invention, the thickness of the metal gate cap along the Y direction may be between about 4 nm and about 15 nm.

[0023] A gate top metal layer 250 may be disposed above each gate structure 240. The gate top metal layer 250 may include tungsten (W) and, when not cut by the gate dicing member 252, may be used to interconnect adjacent gate structures 240. Figure 2 As shown, gate cleaving members 252 can be directly disposed above dielectric fins 206, such that they work together to electrically isolate two adjacent gate structures 240 (and the gate top metal layer 250 above them). Workpiece 200 also includes a dielectric layer 256 disposed above front source / drain contacts 236 and SAC layer 254. Front gate contacts 260 extend through dielectric layer 256 and SAC layer 254 to directly contact and be electrically coupled to gate top metal layer 250. Gate cleaving members 252 may include silicon oxide, silicon nitride, or silicon oxynitride. Dielectric layer 256 may be an interlayer dielectric (ILD) layer and may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide (such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials). Along the Z-direction, the gate cleavage portion 252 can have a height between approximately 6 nm and approximately 20 nm. In other words, the gate cleavage portion 252 can extend further than the gate structure 240 into the gate top metal layer 250 and the SAC layer 254 by up to approximately 6 nm to approximately 20 nm. As measured from the gate top metal layer 250 to the isolation portion 204, the height of the gate structure 240 can be between approximately 8 nm and approximately 30 nm.

[0024] exist Figure 21 In some alternative embodiments shown, the dielectric fins 206 are omitted from the workpiece 200, and Figure 2 The gate structure 240, separated by dielectric fins 206, can be a common or connected gate structure that encloses two different vertically stacked members of the channel member 208 disposed above the two mesa structures. That is, the common or connected gate structure can be configured to activate two MBC transistors instead of one.

[0025] refer to Figure 1 and Figure 3 Method 100 includes block 104, in which workpiece 200 is flipped upside down. To flip workpiece 200 upside down, a carrier substrate (not explicitly shown) is bonded to the front side FS of workpiece 200, away from substrate 202. In some embodiments, the carrier substrate may be bonded to workpiece 200 by fusion bonding, by using an adhesive layer, or a combination thereof. In some cases, the carrier substrate may be formed of a semiconductor material such as silicon, sapphire, glass, a polymer material, or other suitable material. In embodiments using fusion bonding, the carrier substrate includes a bottom oxide layer, and workpiece 200 includes a top oxide layer. After processing the bottom and top oxide layers, they are placed in fuzzy contact with each other for direct bonding at room temperature or high temperature. Once the carrier substrate is bonded to workpiece 200, as... Figure 3 As shown, workpiece 200 is flipped over. After flipping workpiece 200, the back side BS of workpiece 200 is thinned by grinding and planarization techniques until the isolation component 204, sacrificial plug 218, first mezzanine structure 202-1, second mezzanine structure 202-2 and third mezzanine structure 202-3 are exposed on the back side BS of workpiece 200, and the back side BS is now facing upwards.

[0026] refer to Figure 1 and Figure 4 Method 100 includes block 106, wherein a protective layer 264 is selectively formed over a mesa structure (such as a first mesa structure 202-1, a second mesa structure 202-2, or a third mesa structure 202-3). In an example process, the mesa structures (such as the first mesa structure 202-1, the second mesa structure 202-2, and the third mesa structure 202-3) are selectively etched back to deposit a dielectric material over the back side BS of the workpiece 200, and a planarization process is performed to form the protective layer 264 over the mesa structures. In some embodiments, a selective etching process (such as a selective wet etching process or a selective dry etching process) can be used to perform the etch back at block 106. An example selective wet etching process for etching back the mesa structures may include using ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), hydrogen peroxide (H2O2), ammonium fluoride (NH4F), or a suitable wet etchant. Example selective dry etching processes for etching back the mesa structure may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), hydrogen bromide (HBr), argon, or mixtures thereof. In some embodiments, the etching back is time-controlled to etch the mesa structure back to a depth between about 5 nm and about 30 nm. After the etching back, a dielectric material, such as silicon oxide, may be deposited over the back side (BS) of the workpiece 200. A planarization process, such as a chemical mechanical polishing (CMP) process, is performed to remove excess dielectric material over the sacrificial plug 218. In some embodiments, the protective layer 264 may have a composition similar to that of the insulating member 204. In one embodiment, the protective layer 264 is formed of silicon oxide and may have a thickness between about 5 nm and about 30 nm along the Z direction.

[0027] refer to Figure 1 and Figure 5Method 100 includes a frame 108 in which a patterned first hard mask layer 267 is formed to expose the sacrificial plug 218. In an example process, the first hard mask layer 267 is blanket-deposited over the back side (BS) of a workpiece 200 using CVD. The first hard mask layer 267 may be a single layer or multiple layers. In the depicted embodiment, the first hard mask layer 267 is multilayered and may include a nitride layer 266 and an oxide layer 268 situated above the nitride layer 266. After the deposition of the first hard mask layer 267, photolithography and etching processes may be performed to pattern the first hard mask layer 267 to form a patterned first hard mask layer 267 to expose the sacrificial plug 218. In some cases, a photoresist layer is deposited over the first hard mask layer 267. To pattern the photoresist layer, the photoresist layer is exposed to radiation reflected from or transmitted through the photomask, baked in a post-exposure bake process, and developed in a developer. Then, a patterned photoresist layer is applied as an etching mask to etch the first hard mask layer 267, thereby forming the patterned first hard mask layer 267. (See reference) Figure 5 The patterned first hard mask layer 267 includes a first mask opening 271 substantially aligned with the first back-side source / drain contact opening 272 to be formed (described below). According to the invention, the patterned first hard mask layer 267 is used to mask the unetched sacrificial plug 218 at the frame 108. Whether a portion of the protective layer 264 is exposed in the first mask opening 271 is not important. Figure 5 As shown, the first mask opening 271 may not share an end with a portion of the protective layer 264 on the mesa structure. This is because the etching process at frame 110 is selective for the sacrificial plug 218.

[0028] refer to Figure 1 and Figure 6Method 100 includes block 110, in which an exposed sacrificial plug 218 is selectively removed to form a first back-side source / drain contact opening 272. In some embodiments, the removal of the sacrificial plug 218 may be self-aligned because the sacrificial plug 218 (formed of silicon germanium (SiGe)) is disposed between an isolation member 204 (formed of a dielectric material) and a protective layer 264 (which may be formed of silicon oxide). In these embodiments, a selective wet etching process can be used to perform the selective removal of the sacrificial plug 218. Example selective wet etching processes may include using a solution of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2). Because the selective etching process at block 110 etches the sacrificial plug 218 faster than etching the isolation member 204 or the protective layer 264, the sacrificial plug 218 can be removed with minimal damage to the isolation member 204 or the protective layer 264. In the depicted embodiments, the selective removal of the sacrificial plug 218 may also remove a portion of the exposed source / drain portion beneath the sacrificial plug 218. The removal of the sacrificial plug 218 forms a first back-side source / drain contact opening 272 to expose the source / drain component 230.

[0029] refer to Figure 1 and Figure 7 Method 100 includes block 112, wherein a back-side source / drain contact 274 is formed in a first back-side source / drain contact opening 272. Although not explicitly shown, each back-side source / drain contact 274 may include a silicide layer 275. Figure 7 Not shown in the image, but... Figure 17 (As shown in the diagram) to intersect with the source / drain component 230 and the metal filler layer disposed above the silicide layer 275. In the example process, after forming the first back-side source / drain contact opening 272, a metal precursor is deposited over the exposed source / drain component 230, and an annealing process is performed to induce silicide formation between the source / drain component 230 and the metal precursor to form a silicide layer. In some embodiments, the metal precursor may include titanium (Ti), chromium (Cr), tantalum (Ta), molybdenum (Mo), zirconium (Zr), nickel (Ni), cobalt (Co), manganese (Mn), tungsten (W), iron (Fe), ruthenium (Ru), or platinum (Pt), and the silicide layer 275 may include titanium silicide (TiSi), chromium silicide (CrSi), tantalum silicide (TaSi), molybdenum silicide (MoSi), nickel silicide (NiSi), cobalt silicide (CoSi), manganese silicide (MnSi), tungsten silicide (WSi), iron silicide (FeSi), ruthenium silicide (RuSi), or platinum silicide (PtSi). In some cases, the thickness of the silicide layer 275 may be between about 1 nm and about 10 nm. After forming the silicide layer 275, a metal filler material may be deposited in the first back-side source / drain contact opening 272 to form the back-side source / drain contact 274, such as... Figure 7 As shown. The metal filler material may include tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), or nickel (Ni), and may be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD). In some embodiments, the back-side source / drain contact 274 may optionally include a barrier layer 273 disposed at its interface with the isolation member 204 and at its interface with the adjacent mesa structure. Optional barrier layer 273 may include silicon nitride, silicon carbonitride, silicon carbonoxylate, or silicon carbonitride and may have a thickness between about 0.5 nm and about 5 nm. After the deposition of the metal filler material, a planarization process such as CMP may be performed to remove excess material and provide a flat top surface. At the end of operation of block 112, the back-side source / drain contact 274 is coupled to the source / drain component 230 and may have a height between about 6 nm and about 50 nm, as measured from the source / drain component 230 to the back-side conductive component (described below). In one embodiment, the back-side source / drain contact 274 is formed above the source / drain component 230, which serves as the source component, and may be referred to as the back-side source / drain contact 274. In some alternative embodiments, the first back-side source / drain contact opening 272 may extend partially into the source / drain component 230. As a result, it is possible to form Figure 18 The extended back-side source / drain contact 2740 is shown.

[0030] refer to Figure 1 , Figure 8 and Figure 9 Method 100 includes a frame 114 in which the mesa structure is replaced with a pad 278 and a back-side dielectric layer 280. Operations at frame 114 may include selective removal of the mesa structure (e.g., Figure 8 As shown), deposited pad 278 and deposited back-side dielectric layer 280 (as shown) Figure 9 (As shown). Reference Figure 8 First, selective wet etching or selective dry etching is used to selectively remove mesa structures, such as the first mesa structure 202-1, the second mesa structure 202-2, and the third mesa structure 202-3. Example selective wet etching processes for etching back mesa structures may include using ethylenediamine catechol (EDP), tetramethylammonium hydroxide (TMAH), nitric acid (HNO3), hydrofluoric acid (HF), ammonia (NH3), hydrogen peroxide (H2O2), ammonium fluoride (NH4F), or suitable wet etchants. Example selective dry etching processes for etching back mesa structures may include sulfur hexafluoride (SF6), hydrogen (H2), ammonia (NH3), hydrogen fluoride (HF), carbon tetrafluoride (CF4), hydrogen bromide (HBr), argon, or mixtures thereof. Figure 8As shown, the removal of the mesa structure directly forms the gate access opening 276 above the gate structure 240. (Reference) Figure 9 A pad 278 is deposited along the sidewalls and bottom surface of the gate access opening 276. The pad 278 may comprise silicon nitride, silicon carbonitride, silicon carbide, or silicon carbonitride and may have a thickness between about 0.5 nm and about 5 nm. A back-side dielectric layer 280 is then deposited over the pad 278 and in the gate access opening 276. The back-side dielectric layer 280 may comprise silicon oxide, silicon carbonitride, silicon oxynitride, or silicon carbonitride and may be deposited using spin coating, chemical vapor deposition (CVD), flowable CVD (FCVD), or plasma-enhanced CVD (PECVD). A planarization process, such as a CMP process, may be performed to remove excess material, such that the top surfaces of the back-side dielectric layer 280, isolation member 204, sacrificial plug 218, pad 278, and back-side source / drain contact 274 are coplanar. The operation at block 114 can be collectively referred to as a mesa removal process. Replacing the silicon mesa structure with pad 278 and back-side dielectric layer 280 can reduce the off-state leakage current entering or passing through the bulk substrate 202.

[0031] refer to Figure 1 , Figure 10 and Figure 11 Method 100 includes block 116, wherein the remaining pseudo-epicentric plugs 218 are replaced with dielectric plugs 284. The operation at block 116 may include selective removal of the sacrificial plugs 218 (e.g., Figure 10 (as shown) and forming dielectric plug 284 (as shown) Figure 11 (As shown). In some embodiments, the removal of the sacrificial plug 218 can be self-aligned because the sacrificial plug 218, formed of silicon germanium (SiGe), is disposed between the isolation component 204, the pad 278, the back-side dielectric layer 280, and the back-side source / drain contact 274. In these embodiments, the selective removal of the sacrificial plug 218 can be performed using a selective wet etching process. Example selective wet etching processes may include using a solution of ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2). Because the selective etching process at frame 116 etches the sacrificial plug 218 faster than etching the isolation component 204, the pad 278, the back-side dielectric layer 280, or the back-side source / drain contact 274, the sacrificial plug 218 can be removed with minimal damage to the pad 278, the back-side dielectric layer 280, and the back-side source / drain contact 274. In the depicted embodiment, selective removal of the sacrificial plug 218 may also remove a portion of the exposed source / drain component 230 beneath the sacrificial plug 218. Removal of the sacrificial plug 218 forms a second back-side source / drain contact opening 282 to expose the source / drain component 230. Each of the second back-side source / drain contact openings 282 is defined between the gasket 278 and the isolation member 204, while Figure 6The first back-side source / drain contact opening 272 shown is defined between the third mesa structure 202-3 and the isolation member 204. (Reference) Figure 11 A dielectric material is then deposited over the back side BS of workpiece 200, and workpiece 200 is planarized to form a dielectric plug 284 in the second back side source / drain contact opening 282. The dielectric material used for the dielectric plug 284 may include silicon nitride, silicon carbonitride, silicon carbide, silicon carbonitride, or other low-k dielectric materials with a dielectric constant less than 7. Note that the dielectric plug 284 and the back side dielectric layer 280 may not have the same composition, or the back side dielectric layer 280 may be non-selectively etched in subsequent steps. In some cases, as measured along the X direction, each sacrificial plug 218 may have a width between approximately 10 nm and approximately 30 nm, similar to the width of the source / drain component 230 along the X direction. Because silicon germanium has a dielectric constant greater than 11.7, replacing the sacrificial plug 218 with the dielectric plug 284 helps reduce the parasitic capacitance between the back side gate contact to be formed and the adjacent source / drain component 230.

[0032] refer to Figure 1 and Figure 12 Method 100 includes block 118, wherein a patterned second hard mask layer 287 is formed to expose a region of the back-side dielectric layer 280 directly above the gate structure 240. In an example process, the second hard mask layer 287 is blanket-deposited over the back-side (BS) of the workpiece 200 using CVD. The second hard mask layer 287 may be a single layer or multiple layers. In the depicted embodiment, the second hard mask layer 287 is multilayered and may include a metal hard mask layer 286 and a semiconductor nitride layer 288 located above the metal hard mask layer 286. The metal hard mask layer 286 may include titanium nitride, and the semiconductor nitride layer 288 may include silicon nitride. After depositing the second hard mask layer 287, photolithography and etching processes may be performed to pattern the second hard mask layer 287 to form a patterned second hard mask layer 287 to expose the region of the back-side dielectric layer 280 directly above the gate structure 240. In some cases, a photoresist layer is deposited over the second hard mask layer 287. To pattern the photoresist layer, the photoresist layer is exposed to radiation reflected or transmitted through the photomask, baked in a post-exposure baking process, and developed in a developer. The patterned photoresist layer is then applied as an etch mask to etch a second hard mask layer 287, thereby forming the patterned second hard mask layer 287. (Reference) Figure 12 The patterned second hard mask layer 287 includes a second mask opening 290 perpendicularly aligned with a region of the back-side dielectric layer 280 directly above the gate structure 240. According to the invention, the patterned second hard mask layer 287 is used to mask the back-side dielectric layer 280 and other regions of the isolation member 204.

[0033] refer to Figure 1 and Figure 13 Method 100 includes block 120, wherein the exposed back-side dielectric layer 280 in the second mask opening 290 is selectively removed to expose the gate structure 240 in the back-side gate contact opening 292. The selective removal of the back-side dielectric layer 280 can be implemented using a dry etching process. Example selective dry etching processes for etching back mesa structures may include sulfur hexafluoride (SF6), carbon tetrafluoride (CF4), nitrogen trifluoride (NF3), other fluorine-containing gases, oxygen (O2), or mixtures thereof. In some embodiments, the composition of the dielectric plug 284 or the pad 278 differs from the composition of the back-side dielectric layer 280. This allows for the selective removal of exposed portions of the back-side dielectric layer 280 without damaging the pad 278 or the dielectric plug 284. In this respect, the removal of the back-side dielectric layer 280 at block 120 is self-aligned. Figure 13 As shown, the etching process at block 120 is performed until the gate electrode layer 246 of the gate structure 240 is exposed in the back-side gate contact opening 292. That is, the etching process at block 120 also removes the gate dielectric layer 244 and the interface layer 242. After forming the back-side gate contact opening 292, the patterned second hard mask layer 287 is removed by selective etching.

[0034] refer to Figure 1 and Figure 14 Method 100 includes block 122, wherein a back-side gate contact 294 is formed in a back-side gate contact opening 292. At block 122, a metal filler material can be deposited over the back side BS of the workpiece 200, including over the back-side gate contact opening 292. The metal filler material may include tungsten (W), ruthenium (Ru), cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), molybdenum (Mo), or aluminum (Al), and can be deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD). In some embodiments, the back-side gate contact 294 may optionally include a barrier layer 295 disposed along the sidewall of the back-side gate contact 294 (e.g., Figure 17 (As shown). Optional barrier layer 295 may include silicon nitride or titanium nitride. A planarization process, such as CMP, can be performed after the deposition of the metal filler material to remove excess material and provide a flat top surface. At the end of operation at block 122, the back-side gate contact 294 is coupled to and in direct contact with the gate electrode layer 246 of the gate structure 240. In some alternative embodiments, etching at block 120 may also remove a portion of the gate electrode layer 246 and form a recess in the gate electrode layer 246. As a result, a [missing information - likely a specific structure or feature] can be formed. Figure 18The extended back-side gate contact 2940 is shown. In some other embodiments, the etching at frame 120 also moderately etches the top edge of the pad 278 and can form Figure 19 The tapered back-side gate contact 2942 is shown. Due to the peeling of the pad 278, the tapered back-side gate contact 2942 includes a smaller end face adjacent to the gate electrode layer 246 and a larger end face away from the gate electrode layer 246. As measured from the interface with the gate electrode layer 246 to the interface with the back-side conductive component (described below), the back-side gate contact 294 can have a height between about 6 nm and about 50 nm.

[0035] refer to Figure 1 , Figure 15 and Figure 16 Method 100 includes block 124, wherein at least one back-side conductive component is coupled to back-side gate contact 294 and back-side source / drain contact 274. Figure 15 and Figure 16 yes Figure 14The partial top view of workpiece 200 shown may include additional components such as a first back-side gate contact 294-1, a second back-side gate contact 294-2, a first back-side source / drain contact 274-1, and a second back-side source / drain contact 274-2. The formation of at least one back-side conductive component may include depositing an insulating layer 300, patterning the insulating layer 300 to form a trench, and forming at least one conductive component in the trench. The insulating layer 300 may have a composition similar to that of the ILD layer described above. The insulating layer 300 may include tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide, such as borosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), and / or other suitable dielectric materials. An insulating layer 300 is deposited over the back side BS of the workpiece 200, including a back side dielectric layer 280, back side source / drain contacts, isolation member 204, pad 278, and back side gate contacts. Trenches are then patterned in the insulating layer 300 to selectively expose either the back side gate contact 294 or the back side source / drain contact 274. Subsequently, a metal filler material is deposited into the trenches to form at least one back side conductive member. In some embodiments, the metal filler material in the at least one back side conductive member may include titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), tungsten (W), cobalt (Co), nickel (Ni), molybdenum (Mo), or combinations thereof. In some embodiments, a barrier layer may be optionally deposited prior to depositing the metal filler material to separate the metal filler material from the insulating layer. The barrier layer may include titanium nitride (TiN), tantalum nitride (TaN), cobalt nitride (CoN), nickel nitride (NiN), or tungsten nitride (WN). When forming the barrier layer, both the barrier layer and the metal filler material can be considered part of at least one back-side conductive component. The barrier layer and metal filler layer can be deposited using PVD, CVD, ALD, or chemical plating. A planarization process, such as CMP, can be performed to remove excess material over the insulating layer. Although not explicitly shown, further interconnect structures can be formed over the insulating layer 300 and at least one back-side conductive component.

[0036] exist Figure 15In some embodiments shown, at least one back-side conductive component includes a first back-side conductive component 302 and a second back-side conductive component 304. The first back-side conductive component 302 is electrically coupled to a first back-side gate contact 294-1 and a first back-side source / drain contact 274-1, thereby interconnecting them. The second back-side conductive component 304 is electrically coupled to a second back-side gate contact 294-2 and a second back-side source / drain contact 274-2, thereby interconnecting them. Each of the first back-side conductive component 302 and the second back-side conductive component 304 spans over the isolation component 204 along the Y direction. Figure 15 In the diagram, when viewed along the Z-direction, the first back-side gate contact 294-1 is spaced apart from the second back-side source / drain contact 274-2 by a pad 278, a dielectric plug 284, and a back-side dielectric layer 280. Figure 16 In some other embodiments shown, at least one back-side conductive component includes a third back-side conductive component 306. The third back-side conductive component 306 is electrically coupled to a first back-side gate contact 294-1, a first back-side source / drain contact 274-1, a second back-side gate contact 294-2, and a second back-side source / drain contact 274-2, thereby interconnecting them all.

[0037] Embodiments of the present invention offer advantages. For example, the method of the present invention forms a back-side gate contact directly coupled to the gate structure. The introduction of the back-side gate contact enables further interconnect structures and routing on the back side of the semiconductor structure, thereby reducing the number of metal lines on the front side. For example, back-side conductive components can locally connect the back-side gate contact to back-side source / drain contacts. Furthermore, the method of the present invention replaces the semiconductor mesa structure with a dielectric layer to reduce off-state leakage current through or via the bulk substrate.

[0038] In one exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a first nanostructure; a first gate structure enclosing each of the first nanostructures and disposed above an isolation structure; and a back-side gate contact disposed below the first nanostructures and adjacent to the isolation structure. The bottom surface of the first gate structure is in direct contact with the back-side gate contact.

[0039] In some embodiments, the semiconductor structure may further include: a second nanostructure; a second gate structure enclosing each of the second nanostructures and disposed above the isolation structure; and a front gate contact disposed above the second nanostructures and away from the isolation structure. The second gate structure is electrically coupled to the front gate contact. In some embodiments, the front gate contact is electrically coupled to the second gate structure through a gate capping layer. In some cases, the semiconductor structure may further include a first source / drain component coupled to an end face of the second nanostructure, and a back source / drain contact disposed below the second nanostructure and adjacent to the isolation structure. The back source / drain contact is electrically coupled to the first source / drain component. In some embodiments, the semiconductor structure may further include a second source / drain component coupled to the first nanostructure and the second nanostructure and sandwiched between the first nanostructure and the second nanostructure, and a dielectric plug disposed below the second source / drain component. The dielectric plug is adjacent to the isolation structure and the back gate contact. In some embodiments, the semiconductor structure may further include a pad extending from between the back gate contact and the isolation structure to between the back gate contact and the dielectric plug. In some cases, the dielectric plug and isolation structure comprises silicon oxide, and the pad comprises silicon nitride. In some embodiments, a second nanostructure is disposed above the back-side dielectric layer. In some embodiments, the back-side dielectric layer is spaced apart from the dielectric plug and isolation structure by the pad. In some cases, the dielectric plug and back-side dielectric layer comprise silicon oxide, and the pad comprises silicon nitride.

[0040] In another exemplary aspect, the present invention relates to a semiconductor structure. The semiconductor structure includes: a first plurality of nanostructures; a first gate structure enclosing each of the first plurality of nanostructures; a first capping layer disposed on a top surface of the first gate structure; a back-side gate contact directly contacting a bottom surface of the first gate structure, the bottom surface being opposite to the top surface; a second plurality of nanostructures; a second gate structure enclosing each of the second plurality of nanostructures; a second capping layer disposed on the second gate structure; and a front-side gate contact directly contacting the second capping layer.

[0041] In some embodiments, the back-side gate contact extends partially into the first gate structure. In some embodiments, the semiconductor structure may further include a first source / drain component disposed between and in direct contact with the first and second nanostructures, and a second source / drain component in direct contact with the second nanostructures. The second nanostructures extend between the first and second source / drain components. In some embodiments, the semiconductor structure may further include a dielectric plug disposed below the first source / drain component and a back-side source / drain contact disposed below the second source / drain component. In some cases, the dielectric plug is spaced apart from the back-side gate contact by a pad. The dielectric plug comprises silicon oxide, and the pad comprises silicon nitride. In some embodiments, the back-side source / drain contact extends partially into the second source / drain component.

[0042] In yet another exemplary aspect, the present invention relates to a method. The method includes receiving a workpiece comprising a first nanostructure disposed above a first mesa structure, a second nanostructure disposed above a second mesa structure, a first gate structure enclosing the first nanostructure, a second gate structure enclosing the second nanostructure, a first source / drain component sandwiched between the first and second nanostructures, a second source / drain component spaced apart from the first source / drain component by the second nanostructure, a first pseudo-epicentric plug located below the first source / drain component and between the first and second mesa structures, and a second pseudo-epicentric plug located below the second source / drain component and adjacent to the second mesa structure. The method further includes replacing the second pseudo-epicentric plug with a back-side source / drain contact, replacing the first mesa structure with a back-side dielectric component, replacing the first pseudo-epicentric plug with a dielectric plug, and replacing the back-side dielectric component with a back-side gate contact that directly contacts the first gate structure.

[0043] In some embodiments, the first mesa structure and the second mesa structure comprise silicon. The first pseudo-epicentric plug and the second pseudo-epicentric plug comprise silicon-germanium. In some embodiments, replacing the first mesa structure includes selectively removing the first mesa structure, depositing a pad over the workpiece, and forming a back-side dielectric component over the pad after depositing the pad. In some cases, replacing the back-side dielectric component includes selectively removing the back-side dielectric component, and after selectively removing the back-side dielectric component, anisotropically etching the pad to form a back-side gate contact opening to expose the first gate structure, and forming a back-side gate contact in the back-side gate contact opening.

[0044] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a base to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent configurations do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made to them herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, comprising: First nanostructure; A first gate structure is formed, which encapsulates each of the first nanostructures and is disposed above the isolation structure; A dielectric structure is disposed on the isolation structure and in contact with the sidewall of the first gate structure; as well as A back-side gate contact is disposed below the first nanostructure and adjacent to the isolation structure. The bottom surface of the first gate structure is in direct contact with the back gate contact.

2. The semiconductor structure according to claim 1, further comprising: Second nanostructure; A second gate structure is formed, which encloses each of the second nanostructures and is disposed above the isolation structure; as well as The front gate contact is disposed above the second nanostructure and away from the isolation structure. The second gate structure is electrically coupled to the front gate contact.

3. The semiconductor structure according to claim 2, wherein, The front gate contact is electrically coupled to the second gate structure through the gate cover layer.

4. The semiconductor structure according to claim 2, further comprising: The first source / drain component is coupled to the end face of the second nanostructure; as well as The back-side source / drain contacts are disposed below the second nanostructure and adjacent to the isolation structure. The back-side source / drain contact is electrically coupled to the first source / drain component.

5. The semiconductor structure according to claim 2, further comprising: A second source / drain component is coupled to the first nanostructure and the second nanostructure and sandwiched between the first nanostructure and the second nanostructure; as well as A dielectric plug is disposed below the second source / drain component. The dielectric plug is adjacent to the isolation structure and the back gate contact.

6. The semiconductor structure according to claim 5, further comprising: A gasket extends from between the back-side gate contact and the isolation structure to between the back-side gate contact and the dielectric plug.

7. The semiconductor structure according to claim 6, in, The dielectric plug and the isolation structure comprise silicon oxide. The pad includes silicon nitride.

8. The semiconductor structure according to claim 5, wherein, The second nanostructure is disposed above the back dielectric layer.

9. The semiconductor structure according to claim 8, wherein, The back dielectric layer is spaced apart from the dielectric plug and the isolation structure by a pad.

10. The semiconductor structure according to claim 9, in, The dielectric plug and the back-side dielectric layer comprise silicon oxide. The pad includes silicon nitride.

11. A semiconductor structure, comprising: The first multiple nanostructures; A first gate structure encapsulates each of the first plurality of nanostructures; A first cover layer is disposed on the top surface of the first gate structure; The back-side gate contact is in direct contact with the bottom surface of the first gate structure, and the bottom surface is opposite to the top surface. The second set of multiple nanostructures; A second gate structure encapsulates each of the second plurality of nanostructures; A second cover layer is disposed on the second gate structure; as well as The front gate contact is in direct contact with the second cover layer. The back-side gate contact extends to the other bottom surface of the first gate structure.

12. The semiconductor structure according to claim 11, wherein, The back-side gate contact extends partially into the first gate structure.

13. The semiconductor structure according to claim 11, further comprising: A first source / drain component is disposed between the first plurality of nanostructures and the second plurality of nanostructures and is in direct contact with the first plurality of nanostructures and the second plurality of nanostructures; as well as The second source / drain component is in direct contact with the second plurality of nanostructures. The second plurality of nanostructures extend between the first source / drain component and the second source / drain component.

14. The semiconductor structure according to claim 13, further comprising: A dielectric plug is disposed below the first source / drain component; as well as The back-side source / drain contact is disposed below the second source / drain component.

15. The semiconductor structure according to claim 14, in, The dielectric plug is spaced apart from the back-side gate contact by a gasket. The dielectric plug comprises silicon oxide. The pad includes silicon nitride.

16. The semiconductor structure according to claim 14, wherein, The back-side source / drain contact extends partially into the second source / drain component.

17. A method for forming a semiconductor structure, comprising: Receive a workpiece, the workpiece comprising: The first nanostructure is positioned above the first mesa structure. The second nanostructure is positioned above the second mesa structure. The first gate structure encapsulates the first nanostructure. The second gate structure encapsulates the second nanostructure. The first source / drain component is sandwiched between the first nanostructure and the second nanostructure. The second source / drain component is spaced apart from the first source / drain component by the second nanostructure. The first pseudo-epicentric plug is located below the first source / drain component and between the first mesa structure and the second mesa structure. The second pseudo-epicentric plug is located below the second source / drain component and adjacent to the second mesa structure; Replace the second pseudo epitaxial plug with the back-side source / drain contact; Replace the first platform structure with a back-side dielectric component; Replace the first pseudo-epicentric plug with a dielectric plug; and The back-side dielectric component is replaced with a back-side gate contact that is in direct contact with the first gate structure, wherein a portion of the back-side gate contact extends over the other bottom surface of the first gate structure.

18. The method according to claim 17, in, The first mesa structure and the second mesa structure comprise silicon. The first pseudo-epilithographic plug and the second pseudo-epilithographic plug comprise silicon and germanium.

19. The method of claim 17, wherein, The replacement of the first countertop structure includes: The first platform structure is selectively removed; A liner is deposited above the workpiece; and After the liner is deposited, the back-side dielectric component is formed on top of the liner.

20. The method according to claim 19, wherein, Replacing the back-side dielectric component includes: Selectively remove the back-side dielectric component; After selectively removing the back-side dielectric components, the pads are anisotropically etched to form back-side gate contact openings to expose the first gate structure; and The back-side gate contact is formed in the opening of the back-side gate contact.

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