Flat panel detector and method of manufacturing the same

Abstract

The application discloses a flat panel detector and a manufacturing method thereof, and aims at solving the technical problem of poor imaging effect of a large-size flat panel detector in the prior art. The flat panel detector comprises: a substrate base plate which is divided into multiple detection areas; multiple photoelectric detectors which are arranged in an array and are distributed in the multiple detection areas; multiple scanning lines and multiple data lines which are electrically connected with the photoelectric detectors respectively, and the scanning lines and the data lines are discontinuously arranged at corresponding positions in the multiple detection areas; a protective layer which is located on a side, away from the substrate base plate, of a layer where the scanning lines are located and a layer where the data lines are located, the protective layer covers the scanning lines, the data lines and the positions where the scanning lines and the data lines are disconnected, and is arranged in the same layer with the scanning lines and the data lines at the positions where the scanning lines and the data lines are disconnected; and multiple driving circuits which are corresponding to the multiple detection areas, and the driving circuits are electrically connected with the scanning lines and the data lines connected with the photoelectric detectors in the corresponding detection areas.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of flat panel detector, in particular to a flat panel detector and a manufacturing method thereof. BACKGROUND

[0002] At present, when shooting large-size bones such as spine, a large-size x-ray flat panel detector is usually needed.

[0003] However, due to the limitations of the process manufacturing difficulty and imaging performance of the flat panel detector, the maximum size of the integrally manufactured flat panel detector is about 17 inches x 17 inches, and the larger size detector is usually composed of multiple integrally manufactured flat panel detectors. However, the large-size flat panel detector obtained by splicing is prone to have splicing defects, and the requirement for reading and correcting algorithm is high. Therefore, a large-size flat panel detector urgently needs an integrated manufacturing method that can ensure the imaging performance.

[0004] In actual production, even if a large-size integrally manufactured flat panel detector can be manufactured in terms of process technology, it will still face the problem of insufficient driving capacity, which makes the imaging effect of the large-size integrally manufactured flat panel detector not good.

[0005] Therefore, how to manufacture a large-size flat panel detector with good imaging effect has become a technical problem to be solved. SUMMARY

[0006] The present application provides a flat panel detector and a manufacturing method thereof to solve the technical problem of poor imaging effect of a large-size flat panel detector in the prior art.

[0007] In a first aspect, to solve the above technical problem, the technical scheme of a flat panel detector provided by an embodiment of the present application is as follows:

[0008] A substrate substrate is divided into a plurality of detection regions by the positions where the plurality of detection regions are divided;

[0009] A plurality of photodetectors arranged in an array, the plurality of photodetectors are distributed in the plurality of detection regions;

[0010] A plurality of scanning lines and a plurality of data lines electrically connected to each of the photodetectors, the scanning lines and the data lines are discontinuously arranged at the positions corresponding to the positions where the plurality of detection regions are divided;

[0011] A protective layer located on the side of the scanning line layer and the data line layer away from the substrate substrate, the protective layer covers the scanning lines, the data lines, and the positions where the scanning lines and the data lines are discontinuously arranged, and is arranged in the same layer as the scanning lines and the data lines at the positions where the scanning lines and the data lines are discontinuously arranged;

[0012] a plurality of driving circuits corresponding to the detection regions, the driving circuits being electrically connected with the scan lines and the data lines connected with the photodetectors in the corresponding detection regions.

[0013] In a possible implementation, the flat panel detector further includes a protective layer located on a side of the layer where the scan lines are located and the layer where the data lines are located, away from the substrate, the protective layer covering the scan lines, the data lines, and the positions where the scan lines and the data lines are disconnected.

[0014] In a possible implementation, the flat panel detector further includes at least one insulating layer located between the layer where the scan lines are located and the protective layer, and at least one insulating layer located between the layer where the data lines are located and the protective layer.

[0015] Each of the insulating layers has a through hole covering the positions where the scan lines and the data lines are disconnected.

[0016] In a possible implementation, the through hole of each of the insulating layers is gradually reduced in a direction along the substrate pointing to the protective layer.

[0017] In a possible implementation, the flat panel detector further includes:

[0018] a thin film transistor, a gate of the thin film transistor being electrically connected with a corresponding scan line, a first pole of the thin film transistor being electrically connected with a corresponding data line, and a second pole of the thin film transistor being electrically connected with a corresponding photodetector.

[0019] The gate of the thin film transistor is arranged in the same layer as the scan line, and the first pole and the second pole of the thin film transistor are respectively arranged in the same layer as the data line.

[0020] In a possible implementation, the at least one insulating layer located between the layer where the scan lines are located and the protective layer specifically includes a gate insulating layer, a first insulating layer, and a second insulating layer.

[0021] The at least one insulating layer located between the layer where the data lines are located and the protective layer specifically includes the first insulating layer and the second insulating layer.

[0022] In a possible implementation, a length of a fracture at the position where the scan lines and the data lines are disconnected is less than an inner diameter of the through hole of a bottommost insulating layer of the at least one insulating layer.

[0023] In a possible implementation, a length of a fracture at the position where the scan lines and the data lines are disconnected is less than a length of a pixel corresponding to one photodetector.

[0024] In a second aspect, an embodiment of the present application provides a manufacturing method of a flat panel detector, including:

[0025] A substrate is provided, the substrate being divided into multiple detection regions;

[0026] Original scan lines and original data lines are formed on the substrate, and the original scan lines and original data lines respectively pass through the positions where the plurality of detection regions are segmented and intersect with them;

[0027] A photodetector is formed on the substrate and arranged in an array within each detection area;

[0028] The original scan lines and the original data lines are broken at the positions corresponding to the division of the multiple detection areas, forming scan lines and data lines that do not overlap with the division positions of the multiple detection areas;

[0029] On the side of the photodetector facing away from the substrate, a protective layer is formed covering the scan line, the data line, and the location where the scan line and the data line are disconnected; wherein, at the location where the scan line and the data line are disconnected, a protective layer is formed in the same layer as the scan line and the data line;

[0030] A corresponding driving circuit is bound to each of the detection areas, and the driving circuit is electrically connected to the scan line and data line connected to the photodetector in the corresponding detection area.

[0031] One possible implementation involves forming raw scan lines and raw data lines on the substrate, specifically including:

[0032] A gate metal layer is formed on the substrate, the gate metal layer including the original scan line and the gate of the thin film transistor;

[0033] A gate insulating layer is formed on the gate metal layer;

[0034] A source-drain metal layer is formed on the gate insulating layer, the source-drain metal layer including the original data line and the first and second electrodes of the thin film transistor.

[0035] One possible implementation further includes, after forming a gate insulating layer on the gate metal layer:

[0036] At the locations where the original scan lines and the multiple detection regions overlap, the gate insulating layer is etched to form blind vias in the gate insulating layer.

[0037] One possible implementation includes forming a first insulating layer and a second insulating layer while forming the photodetector.

[0038] One possible implementation, after forming the first insulating layer, further includes:

[0039] At the location where the original scan line and the multiple detection areas are divided, the first insulating layer is etched to form a through hole penetrating the first insulating layer.

[0040] At the location where the original data line and the plurality of detection areas overlap, the first insulating layer is etched to form a blind hole in the first insulating layer.

[0041] One possible implementation, after forming the second insulating layer, further includes:

[0042] The second insulating layer is etched at the locations where the original scan line, the original data line, and the multiple detection areas overlap, respectively, to form through holes penetrating the second insulating layer.

[0043] One possible implementation involves breaking the original scan lines and the original data lines at positions corresponding to the division of the plurality of detection regions, forming scan lines and data lines that do not overlap with the division positions of the plurality of detection regions, including:

[0044] At the location where the original scan line and the multiple detection areas are divided, the film layer between the original scan line and the protective layer is etched to form a through hole that penetrates the film layer between the original scan line and the protective layer.

[0045] At the location where the original data line and the multiple detection areas overlap, the film layer between the original data line and the protective layer is etched to form a through hole that penetrates the film layer between the original data line and the protective layer.

[0046] One possible implementation involves breaking the original scan lines and the original data lines at positions corresponding to the division of the plurality of detection regions, forming scan lines and data lines that do not overlap with the division positions of the plurality of detection regions, including:

[0047] The blind hole is etched into the through hole;

[0048] Etching is performed in the area where the via of the gate insulating layer is projected onto the original scan line to form scan lines that do not overlap with the positions where the multiple detection areas are divided.

[0049] Etching is performed in the area where the through-hole of the first insulating layer is projected onto the original data line to form a data line that does not overlap with the positions where the multiple detection areas are divided. Attached Figure Description

[0050] Figure 1A schematic diagram of the structure of a flat panel detector provided for the implementation of the present invention;

[0051] Figure 2 This is a schematic diagram of the protective layer area in a flat panel detector provided by an embodiment of the present invention;

[0052] Figure 3 This is a schematic diagram of the film layer at the scan line break position provided in an embodiment of the present invention;

[0053] Figure 4 This is a schematic diagram of the film layer at the data line disconnection location provided in an embodiment of the present invention;

[0054] Figure 5 This is a schematic diagram showing the position of the thin-film transistor in the flat panel detector provided in an embodiment of the present invention;

[0055] Figure 6 A schematic diagram showing the location of the through-hole in the insulating layer in a flat panel detector, provided in an embodiment of the present invention;

[0056] Figure 7 A cross-sectional view of an insulating layer at the location where the scan line is broken, provided as an embodiment of the present invention;

[0057] Figure 8 A cross-sectional view of an insulating layer at the location where a data line is disconnected, provided as an embodiment of the present invention;

[0058] Figure 9 A cross-sectional view of another insulating layer at the location where the scan line is broken, provided in an embodiment of the present invention;

[0059] Figure 10 A cross-sectional view of another insulating layer at the location where the data line is disconnected, provided as an embodiment of the present invention;

[0060] Figure 11 A schematic diagram showing the location where the scan line and data line are disconnected in a flat panel detector according to an embodiment of the present invention;

[0061] Figure 12 A schematic diagram showing the location where the scan line and data line are disconnected in another flat panel detector provided in an embodiment of the present invention;

[0062] Figure 13 A flowchart illustrating a method for manufacturing a flat panel detector according to an embodiment of the present invention;

[0063] Figure 14 This is a schematic diagram of the interlayer film between the substrate and the gate insulating layer, corresponding to the overlapping positions of the original scan lines and the segmented multiple detection regions provided in an embodiment of the present invention.

[0064] Figure 15This is a schematic diagram of the interlayer film between the substrate and the gate insulating layer, corresponding to the overlapping positions of the original scan line and the segmented multiple detection areas provided in an embodiment of the present invention.

[0065] Figure 16 This is a schematic diagram of the substrate to the second insulating interlayer film layer corresponding to the overlapping positions of the original scan lines and the segmented multiple detection areas provided in an embodiment of the present invention.

[0066] Figure 17 This is a schematic diagram of the substrate to the second insulating interlayer film corresponding to the overlapping position of the original scan line and the segmented multiple detection areas provided in another embodiment of the present invention.

[0067] Figure 18 This provides another schematic diagram of forming through holes in each insulating layer for an embodiment of the present invention;

[0068] Figure 19 A schematic diagram of etching blind holes into through holes is provided for an embodiment of the present invention;

[0069] Figure 20 A flowchart for forming scan lines is provided for embodiments of the present invention;

[0070] Figure 21 A flowchart for forming a data line is provided for an embodiment of the present invention.

[0071] Substrate 10, detection area AA, photodetector 20, scan line 30, data line 40, driving circuit 50, protective layer 60, thin film transistor 70, gate 701, first electrode 702, second electrode 703, insulating layer 80, gate insulating layer 801, first insulating layer 802, second insulating layer 803, through hole H. Detailed Implementation

[0072] This invention provides a flat panel detector and its manufacturing method to solve the technical problem of poor imaging effect of large-size flat panel detectors in the prior art.

[0073] Please see Figures 1-4 , Figure 1 A schematic diagram of a flat panel detector provided for implementation of the present invention. Figure 2 This is a schematic diagram of the protective layer area in a flat panel detector provided by an embodiment of the present invention. Figure 3 This is a schematic diagram of the film layer at the scan line break position provided in an embodiment of the present invention. Figure 4 This is a schematic diagram of the film layer at the scan line break position provided in an embodiment of the present invention. An embodiment of the present invention provides a flat panel detector, comprising:

[0074] Substrate 10 is divided into multiple detection regions AA; such asFigure 1 The area within the double-dotted line is the detection area AA. Figure 1 The intermediate substrate 10 is divided into 4 detection areas AA.

[0075] Multiple photodetectors 20 are arranged in an array and distributed within multiple detection areas AA;

[0076] Multiple scan lines 30 and multiple data lines 40 are electrically connected to each photodetector 20, and the scan lines 30 and data lines 40 are disconnected at the positions where multiple detection areas AA are divided. Figure 1 In the diagram, k1 is the position where a scan line 30 is disconnected, and k2 is the position where a data line 40 is disconnected.

[0077] A protective layer 60 is located on the side of the layer where the scan line 30 and the data line 40 are located away from the substrate 10. The protective layer 60 covers the scan line 30, the data line 40, and the location where the scan line 30 and the data line 40 are disconnected. At the location where the scan line 30 and the data line 40 are disconnected, the protective layer 60 is disposed on the same layer as the scan line 30 and the data line 40. Figure 2 The area covered by the middle protective layer 60 is shown in grid lines. Figure 3 The diagram shows that the cut-off location (k1) of scan line 30 is filled with a protective layer. That is, at the cut-off location (k1) of scan line 30, the protective layer 60 and scan line 30 are set in the same layer. Similarly, at the cut-off location of data line 40, the protective layer 60 and data line 40 are also set in the same layer. This film layer deposition method is because the scan line 30 and data line 40 are cut off before the protective layer 60 is formed during manufacturing, rather than immediately after the scan line 30 and data line 40 are formed. This can prevent tip discharge when the scan line 30 and data line 40 are cleaned by ultraviolet (UV) irradiation during the production process, thereby effectively avoiding electrostatic damage caused by tip discharge of metal traces during the production process.

[0078] Each detection area AA has multiple driving circuits 50, which are electrically connected to the scan lines 30 and data lines 40 of the photodetectors 20 within the corresponding detection area AA. The number of photodetectors 20 distributed within each detection area AA is within the driving capability range of the driving circuit 50 used in that detection area AA. Since the size of the photodetectors 20 is fixed in the flat panel detector, and the distance between the photodetectors 20 is also fixed, the size of each detection area AA is within the driving capability range of the corresponding driving circuit 50. This allows multiple detection areas AA to be combined into a larger detection area AA, and the photodetectors 20 within the detection area AA can be driven normally within the driving capability range of the driving circuit 50. This enables the flat panel detector to detect large objects and improve the imaging effect of large objects.

[0079] It should be understood that the above-mentioned large size should be understood as the maximum size of the detected object that can be imaged normally using a conventional flat panel detector. The size of the flat panel detector in this invention is usually larger than the maximum size of the conventional flat panel detector mentioned above.

[0080] In the embodiments provided by this invention, by fabricating multiple photodetectors 20 within multiple detection areas AA on a single substrate 10, problems such as splicing defects and high requirements for image reading and correction algorithms, which are common in existing flat panel detectors formed by splicing, can be avoided. At the locations where the multiple detection areas AA are divided, the multiple scan lines 30 and multiple data lines 40 connected to each photodetector 20 are disconnected. At the same time, a corresponding driving circuit 50 is provided for each detection area AA, so that each detection area AA has an independent driving circuit 50. This allows the size of each detection area AA to be controlled within the range that meets the driving capability of the driving circuit 50. This results in a flat panel detector that can detect large-sized objects while improving the imaging effect. Unlike existing integrated flat panel detectors, which are prone to insufficient driving force due to the large size of the flat panel detector, leading to significant differences in imaging effects between the photodetectors 20 near and far from the driving circuit 50 and resulting in poor imaging, this invention avoids such problems.

[0081] It should be noted that, in Figure 1 The diagram shows the substrate 10 divided into 4 detection areas AA. In practical applications, the substrate 10 can also be divided into 2 detection areas AA, or 6 detection areas AA, etc., which will not be elaborated here.

[0082] In the embodiments provided by this invention, if the photodetector 20 is a passive device, a passive drive is used; if it is an active device, an active drive is used. Please refer to [link to relevant documentation]. Figure 5 This is a schematic diagram showing the position of the thin-film transistor in a flat panel detector provided in an embodiment of the present invention. In this embodiment, the flat panel detector further includes:

[0083] Thin-film transistor 70, the gate 701 of thin-film transistor 70 is electrically connected to the corresponding scan line 30, the first electrode 702 of thin-film transistor 70 is electrically connected to the corresponding data line 40, and the second electrode 703 of thin-film transistor 70 is electrically connected to the corresponding photodetector 20.

[0084] The gate 701 of the thin film transistor 70 is disposed on the same layer as the scan line 30, and the first electrode 702 and the second electrode 703 of the thin film transistor 70 are disposed on the same layer as the data line 40.

[0085] It should be understood that, for ease of viewing, Figure 3The location where data line 40 and scan line 30 break is drawn at the same position, which is actually combined with... Figure 1 and Figure 2 It can be seen that the location where data line 40 and the scan disconnect are different.

[0086] Please see Figures 6-8 , Figure 6 This is a schematic diagram showing the location of the through-hole in the insulating layer within a flat panel detector, as provided in an embodiment of the present invention. Figure 7 This is a cross-sectional view of an insulating layer at the location where the scan line is broken, provided in an embodiment of the present invention. Figure 8 A cross-sectional view of an insulating layer at a location where a data line is disconnected, provided as an embodiment of the present invention. In the embodiment provided by the present invention, the flat panel detector further includes:

[0087] At least one insulating layer 80 located between the layer containing the scan line 30 and the protective layer 60, and at least one insulating layer 80 located between the layer containing the data line 40 and the protective layer 60;

[0088] Each insulating layer 80 has a through hole H covering the location where the scan line 30 and data line 40 are disconnected.

[0089] By providing through holes H in each insulating layer 80 at the locations where the scan lines 30 and data lines 40 are disconnected, it is convenient to disconnect the scan lines 30 and data lines 40 at the overlapping locations of the locations where multiple detection areas are divided after the photodetector 20 is formed and before the protective layer 60 is formed, instead of immediately disconnecting the scan lines 30 and data lines 40 at the overlapping locations of the locations where multiple detection areas are divided after the scan lines 30 and data lines 40 are formed. This can prevent tip discharge when the scan lines 30 and data lines 40 are cleaned by ultraviolet (UV) irradiation during the production process, thereby effectively avoiding electrostatic damage caused by tip discharge of metal traces during the production process.

[0090] When the flat panel detector includes a thin film transistor 70, at least one insulating layer 80 located between the layer where the scan line 30 is located and the protective layer 60 specifically includes: a gate insulating layer 801, a first insulating layer 802, and a second insulating layer 803.

[0091] The at least one insulating layer 80 located between the data line 40 layer and the protective layer 60 specifically includes: a first insulating layer 802 and a second insulating layer 803.

[0092] In one possible implementation, along the direction Z from the substrate 10 to the protective layer 60, the vias H of each insulating layer 80 gradually decrease in size.

[0093] The vias formed on at least one insulating layer 80 can be symmetrical. However, in actual production, when the vias H in each insulating layer 80 are patterned after the corresponding insulating layer 80 is formed, misalignment may occur during the patterning of different insulating layers. Therefore, the vias H in different insulating layers 80 may not be symmetrical. Figure 9 This is a cross-sectional view of another insulating layer at the location where the scan line is broken, provided in an embodiment of the present invention. Figure 10 A cross-sectional view of another insulating layer provided in an embodiment of the present invention at the location where the data line is disconnected.

[0094] By gradually reducing the via H of each insulating layer 80 in the direction Z along the substrate 10 toward the protective layer 60, sufficient etching space can be provided for subsequent etching of data lines 40 and scan lines 30, while also protecting the edges of data lines 40 and scan lines 30, preventing the etched length of data lines 40 and scan lines 30 from exceeding the range due to over-etching.

[0095] In the embodiments provided by the present invention, the vias H of each insulating layer 80 can be formed separately when the corresponding insulating layer 80 is patterned, so that the sidewall of the via H of the upper insulating layer 80 covers the sidewall of the via H of the lower insulating layer 80; the vias H of each insulating layer 80 can also be formed by etching all the insulating layers 80 between the film layer where the scan line 30 is located and the protective layer 60 after all the insulating layers 80 between the film layer where the scan line 30 is located and the protective layer 60 are deposited together.

[0096] In the embodiments provided by the present invention, the length of the break at the disconnection position of the scan line 30 and the data line 40 is less than the inner diameter of the through hole H of the bottom insulating layer 80 in at least one insulating layer 80, so that the length of the corresponding data line 40 and the scan line 30 at the disconnection position can be kept within the required range.

[0097] Please see Figure 11 and Figure 12 , Figure 11 This is a schematic diagram illustrating the location where the scan line and data line are disconnected in a flat panel detector according to an embodiment of the present invention. Figure 12 This is a schematic diagram showing the location where the scan line and data line are disconnected in another flat panel detector provided in an embodiment of the present invention.

[0098] In the embodiments provided by this invention, the positions where multiple detection areas AA are divided correspond to breaks in multiple scan lines 30 located in the same column of pixels, and the positions where multiple detection areas AA are divided correspond to breaks in multiple data lines 40 located in the same row of pixels corresponding to photodetectors 20. The length of each break is less than the length of one pixel. For example... Figure 11As shown in the figure, in the direction in which the scan line 30 extends, if the length of one pixel is m, then the length h1 of the break on the scan line 30 is less than m; in the direction in which the data line 40 extends, if the length of one pixel is n, then the length h2 of the break on the data line 40 is less than n.

[0099] As Figure 12 shown, if the breaks of the data line 40 and the scan line 30 do not include the connection points corresponding to the photodetectors 20, the photodetectors 20 corresponding to the breaks can still work properly, which enables all the photodetectors 20 in the entire flat panel detector to work properly and does not affect the imaging effect of the flat panel detector.

[0100] In the embodiment provided by the present invention, by setting the lengths of the breaks at the disconnection positions of the scan line 30 and the data line 40 to be less than the length of one photodetector 20, at most only the photodetectors 20 in the rows and / or columns where the positions where multiple detection regions are divided in the flat panel detector do not work, which does not affect the imaging effect of the flat panel detector.

[0101] Generally, the length of one pixel is 140 micrometers. In the embodiment of the present invention, the lengths of the breaks at the disconnection positions of the scan line 30 and the data line 40 are less than 100 micrometers.

[0102] Based on the same inventive concept, an embodiment of the present invention provides a manufacturing method of a flat panel detector. For the specific implementation of the flat panel detector corresponding to this manufacturing method, reference can be made to the description in the method embodiment part. Repetitive parts will not be elaborated here. Please refer to Figure 13 , and this manufacturing method includes:

[0103] Step 131: Provide a substrate, and the substrate is divided into multiple detection regions;

[0104] Step 132: Form original scan lines and original data lines on the substrate, and the original scan lines and original data lines respectively pass through the positions where multiple detection regions intersect and are divided;

[0105] Step 133: Form photodetectors arranged in an array in each detection region on the substrate;

[0106] Step 134: Disconnect the original scan lines and original data lines at the positions corresponding to the division of multiple detection regions, and form scan lines and data lines that do not overlap with the positions where multiple detection regions are divided;

[0107] Step 135: On the side of the photodetector facing away from the substrate, form a protective layer covering the scan lines, data lines, and the positions where the scan lines and data lines are disconnected; wherein, at the positions where the scan lines and data lines are disconnected, they are provided in the same layer as the scan lines and data lines;

[0108] Step 136: Bind the corresponding driving circuit to each detection area, and electrically connect the driving circuit to the scan line and data line connected to the photodetector in the corresponding detection area.

[0109] In the embodiments provided by this invention, photodetectors are formed in an array on a substrate, located within each detection region. After forming the photodetectors, the original scan lines and data lines are disconnected at the points where the multiple detection regions are segmented, forming scan lines and data lines that do not overlap with the segmented locations. This makes the scan lines and data lines of each detection region independent, and a corresponding driving circuit is bound to each detection region. Each detection region can use its own driving circuit to drive its own photodetector, thus enabling the flat panel detector composed of multiple detection regions to detect objects larger than a single detection region while maintaining the same driving capability as a single detection region. This allows the flat panel detector to effectively detect large-sized objects while maintaining high imaging quality. Furthermore, disconnecting the scan lines and data lines after forming the photodetectors prevents tip discharge during UV irradiation cleaning of the scan lines and data lines during production, effectively avoiding electrostatic damage caused by tip discharge of metal traces during production.

[0110] In the embodiments provided by this invention, the photodetector may be a passive device or an active device. When the photodetector is a passive device, a passive driving method is used, that is, there is no need to set a thin-film transistor for the photodetector. When the photodetector is an active device, an active driving method is used, that is, a thin-film transistor needs to be set for the photodetector. In this case, the original scan lines and original data lines are formed on the substrate, specifically including:

[0111] A gate metal layer is formed on a substrate, the gate metal layer including the original scan line and the gate of the thin film transistor;

[0112] A gate insulating layer is formed on the gate metal layer;

[0113] A source-drain metal layer is formed on the gate insulating layer. The source-drain metal layer includes the original data line and the first and second electrodes of the thin-film transistor.

[0114] Please see Figure 14 This is a schematic diagram of the interlayer film between the substrate and the gate insulating layer, corresponding to the overlapping positions of the original scan lines and the division of multiple detection areas, provided in an embodiment of the present invention. Figure 14 In the process, a gate metal layer and a gate insulating layer are sequentially formed on the substrate. The gate insulating layer covers the overlapping positions of the original scan line and the multiple detection areas, and the thickness of the gate insulating layer covering the overlapping positions of the original scan line and the multiple detection areas remains unchanged.

[0115] Please see Figure 15 This is a schematic diagram of another substrate-to-gate insulating layer corresponding to the overlapping positions of the original scan line and the segmented multiple detection regions provided in an embodiment of the present invention. After forming the gate insulating layer on the gate metal layer, it further includes:

[0116] At the locations where the original scan lines and multiple detection regions overlap, the gate insulating layer is etched to form blind vias in the gate insulating layer.

[0117] By etching the gate insulating layer at the overlapping locations where the original scan line and multiple detection areas are segmented, blind vias of the gate insulating layer can be formed. This prevents other insulating film layers from being over-etched and damaging the original scan line when forming vias at the overlapping locations where the original scan line and multiple detection areas are segmented.

[0118] One possible implementation includes forming a first insulating layer and a second insulating layer while forming a photodetector.

[0119] Please see Figure 16 This is a schematic diagram of the substrate to the second insulating interlayer film corresponding to the overlapping positions of the original scan lines and multiple detection regions, provided by an embodiment of the present invention. Figure 16 In the process, a gate metal layer, a gate insulating layer, a first insulating layer, and a second insulating layer are sequentially formed on the substrate. The gate insulating layer, the first insulating layer, and the second insulating layer all cover the overlapping positions of the original scan line and the multiple detection areas, and the thickness of the gate insulating layer, the first insulating layer, and the second insulating layer covering the overlapping positions of the original scan line and the multiple detection areas remains unchanged.

[0120] Please see Figure 17 This is a schematic diagram of another substrate layer corresponding to the overlapping positions of the original scan lines and multiple detection regions provided in an embodiment of the present invention, which includes, after forming the first insulating layer:

[0121] At the locations where the original scan lines and multiple detection areas overlap, the first insulating layer is etched to form a through-hole penetrating the first insulating layer; at the locations where the original data lines and multiple detection areas overlap, the first insulating layer is etched to form a blind via of the first insulating layer.

[0122] After the second insulating layer is formed, it also includes:

[0123] The second insulating layer is etched at the locations where the original scan lines, original data lines, and multiple detection areas overlap, forming through holes that penetrate the second insulating layer.

[0124] The method of forming the substrate to the first insulating layer and the second insulating layer at the overlapping positions of the original data lines and the division of multiple detection areas is similar to the method of forming the substrate to the gate insulating layer and the second insulating layer at the overlapping positions of the scan lines and the boundary lines, and will not be described in detail here.

[0125] By setting blind vias in the first insulating layer at the locations where the original data line and multiple detection areas overlap, it is possible to prevent over-etching and damage to the original data line when forming through-holes in the second insulating layer at the corresponding locations.

[0126] One possible implementation involves breaking the original scan lines and original data lines at positions corresponding to the division of multiple detection regions, forming scan lines and data lines that do not overlap with the division positions of the multiple detection regions, including:

[0127] At the location where the original scan line and multiple detection areas overlap, the film layer between the original scan line and the protective layer is etched to form a through hole that penetrates the film layer between the original scan line and the protective layer.

[0128] At the intersection of the original data line and the multiple detection areas, the film layer between the original data line and the protective layer is etched to form a through hole that penetrates the film layer between the original data line and the protective layer.

[0129] Please see Figure 18 This provides another schematic diagram of forming through holes in each insulating layer for an embodiment of the present invention.

[0130] by Figure 16 For example, in Figure 16 After forming the second insulating layer, the gate insulating layer, the first insulating layer, and the second insulating layer are etched one by one to form vias in the corresponding insulating layers. Then, the original scan lines at the via locations are etched to break the original scan lines at the via locations, forming scan lines. Similarly, at the overlapping locations where the original data lines and multiple detection areas are segmented, the film layer between the original data lines and the protective layer can be etched to form vias penetrating the gate insulating layer, the first insulating layer, and the second insulating layer.

[0131] One possible implementation involves breaking the original scan lines and original data lines at positions corresponding to the division of multiple detection regions, forming scan lines and data lines that do not overlap with the division positions of the multiple detection regions, including:

[0132] Etch blind holes into through holes;

[0133] Etching is performed in the area where the via of the gate insulating layer is projected onto the original scan line to form scan lines that do not overlap with the positions where multiple detection areas are separated;

[0134] Etching is performed on the area where the vias in the first insulating layer are projected onto the original data line, forming data lines that do not overlap with the locations where multiple detection areas are separated.

[0135] Please see Figure 19 A schematic diagram of etching blind holes into through holes is provided for an embodiment of the present invention. Figure 19 Therefore Figure 18 For example.

[0136] Please see Figure 20 A flowchart for forming scan lines is provided for an embodiment of the present invention.

[0137] S11: Form the gate metal layer.

[0138] The gate metal layer includes the original scan line and the gate of the thin-film transistor. Figure 19 The locations where the original scan line overlaps with the points where multiple detection regions are segmented do not have the gates of thin-film transistors, and therefore are not shown.

[0139] S12: Forms a gate insulating layer.

[0140] After the gate insulating layer is formed, the gate insulating layer is etched at the location where the original scan line overlaps with the location where multiple detection areas are segmented, forming blind holes in the gate insulating layer.

[0141] S13: Source and drain metal layers and the first insulating layer are formed sequentially.

[0142] The source and drain metal layers include the original data lines and the first and second electrodes of the thin-film transistor. After forming the first insulating layer, the first insulating layer is etched at the locations where the original scan lines overlap with the locations where multiple detection areas are segmented to form vias of the first insulating layer, and at the locations where the original data lines overlap with the locations where multiple detection areas are segmented to form blind vias of the first insulating layer.

[0143] S14: Form the second insulating layer.

[0144] After the second insulating layer is formed, the second insulating layer is etched at the locations where the original scan lines and multiple detection areas are divided, and at the locations where the original data lines and multiple detection areas are divided, to form vias in the second insulating layer.

[0145] S15: Etch the blind vias in the first insulating layer and the blind vias in the gate insulating layer into through holes.

[0146] S16: Disconnect the original data line to form a data line, disconnect the original scan line to form a scan line.

[0147] S17: A photodetector and a protective layer are formed sequentially.

[0148] Please see Figure 21 A flowchart for forming a data line is provided for an embodiment of the present invention.

[0149] S21: The gate metal layer and the gate insulating layer are formed sequentially.

[0150] S22: Form source and drain metal layers.

[0151] S23: Form the first insulating layer.

[0152] S24: Form the second insulating layer.

[0153] S25: Etch the blind vias in the gate insulating layer and the blind vias in the first insulating layer into through holes.

[0154] S26: Disconnect the original scan line to form a scan line; disconnect the original data line to form a data line.

[0155] S27: A photodetector and a protective layer are formed sequentially.

[0156] It is important to understand that the process of forming scan lines and data in the manufacturing of flat panel detectors is actually the same process, and should not be interpreted as different.

[0157] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, embodiments of the present invention can take the form of entirely hardware embodiments, entirely software embodiments, or embodiments combining software and hardware aspects. Furthermore, embodiments of the present invention can take the form of computer program products implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0158] Embodiments of the present invention are described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0159] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0160] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0161] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A flat panel detector, characterized in that, include: A substrate, wherein the substrate is divided into multiple detection areas; Multiple photodetectors arranged in an array, the multiple photodetectors being distributed within the multiple detection areas; Multiple scan lines and multiple data lines are electrically connected to each of the photodetectors, and the scan lines and the data lines are disconnected at the locations where the multiple detection areas are divided; A protective layer is located on the side of the layer containing the scan line and the layer containing the data line away from the substrate. The protective layer covers the scan line, the data line, and the location where the scan line and the data line are disconnected. The portion of the protective layer located at the location where the scan line is disconnected is disposed in the same layer as the scan line, and the portion of the protective layer located at the location where the data line is disconnected is disposed in the same layer as the data line. Multiple driving circuits are provided, with at least one driving circuit corresponding to each detection area. The driving circuits are electrically connected to the scan lines and data lines connected to the photodetectors within the corresponding detection area.

2. The flat panel detector as described in claim 1, characterized in that, Also includes: At least one insulating layer located between the layer containing the scan line and the protective layer, and at least one insulating layer located between the layer containing the data line and the protective layer; Each of the insulating layers has a through-hole covering the location where the scan line and the data line are disconnected.

3. The flat panel detector as described in claim 2, characterized in that, Along the direction from the substrate to the protective layer, the vias of each insulating layer gradually decrease in size.

4. The flat panel detector as described in claim 2, characterized in that, Also includes: A thin-film transistor, wherein the gate of the thin-film transistor is electrically connected to the corresponding scan line, the first electrode of the thin-film transistor is electrically connected to the corresponding data line, and the second electrode of the thin-film transistor is electrically connected to the corresponding photodetector; The gate of the thin-film transistor is disposed on the same layer as the scan line, and the first and second electrodes of the thin-film transistor are respectively disposed on the same layer as the data line.

5. The flat panel detector as described in claim 4, characterized in that, The at least one insulating layer located between the scan line layer and the protective layer specifically includes: a gate insulating layer, a first insulating layer, and a second insulating layer; The at least one insulating layer located between the data line layer and the protective layer specifically includes: the first insulating layer and the second insulating layer.

6. The flat panel detector according to any one of claims 2-5, characterized in that, The length of the break at the location where the scan line and the data line are disconnected is less than the inner diameter of the through hole in the bottommost insulating layer of the at least one insulating layer.

7. The flat panel detector according to any one of claims 1-5, characterized in that, The length of the break at the location where the scan line and the data line are disconnected is less than the length of a pixel corresponding to a photodetector.

8. A method for manufacturing a flat panel detector, characterized in that, include: A substrate is provided, the substrate being divided into multiple detection regions; Original scan lines and original data lines are formed on the substrate, and the original scan lines and original data lines respectively pass through the positions where the plurality of detection regions are segmented and intersect with them; A photodetector is formed on the substrate and arranged in an array within each detection area; The original scan lines and the original data lines are broken at the locations where the multiple detection areas are divided, forming scan lines and data lines that do not overlap with the locations where the multiple detection areas are divided; On the side of the photodetector facing away from the substrate, a protective layer is formed covering the scan line, the data line, and the location where the scan line and the data line are disconnected; wherein, at the location where the scan line and the data line are disconnected, a protective layer is formed in the same layer as the scan line and the data line; A corresponding driving circuit is bound to each of the detection areas, and the driving circuit is electrically connected to the scan line and data line connected to the photodetector in the corresponding detection area.

9. The manufacturing method as described in claim 8, characterized in that, Forming original scan lines and original data lines on the substrate, specifically including: A gate metal layer is formed on the substrate, the gate metal layer including the original scan line and the gate of the thin film transistor; A gate insulating layer is formed on the gate metal layer; A source-drain metal layer is formed on the gate insulating layer, the source-drain metal layer including the original data line and the first and second electrodes of the thin film transistor.

10. The manufacturing method as described in claim 9, characterized in that, After forming a gate insulating layer on the gate metal layer, the method further includes: At the locations where the original scan lines and the multiple detection regions overlap, the gate insulating layer is etched to form blind vias in the gate insulating layer.

11. The manufacturing method as described in claim 9 or 10, characterized in that, The process of forming the photodetector also includes forming a first insulating layer and a second insulating layer.

12. The manufacturing method as described in claim 11, characterized in that, After the first insulating layer is formed, the process also includes: At the location where the original scan line and the multiple detection areas are divided, the first insulating layer is etched to form a through hole penetrating the first insulating layer. At the location where the original data line and the plurality of detection areas overlap, the first insulating layer is etched to form a blind hole in the first insulating layer.

13. The manufacturing method as described in claim 12, characterized in that, After the second insulating layer is formed, the method further includes: The second insulating layer is etched at the locations where the original scan line, the original data line, and the multiple detection areas overlap, respectively, to form through holes penetrating the second insulating layer.

14. The manufacturing method as described in claim 11, characterized in that, The original scan lines and the original data lines are broken at the locations where the multiple detection regions are segmented, forming scan lines and data lines that do not overlap with the locations where the multiple detection regions are segmented, including: At the location where the original scan line and the multiple detection areas are divided, the film layer between the original scan line and the protective layer is etched to form a through hole that penetrates the film layer between the original scan line and the protective layer. At the location where the original data line and the multiple detection areas overlap, the film layer between the original data line and the protective layer is etched to form a through hole that penetrates the film layer between the original data line and the protective layer.

15. The manufacturing method as described in claim 12 or 13, characterized in that, The original scan lines and the original data lines are broken at the locations where the multiple detection regions are segmented, forming scan lines and data lines that do not overlap with the locations where the multiple detection regions are segmented, including: The blind hole is etched into the through hole; Etching is performed in the area where the via of the gate insulating layer is projected onto the original scan line to form scan lines that do not overlap with the positions where the multiple detection areas are divided; Etching is performed in the area where the through-hole of the first insulating layer is projected onto the original data line to form a data line that does not overlap with the positions where the multiple detection areas are separated.

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