Light source control circuit adapting to input signal frequency and operation method thereof

Abstract

A light source control circuit includes a light detector, a frequency detector, a differential amplifier, an NMOS driver, and a light source. The frequency detector determines the signal frequency according to the detection voltage signal output by the light detector and generates a control signal accordingly. The NMOS driver changes the driving current of the light source according to the output of the differential amplifier. The differential amplifier changes its bandwidth according to the control signal from the frequency detector to adjust the response time of changing the driving current of the light source.

Description

Technical Field

[0001] The present invention relates to a light source control circuit, and more particularly to a light source control circuit in an optical encoding system that can adapt to frequency changes of an input signal and an operating method thereof. Background Art

[0002] Optical detection systems usually require that the detected light intensity be stable. One way to do this is to control the system light source to maintain a stable light intensity.

[0003] For example, Figure 1 A conventional optical detection system is shown, which includes a photodetector 91, a reference voltage generator 93, a differential amplifier 95, an NMOS driver 97 and a light emitting diode LED. The photodetector 91 is used to detect modulated light to generate a detection signal, such as Figure 2A The optical detector 91 also extracts the common mode voltage V of the detection signal. CM The reference voltage generator 93 outputs a reference voltage Vref based on the expected common mode voltage. The differential amplifier 95 compares the output signal Vdet with the reference voltage Vref to eliminate common mode noise. The NMOS driver 97 adjusts the driving current of the light emitting diode LED according to the output of the differential amplifier 95 to control its luminous intensity.

[0004] However, the signal frequency of the output signal Vdet of the light detector 91 changes with the rotation speed of the detected shaft, so it is desired that the regulation response time of the light emitting diode LED also changes with the signal frequency of the output signal Vdet.

[0005] In view of this, a light source control circuit of an optical encoding system capable of adapting to the frequency change of a detection signal and an operating method thereof are needed. Summary of the invention

[0006] The present invention provides a light source control circuit of an optical encoding system for adjusting the regulation rate of a light source driving current according to a comparison result between a detection signal frequency and at least one frequency threshold and an operation method thereof.

[0007] The present invention also provides a light source control circuit of an optical encoding system and an operating method thereof for adjusting the adjustment response time of the light source driving current relative to different rotation directions of the encoding medium of the optical encoding system.

[0008] The present invention provides a light source control circuit of an optical encoding system including a controller and a frequency detector. The optical encoding system includes an encoding medium and a light source. The controller is used to receive a first detection signal, a second detection signal, a third detection signal and a fourth detection signal related to the encoding medium, and includes a differential amplifier, which is used to control the driving current of the light source, wherein the phase of the second detection signal leads the fourth detection signal by 90 degrees. The frequency detector is used to receive the second detection signal and the fourth detection signal, and includes a low-pass filter, a first comparator, a second comparator and a trigger. The low-pass filter is used to filter the second detection signal and has a cut-off frequency. The first comparator is used to compare the filtered second detection signal with a first reference voltage to output a comparison signal. The second comparator is used to compare the fourth detection signal with a second reference voltage to output a clock signal. The data input terminal of the trigger is used to receive the comparison signal, the clock input terminal is used to receive the clock signal, and the output terminal is used to generate an output signal to change the bandwidth of the differential amplifier to adjust the response time of the driving current of the light source.

[0009] The present invention also provides a light source control circuit of an optical encoding system including a controller and a frequency detector. The optical encoding system includes an encoding medium and a light source. The controller is used to receive a first detection signal, a second detection signal, a third detection signal and a fourth detection signal related to the encoding medium, and includes a differential amplifier, the output of which is used to control the driving current of the light source, wherein the phase of the second detection signal leads or lags behind the fourth detection signal by 90 degrees. The frequency detector is used to receive the second detection signal and the fourth detection signal, and includes a low-pass filter, a first comparator, a second comparator, a first trigger, a first inverter and a second trigger. The low-pass filter is used to filter the second detection signal and has a cut-off frequency. The first comparator is used to compare the filtered second detection signal with a first reference voltage to output a comparison signal. The second comparator is used to compare the fourth detection signal with a second reference voltage to output a clock signal. The data input terminal of the first trigger is used to receive the comparison signal, the clock input terminal thereof is used to receive the clock signal, and the output terminal thereof is used to generate a first output signal when the phase of the second detection signal leads the fourth detection signal to change the bandwidth of the differential amplifier to adjust the response time of the driving current of the light source. The first inverter is used to invert the phase of the clock signal. The data input terminal of the second trigger is used to receive the comparison signal, the clock input terminal is used to receive the inverted clock signal, and the output terminal is used to generate a second output signal when the phase of the second detection signal lags behind the fourth detection signal to change the bandwidth of the differential amplifier to adjust the response time.

[0010] The present invention also provides an operation method of a light source control circuit of an optical encoding system. The optical encoding system includes an encoding medium and a light source. The light source control circuit includes a differential amplifier, a low-pass filter, a first comparator, a second comparator and a first trigger. The operation method includes the following steps: using the low-pass filter to receive a detection signal related to the encoding medium and outputting a filtered detection signal; using the first comparator to compare the filtered detection signal with a first reference voltage to output a comparison signal; using the second comparator to receive another detection signal related to the encoding medium and compare the other detection signal with a second reference voltage to output a clock signal, wherein the phase of the detection signal leads or lags behind the other detection signal by 90 degrees; and when the phase of the detection signal leads the other detection signal, using the first trigger to receive the comparison signal and the clock signal and generate a first output signal to change the bandwidth of the differential amplifier to adjust the response time of the driving current of the light source.

[0011] In the light source control circuit of the embodiment of the present invention, the reference voltage generating circuit may be formed by a fixed voltage source, a circuit including a reference square circuit and a conversion circuit, or other voltage generators.

[0012] In the optical encoding system of the present invention, different codes are made on the encoding medium to modulate the incident light. The modulated reflected light is incident on different photodiodes of the photodetector to generate current signals with a phase difference of 90 degrees, such as a sine signal and a cosine signal. The transimpedance amplifier is used to amplify the current signal and convert it into a voltage signal.

[0013] In order to make the above and other purposes, features and advantages of the present invention more obvious, the following will be described in detail with reference to the accompanying drawings. In addition, in the description of the present invention, the same components are represented by the same symbols, which are hereby described together. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a schematic diagram of a known light source control circuit;

[0015] Figure 2A yes Figure 1 The light source control circuit outputs a voltage signal without DC offset;

[0016] Figure 2B yes Figure 1 A voltage signal having a DC offset outputted by a light source control circuit;

[0017] Figure 3 is a schematic diagram of an optical encoding system according to an embodiment of the present invention;

[0018] Figure 4 is a block diagram of a light source control circuit according to an embodiment of the present invention;

[0019] Figure 5 is a schematic diagram of a common mode voltage circuit of a light source control circuit according to an embodiment of the present invention;

[0020] Figure 6 is a circuit diagram of a square circuit of a light source control circuit according to an embodiment of the present invention;

[0021] Figure 7 is a partial circuit diagram of a controller of a light source control circuit according to an embodiment of the present invention;

[0022] Figure 8 is a schematic diagram of the sum of square currents of the light source control circuit according to an embodiment of the present invention;

[0023] Fig. 9 is a circuit diagram of a light source control circuit according to an embodiment of the present invention;

[0024] Fig. 10A is a block diagram of a light source control circuit according to another embodiment of the present invention;

[0025] Fig. 10B is another block diagram of a light source control circuit according to another embodiment of the present invention;

[0026] Fig.11 is a block diagram of a frequency detector of a light source control circuit according to another embodiment of the present invention;

[0027] Figures 12A-12F is a signal timing diagram of a frequency detector of a light source control circuit according to another embodiment of the present invention, wherein the signal frequency is lower than the cut-off frequency;

[0028] Figures 13A-13F is a signal timing diagram of a frequency detector of a light source control circuit according to another embodiment of the present invention, wherein the signal frequency is higher than the cut-off frequency;

[0029] Figures 14A-14F is a signal timing diagram of a frequency detector of a light source control circuit according to another embodiment of the present invention, wherein the direction of the coded medium is Figures 12A-12F on the contrary;

[0030] Fig.15 is a block diagram of a light source control circuit according to yet another embodiment of the present invention; and

[0031] Fig.16 is a flow chart of an operating method of a light source control circuit according to another embodiment of the present invention.

[0032] Description of Reference Numerals

[0033] 100, 100', 100" optical encoding system

[0034] 10 Controller

[0035] 20 Reference voltage generation circuit

[0036] 30 Light Source

[0037] 40 Encoded Media

[0038] 50 Photodetector

[0039] 60 Transimpedance Amplifier

[0040] 70 Frequency detector

[0041] 71 Low-pass filter

[0042] 72 First comparator

[0043] 73 Second comparator

[0044] 74 First Trigger

[0045] 75 Second Inverter

[0046] 76 First Inverter

[0047] 77 Second trigger

[0048] 78 OR Gate DETAILED DESCRIPTION

[0049] Please refer to Figure 3 , which is a schematic diagram of an optical encoding system 100 according to an embodiment of the present invention. The optical encoding system 100 includes a controller 10, a reference voltage generating circuit 20, a light source 30, a coding medium 40, a photodetector 50, and a trans-impedance amplifier (TIA) 60. In a non-limiting embodiment, the controller 10, the reference voltage generating circuit 20, the light source 30, the photodetector 50, and the trans-impedance amplifier 60 of the optical encoding system 100 are, for example, formed in the same package to form a control module, and can perform decoding operations as long as they are arranged relative to the coding medium 40.

[0050] In a non-limiting embodiment, the controller 10 , the reference voltage generating circuit 20 and the group amplifier 60 form a light source control circuit of an embodiment of the present invention, which is used to control the light source 30 to emit a stable light intensity according to the detection result of the light detector 50 .

[0051] The coding medium 40 is, for example, a code disk, on which different codes are formed for modulating the incident light from the light source 30. The light source 30 is, for example, a light emitting diode or a laser diode, for emitting a predetermined wavelength of emission light Le (such as red light or infrared light) to illuminate the coding medium 40, so as to generate modulated reflected light Lm through the codes on the coding medium 40. Figure 3 The display code disk is controlled by the motor to rotate counterclockwise, so the different codes on it are illuminated by the emitted light Le of the light source 30 to generate modulated reflected light Lm. Since the encoding method of the coding medium 40 is not the purpose of the present invention, as long as the light detector 50 can detect the modulated reflected light Lm to generate a predetermined current signal (an example will be described later), any known method can be used for encoding.

[0052] The photodetector 50 is disposed at an appropriate position to receive the modulated reflected light Lm. The photodetector 50 is, for example, a CCD image sensor, a CMOS image sensor, or other sensors for detecting light energy to generate electrical signals. For example, the photodetector 50 includes a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, and a fourth photodiode PD4, which are used to receive the modulated reflected light Lm and generate a first current signal I_sin-, a second current signal I_sin+, a third current signal I_cos-, and a fourth current signal I_cos+, respectively, wherein the first current signal I_sin- and the second current signal I_sin+ (for example, a sine signal) are in opposite phases, and the third current signal I_cos- and the fourth current signal I_cos+ (for example, a cosine signal) are in opposite phases, and the first current signal I_sin- and the third current signal I_cos- have a 90-degree phase difference (orthogonal), and the second current signal I_sin+ and the fourth current signal I_cos+ have a 90-degree phase difference (orthogonal).

[0053] It must be pointed out that although Figure 3 Only four photodiodes PD1 to PD4 are shown, but the present invention is not limited thereto. In a non-limiting embodiment, Figure 3 Each photodiode PD1-PD4 may include multiple photodiodes, and each current signal is an average current or current sum relative to each group of multiple photodiodes. For example, the first current signal I_sin- is the output average current or current sum of multiple first photodiodes PD1, the second current signal I_sin+ is the output average current or current sum of multiple second photodiodes PD2, and so on.

[0054] The transimpedance amplifier (TIA) 60 may use a known single-stage or multi-stage transimpedance amplifier without any particular limitation, as long as the input signal can be amplified to a predetermined peak-to-peak value (for example, but not limited to, 1 volt peak-to-peak value) with a predetermined gain. The transimpedance amplifier 60 is used to amplify and convert the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos-, and the fourth current signal I_cos+ to generate and output a first detection signal V_sin-, a second detection signal V_sin+, a third detection signal V_cos-, and a fourth detection signal V_cos+, respectively, wherein the first detection signal V_sin- and the third detection signal V_cos- differ in phase by 90 degrees, the third detection signal V_cos- and the second detection signal V_sin+ differ in phase by 90 degrees, and the second detection signal V_sin+ and the fourth detection signal V_cos+ differ in phase by 90 degrees.

[0055] In one embodiment, the transimpedance amplifier 60 does not change the phase of the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos- and the fourth current signal I_cos+ when performing current-to-voltage conversion, so the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos- and the fourth detection signal V_cos+ have the same phase as the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos- and the fourth current signal I_cos+ respectively.

[0056] In another embodiment, the transimpedance amplifier 60 changes the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos- and the fourth current signal I_cos+ to the same phase when performing current-to-voltage conversion, so that the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos- and the fourth detection signal V_cos+ have the same phase difference as the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos- and the fourth current signal I_cos+, respectively. That is, the phase relationship between the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos- and the fourth detection signal V_cos+ is the same as the phase relationship between the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos- and the fourth current signal I_cos+.

[0057] Please refer to Figure 4 , which is a block diagram of a light source control circuit according to an embodiment of the present invention. Figure 3The reference voltage generating circuit 20 and the transimpedance amplifier 60 are shown to be disposed outside the controller 10 , but the present invention is not limited thereto. In a non-limiting embodiment, the reference voltage generating circuit 20 and the transimpedance amplifier 60 may be included in the controller 10 .

[0058] The detection voltage generating circuit 101 of the controller 10 includes a common mode voltage circuit 110 , a first square circuit 111 , a second square circuit 113 , a square sum circuit and a first conversion circuit 115 . The controller 10 further includes a differential amplifier (error amplifier) ​​13 and an NMOS driver 15 .

[0059] The common mode voltage circuit 110 includes an averaging resistor circuit for averaging the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos-, and the fourth detection signal V_cos+. Figure 5 The average resistance circuit of the common-mode voltage circuit 110 includes an average resistor R1 receiving a first detection signal V_sin-, an average resistor R2 receiving a second detection signal V_sin+, an average resistor R3 receiving a third detection signal V_cos-, and an average resistor R4 receiving a fourth detection signal V_cos+. The average resistance circuit of the common-mode voltage circuit 110 also includes an average resistor R5 connecting the average resistors R1 and R2, and an average resistor R6 connecting the average resistors R3 and R4. The common-mode voltage circuit 110 generates a common-mode voltage signal V according to the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos-, and the fourth detection signal V_cos+. CM .

[0060] The first square circuit 111 is used to receive the first detection signal V_sin-, the second detection signal V_sin+ and the common mode voltage signal V CM And output the first current square signal I_sin 2 Please refer to Figure 6 , which is a circuit diagram of a first square circuit 111 according to an embodiment of the present invention. The first square circuit 111 includes a first transistor group 1111 , a second transistor group 1113 , a first subtraction circuit 1115 and a first bias circuit 1117 . Figure 6 It is shown that the transistors of the first transistor group 1111 , the second transistor group 1113 and the first bias circuit 1117 are PMOS transistors, and the transistors of the first subtraction circuit 1115 are NMOS transistors, but the invention is not limited thereto.

[0061] like Figure 6 As shown, the first transistor group 1111 includes two transistors M1 and M2 whose drains are connected to each other and whose sources are connected to each other. The gates of the two transistors M1 and M2 of the first transistor group 1111 receive the common mode voltage signal VCM The first transistor group 1111 is used to output a first current I1.

[0062] like Figure 6 As shown, the second transistor group 1113 includes two transistors M3 and M4 with their drains and sources connected to each other, and their gates receive the first detection signal V_sin- and the second detection signal V_sin+, respectively. The second transistor group 1113 is used to output the second current I2.

[0063] like Figure 6 As shown, the first bias circuit 1117 is connected between the voltage source Vs and the first transistor group 1111 and the second transistor group 1113. The first bias circuit 1117 includes two transistors M10 and M10' whose gates are connected to each other. The sources of the two transistors M10 and M10' of the first bias circuit 1117 are connected to the voltage source Vs. The gate of one of the two transistors of the first bias circuit 1117 (shown as M10 here) is connected to its drain. The drain of the other of the two transistors of the first bias circuit 1117 (shown as M10' here) is connected to the sources of the two transistors M1 and M2 of the first transistor group 1111 and the sources of the two transistors M3 and M4 of the second transistor group 1113.

[0064] like Figure 6 As shown, the first subtraction circuit 1115 is connected between the ground voltage Vg and the first transistor group 1111 and the second transistor group 1113. The first subtraction circuit 1115 is used to differentiate the first current I1 and the second current I2 to generate a first current square signal I_sin 2 .

[0065] According to transistor principle, the drain current Id3 of transistor M3 can be expressed by equation (1):

[0066] Id3=[Vs-(V G +Vamp1)-Vtp] 2 ×K / 2=(Vr-Vamp1) 2 ×K / 2 (1)

[0067] Where Vr = Vs - V G -Vtp,V G is the gate voltage of transistor M3, Vamp1 is the amplitude of V_sin-, K is the conductive parameter, and Vtp is the threshold voltage.

[0068] Similarly, the drain current Id4 of transistor M4 can be expressed by equation (2):

[0069] Id4=(Vr-Vamp2) 2 ×K / 2 (2)

[0070] Where Vamp2 is the amplitude of V_sin+

[0071] Similarly, the drain current Id1 of transistor M1 and the drain current Id2 of transistor M2 can be expressed by equation (3):

[0072] Id1=Id2=K×Vr 2 (3)

[0073] Assuming Vamp1 = Vamp2 = Vamp, then (Id3 + Id4) - (Id1 + Id2) = K × Vamp 2 =I_sin 2 , referred to as the first current square signal in this specification.

[0074] The first subtraction circuit 1115 includes a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a ninth transistor M9.

[0075] The gate of the fifth transistor M5 is connected to its drain. The drain of the fifth transistor M5 is connected to the drains of the two transistors M1 and M2 of the first transistor group 1111 to receive the first current I1.

[0076] A gate of the sixth transistor M6 is connected to the gate of the fifth transistor M5 , and a drain of the sixth transistor M6 is connected to the drains of the two transistors M3 and M4 of the second transistor group 1113 to receive the second current I2 .

[0077] The gate of the seventh transistor M7 is connected to the drain thereof, the drain of the seventh transistor M7 is connected to the source of the fifth transistor M5 , and the source of the seventh transistor M7 is connected to the ground voltage Vg.

[0078] A gate of the eighth transistor M8 is connected to the gate of the seventh transistor M7 , a drain of the eighth transistor M8 is connected to the source of the sixth transistor M6 , and a source of the eighth transistor M8 is connected to the ground voltage Vg.

[0079] The gate of the ninth transistor M9 is connected to its drain, the drain of the ninth transistor M9 is connected between the drain of the sixth transistor M6 and the second transistor group 1113, and the source of the ninth transistor M9 is connected to the ground voltage Vg. 2 Flows through the ninth transistor M9.

[0080] It must be pointed out that although Figure 6The first current I1 flows through two serially connected transistors M5 and M7, and the second current I2 flows through two serially connected transistors M6 and M8, but the present invention is not limited thereto. The number of transistors through which the first current I1 and the second current I2 flow is not limited to two, and the number is determined according to circuit parameters.

[0081] The second square circuit 113 is used to receive the third detection signal V_cos-, the fourth detection signal V_cos+ and the common mode voltage signal V CM And output the second current square signal I_cos 2 .

[0082] Please refer to Figure 7 , which is a partial circuit diagram of the controller 10 according to an embodiment of the present invention. The second square circuit 113 is similar to the first square circuit 111, and the difference lies in the different detection signals received by the two. The second square circuit 113 includes a third transistor group M11 and M12, a fourth transistor group M13 and M14, a second bias circuit and a second subtraction circuit. To simplify the diagram, Figure 7 The third transistor group, the fourth transistor group, the second bias circuit and the second subtraction circuit are not marked with darts.

[0083] Figure 7 It is shown that the transistors of the third transistor group, the fourth transistor group and the second bias circuit are PMOS transistors, and the transistors of the second subtraction circuit are NMOS transistors, but it is not limited thereto.

[0084] like Figure 7 As shown, the third transistor group includes two transistors M11 and M12 with their drains and sources connected to each other, and the gates of the two transistors M11 and M12 of the third transistor group receive the common mode voltage signal V CM The third transistor group is used to output a third current I3.

[0085] like Figure 7 As shown, the fourth transistor group includes two transistors M13 and M14 with mutually connected drains and sources, and the gates of the two transistors M13 and M14 of the fourth transistor group receive the third detection signal V_cos- and the fourth detection signal V_cos+ respectively. The fourth transistor group is used to output a fourth current I4.

[0086] like Figure 7As shown, the second bias circuit is connected between the voltage source Vs and the third transistor group and the fourth transistor group. The second bias circuit includes two transistors M10 and M10″ whose gates are connected to each other, and the sources of the two transistors M10 and M10″ of the second bias circuit are connected to the voltage source Vs. The gate of one of the two transistors of the second bias circuit (shown as M10 here) is connected to its drain, and the drain of the other of the two transistors of the second bias circuit (shown as M10″ here) is connected to the sources of the two transistors M11 and M12 of the third transistor group and the sources of the two transistors M13 and M14 of the fourth transistor group.

[0087] like Figure 7 As shown, the second subtraction circuit is connected between the ground voltage Vg and the third transistor group and the fourth transistor group, and is used to differentiate the third current I3 and the fourth current I4 to generate a second current square signal I_cos 2 , wherein the second square circuit 113 generates a second current square signal I_cos according to the third current I3 and the fourth current I4 2 The first square circuit 111 generates the first current square signal I_sin in a manner similar to that of the first square circuit 111. 2 , for example, refer to equations (1) to (3), so no further description is given here. The second subtraction circuit includes transistor M15, transistor M16, transistor M17, transistor M18 and transistor M19, and its connection method and function are similar to the first subtraction circuit 1115 and have been shown in Figure 7 , so I will not go into details here.

[0088] Please refer to Figure 7 The square sum circuit 1151 is used to calculate the first current square signal I_sin 2 With the second square circuit I_cos 2 The current square sum (I_sin 2 +I_cos 2 ) to generate a DC signal Idetect, please refer to Figure 8 shown.

[0089] The square sum circuit 1151 includes a fifth transistor group M9' and M19' and a square sum transistor M40, wherein Figure 7The fifth transistor group includes an NMOS transistor and the square sum transistor M40 is a PMOS transistor, but the present invention is not limited thereto. The fifth transistor group includes two transistors M9' and M19' whose drains are connected to each other and whose sources are connected to each other. The gates of the two transistors M9' and M19' of the fifth transistor group are respectively connected to the gate of the transistor M9 of the first subtraction circuit 1115 and the gate of the transistor M19 of the second subtraction circuit to mirror the first current square signal I_sin 2 and the second current square signal I_cos 2 That is, the transistor M9' and the transistor M9 form a current mirror; the transistor M19' and the transistor M19 form another current mirror. It is assumed here that the mirror ratio of the current mirror is 1.

[0090] The source of the square sum transistor M40 is connected to the voltage source Vs, the gate of the square sum transistor M40 is connected to its drain, and the drain of the square sum transistor M40 is connected to the drains of the two transistors M9' and M19' of the fifth transistor group, for generating the square sum of the current Idetect=(I_sin 2 +I_cos 2 ).

[0091] Please refer to Fig. 9 , which is a circuit diagram of a light source control circuit according to an embodiment of the present invention. The first conversion circuit 1153 is used to convert the current square sum Idetect into a detection voltage signal Vdetect. The first conversion circuit 1153 includes a first conversion transistor M40' and a first conversion resistor Rt1 connected to each other.

[0092] The gate of the first conversion transistor M40′ is connected to the gate of the square sum transistor M40 to generate the current square sum (I_sin 2 +I_cos 2 ) of the mirror current Im. When the mirror ratio is 1, the mirror current Im is substantially equal to the square sum of the currents Idetect=(I_sin 2 +I_cos 2 ).

[0093] When the mirror current Im of the current square sum flows through the first conversion resistor Rt1, the detection voltage signal Vdetect is generated. Thus, the detection voltage generating circuit 101 converts the voltage signals of different phases (eg Figure 5 ) is converted into a DC signal, which serves as a negative feedback signal for controlling the driving current of the light source 30.

[0094] The reference voltage generating circuit 20 is used to generate a reference voltage signal Vref to an input terminal of the differential amplifier 13, for example Figure 4 The positive input terminal is shown. The reference voltage signal Vref is a predetermined voltage value used to control the NMOS driver 15 to drive the light source 30 with a desired driving current.

[0095] In a non-limiting embodiment, the reference voltage generating circuit 20 includes a constant voltage source for outputting the reference voltage signal Vref.

[0096] In a non-limiting embodiment, Figure 4 The reference voltage generating circuit 20 includes a reference voltage generator 210, a reference square circuit 211 and a second conversion circuit 215, wherein the reference square circuit 211 uses the same circuit structure as the first square circuit 111 to cope with environmental (voltage, temperature) changes, the difference being that the voltage signals inputted by the two are different.

[0097] The reference voltage generator 210 is used to generate a desired first amplitude voltage V HIGH , the desired second amplitude voltage V LOW and the expected common-mode voltage V CMP (are determined in advance), where the desired common-mode voltage V CMP is the desired first amplitude voltage V HIGH and the desired second amplitude voltage V LOW The average value of the desired first amplitude voltage V HIGH is higher than the desired second amplitude voltage V LOW In a non-limiting embodiment, the first amplitude voltage V HIGH and the desired second amplitude voltage V LOW is selected according to the product specifications. The expected common-mode voltage V CMP is a predetermined voltage value that defines the magnitude of the driving current of the driving light source 30. That is, when the detection voltage signal Vdetect is greater than the expected common mode voltage V CMP When the detection voltage signal Vdetect is less than the expected common mode voltage V CMP , the NMOS driver 15 increases the luminous intensity of the light source 30 to maintain substantially the same driving current.

[0098] The reference square circuit 211 is used to receive the desired first amplitude voltage V HIGH , the desired second amplitude voltage V LOW and the desired common-mode voltage V CMP And output reference current square signal Iref 2 The second conversion circuit 215 includes a second conversion transistor M50′ and a second conversion resistor Rt2 connected to each other for converting the reference current square signal Iref 2The second conversion transistor M50' and the second conversion resistor Rt2 have similar functions to the first conversion transistor M40' and the first conversion resistor Rt1.

[0099] For example, refer to Fig. 9 The reference square circuit 211 includes a sixth transistor group M21 and M22, a seventh transistor group M23 and M24, a third bias circuit M30 and M30', a third subtraction circuit M25 to M29, and a current mirror circuit M50 and M29'.

[0100] like Fig. 9 As shown, the sixth transistor group includes two transistors M21 and M22 (shown as PMOS transistors here) whose drains are connected to each other and whose sources are connected to each other. The gates of the two transistors M21 and M22 of the sixth transistor group receive the desired common mode voltage V CMP The sixth transistor group is used to output a sixth current I6.

[0101] like Fig. 9 As shown, the seventh transistor group includes two transistors M23 and M24 (shown here as PMOS transistors) whose drains are connected to each other and whose sources are connected to each other. The gates of the two transistors M23 and M24 of the seventh transistor group receive the desired second amplitude voltage V LOW and the desired first amplitude voltage V HIGH The seventh transistor group is used to output a seventh current I7.

[0102] The third bias circuit is connected between the voltage source Vs and the sixth transistor group and the seventh transistor group. For example, the third bias circuit includes two transistors M30 and M30' (shown here as PMOS transistors) whose gates are connected to each other, the sources of the two transistors M30 and M30' of the third bias circuit are connected to the voltage source Vs, the gate of one of the two transistors of the third bias circuit (shown here as M30) is connected to its drain, and the drain of the other of the two transistors of the third bias circuit (shown here as M30') is connected to the sources of the two transistors M21 and M22 of the sixth transistor group and the sources of the two transistors M23 and M24 of the seventh transistor group.

[0103] The third subtraction circuit is connected between the ground voltage Vg and the sixth transistor group and the seventh transistor group, and is used to differentiate the sixth current I6 and the seventh current I7 to generate a reference current square signal Iref 2 For example, the third subtraction circuit includes a transistor M25, a transistor M26, a transistor M27, a transistor M28, and a transistor M29, wherein Fig. 9 It is shown that the third subtraction circuit includes NMOS transistors, but is not limited thereto.

[0104] The gate of the transistor M25 is connected to its drain. The drain of the transistor M25 is connected to the drains of the two transistors M21 and M22 of the sixth transistor group to receive the sixth current I6.

[0105] The gate of the transistor M26 is connected to the gate of the transistor M25 , and the drain of the transistor M26 is connected to the drains of the two transistors M23 and M24 of the seventh transistor group to receive the seventh current I7 .

[0106] The gate of the transistor M27 is connected to the drain thereof, the drain of the transistor M27 is connected to the source of the transistor M25, and the source of the transistor M27 is connected to the ground voltage Vg.

[0107] The gate of the transistor M28 is connected to the gate of the transistor M27 , the drain of the transistor M28 is connected to the source of the transistor M26 , and the source of the transistor M28 is connected to the ground voltage Vg.

[0108] The gate of transistor M29 is connected to its drain, the drain of transistor M29 is connected between the drain of transistor M26 and the seventh transistor group, and the source of transistor M29 is connected to the ground voltage Vg. The drain current of transistor M29 is the seventh current I7 minus the sixth current I6 to serve as the reference current square signal Iref. 2 Generate Iref 2 The method is similar to I_sin 2 , so we can refer to equations (1) to (3).

[0109] The current mirror circuit is used to generate the reference current square signal Iref 2 When the mirror ratio is 1, the first mirror current Im1 is approximately equal to the reference current square signal Iref. 2 The current mirror circuit includes a transistor M29 ′ for forming a current mirror with the transistor M29 , and includes a transistor M50 for forming a current mirror with the second conversion transistor M50 ′ in the second conversion circuit 25 .

[0110] The second conversion circuit 25 includes a second conversion transistor M50' and a second conversion resistor Rt2 connected to each other. The gate of the second conversion transistor M50' is connected to the gate of the transistor M50 of the current mirror circuit to mirror the first mirror current Im1 to generate the reference current square signal Iref 2 Similarly, when the mirror ratio of the second current mirror M50 and M50' is 1, the second mirror current Im2 is equal to the reference current square signal Iref 2 When the reference current square signal Iref 2When the second mirror current Im2 flows through the second conversion resistor Rt2, a reference voltage signal Vref is generated.

[0111] For connections of other components not described, refer to Fig. 9 shown.

[0112] The first input terminal (shown as the - terminal here) of the differential amplifier 13 receives the detection voltage signal Vdetect, and the second input terminal (shown as the + terminal here) of the differential amplifier 13 receives the reference voltage signal Vref for comparison. It should be noted that the voltage signals received by the first input terminal and the second input terminal of the differential amplifier 13 can be interchangeable.

[0113] The NMOS driver 15 is connected to the output terminal of the differential amplifier 13 , and is used to adjust the drain current Id according to the comparison result output by the differential amplifier 13 , wherein the drain current Id serves as the driving current of the light source 30 .

[0114] It should be noted that, although the mirror ratio of each current mirror is assumed to be 1 in the above embodiment for illustration, it is not intended to limit the present invention. As long as the reference voltage signal Vref input to the differential amplifier 13 is controlled to be a desired value, the mirror ratio of each current mirror may not be 1.

[0115] It should be noted that, although the encoding medium 40 is described as reflective and rotating in the above embodiment, the present invention is not limited thereto. In other embodiments, the encoding medium 40 may be transmissive (i.e., the light source and the light detector are located on different sides thereof) and the encoding medium 40 may be transparent or semi-transparent to the light of the light source 30. In other embodiments, the encoding medium 40 may perform one-dimensional, two-dimensional, or three-dimensional linear motion.

[0116] It must be noted that, although the light source control circuit is described in the above embodiment by taking the application in the optical encoding system 100 as an example, the present invention is not limited thereto. The light source control circuit can be applied to any application that requires stable control of the light intensity of the light source. In addition, controlling the light intensity of the light source is not limited to controlling its driving current, but can also control its driving voltage, depending on the light source used. For example, the drain current flowing through the NMOS driver is made to flow through a resistor to generate a driving voltage.

[0117] The present invention also provides an optical encoding system 100' and 100". that adjusts the adjustment response time of the drain current of the NMOS driver following the rotation speed of the encoding medium 40 (relative to the motor rotation speed). The optical encoding system 100' and 100" detects the signal frequency of the detection signal related to the encoding medium 40 (which is determined by the rotation speed of the encoding medium 40) by using a frequency detector 70. The control signal I_ctrl output by the frequency detector 70 is used to turn on or off the bias current 131 in the differential amplifier 13 to adjust the response time of the driving current (i.e., the drain current) of the light source 30.

[0118] Please refer to Fig. 10A , which is a block diagram of an optical encoding system 100 ′ according to another embodiment of the present invention. Fig. 10A and Figure 3 The difference is that Fig. 10A The optical encoding system 100' also includes a frequency detector 70 that receives detection signals (here shown as the second detection signal V_sin+ and the fourth detection signal V_cos+) and determines the signal frequency accordingly, and controls the bias current 131 in the differential amplifier 13 according to the comparison result between the signal frequency and the predetermined frequency, wherein the bias current 131 can increase or decrease the bandwidth of the differential amplifier 13 to adjust the response time of the driving current of the light source 30.

[0119] In more detail, when the rotation speed of the coding medium 40 is high, the adjustment response time of the light source 30 is preferably relatively fast to increase the adjustment speed; and when the rotation speed of the coding medium 40 is low, the adjustment response time of the light source 30 is preferably relatively low to reduce the adjustment speed.

[0120] like Fig. 10A As shown, the controller 10 receives a first detection signal V_sin-, a second detection signal V_sin+, a third detection signal V_cos- and a fourth detection signal V_cos+ related to the coded medium 40 , wherein the method of generating these four detection signals has been described above and will not be repeated here.

[0121] Please refer to Fig. 10B , which is another block diagram of an optical encoding system 100' according to another embodiment of the present invention. As mentioned above, the optical encoding system 100' includes a detection voltage generating circuit 101, a differential amplifier 13, and an NMOS driver 15, wherein the output of the differential amplifier 13 is used to control the driving current of the light source 30, which has been described above and will not be described again here. The differential amplifier 13 of the optical encoding system 100' includes a bias current 131 which is controlled by a control signal I_ctrl, such as being turned on or off or increasing or decreasing. It must be noted that the implementation of the controller 10 is not limited to Fig. 10BAs shown, any circuit can be used to generate a detection voltage signal according to the first detection signal V_sin-, the second detection signal V_sin+, the third detection signal V_cos- and the fourth detection signal V_cos+ to serve as an input of the differential amplifier 13 to be compared with the reference voltage signal.

[0122] Please refer to Fig.11 , which is a block diagram of a frequency detector 70 of a light source control circuit of an optical encoding system 100' according to another embodiment of the present invention. The frequency detector 70 receives the second control signal V_sin+ and the fourth detection signal V_cos+ and generates a control signal I_ctrl for controlling the bias current 131 in the differential amplifier 13. In one embodiment, the frequency detector 70 includes a low-pass filter 71, a first comparator 72, a second comparator 73, a first trigger 74, and a second inverter 75. In another embodiment, according to the circuit configuration in the differential amplifier 13, the frequency detector 70 may not include the second inverter 75, for example, the differential amplifier 13 includes an inverter connected upstream of the bias current 131 as one of the control elements of the bias current 131.

[0123] Please also refer to Figures 12A to 12F As shown, the operation of the frequency detector 70 is described below when the phase of the second detection signal V_sin+ leads the fourth detection signal V_cos+ (eg, about 90 degrees) and the input signal is a low frequency.

[0124] The low-pass filter 71 has a cut-off frequency Fc (for example, used as a frequency threshold for determining the frequency of a signal) and is used to filter the second detection signal V_sin+, which has a signal frequency Fin. Fig. 12A As shown, it is assumed that the signal frequency Fin is less than the cut-off frequency Fc and has a peak-to-peak value of about 1 volt. Since the signal frequency Fin is less than the cut-off frequency Fc, as shown in FIG. Fig. 12B The peak-to-peak value of the filtered second detection signal V_sin+_F is substantially equal to (if the attenuation of the filter is ignored) the second detection signal V_sin+.

[0125] The first comparator 72 is used to compare the filtered second detection signal V_sin+_F with the first reference voltage CVref to output a comparison signal C_out. The first reference voltage CVref is, for example, set to the average voltage of the second detection signal V_sin+ (e.g., 2.5 volts) plus a predetermined voltage value (e.g., 0.35 volts). Fig. 12B As shown, CVref is 2.85 volts, but the present invention is not limited thereto. As long as the first reference voltage CVref is less than the peak value of the second detection signal V_sin+ to generate Fig. 12C The first reference voltage CVref can be set to any appropriate value.

[0126] like Fig. 12C As shown, when the filtered second detection signal V_sin+_F is greater than the first reference voltage CVref, a positive pulse appears in the comparison signal C_out.

[0127] The second comparator 73 is used to compare the fourth detection signal V_cos+ with the second reference voltage Vs / 2 to output a clock signal CLK. Fig.12D As shown, Vs is, for example, the voltage source voltage of the controller 10, but is not limited thereto. Fig.12D When the fourth detection signal V_cos+ is greater than the second reference voltage Vs / 2, a positive pulse of the clock signal CLK is generated.

[0128] The data input terminal D of the first trigger 74 is used to receive the comparison signal C_out, the clock input CLK_in thereof is used to receive the clock signal CLK, and the output terminal Q thereof is used to generate the first output signal F1_out, which is used to change the bandwidth of the differential amplifier 13 to adjust the response time of the driving current of the light source 30. FIG. 12C to FIG. 12D As shown, the output terminal Q of the first flip-flop 74 tracks the comparison signal C_out at the rising edge of the clock signal CLK, so the first output signal F1_out is a high level (for example, 1 volt, but not limited thereto). Fig.12E shown.

[0129] As described above, when the frequency detector 70 does not include the second inverter 75, the frequency detector 70 outputs the high-level first output signal F1_out (as the control signal I_ctrl) to the differential amplifier 13, and the frequency detector 70 may not include the OR gate 78. When the frequency detector 70 includes the second inverter 75 connected between the first trigger 74 and the differential amplifier 13, the frequency detector 70 outputs the low-level control signal I_ctrl (for example, 0 volts, but not limited thereto) to the differential amplifier 13, as shown in FIG. Fig.12F shown.

[0130] In this embodiment, when the signal frequency Fin of the second detection signal V_sin+ is lower than the cut-off frequency Fc, the control signal I_ctrl does not turn on the bias current 131. In the present invention, turning on the bias current 131 means speeding up the response time of the differential amplifier 13.

[0131] Next, the operation of the frequency detector 70 is described when the phase of the second detection signal V_sin+ leads the fourth detection signal V_cos+ (eg, by about 90 degrees) and the input signal is a high frequency.

[0132] like Fig.13AAs shown, it is assumed that the signal frequency Fin is greater than or equal to the cut-off frequency Fc and has a peak-to-peak value of about 1 volt. Since the signal frequency Fin is greater than the cut-off frequency Fc, the peak-to-peak value of the filtered second detection signal V_sin+_F will be smaller than the second detection signal V_sin+, as shown in FIG. Fig. 13B shown.

[0133] The first comparator 72 is used for comparing the filtered second detection signal V_sin+_F with the first reference voltage CVref to output a comparison signal C_out.

[0134] like Fig. 13C As shown, since the second detection signal V_sin+_F is always smaller than the first reference voltage CVref, the comparison signal C_out is substantially 0, but its value is not limited to 0.

[0135] Similarly, the second comparator 73 is used to compare the fourth detection signal V_cos+ with the second reference voltage Vs / 2 to output the clock signal CLK. Fig.13D When the fourth detection signal V_cos+ is greater than the second reference voltage Vs / 2, a positive pulse of the clock signal CLK is generated.

[0136] Similarly, the data input terminal D of the first flip-flop 74 is used to receive the comparison signal C_out, the clock input CLK_in thereof is used to receive the clock signal CLK, and the output terminal Q thereof is used to generate the first output signal F1_out. Figure 13C to Figure 13D As shown, the output terminal Q of the first flip-flop 74 tracks the comparison signal C_out at the rising edge of the clock signal CLK, so the first output signal F1_out is always at a low level (for example, 0 volts, but not limited thereto). Fig.13E shown.

[0137] As described above, when the frequency detector 70 does not include the second inverter 75, the frequency detector 70 outputs the first output signal F1_out of low level (as the control signal I_ctrl) to the differential amplifier 13. When the frequency detector 70 includes the second inverter 75 connected between the first trigger 74 and the differential amplifier 13, the frequency detector 70 outputs the control signal I_ctrl of high level (for example, 1 volt, but not limited thereto) to the differential amplifier 13, as shown in FIG. Fig.13F shown.

[0138] In this embodiment, when the signal frequency Fin of the second detection signal V_sin+ is higher than the cut-off frequency Fc, the control signal I_ctrl turns on the bias current 131 to accelerate the adjustment response time of the differential amplifier 13 to correspond to the faster rotation speed of the encoding medium 40 .

[0139] The above embodiment illustrates that the coding medium 40 can only rotate in one direction (i.e., the direction in which V_sin+ leads V_cos+). When the coding medium 40 can rotate in two opposite directions, so that the phase of the second detection signal V_sin+ leads or lags behind the fourth detection signal V_cos+ by about 90 degrees, in order to control the bias current 131 in the differential amplifier 13 in both directions, the frequency detector 70 further includes a first inverter 76, a second trigger 77, and an OR gate 78. Fig.11 .

[0140] When the coding medium 40 rotates in a direction such that V_sin+ leads V_cos+, the frequency detector 70 Figures 12A to 12F as well as Figures 13A to 13F , so that the first flip-flop 74 generates a first output signal F1_out to the OR gate 78 .

[0141] When the coding medium 40 rotates in a direction such that V_sin+ lags behind V_cos+, the first inverter 76 inverts the phase of the clock signal CLK to generate an inverted clock signal CLK_B. The data input terminal D of the second flip-flop 77 is used to receive the comparison signal C_out, the clock input CLK_in thereof is used to receive the inverted clock signal CLK_B, and the output terminal Q thereof is used to generate a second output signal F2_out to change the bandwidth of the differential amplifier 13 to adjust the response time of the driving current of the light source 30.

[0142] Please also refer to Figures 14A to 14F Next, the operation of the frequency detector 70 is described when the phase of the second detection signal V_sin+ lags behind the fourth detection signal V_cos+ (eg, about 90) degrees and the input signal is a low frequency.

[0143] The low-pass filter 71 has a cut-off frequency Fc and is used to filter the second detection signal V_sin+, which has a signal frequency Fin. Fig.14A As shown, assuming that the signal frequency Fin is less than the cutoff frequency Fc and has a peak-to-peak value of about 1 volt, since the signal frequency Fin is less than the cutoff frequency Fc, the peak-to-peak value of the filtered second detection signal V_sin+_F is substantially equal to the second detection signal V_sin+.

[0144] The first comparator 72 is used to compare the filtered second detection signal V_sin+_F with the first reference voltage CVref ( Fig. 14B The voltage (also shown as 2.85 volts, but not limited thereto) is used to output a comparison signal C_out.

[0145] like Fig. 14CAs shown, when the filtered second detection signal V_sin+_F is greater than the first reference voltage CVref, a positive pulse appears in the comparison signal C_out.

[0146] Similarly, the second comparator 73 is used for comparing the fourth detection signal V_cos+ with the second reference voltage Vs / 2 to output the clock signal CLK. Fig.14D The inverted clock signal CLK_B after passing through the first inverter 76 is shown.

[0147] The data input terminal D of the second trigger 77 is used to receive the comparison signal C_out, the clock input CLK_in is used to receive the inverted clock signal CLK_B, and the output terminal Q is used to generate a second output signal F2_out, which is used to change the bandwidth of the differential amplifier 13 to adjust the response time of the driving current of the light source 30. Figure 14C to Figure 14D As shown, the output terminal Q of the second flip-flop 77 tracks the comparison signal C_out at the rising edge of the inverted clock signal CLK_B, so its second output signal F2_out is a high level (for example, 1 volt, but not limited thereto). Fig.14E shown.

[0148] In this embodiment, the first trigger 74 will also operate but will only output the first output signal F1_out of a low water level.

[0149] When the phase of the second detection signal V_sin+ lags behind the fourth detection signal V_cos+ (for example, about 90 degrees) and the input signal is a high frequency, the operation mode of the frequency detector 70 is as follows: Figures 13A to 13F and Figures 14A to 14F You can understand it after reading the explanation, so I will not go into details here.

[0150] In this embodiment, the OR gate 78 is used to receive the first output signal F1_out and the second output signal F2_out. When the frequency detector 70 does not include the second inverter 75, the output of the OR gate 78 is used as the control signal I_ctrl to control the bias current 131 in the differential amplifier 13. When the frequency detector 70 includes the second inverter 75 connected between the OR gate 78 and the differential amplifier 13, the output of the second inverter 75 is used as the control signal I_ctrl.

[0151] In this embodiment, when the signal frequency Fin of the second detection signal V_sin+ is lower than the cutoff frequency Fc, the control signal I_ctrl (i.e., the first output signal F1_out, the second output signal F2_out, the inverted first output signal or the inverted second output signal) does not turn on the bias current 131; when the signal frequency Fin of the second detection signal V_sin+ is higher than or equal to the cutoff frequency Fc, the control signal I_ctrl turns on the bias current 131 to accelerate the adjustment response time of the differential amplifier 13 corresponding to the encoding medium 40 with a faster rotation speed.

[0152] In addition, the present invention can also control different current values ​​of the bias current 131 according to different rotation speeds of the encoding medium 40. Fig.15 , which is a block diagram of an optical encoding system 100" according to yet another embodiment of the present invention. Fig.15 Its Fig. 10A The difference is that Fig.15 The optical encoding system 100" includes a plurality of frequency detectors (for example, a first frequency detector 70, a second frequency detector 70' and a third frequency detector 70", but the number is not limited to 3).

[0153] Each of the plurality of frequency detectors has Fig.11 The structure is used to generate control signals (such as I_ctrl1, I_ctrl2 and I_ctrl3) according to the second detection signal V_sin+ and the fourth detection signal V_cos+ to change the bandwidth of the differential amplifier 13 to adjust the response time of the driving current of the light source 30. In this embodiment, the low-pass filter of each of the plurality of frequency detectors has a respective cut-off frequency Fc, which is used as a frequency threshold compared with the signal frequency Fin of the input signal (i.e., the detection signal), and is used to generate respective control signals corresponding to different motor speeds, wherein the manner in which each frequency detector generates its own control signal is as described above, and thus will not be repeated here.

[0154] If using Fig.15 The optical encoding system 100" shown can control the differential amplifier 13 to generate six (combining three control signals) or three (not combining three control signals) adjustment response times relative to six or three motor speeds. The control signals I_ctrl1, I_ctrl2 and I_ctrl3 can control their respective bias currents respectively or control the same bias current together.

[0155] Similarly, Fig.15 An embodiment of the controller 10 is as follows Fig. 10B As shown, the detection voltage generating circuit 101, the differential amplifier 13 and the NMOS driver 15 are also included, but not limited thereto.

[0156] Please refer to Fig.16 , which is a flowchart showing the operation of the light source control circuit of the optical encoding system 100' according to an embodiment of the present invention, comprising the following steps: using a low-pass filter 71 to receive a detection signal related to the encoding medium 40 and outputting a filtered detection signal (step S161); using a first comparator 72 to compare the filtered detection signal with a first reference voltage to output a comparison signal (step S162); using a second comparator 73 to receive another detection signal related to the encoding medium 40 and compare the other detection signal with a second reference voltage to output a clock signal, wherein the phase of the detection signal leads or lags behind the other detection signal by 90 degrees (step S163); and when the phase of the detection signal leads the other detection signal, using a first trigger 71 to receive the comparison signal and the clock signal and generate a first output signal to change the bandwidth of the differential amplifier 13 to adjust the response time of the driving current of the light source 30 (step S164).

[0157] As described above, the transimpedance amplifier 60 generates a first detection signal V_sin-, a second detection signal V_sin+, a third detection signal V_cos- and a fourth detection signal V_cos+ according to the first current signal I_sin-, the second current signal I_sin+, the third current signal I_cos- and the fourth current signal I_cos+ generated by the photodetector 50. The low-pass filter 71 receives the second detection signal V_sin+ to output a filtered detection signal V_sin+_F (step S161). Then, the first comparator 72 compares the filtered detection signal V_sin+_F with the first reference voltage CVref to output a comparison signal C_out (step S162). At the same time, the second comparator 73 receives the fourth detection signal V_cos+ and compares the fourth detection signal V_cos+ with the second reference voltage Vs / 2 to output a clock signal CLK (step S163). When the phase of the second detection signal V_sin+ leads the fourth detection signal V_cos+, the first trigger 71 receives the comparison signal C_out and the clock signal CLK and generates the first output signal F1_out. Figures 12A to 12F , Figures 13A to 13F and related instructions.

[0158] When the encoding medium 40 can only detect a single direction of rotation, the first output signal F1_out or the first output signal after inversion by the second inverter 75 is used as the control signal I_ctrl.

[0159] However, when the second detection signal V_sin+ lags behind the fourth detection signal V_cos+ due to the different rotation of the coding medium 40, the first inverter 76 inverts the clock signal CLK to generate an inverted clock signal CLK_B. Then, the second flip-flop 77 receives the comparison signal C_out and the inverted clock signal CLK_B and generates a second output signal F2_out. Figures 14A to 14F and its description.

[0160] Next, the OR gate 78 receives the first output signal F1_out and the second output signal F2_out. It should be noted that the first flip-flop 74 and the second flip-flop 77 can operate simultaneously, but only one of them will output a high-level output signal at a low input signal frequency.

[0161] As mentioned above, when the light source control circuit does not include the second inverter 75, the output signal of the OR gate 78 is used as the control signal I_ctrl to change the bandwidth of the differential amplifier 13 to adjust the response time of the driving current of the light source 30. When the light source control circuit includes the second inverter 75, the second inverter 75 inverts the output signal of the OR gate 78, and the inverted signal is used as the control signal I_ctrl.

[0162] As mentioned earlier, in Fig.11 Under the architecture, when the signal frequency Fin of the second detection signal V_sin+ is lower than the cut-off frequency Fc of the low-pass filter 71, the first output signal F1_out or the second output signal F2_out does not turn on the bias current 131; when the signal frequency Fin of the second detection signal V_sin+ is higher than or equal to the cut-off frequency Fc of the low-pass filter 71, the first output signal F1_out or the second output signal F2_out turns on the bias current 131.

[0163] It must be pointed out that although Figure 10A to Figure 10B , Fig.11 and Fig.15 The display frequency detector 70 generates the control signal I_ctrl according to the second detection signal V_sin+ and the fourth detection signal V_cos+, but the present invention is not limited thereto. In other embodiments, the frequency detector 70 generates the control signal I_ctrl according to the first control signal V_sin- and the third detection signal V_cos-. That is, one of the input signals of the frequency detector 70 is a sine voltage signal and the other is a cosine voltage signal.

[0164] It must be pointed out that although Figure 12A to Figure 12B , Figures 13A to 13B and Figure 14A to Figure 14B The detection signal is shown as a sine wave, but the present invention is not limited thereto. Depending on the different configurations of the slits on the coding medium 40, the detection signal may have other waveforms.

[0165] It must be noted that, in the above embodiment, although the frequency detector 70 is described as including a low-pass filter 71, the present invention is not limited thereto. In other embodiments, the frequency detector 70 may include a high-pass filter or a band-pass filter to replace the low-pass filter, so that when the filtered detection signal input to the first comparator 72 is within or outside the predetermined signal frequency range, the comparison signal can generate or not generate a positive pulse, which can be used as the data input of the trigger. For example, when a high-pass filter is used, the frequency detector 70 does not include the second inverter 75.

[0166] When necessary, the control signal I_ctrl output by the frequency detector 70 may also be used to control other components in the optical encoding systems 100 ′ and 100 ″ except the differential amplifier 13 .

[0167] In summary, the conventional light source control circuit is affected by dark current leakage and reflected light leakage and cannot accurately control the brightness of the light source. Therefore, the present invention further provides a light source control circuit ( Fig. 9 ) and optical coding systems ( Figure 1 ), which eliminates the common mode voltage of the detection signal through a square circuit and then compares the detection voltage signal with the desired control voltage. Since the DC offset has been eliminated in the differential operation and the desired control voltage also changes synchronously according to environmental changes, the driving current of the power supply can be effectively stabilized.

[0168] Although the present invention has been disclosed through the above examples, they are not intended to limit the present invention. Any person skilled in the art with ordinary knowledge in the art to which the present invention belongs can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the appended claims.

Claims

1. A light source control circuit of an optical encoding system, the optical encoding system comprising an encoding medium and a light source, the light source control circuit comprising: a controller for receiving a first detection signal, a second detection signal, a third detection signal, and a fourth detection signal associated with the coded media, and comprising a differential amplifier for controlling a driving current of the light source, wherein a phase of the second detection signal leads the fourth detection signal by 90 degrees; and A frequency detector, the frequency detector is used to receive the second detection signal and the fourth detection signal, and comprises: a low-pass filter, the low-pass filter being used for filtering the second detection signal and having a cut-off frequency; A first comparator, the first comparator being used to compare the filtered second detection signal with a first reference voltage to output a comparison signal; a second comparator, the second comparator being used for comparing the fourth detection signal with a second reference voltage to output a clock signal; and A trigger, wherein the data input terminal of the trigger is used to receive the comparison signal, the clock input terminal of the trigger is used to receive the clock signal, and the output terminal of the trigger is used to generate an output signal to change the bandwidth of the differential amplifier to adjust the response time of the driving current of the light source. 2 . The light source control circuit according to claim 1 , wherein the frequency detector further comprises an inverter connected between the trigger and the differential amplifier.

3. The light source control circuit according to claim 1, wherein the differential amplifier comprises a bias current for changing the bandwidth, When the signal frequency of the second detection signal is lower than the cut-off frequency, the output signal does not turn on the bias current, and When the signal frequency of the second detection signal is higher than the cut-off frequency, the output signal turns on the bias current.

4. The light source control circuit according to claim 3 further comprises another frequency detector for generating another output signal according to the second detection signal and the fourth detection signal to change the bandwidth of the differential amplifier to adjust the response time, wherein another cutoff frequency of another low-pass filter of the another frequency detector is different from the cutoff frequency of the low-pass filter.

5. The light source control circuit according to claim 1, wherein: The first reference voltage is the average voltage of the second detection signal plus a predetermined voltage value, and The first reference voltage is smaller than a peak value of the second detection signal. 6 . The light source control circuit according to claim 1 , wherein the second reference voltage is half of a voltage source voltage of the controller. 7 . The light source control circuit according to claim 1 , wherein the second detection signal is a sinusoidal voltage signal and the fourth detection signal is a cosine voltage signal.

8. A light source control circuit of an optical encoding system, the optical encoding system comprising an encoding medium and a light source, the light source control circuit comprising: a controller, the controller being used to receive a first detection signal, a second detection signal, a third detection signal and a fourth detection signal associated with the coded medium, and comprising a differential amplifier, the differential amplifier being used to control a driving current of the light source, wherein a phase of the second detection signal leads or lags behind the fourth detection signal by 90 degrees; A frequency detector, the frequency detector is used to receive the second detection signal and the fourth detection signal, and comprises: a low-pass filter, the low-pass filter being used for filtering the second detection signal and having a cut-off frequency; A first comparator, the first comparator being used to compare the filtered second detection signal with a first reference voltage to output a comparison signal; a second comparator, the second comparator being used for comparing the fourth detection signal with a second reference voltage to output a clock signal; a first trigger, wherein a data input terminal of the first trigger is used to receive the comparison signal, a clock input terminal of the first trigger is used to receive the clock signal, and an output terminal of the first trigger is used to generate a first output signal when the phase of the second detection signal leads the fourth detection signal so as to change the bandwidth of the differential amplifier to adjust the response time of the driving current of the light source; A first inverter, the first inverter being used to invert the phase of the clock signal; and A second trigger, whose data input terminal is used to receive the comparison signal, whose clock input terminal is used to receive the inverted clock signal, and whose output terminal is used to generate a second output signal when the phase of the second detection signal lags behind the fourth detection signal to change the bandwidth of the differential amplifier to adjust the response time.

9. The light source control circuit according to claim 8, wherein the frequency detector further comprises: an OR gate, the OR gate being configured to receive the first output signal and the second output signal; and A second inverter is connected between the OR gate and the differential amplifier.

10. The light source control circuit according to claim 8, wherein the differential amplifier comprises a bias current for changing the bandwidth, When the signal frequency of the second detection signal is lower than the cut-off frequency, the first output signal or the second output signal does not turn on the bias current, and When the signal frequency of the second detection signal is higher than the cut-off frequency, the first output signal or the second output signal turns on the bias current.

11. The light source control circuit according to claim 10 further comprises another frequency detector for generating another output signal according to the second detection signal and the fourth detection signal to change the bandwidth of the differential amplifier to adjust the response time, wherein another cutoff frequency of another low-pass filter of the another frequency detector is different from the cutoff frequency of the low-pass filter.

12. The light source control circuit according to claim 8, wherein: The first reference voltage is the average voltage of the second detection signal plus a predetermined voltage value, and The first reference voltage is smaller than a peak value of the second detection signal. 13 . The light source control circuit according to claim 8 , wherein the second reference voltage is half of a voltage source voltage of the controller. 14 . The light source control circuit according to claim 8 , wherein the second detection signal is a sinusoidal voltage signal and the fourth detection signal is a cosine voltage signal.

15. An operating method of a light source control circuit of an optical encoding system, the optical encoding system comprising an encoding medium and a light source, the light source control circuit comprising a differential amplifier, a low-pass filter, a first comparator, a second comparator and a first trigger, the operating method comprising: receiving a detection signal associated with the encoded media with the low-pass filter and outputting a filtered detection signal; comparing the filtered detection signal with a first reference voltage using the first comparator to output a comparison signal; The second comparator receives another detection signal related to the coded medium and compares the other detection signal with a second reference voltage to output a clock signal, wherein: The phase of the detection signal leads or lags behind the other detection signal by 90 degrees; as well as When the phase of the detection signal leads the other detection signal, the first trigger receives the comparison signal and the clock signal and generates a first output signal to change the bandwidth of the differential amplifier to adjust the response time of the driving current of the light source.

16. The operating method according to claim 15, wherein the light source control circuit further comprises a first inverter and a second trigger, and when the phase of the detection signal lags behind the other detection signal, the operating method further comprises: Inverting the clock signal using the first inverter; and The second flip-flop receives the comparison signal and the inverted clock signal and generates a second output signal to change the bandwidth of the differential amplifier to adjust the response time.

17. The operating method according to claim 16, wherein the light source control circuit further comprises an OR gate and a second inverter connected between the OR gate and the differential amplifier, and the operating method further comprises: receiving the first output signal and the second output signal by the OR gate; and The output signal of the OR gate is inverted by the second inverter.

18. The operating method according to claim 15, wherein the light source control circuit further comprises a second inverter connected between the first trigger and the differential amplifier, and the operating method further comprises: The first output signal is inverted by the second inverter.

19. The operating method of claim 15, wherein the low pass filter has a cutoff frequency and the differential amplifier comprises a bias current for changing the bandwidth, the operating method further comprising: When the signal frequency of the detection signal is lower than the cut-off frequency, the first output signal does not turn on the bias current, and When the signal frequency of the detection signal is higher than the cut-off frequency, the first output signal turns on the bias current.

20. The operating method according to claim 19, wherein the signal frequency of the detection signal is determined by a rotation speed of the encoding medium.

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