Configure a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm

Abstract

Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes: parsing sequential FHE logic gate code; transforming the FHE logic gate code into a set of code modules, each code module in the set of code modules having an input and an output that is a function of the input and not passing control to other functions; creating node wrappers around each code module; configuring at least one of the main processing cores to implement an equivalent logic element of each element in a streaming mode of operation, wherein a data stream flowing out of a corresponding arithmetic logic unit flows into main memory and into other arithmetic logic units among a plurality of arithmetic logic units.

Description

[0001] Related patent application materials

[0002] This application is a partial continuation application of a U.S. application with application number 15 / 970,915 filed on May 4, 2018. This application claims the priority of a U.S. provisional application with application number 62 / 883,967 filed on August 7, 2019. The entire disclosure of the above patent applications is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a system and method for configuring a reduced instruction set computer processor architecture to execute a fully homomorphic encryption algorithm in a streaming mode. Background Art

[0004] In the past several years, computing requirements have changed significantly. Since the 1980s, computer processor design has focused on optimizing processors to execute very large amounts of computer code. For example, Microsoft Office, a popular office suite, is estimated to have tens of millions of lines of code. However, the size of the data manipulated by these large code bases is relatively small. For example, in most cases, all the data manipulated by the code base is just a few megabytes of Word documents. Other applications, such as graphics processing applications, also have the same imbalance of using large code bases to manipulate relatively small working sets of data when generating large amounts of data. Therefore, the design of conventional graphics processors often is based on techniques similar to those of processors for more code-intensive applications.

[0005] In the processor design on which complex instruction set computing (CISC) processors are based, a single instruction can execute several low-level operations (such as loading from memory, arithmetic operations, and memory storage), or can perform multi-step operations or addressing modes within a single instruction. CISC processors are characterized by each instruction having many clock cycles, a slow overall clock due to the large amount of circuitry required to implement each complex instruction, and a single control thread, so CISC processors are characterized as control-centric. As mentioned herein, the term "control-centric" refers to a processor that mainly relies on fetching and executing instructions for processing and moving data. In most applications, moving data is the most resource-consuming operation.

[0006] More recently, Reduced Instruction Set Computer (RISC) processors have become popular. A RISC processor is one whose instruction set architecture has a set of properties that allow it to have a much simpler circuit required to implement its instructions, and thus each instruction has fewer cycles than a Complex Instruction Set Computer. Processors with a small set of simple and general instructions that run faster usually have higher efficiency compared to processors with a large set of complex and specialized instructions that run slower. RISC processors are characterized by having relatively few clock cycles per instruction, a fast clock, a single clock thread, and RISC processors are characterized as control-centered.

[0007] Due to the requirement that the processor must run a very large instruction code base, RISC processors have been optimized with multi-level memory caches backed by an even larger Double Data Rate (DDR) DRAM memory. From the perspective of clock cycle access, smaller memory caches are faster than large DRAMs. Since the code exhibits "locality of calls", i.e., the likelihood that the next instruction to be executed in the code base is relatively close (distance defined by its address), the DRAM holds most of the executable code, and the specific code to be executed is loaded from the DRAM into the memory cache so that the next instruction to be accessed can be directly obtained in the cache with a high probability. Although this multi-level cache system is excellent at accelerating the execution of large code bases, it fails when moving large amounts of data.

[0008] Modern RISC processor designs consist of multiple levels of caches. For large executable code bases, this allows flexibility in the instruction stream, but it is not efficient for large amounts of data. Moving data in and out of the cache is relatively slow, maintaining cache coherence across all levels of caches and memory requires additional circuit overhead, and it requires a large amount of energy. Such a "penalty effect" is acceptable when a set of instructions is fetched from the DRAM and executed multiple times from the cache, but it is very inefficient for data movement. Data that only needs to be processed once still has to go through the cache overhead of the cache (additional power consumption, additional circuits that mean a slower clock speed, and multiple copies in multiple caches).

[0009] The data movement penalty effect is characteristic of modern processor architectures including Graphics Processing Units (GPUs). The multi-core design of processors and GPUs replicates caches for each individual processor core, which only exacerbates the penalty effect in terms of performance and power consumption when using these traditional architectures to solve problems that require a large amount of data movement. Recent developments in computing technologies such as Fully Homomorphic Encryption (FHE), Artificial Intelligence (AI), Deep Learning (DL), Machine Learning (ML), Machine Intelligence (MI), and Neural Networks (NN) require vast amounts of computing resources, with the overall combined performance of the required number of processor cores measured in TeraOperations or TeraFLOPS per second and power consumption measured in units of 100 watts.

[0010] It is well known that data is encrypted using various encryption algorithms to secure the data during transmission and storage. However, generally speaking, the encrypted data must be decrypted in order to process the data. This means that the data is insecure at least within the time window during which the data is being processed. During this time window, the unencrypted data may be copied or tampered with by an attacker. For this reason, it is not common to process data in cloud-based environments and other potentially insecure environments for data that requires a very high level of security.

[0011] Recently, the concept of "Fully Homomorphic Encryption" (FHE), an encryption scheme that can perform arbitrary functions on encrypted data without decryption (e.g., for given encryptions E(m1) … E(mt) of m1 … mt, it can efficiently compute a compact ciphertext of the encryption f(m1 … mt) for any computable function f). In other words, after decryption, the result of the function applied to the encrypted data will be the same as the result of the corresponding function applied to the decrypted input data. For example, the document "Fully Homomorphic Encryption Scheme", Craig Gentry, September 2009, teaches such an encryption scheme. However, since FHE algorithms are implemented by a complex set of control-centric instruction modules that operate as sequential code and call other modules that also operate as sequential code, FHE algorithms have not yet become widely feasible. Therefore, for the reasons listed above, the practical use of FHE algorithms typically requires a level of computing resources that is not easily achievable based on conventional processor technologies.

[0012] For example, TFHE is an open-source software library for FHE processing. TFHE is distributed under the terms of the Apache 2.0 license. The conference paper "Faster Fully Homomorphic Encryption: Bootstrapping in Less Than 0.1 Seconds" from the IACR conference Asiacrypt 2016, by Ilaria Chillotti, Nicolas Gama, Mariya Georgieva, and Malika Izabachène, describes the underlying scheme of TFHE. TFHE is a C / C++ software library that allows for FHE evaluation of any Boolean circuit composed of binary gates and encrypted data using a gate-by-gate bootstrapping procedure. TFHE supports homomorphic evaluation of 10 binary gates (AND, OR, XOR, NAND, NOR, etc...) as well as negation gates and multi-channel gates.

[0013] The software library implements a ring variant of the GSW cryptosystem. It also implements a specialized fast Fourier transform (FFT) for the anti-cyclic ring and vectorizes the instructions using AVX components. The default parameter set achieves 110-bit cryptographic security based on the ideal lattice assumption. The software library interface can be used for the implementation of conventional C code.

[0014] Since the FFT function is crucial in FHE, a specialized FFT processor is required to run TFHE. FHE is indeed notoriously difficult to implement. Due to the huge computational requirements of FHE, tasks that typically take only a few milliseconds in unencrypted form often take hours when processed in FHE form. The huge computational requirements of FHE are mainly due to the for loops in the FHE code. For each encrypted Boolean gate operation:

[0015] ● There are 500 iterations of the ring,

[0016] ● There are five steps in each ring iteration,

[0017] ● One step consists of four 1024-point IFFTs, and

[0018] ● Another step consists of two 1024-point FFTs.

[0019] This results in 3000 IFFTs / FFTs in each encrypted Boolean gate operation. In addition, since each ring iteration contains five steps, these five steps cannot be pipelined in a conventional processor architecture but must be executed serially. Also, each of these 500 iterations must be executed serially. This results in 2500 steps that must be executed serially. This poses a huge computational burden when using conventional processing architectures and technologies. Summary of the Invention

[0020] The embodiments described herein include creating a data - centric streaming topology obtained from a TFHE function. When transformed into a streaming topology in the manner described herein, the TFHE function can be implemented with far fewer computational resources. In other words, the methods and apparatuses disclosed herein enable a computer to operate in a more efficient manner in terms of being able to implement the FHE algorithm in a significantly faster and more practical way.

[0021] One aspect of the disclosed embodiments is a method for configuring a reduced instruction set computer processor architecture to process a discrete Fourier transform (DFT) of a finite - length sequence N, where the computer processor architecture includes a plurality of main processing cores defined by a RISC processor, each main processing core including a main memory, at least one cache memory, and a plurality of arithmetic logic units, each main core having an associated node wrapper, the node wrapper including access memories associated with each arithmetic logic unit, load / store matrices associated with each arithmetic logic unit, the method comprising: (a) applying a decimation - in - frequency algorithm to the DFT to decompose the DFT of the finite - length sequence N into two derived DFTs of respective N / 2 lengths; (b) constructing equivalent logic elements for each stage of the derived DFTs, the inputs and outputs of the constructed equivalent logic elements being composed of real and imaginary components; (c) repeating (a) and (b) for each stage of the DFT, except for the endpoint stages of the DFT; (d) for each endpoint stage of the DFT, constructing equivalent logic elements for the corresponding stage of the derived DFTs, the inputs and outputs of the constructed equivalent logic elements being composed only of real components; (e) configuring at least one main core of the computer processor architecture to implement the equivalent logic elements of each stage of the DFT in a stream - mode operation, where the data stream flowing out of a corresponding arithmetic logic unit flows into the main memory and other arithmetic logic units among the plurality of arithmetic logic units; and (f) configuring the computer processor architecture to couple the output of each stage of the DFT to the input of the subsequent stage.

[0022] Another aspect of the disclosed embodiments is a method for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology, wherein the computer processor architecture includes a plurality of main processing cores defined by a RISC processor, each main processing core including a main memory, at least one cache memory, and a plurality of arithmetic logic units, each main core having an associated node wrapper, the node wrapper including access memory associated with each arithmetic logic unit, a load / unload matrix associated with each arithmetic logic unit, the method including: parsing sequential FHE logic gate code; transforming the FHE logic gate code into a set of code modules, each code module in the set of code modules having an input and an output that is a function of the input and not passing control to other functions; creating a node wrapper around each code module; configuring at least one of the main processing cores in the main processing cores to implement an equivalent logic element of each element in a streaming mode of operation, wherein a data stream flowing out of a corresponding arithmetic logic unit flows into the main memory and other arithmetic logic units among the plurality of arithmetic logic units.

[0023] Another aspect of the disclosed embodiments is a computer processor architecture for processing a discrete Fourier transform (DFT) of a finite length sequence N, wherein the computer processor architecture includes: a plurality of main processing cores defined by a RISC processor, each main processing core including a main memory, at least one cache memory, and a plurality of arithmetic logic units, each main core having an associated node wrapper, the node wrapper including access memory associated with each arithmetic logic unit, a load / unload matrix associated with each arithmetic logic unit; wherein a plurality of stages of the DFT are constructed by the following steps: (a) applying a frequency domain decimation algorithm to the DFT to decompose the DFT of the finite length sequence N into two derived DFTs each of length N / 2, (b) constructing an equivalent logic element for each stage of the derived DFT, the input and output of the constructed equivalent logic element consisting of real and imaginary components, (c) repeating (a) and (b) for each stage of the DFT, except for the end stages of the DFT, (d) for each end stage of the DFT, constructing an equivalent logic element for the corresponding stage of the derived DFT, the input and output of the constructed equivalent logic element consisting only of real components; wherein at least one main core of the computer processor architecture is configured to implement the equivalent logic element of each stage of the DFT in a streaming mode of operation, wherein a data stream flowing out of a corresponding arithmetic logic unit flows into the main memory and other arithmetic logic units among the plurality of arithmetic logic units; and wherein the computer processor architecture is configured to couple the output of each stage of the DFT to the input of a subsequent stage.

[0024] Another aspect of the disclosed embodiments is a computer processor architecture for performing fully homomorphic encryption (FHE) logic gates as a streaming topology, where the computer processor architecture includes: a plurality of main processing cores defined by RISC processors, each main processing core including a main memory, at least one cache memory, and a plurality of arithmetic logic units, each main core having an associated node wrapper, the node wrapper including access memory associated with each arithmetic logic unit, a load / unload matrix associated with each arithmetic logic unit; where sequential FHE logic gate code is transformed into a set of code modules, each code module in the set of code modules having an input and an output that is a function of the input and not passing control to other functions, and a node wrapper is created around each code module; and where at least one of the main processing cores is configured to implement an equivalent logic element for each element in a streaming mode of operation, where the data stream flowing out of the corresponding arithmetic logic unit flows into the main memory and other arithmetic logic units among the plurality of arithmetic logic units.

[0025] After referring to the accompanying drawings and reading the following detailed description and the appended claims, these and other features and characteristics of the technical solutions of the present application, its operation methods and the functions of related structural elements, the combination of structural components and manufacturing steps, will become more easily understood. All of these form a part of this specification, where like reference numerals in the various drawings represent corresponding components. However, it should be clearly understood that the drawings are for illustrative and explanatory purposes only and are not intended to limit the scope of the present invention. The singular forms "a", "an", and "the" mentioned in the specification and claims also include the meaning of a plurality of referents unless the context clearly dictates otherwise.

[0026] Brief Description of the Drawings

[0027] Figure 1 Is a schematic diagram of a processor architecture according to one or more embodiments.

[0028] Figure 2a Is a schematic diagram of a single RISC processor and related hardware showing the data flow in both control mode and streaming mode.

[0029] Figure 2b Is a schematic diagram of a processor architecture showing a kernel mode that can be dynamically and flexibly configured.

[0030] Figure 3 Is a flowchart of a pipeline of a processor architecture in streaming transfer mode according to one or more embodiments.

[0031] Figure 4 Is a schematic diagram of a secondary core in streaming mode according to one or more embodiments.

[0032] Figure 5 Schematic diagram of a specific topology of a co - core according to one or more embodiments.

[0033] Figure 6 Flowchart of a method for configuring an architecture according to one or more embodiments.

[0034] Figure 7 Schematic diagram of a SegNet architecture.

[0035] Figure 8 Flowchart of a data flow that is part of a SegNet embodiment.

[0036] Figure 9 Schematic diagram of a compressed data structure.

[0037] Figure 10 Flowchart of an embodiment of an XEncoder.

[0038] Figure 11 Flowchart of an embodiment of a ZMac.

[0039] Figure 12 Shows a top - level topology obtained from the bootsAND function in a TFHE library for fully homomorphic encryption according to one or more embodiments.

[0040] Figure 13 Shows a bootsAND top - level topology that utilizes partial unfolding of the tfhe_MuxRotate_FFT loop according to one or more embodiments.

[0041] Figure 14 Shows a top - level topology obtained from the tGswFFTExternMulToTLwe function according to one or more embodiments.

[0042] Figure 15 Graphically shows how frequency extraction according to one or more embodiments can be used to decompose an N = 8 - point DFT into two N / 2 = 4 - point DFTs.

[0043] Figure 16 Flowchart of a frequency - extraction decomposition that decomposes an 8 - point DFT into four 2 - point DFTs according to one or more embodiments.

[0044] Figure 17 Basic flowchart of an FFT butterfly structure.

[0045] Figure 18 Logical element diagram of an FFT butterfly function according to one or more embodiments.

[0046] Figure 19illustrates the Figure 18 butterfly function mapped to the physical cores of a streaming topology according to one or more embodiments.

[0047] Figure 20 Is a flowchart of decimation-in-time (DIT) that decomposes an N = 8-point DFT into two N / 2 = 4-point calculations according to one or more embodiments.

[0048] Figure 21 Is a flowchart of decimation-in-time that decomposes an N = 8-point DFT into four 2-point calculations according to one or more embodiments.

[0049] Figure 22 Illustrates an illustration of the input butterfly operation for a single stage according to one or more embodiments.

[0050] Figure 23 illustrates the Figure 22 logic element illustration of the butterfly operation according to one or more embodiments.

[0051] Figure 24 illustrates the Figure 23 logic elements mapped to the cores of the streaming topology described herein according to one or more embodiments.

[0052] Figure 25 Illustrates polynomial multiplication showing coefficient representation and point-value pair representation according to one or more embodiments.

[0053] Figure 26 Illustrates an equivalent simplified logic flow according to one or more embodiments.

[0054] Figure 27 Illustrates a first-stage streaming topology according to one or more embodiments.

[0055] Figure 28 Illustrates a special last-stage streaming topology according to one or more embodiments.

[0056] Figure 29 Illustrates the last stage of an optimized IFFT in simplified form according to one or more embodiments.

[0057] Figure 30 Illustrates the last-stage streaming topology mapped to the cores according to one or more embodiments.

[0058] Figures 31A - 31D Illustrates the entire FFT mapped to the cores according to one or more embodiments.

[0059] Figures 32A - 32D Illustrates the entire IFFT mapped to the cores according to one or more embodiments. DETAILED DESCRIPTION

[0060] The inventors have developed an architecture and method that allows a processor core, such as a known RISC processor, to be used to increase computing power. A processor core, herein referred to as a "master core", is split into control logic elements and simple processing elements, such as arithmetic logic units. A node wrapper allows the architecture to be configured into a flow mode ("fragmentation mode") in which a pipeline can be defined and data can be streamed directly to execution units / processing elements that are "slave cores". The applicant refers to the slave cores using the trade name "Fractal CoresTM". In the flow mode, the control logic of the processor is not used. The slave cores are independently addressable, and the need to store data in a temporary storage device is reduced as data is streamed from one point to another in the pipeline. The architecture is scalable on chips, motherboards, and racks.

[0061] Figure 1 An example of a computing architecture is shown. As shown in Figure 1 the architecture 102 includes a plurality of master processing cores 108a, 108b... 108n. As described in more detail below, each master processing core 108 may include corresponding node wrappers 110a, 110b... 110n (only some of these corresponding node wrappers are labeled in Figure 1 for clarity). Each master processing core 108 may be defined by a RISC processor such as an "Altera NIOS TM " processor. As a non-limiting example, each master processing core 108 may include corresponding main memories 112a, 112b... 112n having a plurality of caches (only some of these corresponding main memories are labeled in Figure 1 for clarity). The node wrapper 110 may include access memories associated with each slave core, and load / unload matrices associated with each slave core. Each master processing core 108 may also include a set of processing units 114a, 114b... 114n, such as arithmetic logic units (ALUs), that may independently or jointly define the slave processing cores described in detail below.

[0062] A "wrapper" is generally referred to as hardware or software that houses ("wraps around them") other hardware, data, or software so that the contained elements can exist in a newer system. The wrapper provides a new interface to the existing elements. In an embodiment, the node wrapper provides a configurable interface that can be configured to allow execution in a conventional control-centric mode, or in a flow mode, or in a fragmentation mode, as described below.

[0063] In a conventional control-centric mode (RISC mode), the architecture uses kernel control logic to control the data flow and operates in such a way that data is read from and written to the cache memory, and the data is processed by the main kernel according to the control logic. However, as described in more detail below, as part of the pipeline, the co-kernel 114 can be selectively "fragmented" to operate in a fragmentation mode, in which the data flow flowing out of the corresponding co-kernel flows into the main memory and into other co-kernels among the multiple co-kernels, and the data flow flowing out of the main memory and other co-kernels flows into the corresponding kernel. For example, rectangular partitions can be created from the result matrix y using single-precision floating-point arithmetic.

[0064] The node wrapper 110 can be configured to partition the logic components and the input state machine for transferring data from the memory to the processing element, and each arithmetic logic unit has an output associated with the output memory. During the entire processing, the output memory can be updated with the latest sum value during the calculation. The arithmetic logic unit 114 of the RISC processor can be used as a streaming co-kernel in the streaming mode. Each node wrapper 110 can be configured to define multiple hardware streams for a specific multiple of kernels to be assigned to the kernels, i.e., the pipeline.

[0065] Figure 2a Two possible operating modes of the architecture are shown, namely the RISC mode and the fragmentation mode. As Figure 2a shown, the RISC processor 208 includes two processing elements, ALU1 and ALU2. The node wrapper 210 includes two co-node wrappers NW0 and NW1. The memory 212 includes co-memories M0 and M1. In the RISC mode, the data flow indicated by the solid line flows from the on-chip network (NOC) such as the PCIe bus to the memory 112 to be processed by the RISC processor 208. In the fragmentation mode, the flow is indicated by the dashed line. In the fragmentation mode, the node wrapper 210 is used as the co-node wrappers NW0 and NW1, and the memory 212 is used as the co-memories M0 and M1 to define two data flows in this instance. One data flow passes through ALU1 and the other data flow passes through ALU2, where ALU1 and ALU2 each define a co-kernel. Of course, the RISC processor can have any number of processing elements, and the data flow can be configured as needed. Note that in this instance, the RISC mode includes four data flows and a relatively large memory, while the fragmentation mode includes two data flows and a relatively small memory.

[0066] As in Figure 2bAs schematically shown, some of the cores of the architecture can be configured to operate in RISC mode, while some other cores of the architecture can be configured to operate in fragmented mode, as required by any specific application at any particular time. Additionally, the core mode can be dynamically configured in real time during execution. In Figure 2b the left side of Figure 2b , all cores are configured as primary cores (RISC mode). In

[0067] ● 112 RISC cores / 1480 fragmented (FC) cores: Each 1U server has 896 RISC cores / 12K FC cores, and each rack has 36K RISC cores / 474K FC cores

[0068] ● 480 RISC cores / 7420 FC cores: Each 1U server has 4K RISC cores / 60K FC cores, and each rack has 154K RISC cores / 2.4M FC cores

[0069] ● 8196 RISC cores / 131136 FC cores: Each 1U server has 66K RISC cores / 1M FC cores, and each rack has 2.6M RISC cores / 42M FC cores

[0070] See Figure 1 , various interconnection devices are configured by the node wrapper using a Network-on-Chip (NOC). In this instance, the NOC is a two-layer NOC where the L0 switch is interconnected to the L1 switch via 64-bit channels. The NOC also has an overlay network that interconnects all the secondary cores in a linear fashion, as shown by the red arrows in Figure 1 . In this instance, the switch is a "crossbar" switch, i.e., a collection of switches arranged in a matrix configuration. Each switch can have multiple input lines and output lines that form a cross pattern of interconnecting lines, and connections can be established between the interconnecting lines by closing the switches located at each cross point (the elements of the matrix). In this instance, the PCI Express (PCIe) bus interface is used. PCIe provides a switching architecture where channels can be combined in ×2, ×4, ×8, ×16, and ×32 configurations, thus creating a parallel interface of independently controlled "lanes".

[0071] In some embodiments, the architecture may be formed on a single chip. Each cache memory may be a node memory including multiple small memories. In some embodiments, each core may have multiple arithmetic logic units. In some embodiments, as a non-limiting example, the arithmetic logic unit may include at least one of the following: an integer multiplier, an integer multiplier accelerator, an integer divider, a floating-point multiplier, a floating-point multiplier accelerator, a floating-point divider. In some embodiments, the arithmetic logic unit may be a single instruction multiple data unit. As a simple example, the architecture may be composed of 500 main processing cores 108 each having 16 processing elements. In stream mode, up to 8000 secondary cores 114 may be independently addressed. This allows execution of a large number of mathematical operations as required in artificial intelligence applications. The main cores and secondary cores may be dynamically mixed to implement new algorithms.

[0072] The processes and mechanisms for configuring the architecture are described below. As pointed out above, the fragmentation mode is achieved by defining one or more pipelines for streaming data between the secondary cores. Figure 3 A simple data pipeline is shown in which four arithmetic logic units 302, 304, 306, and 308 are connected in series such that the input from source 301 is processed into output 309. The ALU is an example of the processing element that defines the secondary core as described above. The pipeline is defined by setting the switches L0 and L1 described above in the NOC. Of course, the NOC can be configured in any way to define any one or more data pipelines. One or more suitable node wrappers 110 are capable of executing code to configure the NOC. For example, Figure 2b the pipeline can be configured by executing the C++ code object shown below. Note that the keyword "threadModule" means that the code to be executed will run on a RISC core, and the keyword "streamModule" means that the code to be executed will run on a fragmented core.

[0073]

[0074]

[0075] The code below serves to connect Figure 3 the topology of the pipeline where the source and sink run on RISC cores and four fragmented cores perform MAC (multiply-accumulate):

[0076]

[0077] Figure 4Shows a top - level diagram of an instance of a secondary core 400 defined by processing elements. The pipelined configuration requires a certain number of clock cycles to read a value from the Y memory, add it to the new result value, and send it back to the Y memory before accessing the element again. Result values that arrive before the Y memory element is ready to be read are diverted to the T - FIFO for subsequent accumulation. Memory hazard logic (not shown) can be used to determine whether the location in the Y memory for the new result value has been recently used, which controls the steering of data in the design. The pre - loaded X memory (X mem) holds partitions of the X (right) matrix suitable for the partitions of the Y (result) matrix executed by this sub - core. Applicable partitions of the A (left) matrix flow into the processing element (PE) in a compressed form (only non - zero elements, accompanied by row / column information). As the matrix is computed, the Y memory (Y mem) accumulates the result values. This embodiment may also include point - to - point connections between adjacent processing elements 114 in the ring to allow the processing load of a particular Y element to be divided between two or more processing elements, which helps to make the design scalable to larger matrices without significant performance loss.

[0078] Figure 5 Shows a specific topology of the secondary core 500. The design includes a test architecture created around the processing element that allows a test matrix to be initially stored in the central memory, automatically partitioned and delivered to the processing element, run through the processing element and can be continuously repeated for the test matrix (for power measurement), and then the result partitions are collected and reassembled into a complete output matrix and then sent back to the central memory, where the operation results in the central memory can be easily accessed using the storage initialization and dump tools.

[0079] Figure 5 Each processing element 114 in [the relevant context] is associated on the input side with a node input memory, a partitioning logic component, and an input state machine for transferring data from the local memory to the processing element. On the output side, each processing element 114 is associated with an output memory that is updated with the latest sum value for each Y element during the computation throughout the process. When the matrix processing is complete, the data accumulated in the output memory is transferred back to the central access memory via a combiner that either passes data from the processing element 114 at the previous stage or uses the data from the local processing element 114 to replace the input values to reconstruct the complete matrix when scanning the matrix row - by - row and column - by - column.

[0080] The programming information and data information in the central access memory include setup words for each partition information for the processing element 114 that contains the processing element 114. The setup words configure the partition logic components located at each processing element 114 to use only the data with rows and columns associated with the partition of the processing element. Both the preloaded X matrix data and the streamed A matrix data arrive through the same path and select data from the data stream from the central memory using the same partition settings. The selected data located at each processing element 114 is written to the node input memory and held until the access manager finishes transferring the data and starts processing. When processing starts, the processing uses only the data that has been transferred to the node memory and stops when the end of the data has been reached. If the repeat bit is set in the start word, when the end of the buffered data is reached, the pointer into the node input memory will be reset to 0 and the data will be allowed to repeat indefinitely. This allows power measurements to be made.

[0081] Figure 6 Method 600 for reconfiguring a reduced instruction set computer processor architecture according to one or more embodiments is shown. The operations of method 600 presented below are intended to be exemplary. In some embodiments, method 600 may be implemented using one or more additional operations not described, and / or may be implemented without one or more of the operations discussed. Additionally, the order of operations of method 600 shown and described below is not intended to be restrictive. Figure 6 In

[0082] Operation 602 may include providing configuration code to one or more node wrappers. Operation 604 may include executing the configuration code to configure the interconnecting device of the NOC at least in a manner created on the pipeline. Operation 606 may include operating the architecture in a streaming mode, where the data stream flowing out of the corresponding secondary core flows into the main memory and into other secondary cores among the plurality of secondary cores, and the data stream flowing out of the main memory and other secondary cores flows into the corresponding core in a streaming mode or a control-centered mode.

[0083] Figure 7 and Figure 8Shows a specific instance of the architecture applied to the SegNet topology. As pointed out above, SegNet is a fully convolutional neural network (CNN) architecture for semantic pixel-level segmentation. The kernel-trainable segmentation engine consists of an encoder network, a corresponding decoder network, and a pixel-level classification layer. The architecture of the encoder network is topologically identical to the 13 convolutional layers in the VGG16 network. The role of the decoder network is to map the low-resolution encoder feature maps to full input resolution feature maps for pixel-level classification. The SegNet decoder upsamples one or more of its lower-resolution input feature maps. Specifically, the decoder uses the pooling indices calculated by the corresponding encoder's max pooling step to perform non-linear upsampling. This eliminates the need to learn upsampling. The upsampled map is sparse and is then convolved with trainable filters to produce a dense feature map.

[0084] As shown in Figure 7 , the SegNet topology 700 includes an encoder 710 and a decoder 720. The 3D CNN topology can be transformed into an equivalent 1D topology using the techniques disclosed herein. The first SegNet layer 712 can be transformed into the 77-stage fragmented kernel pipeline 800 shown in Figure 8 . The following operations are performed at the stages shown in Figure 8 :

[0085] - Padding (top), padding (bottom), padding (left), and padding (right) add zero padding around the image. No memory is required.

[0086] - The reordering stage converts the row-based video stream into a window-based stream. On-chip SRAM is accessed.

[0087] - 64 convolutional stages perform convolution for each of the 64 filters (kernels). On-chip SRAM is accessed.

[0088] - The batch normalization stage performs batch normalization. On-chip SRAM is accessed.

[0089] - The ReLU stage implements the rectified linear unit (ReLU) activation function. No memory is required.

[0090] - Three pooling stages perform max pooling. On-chip SRAM is accessed.

[0091] This embodiment is conducive to more efficient data compression. By their definition, neural networks contain a high degree of sparsity. For the SegNet CNN, more than 30% of the computations involve zero elements. Clearly, an architecture that can automatically eliminate redundant data movement for zero data and the redundant multiplication-by-zero operations for both random sparsity and non-random sparsity will result in higher performance and lower power consumption. Data that is not moved results in reduced bandwidth and power savings. Multiplication operations that do not need to be performed also save power consumption and allow the multipliers to be utilized by non-zero data. In terms of multiply-accumulate, the highest bandwidth and computational load occur in the data stream that exits the "reordering" module 801 and is fed to the "convolution" module 802. Automatically compressing the data leaving the reordering module 801 reduces the bandwidth required to be fed to the convolution module and also reduces the maximum MAC (multiply-accumulate) performed by each convolution module. There are several possible zero compression schemes that can be implemented. The one shown takes into account the nature of the convolutional neural network. The input to the convolver 802 consists of a three-dimensional data structure (width * height * channel length). Convolution is defined as summing (accumulating) the products of multiplying each element of W*H*C with a kernel weight data structure that also consists of (width * height * channel length). The data input to the convolver exhibits two types of sparsity - randomly distributed zero bits in the W*H*C data structure and short "bursts" of zero bits across consecutive (W+1)*(H+1)*C data elements. The compressed data structure sent from the reordering module to the convolver module is described in detail in Figure 9 For every 32 possible values, a bitmask value 901 is sent, followed by any non-zero data values 902. Each bit in the bitmask indicates whether there is valid data or zero data at that position. In the case where there is no zero data at that position, 901 will all be zero, followed by 32 data values 902. At the other extreme, where there are 32 zero data values at that position, 901 will all be "1" and no data values 902 will follow. In the case where there is a mixture of non-zero data values and valid data values, the bitmask 901 will indicate this situation and only the non-zero data values will follow in 902. Figure 10 Flowchart of the circuit residing in the reordering module 801 that performs compression.

[0092] Figure 11 Flowchart of the circuit residing in the convolver 802 that performs decompression. Note that the non-zero bits are crucial because the convolution operation must multiply the non-zero data with the correct kernel weights - thus a counter must be maintained ( Figure 11, steps 1 and 5). The advantages are as follows: Given a SegNet reordering / convolution with a width of 7, a height of 7, and a channel length of 64, there is no compression method to send 3136 (7 * 7 * 64) values from the reordering module 801 to each convolutional unit 802, where 3136 multiply-accumulate operations will be performed. With a 50% probability of zero values, the circuit will send 98 bitmasks and only 1568 data values. This results in nearly 50% bandwidth savings and a 50% reduction in the multiply-accumulate operation volume in 64 individual convolutional units. As an alternative, simpler compression schemes such as adding additional bits to each data value to indicate "zero" data and adding several bits to indicate the "count" of zero values can also be used to perform compression, but at the cost of increasing the bit width of the bus carrying the data values.

[0093] As seen above, the streaming topology described herein can be applied to implement FHE processing using far fewer computing resources than those required by conventional processors. FHE has very complex and computationally resource-intensive specialized logic gates. For example, the BootsAND logic gate of TFHE has two inputs (LweSample) each with 501 32-bit integers. Converting FHE logic components (such as TFHE logic components) into the streaming topology desired herein results in a much more efficient processing. The embodiments described herein include topologies obtained from three TFHE functions: (1) bootsAND, (2) tfhe_MuxRotate_FFT, and (3) tGswFFTExternMulToTLwe.

[0094] The following are the constants used in the TFHE code. They are used to calculate the sizes of data members and the for-loop limits in the streaming topology described below.

[0095] static const int32_t N = 1024;

[0096] static const int32_t k = 1;

[0097] static const int32_t n = 500;

[0098] static const int32_t bk_l = 2;

[0099] static const int32_t bk_Bgbit = 10;

[0100] static const int32_t ks_basebit = 2;

[0101] static const int32_t ks_length = 8;

[0102] static const double ks_stdev = 2.44e-5; / / Standard deviation

[0103] static const double bk_stdev = 7.18e-9; / / Standard deviation

[0104] static const double max_stdev = 0.012467; / / Maximum standard deviation for 1 / 4 msg space

[0105] Torus32 is defined as a key type used in TFHE code and in the TruStream topology:

[0106] typedef int int32_t;

[0107] typedef unsigned int uint32_t;

[0108] typedef unsigned long long uint64_t;

[0109] typedef int32_t Torus32; / / avant uint32_t

[0110] The TFHE code is divided into references ("structures"), which are composite data type declarations used to define a list of physical groupings of variables under one name. This structure can be regarded as data processed by functions. For example, the TFHEbootsAND code includes 23 structures that can be classified as 1) static / non-streaming (the data values of these types are fixed / static for a specific Boolean AND gate and can therefore be stored in SRAM) or 2) dynamic / streaming (periodic or changing data values, flowing from one core to another).

[0111] The TFHE code is expressed using C / C++, and both languages are widely used:

[0112] - new (a library function that requests memory allocation on the heap of the process)

[0113] - malloc (a library function that allocates the requested memory and returns a pointer to that memory)

[0114] - free (a library function that requests the removal of a memory allocation on the heap of the process)

[0115] - pointers.

[0116] The streaming topology described herein does not use these system functions. Instead, it uses streams. This has an impact on the 9 dynamic / streaming structures of the TFHE code when adapted for a streaming processor arrangement. The embodiment uses a mechanism to replace the pointer data members in these 9 structures with the actual arrays pointed to, because instead of passing an array pointer from one function to another, a streaming program passes / flows the actual array from one module to another. However, for conventional microprocessors, the benefits of a streaming programming model are often best achieved through streaming pointers. However, for streaming pointers of conventional processors, this arrangement is disadvantageous for the following reasons.

[0117] ●The streaming computing structure is arbitrarily scalable ●The streaming computing structure can achieve higher performance levels

[0118] ● The streaming computing structure does not have any bottlenecks of conventional microprocessors such as cache, context switching, scheduling and dispatching ● The streaming computing structure does not have "bloated" code (such as control code), and the only code running in the streaming computing structure is the application program.

[0119] Sequence code

[0120] ●Streaming computing architecture is far more efficient in terms of energy consumption and silicon asset occupancy

[0121] Therefore, the dynamic structure of the TFHE bootsAND code can be converted into the following structure that can be streamed ("S" refers to the streaming structure).

[0122]

[0123]

[0124]

[0125] The above streaming structure can be created from the original structure by, for example, the following process:

[0126] ●Determine the location of pointers in the code;

[0127] ● Backtrack the code to find the data created and the allocated data blocks pointed to by the pointers;

[0128] ● Determine the size of the allocated block;

[0129] • replacing the pointer with the data array corresponding to the allocated block; and

[0130] • Use the array as streaming data.

[0131] Figure 12Shows the top-level topology obtained from the bootsAND function for fully homomorphic encryption. Note that "housekeeping" functions such as new and delete are irrelevant in the streaming programming model. Similarly, since static function parameters such as TfheGateBootstrappingCloudKeySet, LweBootstrappingKeyFFT, and TgswParams can be stored in the memory of a suitable core of the streaming architecture such as Figure 1 in 112a, they are omitted from Figure 12 . The topology can be obtained by starting with the call stack, creating function blocks with control, and transforming function calls into modules. An example will be listed below. Starting with the tfhe_bootstrap_woKS_FFT function:

[0132]

[0133]

[0134]

[0135]

[0136] As a result, Figure 12 each box represents a streaming function module corresponding to a TFHE function, where one or more module input streams can provide data to the function, and one or more module output streams receive output data from the TFHE function. This output data is ultimately passed to another streaming function module. There is no passing of control or calls to other functions. Each streaming function module is part of the top-level BootsAND topology. This topology allows the BootsAND operation to be replicated on silicon in a way that takes advantage of parallelization and pipelining, and thus allows for much higher efficiency and performance in processing the BootsAND function.

[0137] Figure 13

[0138] Figure 13Shows the bootsAND top-level topology with a partially expanded tfhe_tfhe_blindRotate_FFT loop. In Figure 13 , there are 4 tfhe_blindRotate_FFT modules each containing a for loop with 125 iterations. In contrast, Figure 12 's bootsAND top-level topology has a single instance of the tfhe_blindRotate_FFT module which contains a for loop with 500 iterations. Of course, the bootsAND top-level topology can be further expanded to suit any specific application.

[0139] Figure 14 Shows the top-level topology obtained from the GswFFTExternMulToTLwe function.

[0140] It is necessary to determine the upper bound of the throughput of the streaming topology. The applicant has developed an algorithm for determining the upper bound of the throughput of a streaming topology for a sequence of operations: The upper bound of the throughput (in clock cycles per operation) for a streaming topology is the maximum number of data values carried on a single topology stream during a single operation. This is because the stream can transfer data values at a maximum rate of one data value per clock cycle. For each stream, the transfer of data values for one operation must be completed before the transfer of data values for the next operation can begin. Thus, the operations cannot be executed faster than one operation per N clock cycles, where N is the maximum number of data values carried on a single stream during a single operation.

[0141] For example, Figure 12 the upper bound of the throughput of the topology in Figure 13 is: (size of Ts_TlweSampleint in int32’s) * (number of loop iterations), i.e., 2048 * 500 = 1024000 clock cycles per operation. And

[0142] if Figure 12 the loop in

[0143] Table 1 summarizes the throughput values of the bootsAND function at two clock frequencies: a) 125 MHz, the clock frequency of some FPGA embodiments of the streaming topology, and b) 1 GHz, the expected clock frequency of some custom ASIC embodiments of the topology.

[0144] Table 1:

[0145]

[0146] Using the values in Table 1, we can calculate the time required to perform one thousand of the most common arithmetic operations, including addition, subtraction, minimum, maximum, and average. Table 2 shows the time required to perform one thousand of the most common arithmetic operations, including addition, subtraction, minimum, maximum, and average, using the streaming topology.

[0147] Clock cycle Milliseconds at 125 MHz Milliseconds at 1 GHz bootsAND (no expansion) 1,024,000 8,192 1,024 bootsAND (4x expansion) 256,000 2,048 256 bootsAND (fully expanded) 2,048 16 2

[0148] It can be seen that the streaming topology described herein greatly improves the efficiency of a computer in processing FHE functions. However, the core of FHE processing is the fast Fourier transform (FFT) and the inverse fast Fourier transform (IFFT). Therefore, additional efficiency can be obtained if the FFT and IFFT can be processed faster. The applicant has found that some known techniques for optimizing Fourier transforms can be used to create more efficient processing in a streaming environment.

[0149] The Fourier transform (FT) decomposes a time function into its frequency components. The Fourier transform of a time function is itself a complex-valued function of frequency, whose magnitude (modulus) represents the amount of that frequency present in the original function, and whose argument is the phase shift of the fundamental sine signal at that frequency. The Fourier transform is not limited to time functions, but the domain of the original function is usually referred to as the time domain. The inverse Fourier transform mathematically synthesizes the original function from its frequency-domain representation. Linear operations performed in one domain (time domain or frequency domain) have corresponding operations in the other domain that are sometimes easier to perform. Therefore, the Fourier transform has many applications in data processing and is crucial for some FHE embodiments.

[0150] The embodiments described herein define a new way of processing FFT and IFFT. The FFT can then be mapped to a new computational embodiment with high parallelism, such as the streaming topology described herein. In addition, the embodiments process the FFT of each polynomial, multiply term by term in the frequency domain, and then transform back to the time domain. Conventional processing uses coefficient representation (i.e., multiplying the coefficients of each term). The conventional computational cost is on the order of N2 (where N is the order of the polynomial). The method described herein results in a computational cost of approximately N × Log(N).

[0151] The embodiments described herein create a pipeline architecture that computes the FFT algorithm at specific stages at the endpoints, which computes the product of an Nth-order polynomial. This greatly reduces the computational requirements.

[0152] The discrete Fourier transform (DFT) of a finite-length sequence N is:

[0153]

[0154] where,

[0155] The inverse discrete Fourier transform is given by the following formula

[0156]

[0157] Using the decimation-in-frequency method, we can use the following formula to split the output sequence of the DFT into smaller subsequences.

[0158]

[0159] Equation (2.1) is the (N / 2)-point DFT of the (N / 2)-point sequence g[n] = x[n] + x[n+(N / 2)].

[0160]

[0161] Figure 15 Graphically shows how decimation-in-frequency is used to decompose an N = 8-point DFT into two N / 2 = 4-point DFTs by applying Equation 2.1 to the even outputs and Equation 2.2 to the odd outputs. Figure 16 The flowchart of decimation-in-frequency for decomposing an 8-point DFT into four 2-point DFTs. Note that in Figure 16 there are three columns / stages. The first column has 4 "butterfly" structures each with an input and an output. The butterfly structure of the DFT is part of the calculation that decomposes the result of a larger DFT into sub-transforms. Figure 16 Each column of

[0162] In Figure 17 shows the basic flowchart of the butterfly structure. The input to the upper branch is p, and the input to the lower branch is q. Each butterfly structure can be mapped to a logic element and thus to a series of cores in a streaming topology. Figure 18Logic element diagram for the FFT butterfly function. It can be seen that this logic structure is composed of standard logic elements (adders, multipliers, etc.). To create the flow chart, the complex input is divided into a real part and an imaginary part for calculation. The upper input / output is for the real part, while the lower input / output is for the imaginary part. The input / outputs are cross-accessed as p and q. At different levels, the p inputs and q inputs of the butterfly are selected from different addresses in the input buffer. "Fan out" and "FIFO" accomplish this address selection. The "add", "subtract", and "multiply" logic elements are used to calculate the real part and the imaginary part of the product of the complex input and the complex constant "w". At different levels, the p outputs and q outputs of the butterfly structure are placed in the output buffer at different addresses. "Fan In" accomplishes this addressing.

[0163] Figure 19 shows Figure 18 the mapping of the butterfly function of to the physical core of the streaming topology. As described above, the core contains logic elements that can be configured to represent any processing algorithm. As a result, a single butterfly structure of one stage of the FFT is mapped onto the silicon chip to define a streaming architecture for accomplishing the butterfly function. However, as discussed, processing the FFT requires many butterfly functions.

[0164] The input sequence of FFT(x[n]) can also be decomposed into smaller and smaller subsequences by applying the decimation-in-time (DIT) transform algorithm. As discussed, in the DIF algorithm, decimation is performed in the frequency domain. This is the reason why the frequency indices are arranged in bit-reversed order. In DIT, for example, we start with a single 8-point DFT and then progress to two 4-point DFTs, and finally end up with four 2-point DFTs by applying the following formula 3.1.

[0165]

[0166] Each sum value in formula (3.1) is an (N / 2)-point DFT. The first sum value is the (N / 2)-point DFT of the even points of the original input sequence, and the second sum value is the (N / 2)-point DFT of the odd points of the input sequence. Figure 20 Flow chart of the decimation-in-time (DIT) for decomposing an N = 8-point DFT into two N / 2 = 4-point calculations. Figure 21 Flow chart of the decimation-in-time for decomposing an 8-point DFT into four 2-point DFT calculations. This is achieved by continuing to divide the (N / 2)-point DFT into (N / 4)-point DFTs by applying formula 3.1 until we obtain a 2-point DFT. Figure 22 Illustration of the input butterfly operation for a single stage. Figure 23 is obtained in a manner similar to that described above regarding Figure 18 and Figure 22The logic element diagram corresponding to the butterfly structure. Figure 24 Map the above-mentioned logic structure onto the kernel of the streaming topology described in this article. Of course, the procedures described above can be used to map the logic diagram onto the kernel.

[0167] Figure 25 Shows polynomial multiplication with display coefficient representation and point-value pair representation. Figure 25 The upper side of [the figure] is the conventional method. In Figure 25 On the lower side, according to the embodiments disclosed in this article, A and B of the FFT output are point-multiplied to obtain C. Applying the results of the two methods to the inverse (interpolation) algorithm achieves the same result. Given two polynomials with order bound n and Their product C(x) = A(x)B(x) is a polynomial with order bound 2n - 1.

[0168]

[0169] where,

[0170] When we represent polynomials in point-value format, such calculations take time O(n 2 ).

[0171] c = IFFT 2n [FFT 2n (a) · FFT 2n (b)], (4.3)

[0172] where the vectors a and b are padded with 0s to length 2n, and □ represents the element-wise dot product of two element vectors of length 2n.

[0173] Considering that the elements in these vectors are real numbers (contrary to the case of complex numbers used as the standard input for FFT) and the vectors have length n and are zero-padded to length 2n, the FFT can be optimized by deploying a special first stage and (n / 2)-point FFTs, as Figure 25 shown. As a result, the first stage of the optimized FFT has a very simple equivalent logic flow, as Figure 26 shown. This results in a first-stage streaming topology as Figure 27 shown. For the same reason, a similar optimized (N / 2)-point IFFT (along with the corresponding relatively simple logic structure and streaming topology) can be used as the last stage. This specific last stage is shown in Figure 28 As a result, the last stage of the optimized IFFT has a very simple equivalent logic flow, as Figure 29 shown. This results in the last-stage streaming topology mapped to the kernel as Figure 30 shown.

[0174] In theory, to multiply two Nth-degree polynomials, an efficient way is to apply the FFT to the coefficients of each polynomial, perform pointwise multiplication on the FFT coefficients, and then perform the inverse FFT. The dimensions of the FFT and IFFT should be 2N. The coefficients of each polynomial are "zero-padded" to become vectors of dimension 2N. The product of two Nth-degree polynomials is of degree 2N - 1. In TFHE, polynomial-based modular arithmetic operations are required. After multiplying two torus polynomials, the final product (a polynomial of degree 2N - 1) is simplified to X according to the following formula N+1 modulo.

[0175] c(i) = p(i) - p(N + i), for i = 0, 1,..., N - 1

[0176] c(N - 1) = p(N - 1)

[0177] In terms of the FFT implementation, before performing the 2N-point FFT, the FFT input is adjusted using the following formula to achieve this modular operation.

[0178]

[0179] Due to this unique input structure, the decimation-in-frequency decomposition can be applied to optimize the FFT by deploying a special first stage and an (N)-point FFT. Similarly, the IFFT can be optimized by deploying an (N)-point IFFT and a special last stage. Due to the modular arithmetic operations of the polynomials in TFHE, for i = N, N + 1,..., 2N - 1, the IFFT coefficients do not need to be calculated.

[0180] The respective stages of the streaming topologies of the FFT and IFFT mentioned above can be connected to create a separate streaming topology for each of them. The result is the FFT topology shown in Figures 31A - 31D and the IFFT shown in Figures 32A - 32D . Note that Figures 31A - 31D includes a special first stage 320 and Figures 32A - 32D includes a special last stage 330. It can be seen that the FFT and IFFT processed in the above manner can be mapped to a relatively simple kernel topology in the streaming environment described herein. This allows the FFT and IFFT to be processed in the streaming environment and thus allows FHE operations to be processed in the streaming environment. As mentioned above, the streaming topology enables the computing device to operate with higher efficiency and thus reduces computing resources. It can be seen that all stages of the FFT and IFFT calculations are streaming. Conventional FFT calculations are done one stage at a time in a recursive manner. This embodiment allows all stages of the FFT and IFFT to be laid out in hardware using multiple kernels in the manner described above.

[0181] The embodiments described herein can be used in conjunction with a variety of computing platforms. The computing platform can include an electronic storage device, one or more processors, and / or other components. The computing platform can include communication lines or ports to enable information exchange with a network and / or other computing platforms. The computing platform may include multiple components of hardware, software, and / or firmware that operate together to provide the functions described herein. The electronic storage device can include a non-transitory storage medium that stores information electronically.

[0182] Although the technical solutions of the present application have been described in detail for purposes of illustration based on what are currently considered to be practical embodiments, it should be understood that such details are for that purpose only, and the technical solutions of the present application are not limited to the disclosed embodiments, but on the contrary, are intended to cover modified embodiments and equivalent embodiments within the spirit and scope of the appended claims. For example, it should be understood that for the technical solutions of the present application, it is contemplated that, to the extent possible, one or more features of any embodiment can be combined with one or more features of any other embodiment.

Claims

1. A method for configuring a reduced instruction set computer processor architecture to process a discrete Fourier transform (DFT) of a finite length sequence N, wherein the computer processor architecture includes a plurality of main processing cores defined by a RISC processor, each main processing core includes a main memory, at least one cache memory, and a plurality of arithmetic logic units, each main processor core has a node wrapper associated with the main processor core, and the node wrapper includes an access memory associated with each arithmetic logic unit and a load / store matrix associated with each arithmetic logic unit, the method comprising: (a) Applying a decimation-in-frequency algorithm to the DFT to decompose the DFT of the finite length sequence N into two derived DFTs of respective N / 2 lengths; (b) Constructing equivalent logic elements for each stage of the derived DFT, wherein the inputs and outputs of the constructed equivalent logic elements are composed of real and imaginary components; (c) Repeating (a) and (b) for each stage of the DFT except for the final stage of the DFT; (d) For each final stage of the DFT, constructing equivalent logic elements for the corresponding stage of the derived DFT, wherein the inputs and outputs of the constructed equivalent logic elements are composed only of real components; (e) Configuring at least one main processor core of the computer processor architecture to implement the equivalent logic elements of each stage of the DFT in a streaming mode of operation, wherein the data stream flowing out from a corresponding arithmetic logic unit flows into the main memory and other arithmetic logic units among the plurality of arithmetic logic units; and (f) Configuring the computer processor architecture to couple the output of each stage of the DFT to the input of the subsequent stage.

2. The method according to claim 1, wherein the logic of each stage includes a plurality of butterfly operations.

3. The method according to claim 2, wherein step (b) includes configuring the butterfly operation such that a first input / output is for the real part and a second input / output is for the imaginary part, and the input / outputs are cross-accessed as p and q, wherein at different stages, the p input and the q input of the butterfly operation are selected from different addresses in the input buffer.

4. The method according to claim 3, wherein "add", "subtract", and "multiply" logic elements are used to calculate the real and imaginary parts of the product of a complex input and a complex constant "w".

5. A computer processor architecture for processing a discrete Fourier transform (DFT) of a finite length sequence N, wherein the computer processor architecture includes: A plurality of main processing cores defined by a RISC processor, each main processing core includes a main memory, at least one cache memory, and a plurality of arithmetic logic units, each main processor core has a node wrapper associated with the main processor core, and the node wrapper includes an access memory associated with each arithmetic logic unit and a load / store matrix associated with each arithmetic logic unit; The multiple stages of the DFT are constructed through the following steps: (a) applying a frequency-domain decimation algorithm to the DFT to decompose the DFT of a finite-length sequence N into two derived DFTs each of length N / 2, (b) constructing equivalent logic elements for each stage of the derived DFTs, the inputs and outputs of the constructed equivalent logic elements being composed of real components and imaginary components, (c) repeating (a) and (b) for each stage of the DFT except for the final stage of the DFT, and (d) for each final stage of the DFT, constructing equivalent logic elements for the corresponding stage of the derived DFTs, the inputs and outputs of the constructed equivalent logic elements being composed only of real components; where at least one main processor core of the computer processor architecture is configured to implement the equivalent logic elements of each stage of the DFT in a manner that operates in a streaming mode, wherein the data stream flowing out from the corresponding arithmetic logic unit flows into the main memory and other arithmetic logic units among the multiple arithmetic logic units; and where the computer processor architecture is configured to couple the output of each stage of the DFT to the input of the subsequent stage.

6. The architecture according to claim 5, wherein the logic of each stage includes a plurality of butterfly operations.

7. The architecture according to claim 6, wherein step (b) includes configuring the butterfly operation such that the first input / output is for the real part and the second input / output is for the imaginary part, and the inputs / outputs are cross-accessed as p and q, wherein at different stages, the p input and the q input of the butterfly operation are selected from different addresses in the input buffer.

8. The architecture according to claim 7, wherein "add", "subtract", and "multiply" logic elements are used to calculate the real part and the imaginary part of the product of a complex input and a complex constant "w".

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