Active matrix substrate

Abstract

An active matrix substrate includes a plurality of oxide semiconductor TFTs each including a plurality of first TFTs. The oxide semiconductor layer of each oxide semiconductor TFT includes a channel region, a source contact region, and a drain contact region. The channel region has a first end portion and a second end portion that face each other, a source side end portion on the source contact region side located at these two end portions, and a drain side end portion on the drain contact region side located at these two end portions. Each first TFT further includes a light-shielding layer located between the oxide semiconductor layer and the substrate. The light-shielding layer includes an opening region and a light-shielding region. When viewed from the normal direction of the substrate, the light-shielding region includes a first light-shielding portion located at the first end portion and a second light-shielding portion located at the second end portion. The first light-shielding portion and the second light-shielding portion each have a first edge portion and a second edge portion that face each other. At least a part of the first edge portion overlaps with the channel region, and the second edge portion is located outside the channel region and does not overlap with the channel region.

Description

Technical Field

[0001] The present invention relates to an active matrix substrate. Background Art

[0002] An active matrix substrate for a display device includes: a display area including a plurality of pixel areas; and a non-display area (also referred to as a "border area" or "peripheral area") outside the display area. A pixel area is an area corresponding to a pixel of the display device. A thin film transistor (Thin Film Transistor: hereinafter referred to as "TFT") is disposed as a switching element in each pixel area.

[0003] In recent years, it has been proposed to use an oxide semiconductor instead of amorphous silicon or polycrystalline silicon as a material for an active layer of a TFT. Such a TFT is referred to as an "oxide semiconductor TFT". The oxide semiconductor has a higher mobility than amorphous silicon. Therefore, the oxide semiconductor TFT can operate at a faster speed than an amorphous silicon TFT. In addition, the oxide semiconductor film is formed by a simpler process than a polycrystalline silicon film, and thus can also be applied to a device that requires a large area.

[0004] Although most oxide semiconductor TFTs are bottom-gate type TFTs, a top-gate type oxide semiconductor TFT has also been proposed. For example, Patent Document 1 discloses a top-gate type TFT in which a gate electrode is disposed on a part of an oxide semiconductor layer with a gate insulating layer interposed therebetween.

[0005] Sometimes a driving circuit such as a gate driver is monolithically (integrally) formed in a non-display area of the active matrix substrate. By monolithically forming the driving circuit, miniaturization of the non-display area and cost reduction due to simplification of the mounting process can be achieved. For example, sometimes a gate driving circuit is monolithically formed in the non-display area, and a source driving circuit is mounted in a COG (Chip on Glass) manner.

[0006] In devices with high requirements for narrow bezels such as smartphones, it has been proposed to monolithically form a multiplexing circuit such as a source switching (Source Shared Driving: SSD; source shared driving) circuit in addition to the gate driver. The SSD circuit is a circuit that distributes a display signal from one video signal line of each terminal of a source driver to a plurality of source buses. By mounting the SSD circuit, the area (terminal portion forming area) for arranging terminal portions in the non-display area can be further narrowed. In addition, the number of outputs from the source driver is reduced, the circuit scale can be reduced, and thus the cost of the driving IC can be reduced.

[0007] Peripheral circuits such as a driving circuit and an SSD circuit include TFTs. In this specification, the TFTs configured as switching elements in each pixel of the display region are referred to as "pixel TFTs", and the TFTs constituting the peripheral circuits are referred to as "circuit TFTs". In addition, among the circuit TFTs, the TFTs used as switching elements in the SSD circuit are referred to as "TFTs for SSD circuits", and the TFTs used for the gate driving circuit are referred to as "TFTs for gate driving circuits". In an active matrix substrate using an oxide semiconductor TFT as a pixel TFT, from the viewpoint of the manufacturing process, it is desirable to form oxide semiconductor TFTs using the same oxide semiconductor film as that used for the pixel TFTs as circuit TFTs.

[0008] Prior art documents

[0009] Patent documents

[0010] Patent Document 1: International Publication No. 2017 / 085591 Summary of the Invention

[0011] Problems to be solved by the invention

[0012] Through the research of the inventors of the present invention, in some of the TFTs formed on the active matrix substrate, due to the driving of the active matrix substrate, the threshold voltage thereof may shift in the positive direction (positive shift). As a result, the desired TFT characteristics cannot be obtained, and there is a possibility of reducing the reliability of the active matrix substrate. For example, in the TFTs for SSD circuits or some of the TFTs for gate driving circuits, the positive shift of the threshold voltage is likely to become larger. The details will be described later.

[0013] An embodiment of the present invention provides an active matrix substrate including an oxide semiconductor TFT capable of suppressing the positive shift of the threshold voltage.

[0014] Solutions for solving the problems

[0015] This specification discloses the active matrix substrate described in the following items.

[0016] [Item 1]

[0017] An active matrix substrate having:

[0018] A substrate;

[0019] A plurality of source buses and a plurality of gate buses supported by the above substrate; and

[0020] A plurality of oxide semiconductor TFTs are supported on the above-mentioned substrate. Each oxide semiconductor TFT has an oxide semiconductor layer, a gate electrode disposed on a part of the above-mentioned oxide semiconductor layer with a gate insulating layer therebetween, and a source electrode and a drain electrode.

[0021] The above-mentioned oxide semiconductor layer includes a channel region, a source contact region electrically connected to the above-mentioned source electrode, and a drain contact region electrically connected to the above-mentioned drain electrode.

[0022] The above-mentioned channel region is a region that is located between the above-mentioned source contact region and the above-mentioned drain contact region and overlaps with the above-mentioned gate electrode when viewed from the normal direction of the above-mentioned substrate.

[0023] When viewed from the normal direction of the above-mentioned substrate, the above-mentioned channel region has:

[0024] A first end portion and a second end portion that face each other and extend in a first direction from the side of the above-mentioned source contact region toward the side of the above-mentioned drain contact region;

[0025] A source-side end portion that is located on the side of the above-mentioned source contact region of the above-mentioned first end portion and the above-mentioned second end portion and extends in a second direction intersecting the above-mentioned first direction; and

[0026] A drain-side end portion that is located on the side of the above-mentioned drain contact region of the above-mentioned first end portion and the above-mentioned second end portion and extends in the above-mentioned second direction.

[0027] The above-mentioned plurality of oxide semiconductor TFTs include a plurality of first TFTs. Each first TFT further has a light-shielding layer located between the above-mentioned oxide semiconductor layer and the above-mentioned substrate.

[0028] When viewed from the normal direction of the above-mentioned substrate, the above-mentioned light-shielding layer includes:

[0029] An opening region that overlaps with a part of the above-mentioned channel region; and

[0030] A light-shielding region that overlaps with another part of the above-mentioned channel region.

[0031] When viewed from the normal direction of the above-mentioned substrate, the above-mentioned light-shielding region includes:

[0032] A first light-shielding portion that extends along the above-mentioned first direction on the above-mentioned first end portion of the above-mentioned channel region; and

[0033] A second light-shielding portion that extends along the above-mentioned first direction on the above-mentioned second end portion of the above-mentioned channel region.

[0034] When viewed from the normal direction of the above substrate, the above first light-shielding portion and the above second light-shielding portion respectively have a first edge portion and a second edge portion that face each other and extend in the above first direction. At least a part of the above first edge portion overlaps with the above channel region, and the above second edge portion is located outside the above channel region and does not overlap with the above channel region.

[0035] [Item 2]

[0036] The active matrix substrate according to Item 1,

[0037] In each of the above first TFTs, when viewed from the normal direction of the above substrate, the above light-shielding layer further includes:

[0038] A third light-shielding portion that extends along the above second direction on the above source-side end portion of the above channel region; and

[0039] A fourth light-shielding portion that extends along the above second direction on the above drain-side end portion of the above channel region,

[0040] The above third light-shielding portion and the above fourth light-shielding portion respectively have a third edge portion and a fourth edge portion that face each other and extend in the above second direction. At least a part of the above third edge portion overlaps with the above channel region, and the above fourth edge portion is located outside the above channel region and does not overlap with the above channel region.

[0041] [Item 3]

[0042] The active matrix substrate according to Item 1 or 2,

[0043] In each of the above first TFTs, the length of the portion of the above first end portion covered by the above first light-shielding portion is substantially equal to the length of the portion of the above second end portion covered by the above second light-shielding portion.

[0044] [Item 4]

[0045] The active matrix substrate according to any one of Items 1 to 3,

[0046] In each of the above first TFTs, the width of the above first light-shielding portion and the above second light-shielding portion in the direction orthogonal to the above first direction is 3 μm or more and less than 1 / 2 of the channel width of each of the above first TFTs.

[0047] [Item 5]

[0048] The active matrix substrate according to any one of Items 1 to 4,

[0049] In each of the above-described first TFTs, when viewed from the normal direction of the above-described substrate, the above-described light-shielding layer further includes an intermediate light-shielding portion located between the above-described first light-shielding portion and the above-described second light-shielding portion and at least partially overlapping with the above-described channel region.

[0050] When viewed from the normal direction of the above-described substrate, the above-described opening region includes a first opening region and a second opening region disposed sandwiching the above-described intermediate light-shielding portion.

[0051] [Item 6]

[0052] An active matrix substrate having:

[0053] A substrate;

[0054] A plurality of source buses and a plurality of gate buses supported by the above-described substrate; and

[0055] A plurality of oxide semiconductor TFTs supported by the above-described substrate, each oxide semiconductor TFT having an oxide semiconductor layer, a gate electrode disposed on a part of the above-described oxide semiconductor layer with a gate insulating layer therebetween, and a source electrode and a drain electrode,

[0056] The above-described oxide semiconductor layer includes a channel region, a source contact region electrically connected to the above-described source electrode, and a drain contact region electrically connected to the above-described drain electrode,

[0057] The above-described channel region is a region located between the above-described source contact region and the above-described drain contact region and overlapping with the above-described gate electrode when viewed from the normal direction of the above-described substrate,

[0058] When viewed from the normal direction of the above-described substrate, the above-described channel region has:

[0059] A first end portion and a second end portion that face each other and extend in a first direction from the above-described source contact region side toward the above-described drain contact region side;

[0060] A source-side end portion that is located on the above-described source contact region side of the above-described first end portion and the above-described second end portion and extends in a second direction intersecting the above-described first direction; and

[0061] A drain-side end portion that is located on the above-described drain contact region side of the above-described first end portion and the above-described second end portion and extends in the above-described second direction,

[0062] The above-described plurality of oxide semiconductor TFTs include a plurality of first TFTs, and each first TFT further has a light-shielding layer located between the above-described oxide semiconductor layer and the above-described substrate,

[0063] When viewed from the normal direction of the above-described substrate, the above-described light-shielding layer includes:

[0064] An opening region that overlaps with a part of the above-mentioned channel region; and

[0065] A light-shielding region that overlaps with another part of the above-mentioned channel region,

[0066] When viewed from the normal direction of the above-mentioned substrate, the above-mentioned light-shielding region further includes:

[0067] A third light-shielding portion that extends along the above-mentioned second direction on the source-side end portion of the above-mentioned channel region; and

[0068] A fourth light-shielding portion that extends along the above-mentioned second direction on the drain-side end portion of the above-mentioned channel region,

[0069] The above-mentioned third light-shielding portion and the above-mentioned fourth light-shielding portion respectively have a third edge portion and a fourth edge portion that face each other and extend in the above-mentioned second direction. At least a part of the above-mentioned third edge portion overlaps with the above-mentioned channel region, and the above-mentioned fourth edge portion is located outside the above-mentioned channel region and does not overlap with the above-mentioned channel region.

[0070] [Item 7]

[0071] The active matrix substrate according to Item 2 or 6,

[0072] In each of the above-mentioned first TFTs, the length of the portion of the source-side end portion covered by the above-mentioned third light-shielding portion is substantially equal to the length of the portion of the drain-side end portion covered by the above-mentioned fourth light-shielding portion.

[0073] [Item 8]

[0074] The active matrix substrate according to any one of Items 2, 6, and 7,

[0075] In each of the above-mentioned first TFTs, the width of the above-mentioned third light-shielding portion and the above-mentioned fourth light-shielding portion in the direction orthogonal to the above-mentioned second direction is 3 μm or more and less than 1 / 2 of the channel length of each of the above-mentioned first TFTs.

[0076] [Item 9]

[0077] The active matrix substrate according to any one of Items 1 to 8,

[0078] In each of the above-mentioned first TFTs, when viewed from the normal direction of the above-mentioned substrate, the above-mentioned opening region includes an opening, a cutout, or a recess of the above-mentioned light-shielding layer.

[0079] [Item 10]

[0080] The active matrix substrate according to any one of Items 1 to 9,

[0081] In at least a part of the above-mentioned plurality of first TFTs,

[0082] The above-mentioned gate electrode includes a first gate portion and a second gate portion that are electrically connected to each other.

[0083] When viewed from the normal direction of the above-mentioned substrate, the above-mentioned channel region includes a first channel portion that overlaps with the above-mentioned first gate portion, and a second channel portion that is located on the drain electrode side of the above-mentioned first channel portion and overlaps with the above-mentioned second gate portion.

[0084] When viewed from the normal direction of the above-mentioned substrate, the above-mentioned light-shielding layer includes a first layer that overlaps with a part of the above-mentioned first channel portion, and a second layer that overlaps with a part of the above-mentioned second channel portion.

[0085] The first end portion of the above-mentioned channel region includes the ends of the above-mentioned first channel portion and the above-mentioned second channel portion that extend in the above-mentioned first direction, and the second end portion includes the ends of the above-mentioned first channel portion and the above-mentioned second channel portion that are opposite to the above-mentioned first end portion and extend in the above-mentioned first direction.

[0086] The source-side end portion is the end portion located on the source contact region side of the above-mentioned first channel portion, and the drain-side end portion is the end portion located on the drain contact region side of the above-mentioned second channel portion.

[0087] [Item 11]

[0088] The active matrix substrate according to Item 10.

[0089] At least a part of the above-mentioned first TFTs further includes an intermediate electrode.

[0090] When viewed from the normal direction of the above-mentioned substrate, the above-mentioned intermediate electrode is electrically connected to the portion of the above-mentioned oxide semiconductor layer located between the above-mentioned first channel portion and the above-mentioned second channel portion.

[0091] [Item 12]

[0092] The active matrix substrate according to any one of Items 1 to 11.

[0093] When viewed from the normal direction of the above-mentioned substrate, the channel region of each of the above-mentioned first TFTs has: a light-shielded portion that overlaps with the light-shielded region of the above-mentioned light-shielding layer; and an irradiated portion that overlaps with the opening region of the above-mentioned light-shielding layer, and the ratio AR of the area of the light-shielded portion to the area of the channel region is 25% or more and 75% or less.

[0094] [Item 13]

[0095] The active matrix substrate according to any one of Items 1 to 12.

[0096] The above active matrix substrate has: a display area including a plurality of pixel areas; and a non-display area located at the periphery of the display area and including a circuit formation area where a peripheral circuit is formed.

[0097] The above-mentioned plurality of first TFTs are arranged in the above-mentioned circuit formation area.

[0098] [Item 14]

[0099] The active matrix substrate according to Item 13.

[0100] The above-mentioned peripheral circuit includes an SSD circuit that distributes display signals to n source buses among the above-mentioned plurality of source buses.

[0101] The above-mentioned plurality of first TFTs include a plurality of TFTs for SSD circuits that constitute the above-mentioned SSD circuit, and each TFT for SSD circuit supplies a video signal to a corresponding one of the above-mentioned n source buses.

[0102] [Item 15]

[0103] The active matrix substrate according to Item 14.

[0104] No other TFTs are formed between the above-mentioned plurality of TFTs for SSD circuits and the above-mentioned display area.

[0105] [Item 16]

[0106] The active matrix substrate according to Item 14 or 15.

[0107] The above-mentioned SSD circuit further includes a plurality of compensation TFTs respectively connected to a corresponding one of the above-mentioned n source buses.

[0108] A signal having a phase opposite to that of the control signal supplied to the gate electrode of the TFT for SSD circuit connected to the same source bus is supplied to the gate electrode of each compensation TFT.

[0109] The first TFT formation area where the above-mentioned plurality of TFTs for SSD circuits are arranged is located between the second TFT formation area where the above-mentioned plurality of compensation TFTs are arranged and the above-mentioned display area.

[0110] [Item 17]

[0111] The active matrix substrate according to any one of Items 13 to 16.

[0112] The above-mentioned peripheral circuit further includes a gate driver connected to the above-mentioned plurality of gate buses, and the above-mentioned plurality of first TFTs include a plurality of gate driver TFTs that constitute the above-mentioned gate driver.

[0113] [Item 18]

[0114] The active matrix substrate according to any one of Items 13 to 17

[0115] The above-mentioned plurality of oxide semiconductor TFTs further include a second TFT disposed in each pixel region among the above-mentioned plurality of pixel regions.

[0116] Each second TFT has another light-shielding layer located between the above-mentioned oxide semiconductor layer and the above-mentioned substrate. When viewed from the normal direction of the above-mentioned substrate, the above-mentioned other light-shielding layer overlaps with the entire above-mentioned channel region of the above-mentioned second TFT.

[0117] [Item 19]

[0118] The active matrix substrate according to any one of Items 1 to 18

[0119] The above-mentioned oxide semiconductor layer contains an In-Ga-Zn-O-based semiconductor.

[0120] [Item 20]

[0121] The active matrix substrate according to Item 19

[0122] The above-mentioned In-Ga-Zn-O-based semiconductor contains a crystalline part.

[0123] Effects of the invention

[0124] According to an embodiment of the present invention, an active matrix substrate including an oxide semiconductor TFT capable of suppressing a positive shift of the threshold voltage can be provided. Brief Description of the Drawings

[0125] Figure 1 It is a schematic diagram showing an example of the planar structure of the active matrix substrate 1001.

[0126] Figure 2A It is a top view illustrating the first TFT 100 in the active matrix substrate 1001.

[0127] Figure 2B It is a cross-sectional view of the first TFT 100, showing the cross-section along the Figure 2A IIb-IIb' line in

[0128] Figure 3A It is a top view showing an example of the arrangement relationship between the light-shielding layer 103 and the channel region 107c in the first TFT 100.

[0129] Figure 3B It is a top view illustrating the arrangement relationship between the light-shielding layer 103 and the channel region 107c in the case where an alignment deviation occurs in the y direction.

[0130] Figure 3C It is a top view showing the configuration relationship between the light-shielding layer 103 and the channel region 107c in the case where an alignment deviation occurs in the x direction.

[0131] Figure 4 It is a top view showing another example of the configuration relationship between the light-shielding layer 103 and the channel region 107c.

[0132] Figure 5A It is a top view showing yet another example of the configuration relationship between the light-shielding layer 103 and the channel region 107c.

[0133] Figure 5B It is a top view illustrating the configuration relationship between the light-shielding layer 103 and the channel region 107c in the case where an alignment deviation occurs in the y direction.

[0134] Figure 5C It is a top view illustrating the configuration relationship between the light-shielding layer 103 and the channel region 107c in the case where an alignment deviation occurs in the x direction.

[0135] Figure 6 It is a top view showing yet another example of the configuration relationship between the light-shielding layer 103 and the channel region 107c.

[0136] Figure 7A It is a top view illustrating another first TFT 101 in the active matrix substrate 1001.

[0137] Figure 7B It is a cross-sectional view of the first TFT 101, showing the cross-section along the Figure 7A VIIb-VIIb' line in

[0138] Figure 8A It is a top view showing an example of the configuration relationship between the light-shielding layer 103 and the channel region 107c in the first TFT 101.

[0139] Figure 8B It is a top view illustrating the configuration relationship between the light-shielding layer 103 and the channel region 107c in the case where an alignment deviation occurs in the y direction.

[0140] Figure 8C It is a top view illustrating the configuration relationship between the light-shielding layer 103 and the channel region 107c in the case where an alignment deviation occurs in the x direction.

[0141] Figure 9 It is a top view showing yet another example of the configuration relationship between the light-shielding layer 103 and the channel region 107c.

[0142] Figure 10AIt is a top view showing another example of the configuration relationship between the light-shielding layer 103 and the channel region 107c.

[0143] Figure 10B It is a top view showing another example of the configuration relationship between the light-shielding layer 103 and the channel region 107c.

[0144] Figure 11 It is a diagram for explaining the configuration and operation of the SSD circuit Sc.

[0145] Figure 12 It is a diagram illustrating the timing chart of the SSD circuit Sc.

[0146] Figure 13 It is a diagram showing a part of another SSD circuit.

[0147] Figure 14 It is a top view showing a part of the active matrix substrate 1001, and is a diagram showing the position of the TFT formation region located between the edge of the display region and the terminal portion formation region where the active electrode terminals are formed.

[0148] Figure 15 It is an illustration of Figure 14 a diagram showing the configuration of the SSD circuit shown.

[0149] Figure 16 It is a schematic cross-sectional view illustrating the second TFT 200 in the active matrix substrate 1001.

[0150] Figure 17 It is a circuit diagram showing the configuration of the bistable circuit SRk included in the shift register (the configuration of the k-th stage of the shift register).

[0151] Figure 18 It is a timing chart of each bistable circuit of the shift register.

[0152] Figure 19 It is a diagram showing a process flow example for explaining the manufacturing method of the active matrix substrate 1001.

[0153] Figure 20 It is a top view showing a part of the active matrix substrate 2001 of the reference example, and is a diagram showing the position of the TFT formation region located between the edge of the display region and the terminal portion formation region where the active electrode terminals are formed.

[0154] Figure 21A It is a top view showing the sample TFT1 having the second light-shielding structure.

[0155] Figure 21B It is a top view showing the sample TFT2 having the first light-shielding structure.

[0156] Figure 21C FIG. 0 is a top view showing a sample TFT3 without a light-shielding layer. DETAILED DESCRIPTION

[0157] As described above, due to the driving of the active matrix substrate, there is a problem in some circuit TFTs: a positive shift in the threshold voltage occurs, and the desired characteristics cannot be obtained.

[0158] The inventors of the present invention have found through research that when the active matrix substrate operates, the above problem is significant in TFTs in which a predetermined control signal is applied to the gate at a high duty ratio. In these TFTs, the ratio of the conduction state period to one cycle (for example, one horizontal scan period) is large. Therefore, it can be considered that as the active matrix substrate operates, the positive shift of the threshold voltage tends to be aggravated and the shift amount increases. As a result, the operation margin of the TFT becomes smaller, and in some cases, it may not be able to operate normally.

[0159] For example, when the active matrix substrate is driven, a control signal is applied to the gate of the TFT for the SSD circuit at a high duty ratio (for example, about 33% or about 50%), so the positive shift of the threshold voltage tends to become large. In addition, a relatively large positive shift may also occur in a part of the TFT for the gate drive circuit (for example, the output transistor).

[0160] On the other hand, in an oxide semiconductor TFT, since light (for example, backlight light) is incident on the oxide semiconductor layer, there is a problem that the oxygen deficiency in the oxide semiconductor increases and the threshold voltage shifts in the negative direction (negative shift). When the negative shift of the threshold voltage occurs, it is possible that the cut-off leakage current increases or depletion (constant conduction state) occurs. In order to suppress the deterioration of the TFT characteristics (light deterioration) caused by the backlight light, in a top-gate type oxide semiconductor TFT, a structure in which a light-shielding layer is provided on the substrate side of the oxide semiconductor layer is known. In addition, in a bottom-gate type oxide semiconductor TFT, the gate electrode provided on the substrate side of the oxide semiconductor layer also functions as a light-shielding layer, so a light-shielding layer may not be provided separately.

[0161] In contrast, the inventors of the present application have found that in a top-gate type oxide semiconductor TFT, by utilizing the characteristic change caused by light deterioration, the positive shift of the threshold voltage can be suppressed. That is, by not sufficiently shielding the light incident on the oxide semiconductor layer by the light-shielding layer and deliberately allowing a predetermined amount of light to be incident on the oxide semiconductor layer to cause light deterioration. Thereby, a part or all of the shift amount of the threshold voltage in the positive direction generated with the operation of the active matrix substrate can be offset by the shift amount of the threshold voltage in the negative direction caused by light deterioration, so the positive shift of the threshold voltage can be suppressed.

[0162] In order to make a prescribed amount of light enter the channel region, for example, a configuration in which a light-shielding layer is provided in such a way as to shield only a part of the channel region can be considered. However, in the case where a light-shielding layer that shields only a part of the channel region is configured, when an alignment deviation occurs between the light-shielding layer and the channel region, the light-shielding rate of the channel region (the area ratio of the shielded part (shielded portion) in the channel region) changes, and thus it may not be possible to control the amount of light incident on the channel region to the prescribed amount. Therefore, the inventors of the present application studied a TFT structure that can suppress changes in the light-shielding rate caused by alignment deviation and came up with the invention of the present application.

[0163] In an embodiment of the present disclosure, the light-shielding layer has a light-shielding region that can shield the channel region and an opening region that allows light to pass through. The opening region can be, for example, an opening portion, a recessed portion, or a cut portion formed in the light-shielding layer. By providing the opening region, the amount of light incident on the oxide semiconductor layer is adjusted. Thereby, not only can high mobility be ensured, but also the forward shift of the threshold voltage can be suppressed by light degradation to improve reliability. In addition, by configuring the light-shielding region and the channel region so that even if an alignment deviation occurs, the change in the light-shielding rate of the channel region can be reduced, a decrease or unevenness in TFT characteristics caused by alignment deviation can be suppressed.

[0164] (First Embodiment)

[0165] Hereinafter, the active matrix substrate of the first embodiment will be described with reference to the drawings.

[0166] Figure 1 FIG. is a diagram schematically showing an example of the planar structure of the active matrix substrate 1001. The active matrix substrate 1001 has a display region DR that contributes to display and a peripheral region (border region) FR located outside the display region DR. The display region DR includes a plurality of pixel regions PIX arranged in a matrix. The pixel region PIX (sometimes simply referred to as "pixel") is a region corresponding to a pixel of the display device. The non-display region FR is a region located around the display region DR and does not contribute to display.

[0167] The active matrix substrate 1001 includes a substrate 1, a plurality of pixel TFTs 20 supported by the substrate 1, a plurality of pixel electrodes PE, a plurality of gate buses GL1 to GLx (x is an integer of 2 or more, hereinafter collectively referred to as "gate buses GL") that supply gate signals to the pixel TFTs 20, and a plurality of source buses SL1 to SLy (y is an integer of 2 or more, hereinafter collectively referred to as "source buses SL") that supply source signals to the pixel TFTs 20 in the display region DR. Each pixel region PIX is defined by, for example, the gate buses GL and the source buses SL. The source buses SL extend in a direction intersecting the gate buses GL.

[0168] Each pixel TFT20 and each pixel electrode PE are provided corresponding to one pixel region PIX among a plurality of pixel regions PIX. The gate electrode of the pixel TFT20 is electrically connected to one gate bus GL among the gate buses GL, and the source electrode is electrically connected to one source bus SL among the source buses SL. The drain electrode is electrically connected to the pixel electrode PE.

[0169] In the case where the active matrix substrate 1001 is applied to a display device of a transverse electric field mode such as a FFS (Fringe Field Switching) mode, a common electrode (common electrode) CE is provided for a plurality of pixels PIX on the active matrix substrate 1001.

[0170] In the non-display region FR, peripheral circuits such as a driver can be provided. For example, a gate driver GD for driving the gate bus GL, an SSD circuit Sc for driving the source buses SL in a time-division manner, etc. can be formed monolithically. The SSD circuit Sc is connected to a source driver SD mounted in a COG (Chip on Glass) manner, for example. Peripheral circuits such as the SSD circuit and the gate drive circuit each include a plurality of circuit TFTs.

[0171] The SSD circuit Sc is disposed between the source driver SD and the display region DR. The source driver SD includes a plurality of output terminals (not shown). In the region between the source driver SD and the SSD circuit Sc, a plurality of signal output lines (video signal lines) VL1 to VLz (z is an integer of 2 or more, hereinafter collectively referred to as "signal output lines VL") are provided. The SSD circuit Sc distributes the display signal supplied from one signal output line VL to two or more source buses SL (z < y). Thereby, the number of output terminals (output pins) of the source driver SD can be reduced, and thus the area of the non-display region FR can be reduced (narrow bezel).

[0172] <Structure of Oxide Semiconductor TFT>

[0173] The active matrix substrate of the present embodiment includes a plurality of oxide semiconductor TFTs having a top gate structure. The plurality of oxide semiconductor TFTs include TFTs having a light-shielding layer configured to shield only a part of the channel region (hereinafter referred to as "first TFTs").

[0174] The first TFT is not particularly limited, but can be, for example, a circuit TFT disposed in the non-display region. The active matrix substrate typically includes a plurality of first TFTs, but here a single first TFT is illustrated and its configuration is described.

[0175] Figure 2A and Figure 2BThey are a schematic top view and a cross-sectional view illustrating the first TFT 100, respectively. Figure 2B It shows along Figure 2A a cross-section taken along line IIb-IIb’ in

[0176] The first TFT 100 is supported on the substrate 1. The first TFT 100 includes: a light-shielding layer 103 disposed on the substrate 1; an oxide semiconductor layer 107 disposed on the light-shielding layer 103 with a lower insulating layer 5 therebetween; a gate insulating layer 109 disposed on the oxide semiconductor layer 107; a gate electrode GE disposed on the gate insulating layer 109; and a source electrode SE and a drain electrode DE.

[0177] When viewed from the normal direction of the main surface of the substrate 1, the oxide semiconductor layer 107 has a channel region 107c, and a first region and a second region respectively located on both sides of the channel region 107c.

[0178] The first region and the second region are low-resistance regions having a resistivity lower than that of the channel region 7c. The first region and the second region may also be conductor regions. A part 107s of the first region is electrically connected to the corresponding source bus SL via the source electrode SE. A part 107d of the second region is connected to the drain electrode DE. In this specification, the region 107s in the first region that is electrically connected to the source bus SL is referred to as the “source contact region”, and the region 107d in the second region that is connected to the drain electrode DE is referred to as the “drain contact region”. In addition, the “channel region 107c” refers to the region that overlaps the gate electrode GE when viewed from the normal direction of the substrate 1 and is located between the source contact region 107s and the drain contact region 107d.

[0179] The light-shielding layer 103 is located between the substrate 1 and the lower insulating layer 5. When viewed from the normal direction of the substrate 1, the light-shielding layer 103 shields only a part of the channel region 107c of the oxide semiconductor layer 107 (hereinafter referred to as the “first light-shielding structure”). The shape of the light-shielding layer 103 will be described later.

[0180] The light-shielding layer 103 can function as a lower electrode of the TFT 100. For example, the light-shielding layer 103 can be electrically connected to the gate electrode GE (or the corresponding gate bus GL). Alternatively, the light-shielding layer 103 can be fixed to a fixed potential (such as the source potential). Or, it can also be in a floating state.

[0181] The gate insulating layer 109 is configured to cover, for example, a part of the oxide semiconductor layer 107 (at least the channel region 107c), and does not cover the first region and the second region. The gate insulating layer 109 may be located only between the oxide semiconductor layer 107 and the gate electrode GE. When viewed from the normal direction of the substrate 1, the periphery of the gate insulating layer 109 (the periphery of the upper surface of the gate insulating layer 109 in the case where the gate insulating layer 109 has a tapered shape) may be aligned with the periphery of the gate electrode GE. Such a structure can be obtained by using a patterned mask for the gate electrode GE or by patterning the gate insulating layer 109 using the gate electrode GE as a mask.

[0182] The gate electrode GE overlaps the channel region 107c of the oxide semiconductor layer 107 when viewed from the normal direction of the substrate 1. The gate electrode GE is formed, for example, using the same conductive film (gate conductive film) as the gate bus GL. In this specification, a layer including an electrode / wiring formed using the gate conductive film is referred to as a "gate metal layer".

[0183] The oxide semiconductor layer 107, the gate insulating layer 109, and the gate electrode GE are covered by an interlayer insulating layer 10. As the interlayer insulating layer 10, a reducing insulating film (e.g., a silicon nitride film) capable of reducing the oxide semiconductor can be used. Thereby, an increase in the resistivity of the portions (the first region and the second region) of the oxide semiconductor layer 107 in contact with the interlayer insulating layer 10 can be suppressed. A source opening 110s for exposing the source contact region 107s of the first region and a drain opening 110d for exposing the drain contact region 107d of the second region are formed in the interlayer insulating layer 10.

[0184] The source electrode SE is formed on the interlayer insulating layer 10 and within the source opening 110s, and is connected to the source contact region 107s of the oxide semiconductor layer 107 within the source opening 110s. The drain electrode DE is formed on the interlayer insulating layer 10 and within the drain opening 110d, and is connected to the drain contact region 107d of the oxide semiconductor layer 107 within the drain opening 110d. The source electrode SE and the drain electrode DE may be formed using the same conductive film as the source bus SL. In this specification, a layer including an electrode / wiring formed using the source conductive film is referred to as a "source metal layer".

[0185] The source metal layer and the interlayer insulating layer 10 may be covered by an inorganic insulating layer (passivation film) 11.

[0186] <Relationship between the channel region 107c and the light-shielding layer 103>

[0187] Figure 3AThis is a top view showing an example of the positional relationship between the light-shielding layer 103 and the channel region 107c in the first TFT 100. For simplicity, components other than the light-shielding layer 103 and the channel region 107c are not shown.

[0188] As Figure 3A shown, when viewed from the normal direction of the substrate 1, the channel region 107c has: a first end portion e1 and a second end portion e2, which face each other and extend in a first direction from the source contact region 107s side toward the drain contact region 107d side; a source-side end portion e3, which is located on the source contact region 107s side of the first end portion e1 and the second end portion e2 and extends in a second direction intersecting the first direction; and a drain-side end portion e4, which is located on the drain contact region 107d side of the first end portion e1 and the second end portion e2 and extends in the second direction. The first direction is, for example, substantially parallel to the channel length direction (x direction) of the first TFT. The second direction may be a direction orthogonal to the x direction or may be, for example, substantially parallel to the channel width direction (y direction) of the first TFT. As shown in the figure, the periphery of the channel region 17c is substantially rectangular, and its four sides may be the first end portion e1, the second end portion e2, the source-side end portion e3, and the drain-side end portion e4, respectively.

[0189] The light-shielding layer 103 has one or more opening regions (regions that allow visible light to pass through) 30 that at least partially overlap with the channel region 107c. When viewed from the normal direction of the substrate 1, the opening region 30 may be an opening, a cutout, or a recess provided in the light-shielding layer 103.

[0190] In Figure 3A the example shown, the light-shielding layer 103 has a first opening region 31 and a second opening region 32 as the opening regions 30. Here, the first opening region 31 is a recess provided at the edge portion on the source contact region 107s side of the light-shielding layer 103, and the second opening region 32 is a recess provided at the edge portion on the drain contact region 107d side of the light-shielding layer 103.

[0191] The region (region having a function of blocking visible light) 40 in the light-shielding layer 103 other than the opening region 30 is referred to as the "light-shielding region". The light-shielding region 40 of the light-shielding layer 103 includes: a first light-shielding portion 41 that extends along the first direction on the first end portion e1 of the channel region 107c; and a second light-shielding portion 42 that extends along the first direction on the second end portion e2 of the channel region 107c. The first light-shielding portion 41, the second light-shielding portion 42, the first end portion e1, and the second end portion e2 may all extend in the x direction (channel length direction). In addition, the opening region 30 may also be located between the first light-shielding portion 41 and the second light-shielding portion 42.

[0192] The first light-shielding portion 41 has a first edge portion 41a and a second edge portion 41b that face each other and extend in the first direction. When viewed from the normal direction of the substrate 1, at least a part of the first edge portion 41a overlaps with the channel region 107c (that is, is located inside the channel region 107c). The second edge portion 41b is located outside the channel region 107c and does not overlap with the channel region 107c. Similarly, the second light-shielding portion 42 has a first edge portion 42a and a second edge portion 42b that face each other and extend in the first direction. When viewed from the normal direction of the substrate 1, at least a part of the first edge portion 42a overlaps with the channel region 107c, and the second edge portion 42b is located outside the channel region 107c and does not overlap with the channel region 107c.

[0193] The light-shielding region 40 of the light-shielding layer 103 may further include an intermediate light-shielding portion 45 that is located inside the channel region 107c when viewed from the normal direction of the substrate 1. In this example, the intermediate light-shielding portion 45 extends in a direction (here, the y direction) that intersects the first direction. Both ends of the intermediate light-shielding portion 45 are in contact with the first light-shielding portion 41 and the second light-shielding portion 42, and the first opening region 31 and the second opening region 32 are arranged with the intermediate light-shielding portion 45 therebetween (that is, arranged on both sides of the intermediate light-shielding portion 45).

[0194] When viewed from the normal direction of the substrate 1, the channel region 107c includes a light-shielded portion P1 that overlaps with the light-shielding region 40 of the light-shielding layer 103, and an irradiated portion P2 that does not overlap with the light-shielding region 40 of the light-shielding layer 103. The irradiated portion P2 includes a part of the channel region 107c that overlaps with the opening region 30 of the light-shielding layer 103. In this specification, the area ratio P1 / (P1 + P2) (%) of the light-shielded portion P1 to the entire channel region 107c is referred to as the "light-shielding ratio AR" in the channel region 107c.

[0195] <Effect>

[0196] In the first TFT 100 of the present embodiment, when viewed from the normal direction of the substrate 1, the light-shielding layer 103 has an opening region 30 that overlaps with a part of the channel region 107c, and a light-shielding region 40 that overlaps with another part of the channel region 107c. Thus, as Figure 2B shown, a specified amount of light (here, a part of the backlight 130) can be made to enter the channel region 107c. By making the backlight 130 enter the channel region 107c of the oxide semiconductor layer 107, a negative shift in the threshold voltage due to light degradation is intentionally generated. Thus, the shift amount in the positive direction of the threshold voltage can be canceled, and therefore, the change ΔVth in the threshold voltage can be reduced.

[0197] In addition, according to the present embodiment, by adjusting the position, size, and number of the opening regions 30 provided in the light-shielding layer 103, the light-shielding ratio AR of the channel region 107c (i.e., the area ratio P1 / (P1 + P2) of the light-shielded portion P1 in the channel region 107c) can be set to a specified value. Thereby, the amount of light incident on the oxide semiconductor layer 107 can be controlled. The light-shielding ratio AR can be, for example, 25% or more and 75% or less. When the light-shielding ratio AR is too high, it may not be possible to make the forward shift of the threshold voltage small enough. On the other hand, when the light-shielding ratio AR is too low, the photo-degradation of the oxide semiconductor layer 107 becomes large, and the mobility may decrease.

[0198] Moreover, according to the present embodiment, even if an alignment deviation occurs, for example, in the y direction (channel width direction) between the light-shielding layer 103 and the channel region 107c, a change in the area of the light-shielded portion P1 in the channel region 107c can be suppressed. Hereinafter, description will be made with reference to the drawings.

[0199] Figure 3B and Figure 3C are top views respectively illustrating the configuration relationship between the light-shielding layer 103 and the channel region 107c in the case where an alignment deviation occurs in the y direction and in the x direction.

[0200] As Figure 3B shown, if an alignment deviation occurs in the y direction, when viewed from the normal direction of the substrate 1, for example, the area of the portion of the first light-shielding portion 41 overlapping with the channel region 107c increases, and the area of the portion of the second light-shielding portion 42 overlapping with the channel region 107c decreases. In this way, the area changes of the portions overlapping with the channel region 107c of the first light-shielding portion 41 and the second light-shielding portion 42 can compensate for each other, and thus, the change amount of the area of the light-shielded portion P1 caused by the alignment deviation can be reduced. Therefore, a decrease or non-uniformity of the TFT characteristics caused by a change in the light-shielding ratio AR can be suppressed.

[0201] When viewed from the normal direction of the substrate 1, the first edge portion 41a of the first light-shielding portion 41 and the first edge portion 42a of the second light-shielding portion 42 can each cross the channel region 107c in the x direction. That is, the first edge portion 41a and the first edge portion 42a can cross the channel region 107c from the outside of the source-side end portion e3 of the channel region 107c and extend to the outside of the drain-side end portion 4e of the channel region 107c. Thereby, as Figure 3C illustrated, the change amount of the area of the light-shielded portion P1 of the channel region 107c in the case where an alignment deviation occurs in the x direction can be suppressed.

[0202] As Figure 3AAs shown, it is preferable that the length (first length) L1 of the portion covered by the light-shielding region 40 (here, the first light-shielding portion 41) of the light-shielding layer 103 in the first end portion e1 of the channel region 107c is substantially equal to the length (second length) L2 of the portion covered by the light-shielding region 40 (here, the second light-shielding portion 42) of the light-shielding layer 103 in the second end portion e2. Thus, regardless of the alignment deviation in the y direction, the area of the light-shielded portion P1 of the channel region 107c is substantially fixed, and the desired light-shielding ratio AR can be achieved.

[0203] It is preferable that the width w1 of the first light-shielding portion 41 and the width w2 of the second light-shielding portion 42 of the light-shielding layer 103 are 3 μm or more. The width w1 of the first light-shielding portion 41 and the width w2 of the second light-shielding portion 42 are the widths in the direction orthogonal to the first direction (here, the y direction), and when the widths of the respective light-shielding regions are not fixed, it refers to the minimum width. The deviation amount of alignment is less than, for example, 1.5 μm. Therefore, by setting the widths w1 and w2 to 3 μm or more, the change in the light-shielding ratio AR due to the alignment deviation can be more reliably suppressed. On the other hand, the width w1 of the first light-shielding portion 41 and the width w2 of the second light-shielding portion 42 can be, for example, less than 1 / 2 of the channel width Wc, and preferably less than 1 / 4 of the channel width Wc. Thus, an opening region 30 having a specified area can be arranged. In addition, for example, when the first TFT is provided in the pixel region, a high pixel aperture ratio can be ensured.

[0204] The length of the first light-shielding portion 41 and the second light-shielding portion 42 in the x direction may also be 3 μm or more longer than the channel length Lc. Thus, even when an alignment deviation occurs in the x direction, the desired light-shielding ratio AR can be more reliably achieved.

[0205] In addition, in this specification, the channel width Wc refers to the shortest distance between the first end portion e1 and the second end portion e2 of the channel region 107c, and the channel length Lc refers to the shortest distance between the source-side end portion e3 and the drain-side end portion e4 of the channel region 107c.

[0206] As will be described later, the light-shielding layer 103 may further include: a third light-shielding portion that extends along a second direction intersecting the first direction on the source-side end portion e3 of the channel region 107c; and a fourth light-shielding portion that extends along the second direction on the drain-side end portion e4 of the channel region 107c.

[0207] (Modification example)

[0208] Hereinafter, a modification example of the first TFT of the present embodiment will be described with reference to the drawings. In the following drawings, the same reference numerals are assigned to the same components. Regarding the same components, the description will be appropriately omitted. Figures 2A to 3C The same reference numerals are assigned to the same components. Regarding the same components, the description will be appropriately omitted.

[0209] <Modified Example 1>

[0210] Figure 4 This is a top view showing another example of the arrangement relationship between the light-shielding layer 103 and the channel region 107c.

[0211] As shown in the figure, the light-shielding region 40 of the light-shielding layer 103 may further include: a third light-shielding portion 43 that extends along a second direction intersecting the first direction at the source-side end portion e3 of the channel region 107c; and a fourth light-shielding portion 44 that extends along the second direction at the drain-side end portion e4 of the channel region 107c. The second direction may be the y direction. In the illustrated example, the third light-shielding portion 43, the fourth light-shielding portion 44, the source-side end portion e3, and the drain-side end portion e4 extend substantially parallel to each other (here, extending along the y direction).

[0212] The third light-shielding portion 43 has a third edge portion 43a and a fourth edge portion 43b that face each other and extend in the second direction. When viewed from the normal direction of the substrate 1, at least a part of the third edge portion 43a overlaps with the channel region 107c, and the fourth edge portion 43b is located outside the channel region 107c and does not overlap with the channel region 107c. Similarly, the fourth light-shielding portion 44 has a third edge portion 44a and a fourth edge portion 44b that face each other and extend in the second direction. When viewed from the normal direction of the substrate 1, at least a part of the third edge portion 44a overlaps with the channel region 107c, and the fourth edge portion 44b is located outside the channel region 107c and does not overlap with the channel region 107c.

[0213] The light-shielding region 40 of the light-shielding layer 103 may further include an intermediate light-shielding portion 45 that is located inside the channel region 107c when viewed from the normal direction of the substrate 1. In this example, the intermediate light-shielding portion 45 extends in the first direction (here, the x direction). Both ends of the intermediate light-shielding portion 45 are in contact with the third light-shielding portion 43 and the fourth light-shielding portion 44.

[0214] The opening region 30 of the light-shielding layer 103 includes a first opening region 31 and a second opening region 32. The first opening region 31 is a recess provided at the edge portion on the source contact region 107s side of the light-shielding layer 103, and the second opening region 32 is a recess provided at the edge portion on the drain contact region 107d side of the light-shielding layer 103. In this example, the first opening region 31 and the second opening region 32 are respectively arranged on both sides of the intermediate light-shielding portion 45.

[0215] In this modified example, by partially shielding the channel region 107c, it is also possible to reduce the change ΔVth in the threshold voltage. Further, by providing the light-shielding layer 103 with the third light-shielding portion 43 and the fourth light-shielding portion 44, when an alignment deviation occurs in the x direction, the areas of the portions overlapping with the channel region 107c as viewed from the normal direction of the substrate 1 can be compensated for each other by the third light-shielding portion 43 and the fourth light-shielding portion 44. As a result, the change amount of the area of the light-shielded portion P1 caused by the alignment deviation can be reduced. Therefore, it is possible to suppress a decrease or non-uniformity in the TFT characteristics due to a change in the light-shielding ratio AR.

[0216] Preferably, the length (third length) L3 of the portion of the source-side end portion e3 of the channel region 107c covered by the third light-shielding portion 43 of the light-shielding layer 103 is substantially equal to the length (fourth length) L4 of the portion of the drain-side end portion e4 covered by the fourth light-shielding portion 44 of the light-shielding layer 103. Thereby, regardless of whether there is an alignment deviation in the x direction, the area of the light-shielded portion P1 of the channel region 107c is substantially fixed, and a desired light-shielding ratio AR can be achieved.

[0217] Considering the alignment deviation amount (e.g., less than 1.5 μm), it is preferable that the width w3 of the third light-shielding portion 43 and the width w4 of the fourth light-shielding portion 44 of the light-shielding layer 103 are 3 μm or more. The width w3 of the third light-shielding portion 43 and the width w4 of the fourth light-shielding portion 44 are widths in the x direction, and when the widths of the respective light-shielding regions are not fixed, it refers to their minimum widths.

[0218] In the illustrated example, the third length L3 of the third light-shielding portion 43 is smaller than the channel width Wc, and the third light-shielding portion 43 overlaps a part of the second end portion e2 and is arranged at a space (e.g., 1.5 μm or more) from the first end portion e1 of the channel region 107c. Similarly, the fourth length L4 of the fourth light-shielding portion 44 is smaller than the channel width Wc, and the fourth light-shielding portion 44 overlaps a part of the first end portion e1 and is arranged at a space (e.g., 1.5 μm or more) from the second end portion e2 of the channel region 107c. Thereby, even when an alignment deviation occurs in the y direction, it is possible to more effectively suppress a change in the area of the light-shielded portion P1 of the channel region 107c.

[0219] Further, although not illustrated, the third edge portion 43a of the third light-shielding portion 43 and the third edge portion 44a of the fourth light-shielding portion 44 may also extend across the channel region 107c in the y direction. Thereby, regardless of whether there is an alignment deviation in the y direction, the area of the light-shielded portion P1 of the channel region 107c can be made substantially fixed.

[0220] <Modified Example 2>

[0221] Figure 5AIt is a top view showing another example of the configuration relationship between the channel region 107c and the light-shielding layer 103. Figure 5B and Figure 5C They are top views respectively illustrating the configuration relationship between the light-shielding layer 103 and the channel region 107c in the case of alignment deviation occurring in the y direction and the x direction.

[0222] In Modification 2, the light-shielding region 40 of the light-shielding layer 103 includes a first light-shielding portion 41, a second light-shielding portion 42, a third light-shielding portion 43, a fourth light-shielding portion 44, and an intermediate light-shielding portion 45. When viewed from the normal direction of the substrate 1, the intermediate light-shielding portion 45 is located between the first light-shielding portion 41 and the second light-shielding portion 42 and extends in the first direction. The light-shielding region 40 of the light-shielding layer 103 may have an S-shaped planar shape.

[0223] The first light-shielding portion 41 extends along the first direction on the first end portion e1 of the channel region 107c, and the second light-shielding portion 42 extends along the first direction on the second end portion e2 of the channel region 107c. The first edge portion 41a of the first light-shielding portion 41 and the second edge portion 42a of the second light-shielding portion 42 may respectively extend across the channel region 107c in the x direction (that is, the first length L1 and the second length L2 may be equal to the channel length Lc). The third light-shielding portion 43 extends in the second direction on the source-side end portion e3 in a manner connecting the source-side ends of the first light-shielding portion 41 and the intermediate light-shielding portion 45. The fourth light-shielding portion 44 extends in the second direction on the drain-side end portion e4 in a manner connecting the drain-side ends of the second light-shielding portion 42 and the intermediate light-shielding portion 45. As shown in the figure, the first light-shielding portion 41, the second light-shielding portion 42, the intermediate light-shielding portion 45, the first end portion e1, and the second end portion e2 may all extend substantially parallel to each other in the x direction (channel length direction). In addition, the third light-shielding portion 43, the fourth light-shielding portion 44, the source-side end portion e3, and the drain-side end portion e4 may all extend substantially parallel to each other in the y direction (channel width direction).

[0224] The opening region 30 of the light-shielding layer 103 includes a first opening region 31 and a second opening region 32. When viewed from the normal direction of the substrate 1, the first opening region 31 is, for example, a concave portion provided at the edge on the source contact region side of the light-shielding layer 103 and is located between the second light-shielding portion 42 and the intermediate light-shielding portion 45. The second opening region 32 is, for example, a concave portion provided at the edge on the drain contact region side of the light-shielding layer 103 and is located between the first light-shielding portion 41 and the intermediate light-shielding portion 45.

[0225] As Figure 5BAs shown, if an alignment deviation occurs in the y direction, then when viewed from the normal direction of the substrate 1, for example, the area of the portion of the first light-shielding portion 41 that overlaps with the channel region 107c increases, and the area of the portion of the second light-shielding portion 42 that overlaps with the channel region 107c decreases. Therefore, the amount of change in the area of the light-shielded portion P1 caused by the alignment deviation can be reduced. On the other hand, as Figure 5C shown, if an alignment deviation occurs in the x direction, then when viewed from the normal direction of the substrate 1, for example, the area of the portion of the third light-shielding portion 43 that overlaps with the channel region 107c increases, and the area of the portion of the fourth light-shielding portion 44 that overlaps with the channel region 107c decreases. Therefore, the amount of change in the area of the light-shielded portion P1 caused by the alignment deviation can be reduced. Thus, according to this modification, even if alignment deviations in the x direction and the y direction occur, a prescribed light-shielding ratio AR can be achieved, and thus a decrease or non-uniformity in TFT characteristics can be suppressed.

[0226] In this modification example, it is also preferable that the length (first length) L1 of the portion of the first end portion e1 of the channel region 107c covered by the light-shielding region 40 (here, the first light-shielding portion 41) of the light-shielding layer 103 is substantially equal to the length (second length) L2 of the portion of the second end portion e2 covered by the light-shielding region 40 (here, the second light-shielding portion 42) of the light-shielding layer 103. Also, it is preferable that the length (third length) L3 of the portion of the source-side end portion e3 of the channel region 107c covered by the light-shielding region 40 (here, the third light-shielding portion 43) of the light-shielding layer 103 is substantially equal to the length (fourth length) L4 of the portion of the drain-side end portion e4 covered by the light-shielding region 40 (here, the fourth light-shielding portion 44) of the light-shielding layer 103. Thereby, changes in TFT characteristics caused by alignment can be more effectively suppressed.

[0227] <Modification Example 3>

[0228] Figure 6 is a top view showing another example of the arrangement relationship between the channel region 107c and the light-shielding layer 103.

[0229] As shown in the figure, the light-shielding region 40 of the light-shielding layer 103 may also cover the entire periphery of the channel region 107c. Here, the light-shielding region 40 of the light-shielding layer 103 includes the first light-shielding portion 41, the second light-shielding portion 42, the third light-shielding portion 43, and the fourth light-shielding portion 44. The third light-shielding portion 43 extends in a manner connecting the source-side end portions of the first light-shielding portion 41 and the third light-shielding portion 43. The fourth light-shielding portion 44 extends in a manner connecting the drain-side end portions of the second light-shielding portion 42 and the fourth light-shielding portion 44.

[0230] The light-shielding layer 103 has an opening 33 as the opening region 30. When viewed from the normal direction of the substrate 1, the opening 33 is surrounded by the first light-shielding portion 41, the second light-shielding portion 42, the third light-shielding portion 43, and the fourth light-shielding portion 44. In addition, although not shown, two or more openings 33 may be provided in the light-shielding layer 103.

[0231] <Modified Example 4>

[0232] The first TFT in the present embodiment may have a multi-channel structure in which a plurality of channel regions are arranged at intervals in the oxide semiconductor layer. Hereinafter, a TFT having a dual-channel structure in which two channel regions are arranged will be described as an example. The same components as Figures 2A to 3C will be denoted by the same reference numerals, and the description will be appropriately omitted.

[0233] Figure 7A and Figure 7B are a schematic plan view and a cross-sectional view illustrating the first TFT 101 having a dual-channel structure, respectively. Figure 7B shows a cross-section along the Figure 7A VIIb-VIIb' line in

[0234] The first TFT 101 has a dual-channel structure and has a structure electrically equivalent to two TFTs connected in series.

[0235] The first TFT 101 has a light-shielding layer 103 disposed on the substrate 1 and an oxide semiconductor layer 107 disposed on the light-shielding layer 103 with a lower insulating layer 5 interposed therebetween. The oxide semiconductor layer 107 includes a channel region 107c and a first region and a second region disposed on both sides thereof.

[0236] The channel region 107c includes a first channel portion 107cA and a second channel portion 107cB. The region located between the first channel portion 107cA and the second channel portion 107cB is referred to as the "intermediate region". The first region, the second region, and the intermediate region may be low-resistance regions having a resistivity smaller than that of the channel region 107c. The first region includes a source contact region 107s, and the second region includes a drain contact region 107d. In addition, although the case of having one intermediate region and two channel regions is illustrated here, it is not limited thereto, and two or more intermediate regions and three or more channel regions may be provided.

[0237] The first TFT 101 further includes a source electrode SE electrically connected to the source contact region 107s, a drain electrode DE electrically connected to the drain contact region 107d, and an intermediate electrode ME electrically connected to the intermediate region. The intermediate electrode ME can be a so-called floating electrode that does not form an electrical connection at any position. The region 107m in the intermediate region that is connected to the intermediate electrode ME is referred to as the "intermediate contact region". In addition, the two channel portions 107cA, 107cB, the source contact region 107s, the drain contact region 107d, and the intermediate region 107m are all formed in a single continuous oxide semiconductor layer 107.

[0238] The gate electrode GE includes a first gate portion G1 and a second gate portion G2. The first gate portion G1 and the second gate portion G2 can also be electrically connected to each other. The first gate portion G1 is disposed over the first channel portion 107cA of the oxide semiconductor layer 107 with a gate insulating layer 109A therebetween. The second gate portion G2 is disposed over the second channel portion 107cB with a gate insulating layer 109B therebetween.

[0239] When viewed from the normal direction of the substrate 1, the light-shielding layer 103 includes: a first layer 103A configured to partially overlap with the first channel portion 107cA; and a second layer 103B configured to partially overlap with the second channel portion 107cB. Also in this example, the light-shielding layer 103 can function as a lower electrode or can be fixed to a fixed potential. Alternatively, it can also be in an electrically floating state.

[0240] Figure 8A It is a top view illustrating the configuration relationship between the light-shielding layer 103 and the channel region 107c in the first TFT 101. Figure 8B and Figure 8C They are top views respectively illustrating the configuration relationship between the light-shielding layer 103 and the channel region 107c when alignment deviations occur in the y direction and the x direction.

[0241] When viewed from the normal direction of the substrate 1, the first channel portion 107cA is a region that overlaps with the first gate portion G1 and is located between the source contact region 107s and the intermediate region 107m. The second channel portion 107cB is a region that overlaps with the second gate portion G2 and is located between the drain contact region 107d and the intermediate region 107m.

[0242] As Figure 8AAs shown, also in this modified example, when viewed from the normal direction of the substrate 1, the channel region 107c includes: a first end portion e1 and a second end portion e2, which face each other and extend in a first direction from the source contact region 107s toward the drain contact region 107d; and a source-side end portion e3 and a drain-side end portion e4, which face each other and extend in a second direction intersecting the first direction.

[0243] When viewed from the normal direction of the substrate 1, the first end portion e1 includes end portions e1A and e1B of the first channel portion 107cA and the second channel portion 107cB that extend in the first direction. Similarly, the second end portion e2 includes end portions e2A and e2B of the first channel portion 107cA and the second channel portion 107cB that face the first end portion e1 and extend in the first direction. The source-side end portion e3 is an end portion that is located on the source contact region 107s side in the first channel portion 107cA and extends in the second direction. The drain-side end portion e4 is an end portion that is located on the drain contact region 107d side in the second channel portion 107cB and extends in the second direction.

[0244] The light-shielding region 40 of the light-shielding layer 103 includes: a first light-shielding portion 41 that extends along the first direction on the first end portion e1 of the channel region 107c; a second light-shielding portion 42 that extends along the first direction on the second end portion e2; a third light-shielding portion 43 that extends along the second direction on the source-side end portion e3; and a fourth light-shielding portion 44 that extends along the second direction on the drain-side end portion e4.

[0245] In the illustrated example, the first light-shielding portion 41 and the third light-shielding portion 43 are provided in the first layer 103A, and the second light-shielding portion 42 and the fourth light-shielding portion 44 are provided in the second layer 103B. The opening region 30 of the light-shielding layer 103 includes an opening region 30A in the first layer 103A and an opening region 30B in the second layer 103B. More specifically, when viewed from the normal direction of the substrate 1, the first layer 103A of the light-shielding layer 103 includes: the second light-shielding portion 42 that extends along the first direction on the end portion e2A of the first channel portion 107cA; the third light-shielding portion 43 that extends along the second direction on the source-side end portion e3; and an opening region (cutout portion) 30A that is located on the drain side of the third light-shielding portion 43. The second layer 103B includes: the first light-shielding portion 41 that extends along the first direction on the end portion e1B of the second channel portion 107cB; the fourth light-shielding portion 44 that extends along the second direction on the drain-side end portion e4; and an opening region (cutout portion) 30B that is located on the source side of the fourth light-shielding portion 44.

[0246] In this modified example, as Figure 8BAs shown, if an alignment deviation occurs in the y direction, when viewed from the normal direction of the substrate 1, for example, the area of the portion of the first light-shielding portion 41 that overlaps with the channel region 107c increases, and the area of the portion of the second light-shielding portion 42 that overlaps with the channel region 107c decreases. Thus, the change amount of the area of the light-shielded portion P1 caused by the alignment deviation can be reduced. On the other hand, as Figure 8C shown, if an alignment deviation occurs in the x direction, when viewed from the normal direction of the substrate 1, for example, the area of the portion of the third light-shielding portion 43 that overlaps with the channel region 107c increases, and the area of the portion of the fourth light-shielding portion 44 that overlaps with the channel region 107c decreases. Thus, the change amount of the area of the light-shielded portion P1 caused by the alignment deviation can be reduced. In this way, also in this modified example, even if alignment deviations in the x direction and the y direction occur, a prescribed light-shielding ratio AR can be achieved.

[0247] In this modified example, it is also preferable that the first length L1 and the second length L2 are substantially equal. Additionally, it is preferable that the third length L3 and the fourth length L4 are substantially equal. Furthermore, in the case of having a multi-channel structure such as this modified example, these lengths L1 to L4 become the sum of the corresponding lengths in each channel portion. For example, the first length L1 is the sum of the length L1B of the portion covered by the first light-shielding portion 41 and the length L1A of the portion covered by the third light-shielding portion 43. The second length L2 is the sum of the length L2A of the portion covered by the second light-shielding portion 42 and the length L2B of the portion covered by the fourth light-shielding portion 44.

[0248] <Modified Example 5>

[0249] Figure 9 It is a top view showing another example of the configuration relationship between the channel region 107c and the light-shielding layer 103 in the first TFT 101.

[0250] In the light-shielding layer 103 of this modified example, the first light-shielding portion 41 and the second light-shielding portion 42 are formed across the first layer 103A and the second layer 103B, and the light-shielding region 40 further includes an intermediate light-shielding portion 45, which is different from the light-shielding layer 103 of Modified Example 4 in these two points.

[0251] In this modified example, the first layer 103A has an E-shaped planar shape, and the second layer 103B has a planar shape obtained by reversing the E shape left and right.

[0252] When viewed from the normal direction of the substrate 1, the first layer 103A of the light-shielding layer 103 includes: a light-shielding portion 41A that extends along a first direction at an end portion e1A of the first channel portion 107cA; a light-shielding portion 42A that extends along the first direction at an end portion e2A; a light-shielding portion 45A that is located between the light-shielding portions 41A and 42A and extends in the first direction; a third light-shielding portion 43 that extends along a second direction at a source-side end portion e3; and opening regions 34 and 35. The third light-shielding portion 43 extends in a manner that connects the source-side end portions of the light-shielding portions 41A, 42A, and 45A. The opening regions 34 and 35 are disposed sandwiching the light-shielding portion 45A. The second layer 103B includes: a light-shielding portion 41B that extends along the first direction at an end portion e1B of the second channel portion 107cB; a light-shielding portion 42B that extends along the first direction at an end portion e2B; a light-shielding portion 45B that is located between the light-shielding portions 41B and 42B and extends in the first direction; a fourth light-shielding portion 44 that extends along the second direction at a drain-side end portion e4; and opening regions 36 and 37. The fourth light-shielding portion 44 extends in a manner that connects the drain-side end portions of the light-shielding portions 41B, 42B, and 45B. The opening regions 36 and 37 are disposed sandwiching the light-shielding portion 45B.

[0253] In this modified example, the first light-shielding portion 41 of the light-shielding layer 103 includes the light-shielding portion 41A of the first layer 103A and the light-shielding portion 41B of the second layer 103B. The second light-shielding portion 42 includes the light-shielding portion 42A of the first layer 103A and the light-shielding portion 42B of the second layer 103B. The intermediate light-shielding portion 45 includes the light-shielding portion 45A of the first layer 103A and the light-shielding portion 45B of the second layer 103B. The opening region 30 includes the opening regions 34 and 35 of the first layer 103A and the opening regions 36 and 37 of the second layer 103B.

[0254] <Modified Example 6>

[0255] Figure 10A and Figure 10B are top views respectively showing another example of the arrangement relationship between the channel region 107c in the first TFT 101 and the light-shielding layer 103.

[0256] It may be as Figure 10A shown, the first layer 103A of the light-shielding layer 103 only has the first light-shielding portion 41, and the second layer 103B only has the second light-shielding portion 42. In this case, when viewed from the normal direction of the substrate 1, the opening region 30 of the light-shielding layer 103 includes: a region 30A that corresponds to a portion of the first channel portion 107cA that does not overlap with the first light-shielding portion 41; and a region 30B that corresponds to a portion of the second channel portion 107cB that does not overlap with the second light-shielding portion 42.

[0257] Or it may also be as Figure 10BAs shown, the first layer 103A of the light shielding layer 103 has only the third light shielding portion 43, and the second layer 103B has only the fourth light shielding portion 44. In this case, when viewed from the normal direction of the substrate 1, the opening region 30 of the light shielding layer 103 includes: a region 30A corresponding to a portion of the first channel portion 107cA that does not overlap with the third light shielding portion 43; and a region 30B corresponding to a portion of the second channel portion 107cB that does not overlap with the fourth light shielding portion 44.

[0258] In addition, the structure of the light shielding layer 103 in this embodiment is not limited to that of Figures 2A to 10B In the structure described above. In the light-shielding layer 103, it is sufficient to have at least one set of light-shielding portions that are in a relationship of compensating for the change in the area of the light-shielded portion P1 caused by the alignment deviation. That is, it is sufficient to have (i) the first light-shielding portion 41 and the second light-shielding portion 42, (ii) the third light-shielding portion 43 and the fourth light-shielding portion 44, or both (i) and (ii). Thus, it is possible to suppress the change in the light-shielding ratio AR caused by the alignment deviation along the y direction, the x direction, or both directions. In addition, if the light-shielding layer 103 illustrated above has only one of the first light-shielding portion 41 and the second light-shielding portion 42, the light-shielding ratio AR sometimes changes depending on the direction in which the alignment deviation occurs. Therefore, it is preferred that the light-shielding layer 103 has both the first light-shielding portion 41 and the second light-shielding portion 42, or does not have either one. Similarly, it is preferred that the light-shielding layer 103 has both the third light-shielding portion 43 and the fourth light-shielding portion 44, or does not have either one.

[0259] In addition, Figures 2A to 6 , an example is shown in which the channel region 107c has a rectangular planar shape that is long in the y direction, but the shape of the channel region 107c is not limited thereto. For example, the channel region 107c may also have a rectangular planar shape that is long in the x direction.

[0260] <Evaluation of TFT characteristics>

[0261] Since the relationship between the light shielding ratio AR and the shift amount of the threshold voltage Vth was investigated, the result will be described.

[0262] First, three sample TFTs, sample TFT1, sample TFT2, and sample TFT3, which have different light shielding ratios AR, were manufactured.

[0263] Figures 21A to 21C 1 and 2 are top views showing sample TFT1 to sample TFT3, respectively. Figure 21AAs shown, the sample TFT1 includes: an oxide semiconductor layer 7 having a channel region 7c, a source electrode SE, a drain electrode DE, a gate electrode GE, and a light-shielding layer 3a. In the sample TFT1, the light-shielding layer 3a is arranged to shield the entire channel region 7c (referred to as "the second light-shielding structure"). Therefore, the light-shielding ratio AR of the channel region 7c of the sample TFT1 is 100%. Figure 21B The sample TFT2 shown has a first light-shielding structure in which the channel region 7c is partially shielded. In the sample TFT2, the light-shielding layer 3b is arranged to cover only the drain side of the channel region 7c when viewed from the normal direction of the substrate 1, so that the light-shielding ratio AR becomes 50%. Figure 21C The sample TFT3 shown does not have a light-shielding layer (i.e., the light-shielding ratio AR: 0%), which is different from other sample TFTs.

[0264] Next, a gate voltage Vg of +30 V was applied to each TFT in a state where backlight light (luminance: 4500 cd) was irradiated from the back side to the three sample TFTs. The measurement temperature was set to 60°C and the Vg stress application time was set to 0 to 3600 seconds, and the current-voltage characteristics of each sample TFT were measured.

[0265] The measurement results of the threshold voltage of each sample TFT during the Vg stress application time of 3600 seconds are shown in Table 1.

[0266] [Table 1]

[0267] Light-shielding ratio AR Threshold voltage Vth Sample TFT1 100％ 8.12V Sample TFT2 50％ 7.72V Sample TFT3 0％ 4.81V

[0268] From the results shown in Table 1, it can be seen that as the light-shielding ratio AR increases, the offset amount in the positive direction of the threshold voltage becomes larger. It is considered that the reason is that the smaller the light-shielded area in the channel region, that is, the larger the amount of light incident on the channel region, the larger the offset amount in the negative direction of the threshold voltage Vth caused by light degradation. As a result, the positive offset of the threshold voltage is compensated and suppressed. Therefore, it can be seen that by adjusting the light-shielding ratio AR of the TFT according to the characteristics required for the TFT, the desired TFT characteristics can be achieved. In addition, regardless of the planar shape of the light-shielding layer, the positive offset of the threshold voltage can be controlled by the light-shielding ratio AR. Therefore, for example, even if a light-shielding layer having various planar shapes considering alignment is used in the first TFT, the same effect as above can be obtained.

[0269] (Application Example 1 to the Active Matrix Substrate: SSD Circuit)

[0270] The first TFT can be applied to the circuit TFT of the active matrix substrate. The first TFT can be applied to, for example, the SSD circuit. In the SSD circuit, the TFT is applied with a control signal at a relatively high duty ratio, and thus, the amount of positive shift in the threshold voltage tends to increase. By applying the first light-shielding structure to such a TFT, the amount of positive shift in the threshold voltage can be reduced by using the negative shift in the threshold voltage caused by light degradation.

[0271] First, an example of the configuration of the SSD circuit will be described with reference to the drawings.

[0272] Figure 11 FIG. is a diagram for explaining the configuration and operation of the SSD circuit Sc in the active matrix substrate 1001 of the present embodiment.

[0273] The SSD circuit Sc is disposed between the source driver SD and the display area DR. The SSD circuit Sc includes a plurality of SSD circuit TFTs 21A to 21H (hereinafter collectively referred to as "TFT 21"). The TFT 21 is a first TFT having a first light-shielding structure.

[0274] The SSD circuit Sc includes a plurality of unit circuits U supported by the substrate 1. Each of the plurality of unit circuits U distributes the display signal from one signal output line VL to n (n is an integer of 2 or more) source buses SL. In Figure 11 FIG., the case where n = 2 is shown, that is, the case where each unit circuit U distributes the display signal from one signal output line VL to two source buses SL. Although the SSD circuit has a large number of unit circuits, in Figure 11 FIG., only four unit circuits (designated as the first unit circuit U1 to the fourth unit circuit U4) are shown for simplicity.

[0275] Each unit circuit U includes n (here, two) branch wirings BL and n (here, two) SSD circuit TFTs 21 (TFTs 21A and 21C in the first unit circuit U1). The two branch wirings BL are connected to one signal output line VL. In addition, each of the two TFTs 21 is connected to each of the two branch wirings BL. These TFTs 21 individually (independently) perform on / off control of the electrical connection between the two branch wirings BL and the two source buses SL.

[0276] Hereinafter, the configuration of each unit circuit U will be described more specifically by taking the first unit circuit U1 and the second unit circuit U2 as examples.

[0277] The first unit circuit U1 distributes the display signal S(1) from the signal output line VL1 to the source buses SL1 and SL3, and the second unit circuit U2 distributes the display signal S(2) from the signal output line VL2 to the source buses SL2 and SL4.

[0278] One TFT21A in the first unit circuit U1 controls the connection and disconnection of the branch wiring BL1 and the source bus SL1, and another TFT21C controls the connection and disconnection of the branch wiring BL3 and the source bus SL3. The source electrode and the drain electrode of TFT21A are respectively connected to the branch wiring BL1 and the source bus SL1, and the source electrode and the drain electrode of TFT21C are respectively connected to the branch wiring BL3 and the source bus SL3.

[0279] One TFT21B in the second unit circuit U2 controls the connection and disconnection of the branch wiring BL2 and the source bus SL2, and another TFT21D controls the connection and disconnection of the branch wiring BL4 and the source bus SL4. The source electrode and the drain electrode of TFT21B are respectively connected to the branch wiring BL2 and the source bus SL2, and the source electrode and the drain electrode of TFT21D are respectively connected to the branch wiring BL4 and the source bus SL4.

[0280] In addition, the SSD circuit Sc has n (here, 2) control signal lines CL1 and CL2.

[0281] In the first unit circuit U1, the selection signal (SSD control signal) ASW1 is supplied from the control signal line (the first control signal line) CL1 to the gate electrode of TFT21A, and the selection signal (SSD control signal) BSW1 having a phase opposite to that of the selection signal ASW1 is supplied from the control signal line (the second control signal line) CL2 to the gate electrode of TFT21C. In the second unit circuit U2, the selection signal ASW2 is supplied from the first control signal line CL1 to the gate electrode of TFT21B, and the selection signal BSW2 is supplied from the second control signal line CL2 to the gate electrode of TFT21D. These selection signals define the conduction period of the selection switches within the same group and are synchronized with the time-series signal output from the source driver SD. Each unit circuit U writes the data potential obtained by time-division multiplexing the output of the signal output line VL into the corresponding two source buses SL (time-division driving) in time series.

[0282] Figure 12It is a timing diagram showing the operation of the SSD circuit Sc. As shown in the figure, during the first horizontal scan period 1H, the uppermost gate bus GL1 is selected. During this horizontal scan period 1H, the selection signals ASW1 and BSW1 are sequentially turned on, and two TFT21As and 21Cs in the first unit circuit U1 are sequentially selected, so that the data potentials of two pixels located at the intersection of the gate bus GL1 and the source buses SL1 and SL3 are sequentially output to the signal output line VL1. Similarly, the data potentials of two pixels located at the intersection of the gate bus GL1 and the source buses SL2 and SL4 are sequentially output to the signal output line VL2. The same applies to other signal wirings. In addition, the selection signals ASW1 to ASW4 are supplied by the common first control signal main line CL1, and the selection signals BSW1 to BSW4 are supplied by the common second control signal main line CL2.

[0283] The gate electrodes of the two TFT21s in each unit circuit U are respectively connected to the first control signal main line CL1 and the second control signal main line CL2, so that a specified voltage is applied with a high duty ratio of about 50%. Therefore, these TFT21s are liable to have a characteristic shift in which the threshold voltage shifts in the positive direction as they operate. However, in this embodiment, each TFT21 has a first light-shielding structure. Therefore, when the active matrix substrate operates, the backlight light is incident on the oxide semiconductor layer of each TFT21 from the substrate 1 side, and a negative shift of the threshold voltage caused by light can be generated. As a result, part or all of the shift amount of the threshold voltage of the TFT21 in the positive direction is canceled, so that changes in the TFT characteristics can be suppressed.

[0284] In addition, the SSD circuit of this embodiment is not limited to the configuration exemplified above and can have various configurations. For example, each unit circuit U may also be configured for three source buses SL corresponding to R, G, and B pixels (that is, n = 3). In this case, the gate electrodes of the three TFT21s in each unit circuit U are respectively applied with a specified voltage with a high duty ratio of about 33%. Therefore, although a positive shift of the threshold voltage is liable to occur, the shift amount of the threshold voltage can be reduced by deliberately making light incident on the oxide semiconductor layer of the TFT21 as in the above example.

[0285] The SSD circuit sometimes has a plurality of compensation TFTs called cancel elements. Figure 13 It is a diagram showing a part of the SSD circuit including the cancel element.

[0286] A plurality of compensation TFTs 22A to 22H (hereinafter sometimes collectively referred to as "compensation TFTs 22") correspond to a plurality of source buses SL. The source of the compensation TFT 22 is connected between the SSD circuit TFT 21 and the display area DR in the corresponding source bus SL. The drain side of the compensation TFT 22 can be in an electrically floating state or connected to a wiring for supplying a common potential (COM). The gate of the compensation TFT 22 is supplied with a signal having a phase opposite to that of the SSD control signal ASW supplied to the gate of the corresponding SSD circuit TFT 21 (hereinafter referred to as "inverted signal"). For example, the control signal ASW1 may be supplied from the control signal main line CL1 to the gate of the SSD circuit TFT 21A, and the control signal BSW1 having a phase opposite to that of the control signal ASW1 may be supplied from the control signal main line CL2 to the gate of the compensation TFT 22A as the inverted signal.

[0287] In addition, in this example, the inverted signal is supplied using the control signal main lines CL1 and CL2 having opposite phases, but a wiring for supplying the inverted signal may be provided separately. By providing the compensation TFT 22, it is possible to compensate for the change (feed-through) of the video signal in the source bus SL that occurs when the SSD circuit TFT 21 changes from conduction to cutoff.

[0288] In this specification, regarding the operation of the display device using the SSD circuit Sc, the timing chart of time-division driving, etc., the entire disclosure contents of Japanese Patent Application Laid-Open No. 2008-225036, Japanese Patent Application Laid-Open No. 2006-119404, and International Publication No. 2011 / 118079 are incorporated by reference. In addition, regarding the SSD circuit having an elimination element (compensation TFT), the entire disclosure contents of, for example, Japanese Patent Application Laid-Open No. 5-232508 are incorporated by reference.

[0289] (Example of application to an active matrix substrate 2: Formation position of the first TFT in the non-display area)

[0290] The active matrix substrate 1001 can be applied to various display devices such as liquid crystal display devices. The display device includes a display panel, the display panel including the active matrix substrate 1001, a counter substrate having a color filter, a black matrix, etc., and a light modulation layer (such as a liquid crystal layer) disposed between the active matrix substrate 1001 and the counter substrate. The display device further includes a backlight disposed on the back side of the display panel (the side of the active matrix substrate 1001 opposite to the liquid crystal layer). The backlight is configured such that the light emitted from the backlight (backlight light) is incident on the display area of the active matrix substrate 1001. On the other hand, the light going from the backlight to the non-display area is blocked by a support portion such as a frame that holds the backlight and the display panel. However, a part of the light from the backlight may be incident on the area near the display area in the non-display area. For example, a part of the backlight light after being incident on the display area is incident on the non-display area through reflection / scattering etc. within the active matrix substrate. Therefore, in the non-display area, there is a tendency that the closer to the display area, the more the irradiation amount of the backlight light, and the farther from the display area, the less the irradiation amount.

[0291] In the present embodiment, at least a part of the circuit TFTs formed in the non-display area is a first TFT having a first light-shielding structure. In this case, in order to obtain the effect brought by the first light-shielding structure (the effect of reducing the offset amount of the threshold voltage), it is preferable to form the first TFT in the area where the irradiation amount of the backlight light in the non-display area is relatively large. That is, in the non-display area, it is preferable to form the first TFT at a position as close as possible to the display area. In the non-display area, no other TFTs may be disposed between the TFT formation area where the first TFT is formed and the display area.

[0292] Hereinafter, taking the case where the first TFT is applied to the TFT for the above-mentioned SSD circuit as an example, the formation area of the first TFT will be described.

[0293] The SSD circuit is usually provided between the display area and the terminal portion formation area where source end terminals for connecting to the source driver are formed. In the present embodiment, no other TFTs (such as elimination elements) are provided between the TFT for the SSD circuit and the display area. Thereby, the amount of light that can be incident on the TFT for the SSD circuit can be increased. Hereinafter, it will be described with reference to the drawings.

[0294] Figure 14 It is a top view showing a part of the active matrix substrate of the present embodiment, showing the arrangement of the TFTs located between the edge of the display area and the terminal portion formation area where the active electrode terminals are formed. Figure 15 is an illustration Figure 14 showing the configuration of the SSD circuit shown. In addition, for comparison, the arrangement of the TFTs in the active matrix substrate 2001 of the reference example is shown in Figure 20 as well.

[0295] As Figure 14 shown, the region where the SSD circuit is disposed (hereinafter referred to as "circuit formation region SR") is disposed between the display region DR and the terminal portion formation region TR. For example, a TFT (ASL transistor) for lighting inspection for panel lighting inspection is formed between the circuit formation region SR and the terminal portion formation region TR. When the display panel is an in-cell touch panel, a touch panel lighting inspection TFT formation region AR2 for forming a TFT (TP-ASL transistor) used for panel lighting inspection of the touch panel can be disposed between the lighting inspection TFT formation region AR1 and the terminal portion formation region TR. These lighting inspection TFTs can be, for example, top-gate oxide semiconductor TFTs. The light-shielding structure of these TFTs is not particularly limited. The lighting inspection TFT may not have a light-shielding layer.

[0296] The circuit formation region SR includes an SSD circuit TFT formation region R21 for forming a plurality of SSD circuit TFTs (first TFTs). When the SSD circuit has the above-described compensation TFT (cancellation element), the circuit formation region SR further includes a compensation TFT formation region R22 for forming a plurality of compensation TFTs. In the present embodiment, the SSD circuit TFT formation region R21 is disposed at a position closer to the display region DR than the compensation TFT formation region R22. The compensation TFT can be, for example, a top-gate oxide semiconductor TFT. The compensation TFT is a TFT that performs overshoot and undershoot by coupling when an inversion signal is input, and only needs to have a capacitance. Therefore, in the compensation TFT, a forward shift of the threshold voltage does not particularly become a problem, and thus the light-shielding structure of the compensation TFT is not particularly limited. The compensation TFT may not have a light-shielding layer.

[0297] Since the source of the compensation TFT is connected between the display region DR and the SSD circuit TFT in the source bus SL, a layout in which the compensation TFT is disposed closer to the display region DR than the SSD circuit TFT is generally adopted. That is, as Figure 20 shown in the reference example, the compensation TFT formation region R22 is disposed at a position closer to the display region DR than the SSD circuit TFT formation region R21. Therefore, the SSD circuit TFT formation region R21 is far from the display region DR, and there may not be enough light incident on the SSD circuit TFT formation region R21.

[0298] In contrast, in the present embodiment, the SSD circuit TFT formation region R21 is arranged at a position closer to the display region DR than the compensation TFT formation region R22. No other TFTs are provided at a position closer to the display region DR than the SSD circuit TFT formation region R21. As a result, more light can be incident on the SSD circuit TFT formation region R21. Therefore, by allowing a specified amount of light to be incident on the channel region of the SSD circuit TFT, the positive shift of the threshold voltage can be more effectively suppressed.

[0299] (Application Example 3 to the Active Matrix Substrate)

[0300] The active matrix substrate 1001 may include the above-described plurality of first TFTs and a plurality of second TFTs having a light-shielding structure different from the light-shielding structure (first light-shielding structure) of the first TFTs.

[0301] In the second TFT, the light-shielding layer may be arranged to overlap the entire channel region of the oxide semiconductor layer when viewed from the normal direction of the substrate (second light-shielding structure).

[0302] The plurality of first TFTs may include circuit TFTs such as SSD circuit TFTs and gate drive circuit TFTs. The plurality of second TFTs may include, for example, pixel TFTs provided in the display region. For pixel TFTs, a low off-leakage current is required. The reason is that when the off-leakage current is large, the holding characteristics of the potential written to the pixel electrode deteriorate, and display defects such as luminance unevenness and flicker may occur. By providing the pixel TFTs with the second light-shielding structure, the negative shift of the threshold voltage due to light degradation can be suppressed, and thus an increase in the off-leakage current can be suppressed. In addition, the second TFTs may further include a part of the circuit TFTs.

[0303] Hereinafter, the structure of the second TFT will be specifically described with reference to the pixel TFT in the drawings. The first TFT has been described above Figures 2A to 10B and thus will not be described. In addition, hereinafter, an active matrix substrate applied to a display device in the FFS mode will be described as an example. The FFS mode is a transverse electric field mode in which a pair of electrodes are provided on one substrate and an electric field is applied to the liquid crystal molecules in a direction parallel to the substrate surface (transverse direction). In addition, the active matrix substrate of the present embodiment can also be applied to a display device in a longitudinal electric field mode (e.g., TN mode, vertical alignment mode) in which a voltage is applied in the thickness direction of the liquid crystal layer.

[0304] Figure 16 is a cross-sectional view illustrating the second TFT 200.

[0305] The second TFT 200 is supported by the substrate 1. Here, the second TFT 200 is a pixel TFT disposed in each pixel region PIX in the display region DR.

[0306] The second TFT 200 is formed using the same oxide semiconductor film as the first TFT. Each electrode of the second TFT 200 can be provided on the same metal layer as the first TFT. In this example, the TFT structure of the second TFT 200 other than the light-shielding layer is the same as that of the first TFT. In the following description, the differences from the first TFT will be mainly described.

[0307] The second TFT 200 includes: a light-shielding layer 203 disposed on the substrate 1; an oxide semiconductor layer 207 disposed on the light-shielding layer 203 with a lower insulating layer 5 therebetween; a gate insulating layer 209 disposed on the oxide semiconductor layer 207; a gate electrode GE2 disposed on the gate insulating layer 209; and a source electrode SE2 and a drain electrode DE2.

[0308] The oxide semiconductor layer 207 includes a channel region 207c, a source contact region 207s, and a drain contact region 207d that overlap the gate electrode GE2 when viewed from the normal direction of the main surface of the substrate 1, similar to the oxide semiconductor layer of the first TFT. The source contact region 207s is electrically connected to the corresponding source bus SL via the source electrode SE2. The drain contact region 207d is electrically connected to the pixel electrode PE via the drain electrode DE2.

[0309] The light-shielding layer 203 is configured to overlap the entire channel region 207c when viewed from the normal direction of the substrate 1. Thereby, deterioration of the characteristics of the oxide semiconductor layer 207 caused by the light (backlight light) 130 from the substrate 1 side can be more effectively suppressed. In addition, the light-shielding layer 203 may be configured to overlap the entire oxide semiconductor layer 207, or the entire portion of the oxide semiconductor layer 207 between the source contact region 207s and the drain contact region 207d when viewed from the normal direction of the substrate 1.

[0310] The gate electrode GE2 can be integrally formed with (connected to) the gate bus GL. For example, the gate electrode GE2 can be a part of the gate bus GL. In this case, the portion of the gate bus GL that overlaps the oxide semiconductor layer 207 when viewed from the normal direction of the substrate 1 is sometimes referred to as the "gate electrode GE2".

[0311] The source electrode SE2 can be integrally formed with (connected to) the source bus SL. For example, the source electrode SE2 can be a part of the source bus SL. In this case, the portion of the source bus SL that is connected to the oxide semiconductor layer 207 is sometimes referred to as the "source electrode SE2".

[0312] An upper insulating layer 13 is formed over the source metal layer so as to cover the second TFT 200. The upper insulating layer 13 includes, for example, an inorganic insulating layer (e.g., a passivation film) 11. As shown in the figure, the upper insulating layer 13 may have a stacked structure including the inorganic insulating layer 11 and an organic insulating layer 12 formed on the inorganic insulating layer 11. In addition, the organic insulating layer 12 may not be formed. Alternatively, the organic insulating layer 12 may be formed only in the display area.

[0313] A common electrode CE is formed on the upper insulating layer 13. The common electrode CE may not be separated for each pixel region PIX. For example, the common electrode CE may have an opening in a pixel contact region (a region where a pixel contact hole CHp is formed) connecting the pixel electrode PE and the drain electrode DE, and is formed in the entire pixel region PIX except for the pixel contact region.

[0314] The pixel electrode PE is disposed on the common electrode CE with a dielectric layer 17 therebetween. The pixel electrode PE is separated for each pixel region PIX. In each pixel region PIX, one or more slits (openings) or cut portions are provided in the pixel electrode PE.

[0315] The pixel electrode PE is disposed on the dielectric layer 17 and is connected to the drain electrode DE2 within a pixel contact hole CHp formed in the upper insulating layer 13 and the dielectric layer 17.

[0316] In addition, in the illustrated example, the pixel electrode PE is formed on the common electrode CE with the dielectric layer 17 therebetween, but the common electrode CE may also be formed on the pixel electrode PE with the dielectric layer 17 therebetween. In this case, in each pixel region PIX, slits or cut portions are provided in the common electrode CE.

[0317] In addition, the second TFT 200 may not include a drain electrode. In this case, the pixel electrode PE may be directly connected to the drain contact region 207d of the oxide semiconductor layer 207.

[0318] Moreover, although not shown, the source bus SL and the source electrode SE2 of the second TFT 200 may also be formed of the same conductive film as the light-shielding layer 203. A substrate structure in which the source bus SL is disposed closer to the substrate 1 side than the gate metal layer and the oxide semiconductor layer 207 is referred to as a "lower source structure".

[0319] (Application Example 4 to the Active Matrix Substrate: Gate Driver)

[0320] The first TFT can be used for a gate driver, for example. As described above, a positive shift with a relatively large threshold voltage may occur in a part of the TFTs for the gate driving circuit (for example, output transistors). By applying the first light-shielding structure to these TFTs and deliberately allowing light to be incident on the oxide semiconductor layer, the amount of shift in the threshold voltage can be reduced.

[0321] <Configuration of Gate Driver>

[0322] An example of the configuration of a gate driver GD formed monolithically on the active matrix substrate 1001 will be described.

[0323] The gate driver GD is composed of shift registers including a plurality of stages. Each stage of the shift register is provided in a manner corresponding to one pixel row (or a plurality of pixel rows in the case of dual-gate driving) in the display area. Each stage of the shift register is a bistable circuit that becomes either of two states at each point in time and outputs a signal representing that state (hereinafter referred to as a "state signal"). The state signals output from each stage of the shift register are provided as scan signals to the corresponding gate buses.

[0324] In this example, an input terminal and an output terminal are provided for each bistable circuit. The input terminal is used to receive the first clock CKA, the fourth clock CKD, the clear signal CLR, the reference potential VSS, the set signal S, and the reset signal R, and the output terminal is used to output the state signal Q. Moreover, the state signal Q output from the stage two levels before is provided as the set signal S, and the state signal Q output from the stage three levels after is provided as the reset signal R. That is, when focusing on the k-th stage, the scan signal Gout(k - 2) provided to the gate bus of the (k - 2)-th row is provided to the k-th stage as the set signal S, and the scan signal Gout(k + 3) provided to the gate bus of the (k + 3)-th row is provided to the k-th stage as the reset signal R. In addition, the gate start pulse signal GSP is provided to the bistable circuits of the first stage and the second stage of the shift register as the set signal S. Further, the clear signal CLR is provided to the bistable circuits of the last three stages of the shift register as the reset signal R. In addition, the first stage and the last three stages in the bistable circuit are dummy circuits, and the circuits from the second stage to the (1 + x)-th stage (k = 2 to 1 + x) are respectively connected to the gate buses GL1 to GLx.

[0325] In the configuration shown above, when a pulse of the gate start pulse signal GSP serving as the set signal S is provided to the first stage of the shift register, pulses included in the gate start pulse signal GSP (the pulses are included in the state signals Q output from each stage) are sequentially transferred from the first stage to the last stage based on each clock signal. And, corresponding to the transfer of the pulses, the state signals Q output from each stage sequentially become high level. And, the state signals Q output from these stages are provided to each gate bus GL as the scan signal Gout(k).

[0326] Figure 17 is a circuit diagram showing the configuration of the bistable circuit SRk included in the shift register (the configuration of the k-th stage of the shift register). As shown in the figure, the bistable circuit SRk includes a plurality (here, 12) of TFTs and one capacitor C1. The plurality of TFTs include: transistors M2, M3, M12 (also referred to as clear transistors) whose gate electrodes are input with the clear signal CLR; M10 (also referred to as an output transistor) that outputs the output signal Gout(k); a transistor M1 whose gate electrode and drain electrode are input with a set signal (GSP in the case of Gout(k - 2), k = 1, k = 2) (that is, connected in a diode configuration); and a transistor M8 (also referred to as a pull-down transistor) whose source electrode or drain electrode is electrically connected to the gate electrode of the output transistor M10. The node connected to the gate electrode of the transistor M10 is called netA, and the node connected to the gate electrode of the transistor M8 is called netB. The source electrode of the transistor M1 is connected to netA. In addition, the bistable circuit SRk has transistors M3, M6, M6 whose drain electrodes are connected to netB + 。

[0327] Figure 18 is a timing diagram of each bistable circuit of the shift register. When it becomes time point t1, a pulse of Gout(k - 2) is provided to the transistor M1 as a set signal. As a result, the potential of netA changes from a low (LOW) level to a high (HIGH) level. In addition, since the transistor M6 + becomes in a conducting state, the potential of netB becomes a low level.

[0328] When it becomes time point t2, the first clock CKA changes from a low level to a high level. As a result, the potential of netA rises. As a result, the potential of the scan signal Gout(k) rises to the potential of the high level of the first clock CKA, and the gate bus connected to the output terminal of this bistable circuit becomes in a selected state. Since the potential of netA rises, the transistor M6 becomes in a conducting state, and thus, the potential of netB becomes a low level.

[0329] When it becomes time point t3, the potential of the scan signal Gout(k) becomes low. Although the potential of netA decreases compared to the period from t2 to t3, it remains at a high level state. At time point t4, when a pulse of the reset signal (Gout(k+3)) is provided to the gate of the transistor M9, the potential of netA becomes low.

[0330] Among the above-mentioned multiple transistors, it is particularly required to suppress the characteristic shift of the output transistor M10. Therefore, in the present embodiment, at least the output transistor M10 may be a first TFT having a first light-shielding structure. On the other hand, the transistors M3, M6, M6 whose drain electrodes are connected to netB + are not likely to generate a positive shift, and thus may be a TFT (second light-shielding structure) having a light-shielding layer that shields the entire channel region.

[0331] The configuration of the gate driver of the present embodiment is not limited to the illustrated example. The present embodiment can be applied to various known gate drivers. Regarding the configuration and operation of the gate driver, the entire disclosure contents of Japanese Patent Application Laid-Open No. 2019-138923 and Japanese Patent Application Laid-Open No. 2010-192019 are incorporated by reference for reference. In addition, in the above, an example in which the gate driver is formed in the non-display region is shown, but the gate driver may sometimes be formed in the pixel region.

[0332] (Manufacturing method of the active matrix substrate 1001)

[0333] Next, an example of the manufacturing method of the active matrix substrate of the present embodiment will be described with reference to the drawings. Here, mainly the method of manufacturing the first TFT100 (for example Figure 2A 、 2B ) as the circuit TFT and the second TFT200 ( Figure 16 ) as the pixel TFT will be described.

[0334] Figure 19 is a diagram showing a process flow for explaining an example of the manufacturing method of the active matrix substrate 1001.

[0335] · Step 1: Formation of the lower metal layer

[0336] On the substrate 1, a lower conductive film (thickness: for example, 50 nm or more and 500 nm or less) is formed by, for example, sputtering. Next, the lower conductive film is patterned (for example, wet etching) by a known photolithography process. In this way, a lower metal layer including the light-shielding layers 103 and 203 in the first TFT and the second TFT is formed.

[0337] As the substrate 1, a transparent and insulating substrate such as a glass substrate, a silicon wafer substrate, a heat-resistant plastic substrate (resin substrate), etc. can be used.

[0338] The material of the lower conductive film is not particularly limited, and metals such as aluminum (Al), tungsten (W), molybdenum (Mo), tantalum (Ta), chromium (Cr), titanium (Ti), copper (Cu), or their alloys, or films containing their metal nitrides can be appropriately used. In addition, a laminated film formed by laminating these multiple films can also be used. Here, as the lower conductive film, a laminated film (Cu / Ti film) including a Ti film (thickness: 30 nm) and a Cu film (thickness: 200 nm) in this order from the side of the substrate 1 is used.

[0339] ·STEP2: Formation of the lower insulating layer 5

[0340] Next, the lower insulating layer 5 (thickness: for example, 200 nm or more and 600 nm or less) is formed so as to cover the lower metal layer.

[0341] The lower insulating layer 5 is formed by, for example, CVD method. As the lower insulating layer 5, a silicon oxide (SiOx) layer, a silicon nitride (SiNx) layer, a silicon oxynitride (SiOxNy; x > y) layer, a silicon nitride oxide (SiNxOy; x > y) layer, etc. can be appropriately used. The lower insulating layer 5 can be a single layer or can have a laminated structure. For example, a silicon nitride (SiNx) layer, a silicon nitride oxide layer, etc. can be formed on the substrate side (lower layer) to prevent the diffusion of impurities, etc. from the substrate 1, and a silicon oxide (SiO2) layer, a silicon oxynitride layer, etc. can be formed on the layer above it (upper layer) to ensure insulation. Here, as the lower insulating layer 5, a laminated film having a silicon nitride (SiNx) layer (thickness: 50 - 600 nm) as the lower layer and a silicon oxide (SiO2) layer (thickness: 50 - 600 nm) as the upper layer can be formed. When an oxide film such as a silicon oxide film is used as the lower insulating layer 5 (as the uppermost layer in the case where the lower insulating layer 5 has a laminated structure), the oxidation defects generated in the channel region of the oxide semiconductor layer formed later can be reduced by the oxide film, and thus the low-resistance of the channel region can be suppressed.

[0342] ·STEP3: Formation of the oxide semiconductor layers 107 and 207

[0343] Next, an oxide semiconductor film is formed on the lower insulating layer 5. After that, an annealing treatment of the oxide semiconductor film can be performed. The thickness of the oxide semiconductor film can be, for example, 15 nm or more and 200 nm or less.

[0344] Next, patterning of the oxide semiconductor film is performed by a known photolithography process. Patterning of the oxide semiconductor film can be performed, for example, by wet etching using a PAN-based etching solution containing phosphoric acid, nitric acid, and acetic acid, or an oxalic acid-based etching solution. Thereby, oxide semiconductor layers 107 and 207 that become the active layers of the first TFT and the second TFT are obtained.

[0345] The oxide semiconductor film can be formed by, for example, a sputtering method. Here, as the oxide semiconductor film, an In-Ga-Zn-O-based semiconductor film (thickness: 50 nm) containing In, Ga, and Zn is formed.

[0346] ·STEP4: Formation of the gate insulating layer and the gate metal layer

[0347] Next, a gate insulating film (thickness: for example, 80 nm or more and 250 nm or less) and a gate conductive film (thickness: for example, 50 nm or more and 500 nm or less) are formed in order to cover the oxide semiconductor layers 107 and 207.

[0348] As the gate insulating film, the same insulating film as that used for the lower insulating layer 5 (the insulating film exemplified for the lower insulating layer 5) can be used. Here, a silicon oxide (SiO2) layer is formed as the gate insulating film. When an oxide film such as a silicon oxide film is used as the insulating film, oxidation defects generated in the channel regions of the oxide semiconductor layers 107 and 207 can be reduced by the oxide film, and thus low-resistance conversion of the channel regions can be suppressed.

[0349] As the gate conductive film, for example, metals such as molybdenum (Mo), tungsten (W), aluminum (Al), copper (Cu), titanium (Ti), tantalum (Ta), or their alloys can be used. The gate conductive film can have a stacked structure including a plurality of layers formed of different conductive materials. Here, as the gate conductive film, a Cu / Ti stacked film having a Ti film as the lower layer and a Cu film as the upper layer, or a Cu / Mo stacked film having a Mo film as the lower layer and a Cu film as the upper layer is used.

[0350] After that, a barrier layer is formed on the gate conductive film, and patterning of the gate conductive film is performed using the barrier layer as a mask, thereby forming a gate metal layer including gate electrodes GE and GE2 and a gate bus GL. Next, etching of the gate insulating film is performed using the above barrier layer or gate metal layer as a mask, and gate insulating layers 109 and 209 are obtained. Thereby, regions of the oxide semiconductor layers 107 and 207 that overlap with the gate electrodes GE and GE2 with the gate insulating layers 109 and 209 interposed therebetween become channel regions 107c and 207c.

[0351] ·STEP5: Low-resistance conversion treatment and formation of the interlayer insulating layer 10

[0352] Next, a low-resistance treatment of the oxide semiconductor layers 107 and 207 can be performed. As the low-resistance treatment, for example, plasma treatment can be performed. Thereby, regions (the first region and the second region) that are located on both sides of the channel regions 107c and 207c and are exposed when viewed from the normal direction of the main surface of the substrate 1 in the oxide semiconductor layers 107 and 207 become low-resistance regions with a lower resistivity than the channel regions 107c and 207c. The low-resistance regions can be conductor regions (for example, sheet resistance: 200 Ω / square or less).

[0353] Next, an interlayer insulating layer 10 that covers the oxide semiconductor layers 107 and 207, the gate insulating layers 109 and 209, and the gate metal layers is formed. As the interlayer insulating layer 10, an inorganic insulating layer such as a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film can be formed as a single layer or in a stacked manner. The thickness of the inorganic insulating layer can be 100 nm or more and 500 nm or less. When an insulating film that reduces the oxide semiconductor such as a silicon nitride film is used to form the interlayer insulating layer 10, the resistivity of the regions (here, the low-resistance regions) in the oxide semiconductor layers 107 and 207 that are in contact with the interlayer insulating layer 10 can be maintained low, and thus it is preferred. Here, as the interlayer insulating layer 10, for example, a stacked film with a SiO2 layer as the lower layer and a SiNx layer as the upper layer is formed by CVD.

[0354] After that, for example, the interlayer insulating layer 10 is patterned by dry etching. Thereby, source openings 110s and 210s that expose a part of the first region (source contact region) of the oxide semiconductor layers 107 and 207 and drain openings 110d and 210d that expose a part of the second region (drain contact region) are formed in the interlayer insulating layer 10.

[0355] ·STEP6: Formation of source metal layer

[0356] Next, a source conductive film (thickness: for example, 50 nm or more and 500 nm or less) is formed on the interlayer insulating layer 10, and the source conductive film is patterned. Thereby, an upper metal layer including source electrodes SE and SE2, drain electrodes DE and DE2, and a source bus SL is formed. The source electrodes SE and SE2 are connected to the first regions of the oxide semiconductor layers 107 and 207 within the source openings 110s and 210s, respectively. The drain electrodes DE and DE2 are connected to the second regions of the oxide semiconductor layers 107 and 207 within the drain openings 110d and 210d. In this way, the first TFT 100 and the second TFT 200 are manufactured.

[0357] As the conductive film for the source electrode, for example, an element selected from aluminum (Al), chromium (Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo), or tungsten (W), or an alloy containing these elements as components can be used. For example, it can have a three-layer structure such as a titanium film - aluminum film - titanium film, or a three-layer structure such as a molybdenum film - aluminum film - molybdenum film. Here, a stacked film with a Ti film (thickness: 15 - 70 nm) as the lower layer and a Cu film (thickness: 200 - 400 nm) as the upper layer is used.

[0358] ·STEP7: Formation of the inorganic insulating layer 11 and the organic insulating layer 12

[0359] Next, an upper insulating layer 13 is formed to cover the interlayer insulating layer 10 and the source metal layer. Here, as the upper insulating layer 13, an inorganic insulating layer 11 (thickness: for example, 100 nm or more and 500 nm or less) and an organic insulating layer 12 (thickness: for example, 1 - 3 μm, preferably 2 - 3 μm) are formed in sequence. In addition, the entire portion of the organic insulating layer 12 located in the non-display area can be removed. Or, the organic insulating layer 12 may not be formed.

[0360] As the inorganic insulating layer 11, the same inorganic insulating film as the interlayer insulating layer 10 (the insulating films exemplified for the interlayer insulating layer 10) can be used. Here, as the inorganic insulating layer 11, for example, a SiNx layer (thickness: 300 nm) is formed by CVD method. The organic insulating layer 12 can be, for example, an organic insulating film containing a photosensitive resin material (for example, an acrylic resin film).

[0361] After that, patterning of the organic insulating layer 12 is performed. As a result, in each pixel region PIX, a first opening is formed in the organic insulating layer 12 to expose a part of the inorganic insulating layer 11. The first opening is arranged to overlap with the drain electrode DE2 of the pixel TFT (the second TFT) when viewed from the normal direction of the substrate 1.

[0362] ·STEP8: Formation of the common electrode CE

[0363] Next, the common electrode CE is formed on the upper insulating layer 13.

[0364] First, a first transparent conductive film (thickness: 20 to 300 nm), not shown, is formed on the upper insulating layer 13 and within the first opening. Here, for example, an indium-zinc oxide film is formed as the first transparent conductive film by sputtering. As the material of the first transparent conductive film, metal oxides such as indium-tin oxide (ITO), indium-zinc oxide, and ZnO can be used. After that, patterning of the first transparent conductive film is performed. In the patterning, for example, wet etching can be performed using an oxalic acid-based etching solution. Thus, the common electrode CE is obtained. The common electrode CE can be disposed, for example, in substantially the entire range of the display region except for the pixel contact hole formation region where the pixel contact hole CHp is formed.

[0365] ·STEP9: Formation of the dielectric layer 17

[0366] Next, a dielectric layer 17 (thickness: 50 to 500 nm) is formed so as to cover the common electrode CE, and patterning of the dielectric layer 17 and the inorganic insulating layer 11 is performed.

[0367] In the pixel region PIX, the dielectric layer 17 is formed on the organic insulating layer 12, the common electrode CE, and within the first opening. The material of the dielectric layer 17 can be the same as the materials exemplified as the material of the inorganic insulating layer 11. Here, as the dielectric layer 17, for example, a SiN film is formed by CVD.

[0368] After that, a barrier layer (not shown) formed on the dielectric layer 17 is formed by a photolithography process. Using the barrier layer and the organic insulating layer 12 as masks, etching of the dielectric layer 17 and the inorganic insulating layer 11 (for example, dry etching) is performed. The etching of the dielectric layer 17 and the inorganic insulating layer 11 can be performed by the same etching process. Thus, a pixel contact hole CHp that exposes a part of the second region of the oxide semiconductor layer 207 is formed in the pixel region PIX. The pixel contact hole CHp is composed of an opening formed in the inorganic insulating layer 11, a first opening of the organic insulating layer 12, and an opening of the dielectric layer 17.

[0369] ·STEP10: Formation of the pixel electrode PE

[0370] Next, a second transparent conductive film (thickness: 20 to 300 nm), not shown, is formed on the dielectric layer 17 and within the pixel contact hole CHp. The material of the second transparent conductive film can be the same as the materials exemplified as the material of the second transparent conductive film (for example, ITO).

[0371] After that, patterning of the second transparent conductive film is performed. For example, wet etching of the second transparent conductive film can be performed using an oxalic acid-based etching solution. Thereby, the pixel electrode PE is obtained. The pixel electrode PE is formed on the dielectric layer 17 and within the pixel contact hole CHp in the pixel region PIX, and is connected to the drain electrode DE2 of the pixel TFT within the pixel contact hole CHp. In this way, the active matrix substrate 1001 is manufactured.

[0372] (Regarding the oxide semiconductor)

[0373] The oxide semiconductor contained in the oxide semiconductor layer of each TFT in the present embodiment may be an amorphous oxide semiconductor or a crystalline oxide semiconductor having a crystalline portion. Examples of the crystalline oxide semiconductor include a polycrystalline oxide semiconductor, a microcrystalline oxide semiconductor, and a crystalline oxide semiconductor in which the c-axis is substantially perpendicular to the plane.

[0374] The oxide semiconductor layer may have a stacked structure of two or more layers. When the oxide semiconductor layer has a stacked structure, the oxide semiconductor layer may include an amorphous oxide semiconductor layer and a crystalline oxide semiconductor layer. Alternatively, it may include a plurality of crystalline oxide semiconductor layers having different crystal structures. In addition, it may also include a plurality of amorphous oxide semiconductor layers. When the oxide semiconductor layer has a two-layer structure including an upper layer and a lower layer, the energy gap of the oxide semiconductor contained in the layer on the gate electrode side (the lower layer in the case of a bottom gate structure and the upper layer in the case of a top gate structure) may be smaller than the energy gap of the oxide semiconductor contained in the layer on the side opposite to the gate electrode (the upper layer in the case of a bottom gate structure and the lower layer in the case of a top gate structure). However, when the difference in energy gaps between these layers is relatively small, the energy gap of the oxide semiconductor in the layer on the gate electrode side may also be larger than the energy gap of the oxide semiconductor in the layer on the side opposite to the gate electrode.

[0375] The materials, structures, film formation methods, and configurations of the stacked oxide semiconductor layers of the amorphous oxide semiconductor and the above-described crystalline oxide semiconductors are described in, for example, Japanese Patent Application Laid-Open No. 2014-007399. For reference, the entire disclosure of Japanese Patent Application Laid-Open No. 2014-007399 is incorporated herein by reference.

[0376] The oxide semiconductor layer may contain at least one metal element such as In, Ga, and Zn. In the present embodiment, the oxide semiconductor layer contains, for example, an In-Ga-Zn-O-based semiconductor (such as indium gallium zinc oxide). Here, the In-Ga-Zn-O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the ratios (composition ratios) of In, Ga, and Zn are not particularly limited. For example, it includes In:Ga:Zn = 2:2:1, In:Ga:Zn = 1:1:1, In:Ga:Zn = 1:1:2, etc. Such an oxide semiconductor layer can be formed from an oxide semiconductor film containing an In-Ga-Zn-O-based semiconductor.

[0377] The In-Ga-Zn-O-based semiconductor can be amorphous or crystalline. As the crystalline In-Ga-Zn-O-based semiconductor, a crystalline In-Ga-Zn-O-based semiconductor in which the c-axis is oriented substantially perpendicular to the plane is preferred.

[0378] In addition, the crystal structure of the crystalline In-Ga-Zn-O-based semiconductor is disclosed, for example, in the above-mentioned Japanese Unexamined Patent Application Publication No. 2014-007399, Japanese Unexamined Patent Application Publication No. 2012-134475, Japanese Unexamined Patent Application Publication No. 2014-209727, etc. For reference, the entire disclosures of Japanese Unexamined Patent Application Publication No. 2012-134475 and Japanese Unexamined Patent Application Publication No. 2014-209727 are incorporated herein by reference. The TFT having an In-Ga-Zn-O-based semiconductor layer has a high mobility (more than 20 times that of an a-Si TFT) and a low leakage current (less than one percent that of an a-Si TFT). Therefore, it is suitable for use as a driving TFT (for example, a TFT included in a driving circuit provided on the same substrate as a display area including a plurality of pixels) and a pixel TFT (a TFT provided in a pixel).

[0379] The oxide semiconductor layer may also contain other oxide semiconductors to replace the In-Ga-Zn-O based semiconductor. For example, it may contain an In-Sn-Zn-O based semiconductor (such as In2O3-SnO2-ZnO; InSnZnO). The In-Sn-Zn-O based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Alternatively, the oxide semiconductor layer may also contain an In-Al-Zn-O based semiconductor, an In-Al-Sn-Zn-O based semiconductor, a Zn-O based semiconductor, an In-Zn-O based semiconductor, a Zn-Ti-O based semiconductor, a Cd-Ge-O based semiconductor, a Cd-Pb-O based semiconductor, CdO (cadmium oxide), a Mg-Zn-O based semiconductor, an In-Ga-Sn-O based semiconductor, an In-Ga-O based semiconductor, a Zr-In-Zn-O based semiconductor, a Hf-In-Zn-O based semiconductor, an Al-Ga-Zn-O based semiconductor, a Ga-Zn-O based semiconductor, an In-Ga-Zn-Sn-O based semiconductor, an In-W-Zn-O based semiconductor, etc.

Claims

1. An active matrix substrate, characterized in that, having: a substrate; a plurality of source buses and a plurality of gate buses supported on the substrate; and a plurality of oxide semiconductor TFTs supported on the substrate, each oxide semiconductor TFT having an oxide semiconductor layer, a gate electrode disposed on a part of the oxide semiconductor layer with a gate insulating layer therebetween, and a source electrode and a drain electrode, the oxide semiconductor layer including a channel region, a source contact region electrically connected to the source electrode, and a drain contact region electrically connected to the drain electrode, the channel region being a region that overlaps with the gate electrode and is located between the source contact region and the drain contact region when viewed from the normal direction of the substrate, when viewed from the normal direction of the substrate, the channel region has: a first end portion and a second end portion that face each other and extend in a first direction from the source contact region side toward the drain contact region side; a source-side end portion that is located on the source contact region side of the first end portion and the second end portion and extends in a second direction intersecting with the first direction; and a drain-side end portion that is located on the drain contact region side of the first end portion and the second end portion and extends in the second direction, the plurality of oxide semiconductor TFTs including a plurality of first TFTs, each first TFT further having a light-shielding layer located between the oxide semiconductor layer and the substrate, when viewed from the normal direction of the substrate, the light-shielding layer includes: an opening region that overlaps with a part of the channel region; and a light-shielding region that overlaps with another part of the channel region, when viewed from the normal direction of the substrate, the light-shielding region includes: a first light-shielding portion that extends along the first direction on the first end portion of the channel region; and a second light-shielding portion that extends along the first direction on the second end portion of the channel region, when viewed from the normal direction of the substrate, the first light-shielding portion and the second light-shielding portion respectively have a first edge portion and a second edge portion that face each other and extend in the first direction, at least a part of the first edge portion overlaps with the channel region, and the second edge portion is located outside the channel region and does not overlap with the channel region.

2. The active matrix substrate according to claim 1, wherein in each of the first TFTs, when viewed from the normal direction of the substrate, the light-shielding layer further includes: a third light-shielding portion that extends along the second direction on the source-side end portion of the channel region; and a fourth light-shielding portion that extends along the second direction on the drain-side end portion of the channel region, the third light-shielding portion and the fourth light-shielding portion respectively have a third edge portion and a fourth edge portion that face each other and extend in the second direction, at least a part of the third edge portion overlaps with the channel region, and the fourth edge portion is located outside the channel region and does not overlap with the channel region.

3. The active matrix substrate according to claim 1 or 2, wherein In each of the above-described first TFTs, the length of the portion of the first end portion covered by the first light-shielding portion is substantially equal to the length of the portion of the second end portion covered by the second light-shielding portion.

4. The active matrix substrate according to claim 1 or 2, wherein in each of the above-described first TFTs, the widths of the first light-shielding portion and the second light-shielding portion in the direction orthogonal to the first direction are 3 μm or more and less than 1 / 2 of the channel width of each of the first TFTs.

5. The active matrix substrate according to claim 1 or 2, wherein in each of the above-described first TFTs, when viewed from the normal direction of the substrate, the light-shielding layer further includes an intermediate light-shielding portion located between the first light-shielding portion and the second light-shielding portion and at least partially overlapping the channel region, when viewed from the normal direction of the substrate, the opening region includes a first opening region and a second opening region disposed sandwiching the intermediate light-shielding portion.

6. An active matrix substrate, characterized in that, comprising: a substrate; a plurality of source buses and a plurality of gate buses supported by the substrate; and a plurality of oxide semiconductor TFTs supported by the substrate, each oxide semiconductor TFT having an oxide semiconductor layer, a gate electrode disposed on a part of the oxide semiconductor layer with a gate insulating layer interposed therebetween, and a source electrode and a drain electrode, the oxide semiconductor layer includes a channel region, a source contact region electrically connected to the source electrode, and a drain contact region electrically connected to the drain electrode, the channel region is a region that is located between the source contact region and the drain contact region and overlaps the gate electrode when viewed from the normal direction of the substrate, when viewed from the normal direction of the substrate, the channel region has: a first end portion and a second end portion that face each other and extend in a first direction from the source contact region side toward the drain contact region side; a source-side end portion that is located on the source contact region side of the first end portion and the second end portion and extends in a second direction intersecting the first direction; and a drain-side end portion that is located on the drain contact region side of the first end portion and the second end portion and extends in the second direction, the plurality of oxide semiconductor TFTs include a plurality of first TFTs, and each first TFT further has a light-shielding layer located between the oxide semiconductor layer and the substrate, when viewed from the normal direction of the substrate, the light-shielding layer includes: an opening region that overlaps a part of the channel region; and a light-shielding region that overlaps another part of the channel region, when viewed from the normal direction of the substrate, the light-shielding region further includes: a third light-shielding portion that extends along the second direction on the source-side end portion of the channel region; and a fourth light-shielding portion that extends along the second direction on the drain-side end portion of the channel region, The above-described third light-shielding portion and the above-described fourth light-shielding portion respectively have a third edge portion and a fourth edge portion that face each other and extend in the above-described second direction. At least a part of the third edge portion overlaps with the channel region, and the fourth edge portion is located outside the channel region and does not overlap with the channel region.

7. The active matrix substrate according to claim 2 or 6, wherein in each of the first TFTs, the length of the portion of the source-side end covered by the third light-shielding portion is substantially equal to the length of the portion of the drain-side end covered by the fourth light-shielding portion.

8. The active matrix substrate according to claim 2 or 6, wherein in each of the first TFTs, the width of the third light-shielding portion and the fourth light-shielding portion in the direction orthogonal to the second direction is 3 μm or more and less than 1 / 2 of the channel length of each of the first TFTs.

9. The active matrix substrate according to any one of claims 1, 2, and 6, wherein in each of the first TFTs, when viewed from the normal direction of the substrate, the opening region includes an opening portion, a cut portion, or a concave portion of the light-shielding layer.

10. The active matrix substrate according to any one of claims 1, 2, and 6, wherein in at least a part of the plurality of first TFTs, the gate electrode includes a first gate portion and a second gate portion that are electrically connected to each other, when viewed from the normal direction of the substrate, the channel region includes a first channel portion that overlaps with the first gate portion, and a second channel portion that is located on the drain electrode side with respect to the first channel portion and overlaps with the second gate portion, when viewed from the normal direction of the substrate, the light-shielding layer includes a first layer that overlaps with a part of the first channel portion, and a second layer that overlaps with a part of the second channel portion, the first end portion of the channel region includes the ends of the first channel portion and the second channel portion that extend in the first direction, and the second end portion includes the ends of the first channel portion and the second channel portion that face the first end portion and extend in the first direction, the source-side end portion is the end portion located on the source contact region side of the first channel portion, and the drain-side end portion is the end portion located on the drain contact region side of the second channel portion.

11. The active matrix substrate according to claim 10, wherein the at least a part of the first TFTs further includes an intermediate electrode, when viewed from the normal direction of the substrate, the intermediate electrode is electrically connected to the portion of the oxide semiconductor layer located between the first channel portion and the second channel portion.

12. The active matrix substrate according to any one of claims 1, 2, and 6, wherein When viewed from the normal direction of the above-mentioned substrate, the above-mentioned channel regions of the above-mentioned first TFTs each have: a light-shielded portion that overlaps with the above-mentioned light-shielded region of the above-mentioned light-shielding layer; and an irradiated portion that overlaps with the above-mentioned opening region of the above-mentioned light-shielding layer, and the ratio AR of the area of the above-mentioned light-shielded portion to the area of the above-mentioned channel region is 25% or more and 75% or less.

13. The active matrix substrate according to any one of claims 1, 2, and 6, wherein the above-mentioned active matrix substrate has: a display region that includes a plurality of pixel regions; and a non-display region that is located on the periphery of the display region and includes a circuit formation region in which peripheral circuits are formed, the above-mentioned plurality of first TFTs are arranged in the above-mentioned circuit formation region.

14. The active matrix substrate according to claim 13, wherein the above-mentioned peripheral circuit includes an SSD circuit that distributes display signals to n source buses among the above-mentioned plurality of source buses, the above-mentioned plurality of first TFTs include a plurality of SSD circuit TFTs that constitute the above-mentioned SSD circuit, and each SSD circuit TFT supplies a video signal to a corresponding one of the above-mentioned n source buses.

15. The active matrix substrate according to claim 14, wherein no other TFTs are formed between the above-mentioned plurality of SSD circuit TFTs and the above-mentioned display region.

16. The active matrix substrate according to claim 14, wherein the above-mentioned SSD circuit further includes a plurality of compensation TFTs respectively connected to a corresponding one of the above-mentioned n source buses, a signal having a phase opposite to that of the control signal supplied to the gate electrode of the SSD circuit TFT connected to the same source bus is supplied to the gate electrode of each compensation TFT, the first TFT formation region in which the above-mentioned plurality of SSD circuit TFTs are arranged is located between the second TFT formation region in which the above-mentioned plurality of compensation TFTs are arranged and the above-mentioned display region.

17. The active matrix substrate according to claim 13, wherein the above-mentioned peripheral circuit further includes a gate driver connected to the above-mentioned plurality of gate buses, and the above-mentioned plurality of first TFTs include a plurality of gate driver TFTs that constitute the above-mentioned gate driver.

18. The active matrix substrate according to claim 13, wherein the above-mentioned plurality of oxide semiconductor TFTs further include a second TFT arranged in each pixel region of the above-mentioned plurality of pixel regions, each second TFT has another light-shielding layer located between the above-mentioned oxide semiconductor layer and the above-mentioned substrate, and when viewed from the normal direction of the above-mentioned substrate, the above-mentioned another light-shielding layer overlaps with the entire above-mentioned channel region of the above-mentioned second TFT.

19. The active matrix substrate according to any one of claims 1, 2, and 6, wherein the above-mentioned oxide semiconductor layer includes an In-Ga-Zn-O-based semiconductor.

20. The active matrix substrate according to claim 19, wherein the above-mentioned In-Ga-Zn-O-based semiconductor includes a crystalline portion.

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