Single-bit sigma delta dac circuit

Abstract

The application discloses a single-bit sigma delta DAC circuit. The application comprises an up-sampling filter, a high-order single-bit sigma delta modulator, a 1-bit DAC circuit and a threshold generating module. The high-order single-bit sigma delta modulator comprises a noise shaping filter and a quantizer. The threshold generating module comprises a high-low level conversion frequency statistical device, a maximum threshold limiting device and a threshold adjusting device. The high-low level conversion frequency statistical device counts the high-low level conversion frequency of the quantizer output signal per unit time; the maximum threshold limiting device determines the maximum threshold according to the input signal amplitude; and the threshold adjusting device receives the high-low level conversion frequency of the quantizer output signal and the maximum threshold, and inputs the current threshold into the quantizer in combination with the built-in setting frequency. The application saves the circuit cost, avoids the introduced nonlinear error, and reduces the cost and implementation difficulty of the 1-bit DAC.

Description

Technical Field

[0001] This invention belongs to the field of signal processing technology, especially the field of digital-to-analog converter (DAC) technology, and relates to a high-performance single-bit sigma delta DAC circuit with bit-width modulation. Background Technology

[0002] A DAC converts digital signals into analog signals and is a commonly used functional module in modern digital signal processing. The Sigma delta DAC is a DAC technology based on oversampling and noise shaping, widely used in the low-to-medium speed, high-precision DAC field. Sigma delta DACs are divided into single-bit quantization and multi-bit quantization. Because single-bit quantization has inherently high linearity and avoids the requirement for component matching accuracy, it has become an important area of ​​application.

[0003] Existing single-bit sigma-delta DACs use a high-order single-bit sigma-delta modulator to generate a 1-bit data stream, which is then connected to a 1-bit DAC. To achieve the same DAC performance, single-bit sigma-delta DACs require a larger oversampling frequency compared to multi-bit sigma-delta DACs, thus increasing the frequency requirement for the 1-bit DAC. Some solutions, such as patent US20050007266A1, use a multi-bit sigma-delta modulator connected in series with a PWM generator to reduce the frequency requirement for the 1-bit DAC. However, this adds a PWM generator, increasing circuit cost, and the PWM generator also introduces signal errors. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of high-performance single-bit sigma delta DACs that have excessively high frequency requirements for 1-bit DACs, and to provide a high-performance single-bit sigma delta DAC circuit that reduces the signal switching frequency of 1-bit DACs.

[0005] This invention includes an upsampling filter UP, an adjustable-threshold high-order single-bit sigma-delta modulator SDM, a 1-bit DAC circuit, and a threshold generation module T. The high-order single-bit sigma-delta modulator SDM includes a noise shaping filter F and an adjustable-threshold quantizer Q. The quantizer Q compares the output value of the noise shaping filter F with the threshold: if the output value of the noise shaping filter F is greater than the positive threshold, the output value of the quantizer Q is 1; if the output value of the noise shaping filter F is less than the negative threshold, the output value of the quantizer Q is -1; if the output value of the noise shaping filter F is less than or equal to the positive threshold and greater than or equal to the negative threshold, the output value of the quantizer Q is the output value of the previous clock cycle.

[0006] The upsampling filter UP receives external digital signals at its input terminal and is connected to the signal input terminal of the noise shaping filter F. The signal output terminal of the noise shaping filter F is connected to the signal input terminal of the quantizer Q.

[0007] The threshold generation module T includes a device for counting the number of high-low level transitions per unit time, a maximum threshold limiting device, and a threshold adjustment device. Among them:

[0008] The input terminal of the device for counting the number of high-low level transitions of the signal per unit time is connected to the signal output terminal of the quantizer Q. It counts the number of high-low level transitions of the output signal of the quantizer Q per unit time, that is, the number of transitions between the output value 1 and -1 of the quantizer Q: at the beginning of detection, the number of transitions is 0; if the output of the quantizer Q of the current clock is different from the output of the quantizer Q of the previous clock, the number of transitions is incremented by 1; if they are the same, the number of transitions remains unchanged; the total number of transitions at the end of the unit time is the number of high-low level transitions of the output signal of the quantizer Q per unit time. The output terminal of the device for counting the number of high-low level transitions of the signal per unit time is connected to the input terminal of the threshold adjustment device, and the number of high-low level transitions of the quantizer output signal per unit time is sent to the threshold adjustment device.

[0009] The input terminal of the maximum threshold limiting device is connected to the signal input terminal of the upsampling filter UP, receiving the input signal from the receiving circuit; the maximum threshold limiting device has a built-in lookup table, which sets the maximum threshold corresponding to different amplitude values; the maximum threshold limiting device determines the maximum threshold based on the amplitude of the input signal of each clock circuit; the output terminal of the maximum threshold limiting device is connected to the maximum threshold input terminal of the threshold adjustment device, sending the maximum threshold information to the threshold adjustment device.

[0010] The threshold adjustment device has a built-in preset number of times. It receives the number of high-to-low level transitions of the quantizer output signal per unit time, as well as the maximum threshold information. If the received number of transitions per unit time is greater than or equal to the preset number, and the current threshold is less than the maximum threshold, the threshold adjustment device adds 1 unit to the current threshold. If the current threshold is equal to the maximum threshold, the current threshold remains unchanged. If the number of transitions per unit time is less than the preset number, and the current threshold is greater than 0, the threshold adjustment device subtracts 1 unit from the current threshold. If the current threshold is equal to 0, the current threshold remains unchanged. The initial threshold value of the threshold adjustment device is 0. The threshold output terminal of the threshold adjustment device is connected to the threshold input terminal of the quantizer Q. Inputting the current threshold into the quantizer Q results in a positive threshold, and the negative threshold is the negative threshold.

[0011] The signal output terminal of the quantizer Q and the feedback input terminal of the noise shaping filter F are connected to the signal input terminal of the 1-bit DAC circuit. The signal output terminal of the 1-bit DAC circuit serves as the output terminal of the overall circuit, outputting an analog signal.

[0012] Upsampling filters are a mature, existing technology that transforms low-sampling-rate signals into high-sampling-rate signals.

[0013] A 1-bit DAC circuit is a mature, existing technology that converts digital signals into analog low and high levels.

[0014] High-order single-bit sigma delta modulators are a mature, existing technology that shifts quantization noise from the low-frequency band to the high-frequency band.

[0015] Compared to existing technologies that use sigma-delta modulators and PWM generators to generate 1-bit signals, this invention eliminates the need for a PWM generator, saving circuit costs and avoiding the nonlinear errors introduced by PWM generators. Compared to the original sigma-delta modulator, this invention dynamically adjusts the quantizer threshold based on the number of output conversions per unit time, reducing the number of conversions of the 1-bit DAC input signal per unit time. This lowers the operating frequency requirement for the 1-bit DAC, reduces the physical implementation requirements, and lowers the cost and implementation difficulty. However, increasing the quantizer threshold reduces the dynamic range of the DAC signal. This invention protects the maximum threshold of the quantizer, avoiding the drawback of reduced DAC dynamic range due to dynamic threshold adjustment introduced by the quantizer. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure of the present invention. Detailed Implementation

[0017] The present invention will be further described below with reference to embodiments. These embodiments are merely specific examples of the present invention, but the design concept of the present invention is not limited thereto. Any non-substantial modifications made to the present invention using this concept should fall within the protection scope of the present invention.

[0018] like Figure 1 As shown, a single-bit sigma-delta DAC circuit includes an upsampling filter UP, an adjustable-threshold high-order single-bit sigma-delta modulator SDM, a 1-bit DAC circuit, and a threshold generation module T. The high-order single-bit sigma-delta modulator SDM includes a noise shaping filter F and an adjustable-threshold quantizer Q. The signal input terminal 1 of the upsampling filter UP receives an external digital signal, the signal output terminal 2 is connected to the signal input terminal 3 of the noise shaping filter F, and the signal output terminal 4 of the noise shaping filter F is connected to the signal input terminal 5 of the quantizer Q.

[0019] The upsampling filter (UP) transforms a low-sampling-rate signal into a high-sampling-rate signal. A 1-bit DAC circuit converts a digital signal into analog low and high levels. A high-order single-bit sigma-delta modulator (SDM) shifts low-frequency quantization noise to higher frequencies. Specifically, the quantizer Q compares the output value of the noise-shaping filter F with a threshold: if the output value of the noise-shaping filter F is greater than the positive threshold, the output value of the quantizer Q is 1; if the output value of the noise-shaping filter F is less than the negative threshold, the output value of the quantizer Q is -1; if the output value of the noise-shaping filter F is less than or equal to the positive threshold and greater than or equal to the negative threshold, the output value of the quantizer Q is the output value of the previous clock cycle.

[0020] The threshold generation module T includes a device A that counts the number of high-low level transitions per unit time, a maximum threshold limiting device B, and a threshold adjustment device C. Wherein:

[0021] Input 6 of the high-low level conversion count device A is connected to signal output 7 of quantizer Q. It counts the number of high-low level conversions of the quantizer Q's output signal per unit time, i.e., the number of conversions between the output value 1 and -1 of quantizer Q: At the start of detection, the conversion count is 0; if the output of quantizer Q in the current clock is different from the output of quantizer Q in the previous clock, the conversion count is incremented by 1; if they are the same, the conversion count remains unchanged; the total number of conversions at the end of the unit time is the number of high-low level conversions of the quantizer Q's output signal per unit time. Output 8 of the high-low level conversion count device A is connected to input 9 of the high-low level conversion count of the threshold adjustment device C, sending the number of high-low level conversions of the quantizer output signal per unit time to the threshold adjustment device C.

[0022] The input terminal 10 of the maximum threshold limiting device B is connected to the signal input terminal 1 of the upsampling filter UP to receive the input signal of the receiving circuit; the maximum threshold limiting device B has a built-in lookup table, which sets the maximum threshold corresponding to different amplitude values; the maximum threshold limiting device B determines the maximum threshold according to the amplitude of the input signal of each clock circuit; the output terminal 11 of the maximum threshold limiting device B is connected to the maximum threshold input terminal 12 of the threshold adjustment device C to send the maximum threshold information to the threshold adjustment device C.

[0023] The threshold adjustment device C has a built-in set number of times. The threshold adjustment device C receives the number of high-low level transitions of the quantizer output signal per unit time, as well as the maximum threshold information: If the received number of transitions per unit time is greater than or equal to the set number, and the current threshold is less than the maximum threshold, the threshold adjustment device adds 1 unit to the current threshold; if the current threshold is equal to the maximum threshold, the current threshold remains unchanged. If the number of transitions per unit time is less than the set number, and the current threshold is greater than 0, the threshold adjustment device subtracts 1 unit from the current threshold; if the current threshold is equal to 0, the current threshold remains unchanged. The initial value of the threshold adjustment device is 0. The threshold output terminal 13 of the threshold adjustment device is connected to the threshold input terminal 14 of the quantizer Q. The current threshold is input to the quantizer Q, and the current threshold is the positive threshold. The negative value of the current threshold is the negative threshold.

[0024] The signal output terminal 7 of the quantizer Q and the feedback input terminal 15 of the noise shaping filter F are connected to the signal input terminal 16 of the 1-bit DAC circuit. The signal output terminal 17 of the 1-bit DAC circuit serves as the output terminal of the overall circuit, outputting an analog signal.

[0025] In this embodiment, the input signal is a digital signal with a sampling rate of 48kHz, the sigma-delta modulator (SDM) operates at 12.288MHz, and the oversampling rate is 256 times. The threshold generation module T calculates the quantizer output unit time as 1ms. Without using this circuit, the quantizer threshold is 0, and a 1-bit DAC flips a maximum of 12288 times within 1ms.

[0026] The set number of times is 768, which means that the maximum number of flips is set to 768 within 1 second.

[0027] Assuming the initial threshold of the threshold generation module is 0, and the threshold change unit of the threshold generation module is 1 / 1024, the number of changes in the quantizer output within 1 ms is much higher than the set number of 768. Therefore, the threshold of the threshold generation module rises rapidly, thus quickly reducing the number of changes in the quantizer output within 1 ms. When the number of changes in the quantizer output within 1 ms is less than 768, the threshold of the threshold generation module will decrease, thus increasing the number of changes in the quantizer output within 1 ms. Ultimately, the threshold of the threshold generation module will fluctuate within a small range, stabilizing the number of changes in the quantizer output within 1 ms at around 768, a 16-fold reduction compared to the original 12288, significantly reducing the frequency requirement of the 1-bit DAC and the physical implementation requirements of the 1-bit DAC. The maximum threshold limiting device B has a built-in lookup table that outputs 1 / 16 when the input signal amplitude is greater than 0.5 or less than -0.5; and 1 / 8 when the input signal amplitude is less than or equal to 0.5 and greater than or equal to 0.5. Exceeding the quantizer's threshold will reduce the dynamic range of the DAC. Since the number of changes in the quantizer output within 1 ms is inversely proportional to the absolute value of the input signal amplitude, using a smaller maximum threshold limit will not reduce the dynamic range of the DAC when the input signal amplitude is large.

[0028] It should be understood that the above examples are merely illustrative of the present invention and not limitations thereof. Any invention that does not exceed the essential spirit and scope of the present invention falls within the protection scope of the present invention.

Claims

1. A single-bit sigma-delta DAC circuit, comprising an upsampling filter UP, an adjustable-threshold high-order single-bit sigma-delta modulator SDM, and a 1-bit DAC circuit, wherein the high-order single-bit sigma-delta modulator SDM comprises a noise shaping filter F and an adjustable-threshold quantizer Q; the signal input terminal of the upsampling filter UP serves as the input terminal of the overall circuit to receive external digital signals, and its signal output terminal is connected to the signal input terminal of the noise shaping filter F, the signal output terminal of the noise shaping filter F being connected to the signal input terminal of the quantizer Q; characterized in that: It also includes a threshold generation module T; The threshold generation module T includes a device for counting the number of high-low level transitions per unit time, a maximum threshold limiting device, and a threshold adjustment device; wherein: The input terminal of the device for counting the number of high-low level transitions per unit time is connected to the signal output terminal of the quantizer Q. It counts the number of high-low level transitions of the quantizer Q's output signal per unit time: the transition count is 0 at the start of detection; if the output of the quantizer Q in the current clock is different from the output of the quantizer Q in the previous clock, the transition count is incremented by 1; if they are the same, the transition count remains unchanged; the total number of transitions at the end of the unit time is the number of high-low level transitions of the quantizer Q's output signal per unit time. The output terminal of the device for counting the number of high-low level transitions per unit time is connected to the input terminal of the threshold adjustment device, sending the number of high-low level transitions of the quantizer output signal per unit time to the threshold adjustment device. The input terminal of the maximum threshold limiting device is connected to the signal input terminal of the upsampling filter UP, receiving the input signal from the receiving circuit; the maximum threshold limiting device has a built-in lookup table, which sets the maximum threshold corresponding to different amplitude values; the maximum threshold limiting device determines the maximum threshold based on the amplitude of the input signal of each clock circuit; the output terminal of the maximum threshold limiting device is connected to the maximum threshold input terminal of the threshold adjustment device, sending the maximum threshold information to the threshold adjustment device. The threshold adjustment device has a built-in preset number of times. It receives the number of high-to-low level transitions of the quantizer output signal per unit time, as well as the maximum threshold information. If the received number of transitions per unit time is greater than or equal to the preset number, and the current threshold is less than the maximum threshold, the threshold adjustment device adds 1 unit to the current threshold. If the current threshold is equal to the maximum threshold, the current threshold remains unchanged. If the number of transitions per unit time is less than the preset number, and the current threshold is greater than 0, the threshold adjustment device subtracts 1 unit from the current threshold. If the current threshold is equal to 0, the current threshold remains unchanged. The initial threshold value of the threshold adjustment device is 0. The threshold output terminal of the threshold adjustment device is connected to the threshold input terminal of the quantizer Q. Inputting the current threshold into the quantizer Q results in a positive threshold, and the negative threshold is the negative threshold. The signal output terminal of the quantizer Q and the feedback input terminal of the noise shaping filter F are connected to the signal input terminal of the 1-bit DAC circuit. The signal output terminal of the 1-bit DAC circuit serves as the output terminal of the overall circuit, outputting an analog signal.

2. The single-bit sigma-delta DAC circuit as described in claim 1, characterized in that: The quantizer Q compares the output value of the noise shaping filter F with a positive threshold and a negative threshold: if the output value of the noise shaping filter F is greater than the positive threshold, the output value of the quantizer Q is 1; if the output value of the noise shaping filter F is less than the negative threshold, the output value of the quantizer Q is -1; if the output value of the noise shaping filter F is less than or equal to the positive threshold and greater than or equal to the negative threshold, the output value of the quantizer Q is the output value of the previous clock cycle.

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