Split protocol approach to enable access to enhanced persistent memory zones

Abstract

The present disclosure relates to a split protocol approach to accessing a device enabled with an enhanced persistent memory region. A host command is received to configure a system to have a configuration of a first interface standard specified at a first port for exposing a storage element and a second interface standard specified at a second port for exposing a persistent memory region (PMR). The storage element is implemented on a first memory device of the system and the PMR is implemented on a second memory device of the system. The second interface standard implements one or more alternative protocols supported by the first interface standard. The system is configured in accordance with the configuration.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically to a split protocol approach for enabling devices with enhanced persistent memory regions (PMRs). Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. Generally, a host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure provides a system comprising: a first memory device including a non-volatile memory device; a second memory device; and a processing means operatively coupled to the first and second memory devices to perform operations including: receiving a host command to configure the system to have a configuration that specifies a first interface standard at a first port for exposing storage elements implemented on the first memory device and a second interface standard at a second port for exposing persistent memory regions (PMRs) implemented on the second memory device, wherein the second interface standard implements one or more alternative protocols supported by the first interface standard; and configuring the system according to the configuration.

[0004] Another aspect of this disclosure provides a method comprising: receiving a host command to configure a system to have a configuration specifying a first interface standard for exposing storage elements at a first port and a second interface standard for exposing persistent memory regions (PMRs) at a second port, the storage elements being implemented on a first memory device of the system and the PMRs being implemented on a second memory device of the system, wherein the first memory device includes a non-volatile memory device and the second interface standard implements one or more alternative protocols supported by the first interface standard; and configuring the system according to the configuration.

[0005] Another aspect of this disclosure provides a non-transitory computer-readable storage medium including instructions that, when executed by a processing means, cause the processing means to perform operations including: booting a system comprising a first memory means and a second memory means including a non-volatile memory means to have a first configuration associated with a first interface standard; receiving a host command to configure the system to have a second configuration having a first interface standard at a first port for exposing storage elements implemented on the first memory means and a second interface standard at a second port for exposing persistent memory regions (PMRs) implemented on the second memory means, wherein the second interface standard implements one or more alternative protocols supported by the first interface standard; and configuring the system according to the second configuration. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof. However, the drawings should not be construed as limiting this disclosure to the specific embodiments, but are for explanation and understanding only.

[0007] Figure 1 This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 2 This is a flowchart illustrating an example method of a split protocol approach for an enhanced persistent memory region (PMR) access enabling device, according to some embodiments of this disclosure.

[0009] Figure 3 This is a block diagram of an example system of a split protocol approach for an enhanced persistent memory region (PMR) access enablement device, according to some embodiments of the present disclosure.

[0010] Figure 4 This is a block diagram of an example system of a device with enhanced persistent memory region (PMR) access enabled, according to some embodiments of the present disclosure.

[0011] Figure 5 The following is a block diagram illustrating a system for performing capacitor (CAP) testing according to some embodiments of the present invention.

[0012] Figure 6 This is a block diagram of an example computer system in which embodiments of the present disclosure may be operated. Detailed Implementation

[0013] Various aspects of this disclosure relate to implementing a splitting protocol approach for devices having persistent memory regions (PMRs). The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. The following is combined with... Figure 1Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data to be stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0014] The memory subsystem may include high-density non-volatile memory devices, where data retention is required when no power is supplied to the memory devices. An example of a non-volatile memory device is a NAND flash memory device. The following section combines... Figure 1 Other examples of non-volatile memory devices are described. A non-volatile memory device is a package of one or more dies. Each die may consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and has various logic states associated with the number of bits being stored. Logic states may be represented by binary values ​​(such as “0” and “1”) or combinations of such values.

[0015] For various implementations or use cases that can utilize transaction-oriented persistent memory, the area of ​​byte-addressable memory exposed alongside block storage elements has become more important, and modern applications have a significantly increased reliance on transaction consistency. Exemplary implementations that can utilize transaction-oriented persistent memory include, but are not limited to: write logs, logs of software RAID and erase-encoded systems, commit logs of databases, metadata of compressed volumes, deduplication, segmentation of compression, status delivery in failover environments, error / warning logs (e.g., device breadcrumbs), compressed metadata tables for through-block compression, and metadata of cooperative storage domains (e.g., virtual drive groups).

[0016] One implemented solution is to use non-volatile dual in-line memory modules (NVDIMMs). However, NVDIMM implementations can be expensive and have their own limitations. For example, NVDIMMs may become impractical in the future because the technology may not be easily applied to modern system architectures, and because its protection mechanisms between nodes cannot be scaled accordingly.

[0017] Memory devices (e.g., solid-state drives (SSDs)) in a memory subsystem can be accessed via a logical device interface attached to a bus. An example of such a logical device interface for accessing memory devices is Non-Volatile Memory High Speed ​​(NVMe). A host system (“host”) can access the memory subsystem via, for example, a Peripheral Component Interconnect High Speed ​​(PCIe) bus, and access to memory devices in the memory subsystem may be referred to herein as PCIe NVMe. More specifically, a memory subsystem (e.g., an SSD) may include storage elements and persistent memory regions (PMRs). For example, storage elements may include block storage elements. A PMR corresponds to a region of readable persistent memory implemented as a power-protected volatile memory device (e.g., power-protected dynamic random access memory (DRAM)). More specifically, a PMR may be a byte-addressable memory region accessible via a base address register (BAR). An NVMe SSD connected to a memory device may include a PMR, and such a device is referred to as an NVMe SSD device with a PMR.

[0018] While devices such as NVMe SSDs with PMR can provide the desired system-exposed byte-addressable memory alongside the storage element, the potential lack of caching capabilities and / or consistency makes such devices less useful, as it makes management more difficult, may require custom software, and can potentially limit performance. Additionally, for many solutions, the memory resizing within the PMR may be too small. Therefore, these exemplary drawbacks limit widespread industry adoption as a solution that can leverage transaction-oriented persistent memory.

[0019] The aspects of this disclosure address the above and other deficiencies by having a memory subsystem that enables a split protocol approach for access-enabled devices with enhanced PMR. More specifically, a first interface standard can be used to expose storage elements implemented on a non-volatile memory device, and a second interface standard can be used to expose the PMR to access the respective benefits of both the first and second interface standards. For example, the memory subsystem may include an NVMe SSD device with a PMR, wherein the storage elements are NVMe block storage elements. As an example, the PMR may be implemented as a power-protected device on a volatile memory device. Here, the volatile memory device may include DRAM. As another example, the PMR may be implemented on a local non-volatile memory device, such as magnetic RAM (MRAM) or other similar non-volatile memory devices. However, such examples should not be considered limiting. The devices described herein can be used to perform any suitable application. For example, the devices may be implemented as memory buffers to perform one or more persistent memory applications.

[0020] The splitting protocol described herein can be implemented using a dual-port or port forking concept that allocates resources to meet usage objectives and system compatibility. More specifically, a first interface standard for exposing storage elements can be specified at a first port, and a second interface standard for exposing memory resources can be specified at a second port. The second interface standard can implement one or more alternative protocols supported by the first interface standard. For example, the first interface standard can be PCIe, and the second interface standard can implement one or more alternative protocols supported by PCIe (e.g., non-PCIe protocols). Generally, the processor port can be used to negotiate (e.g., auto-negotiate) the PCIe protocol or one or more alternative protocols. For example, the second interface standard can be Compute High-Speed ​​Link (CXL).

[0021] Generally, CXL is an interface standard that supports multiple protocols running on top of PCIe, including the CXL.io, CXL.mem, and CXL.cache protocols. The CXL.io protocol is a PCIe class protocol that can be considered an "enhanced" PCIe protocol. CXL.io can be used for initialization, connection, device discovery and enumeration, and register access, and provides an interface for I / O devices. The CXL.mem protocol enables host access to the memory of attached devices using memory semantics (e.g., load and store commands). This approach supports both volatile and persistent memory architectures. The CXL.cache protocol defines host device interactions to implement efficient caching of host memory with low latency using request and response pathways. Traffic (e.g., NVMe traffic) can be run via the CXL.io protocol, and the CXL.mem and CXL.cache protocols can share a common link layer and transaction layer. Therefore, CXL protocols can be multiplexed and transmitted via the PCIe physical layer.

[0022] If the second interface standard is CXL, then one or more alternative protocols may include at least one of the CXL.io protocol and the CXL.mem protocol or the CXL.cache protocol. More specifically, the split protocol approach described herein supports the CXL.io protocol to allow for protocol setup, configuration, and management. Other aspects of the CXL.io protocol are not required because memory management will be implemented via PCIe. Therefore, as will be described in further detail herein, the CXL.io protocol can be used to expose memory elements, and the CXL.mem protocol and / or the CXL.cache protocol can be used to expose PMR in a manner that provides enhanced PMR access.

[0023] The advantages of this disclosure include, but are not limited to: scalability of storage devices and shared memory from the same apparatus; exposure of byte-addressable memory regions with increased caching capabilities and / or consistency alongside block storage elements; negligible additional latency of block storage elements (e.g., about 25 ns); and compatibility with future central processing units (CPUs) and switching configurations. As an illustrative example, CXL provides memory semantics (e.g., load and store) in a manner that makes it easier to map memory resources containing PMRs into the system in a more cacheable and / or consistent manner.

[0024] Figure 1 An example computing system 100 including a memory subsystem 110 is illustrated according to some embodiments of the present disclosure. The memory subsystem 110 may include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination thereof.

[0025] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0026] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transport), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0027] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediate component), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0028] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). Host system 120 uses memory subsystem 110, for example, to write data to memory subsystem 110 and read data from memory subsystem 110.

[0029] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include, but are not limited to, Serial Advanced Technology Attachment (SATA) interfaces, Peripheral Component Interconnect High Speed ​​(PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Dual Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM sockets supporting Dual Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe bus), host system 120 can further utilize an NVM High Speed ​​(NVMe) interface to access components (e.g., memory device 130). The physical host interface provides an interface for transferring control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1 The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0030] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0031] Some examples of non-volatile memory devices (e.g., memory device 130) include NAND flash memory and in-place write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices, which are crosspoint arrays of non-volatile memory cells. Crosspoint arrays of non-volatile memory cells can perform bit storage based on changes in volume resistance in conjunction with stackable cross-grid data access arrays. Furthermore, crosspoint non-volatile memory can perform in-place write operations, unlike many flash-based memories, where non-volatile memory cells can be programmed without prior erasing. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0032] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell, such as a single-level cell (SLC), may store one bit per cell. Other types of memory cells, such as multi-level cell (MLC), three-level cell (TLC), four-level cell (QLC), and five-level cell (PLC), may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, PLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, QLC portions, or PLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages that may refer to logical units of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0033] Although a 3D cross-point array of non-volatile memory cells and a non-volatile memory component of NAND flash memory (e.g., 2D NAND, 3D NAND) have been described, the memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), select memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0034] The memory subsystem controller 115 (or, for simplicity, controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, or erasing data at the memory device 130, and other such operations. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system with dedicated (i.e., hard-decoded) logic to perform the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0035] The memory subsystem controller 115 may include a processing means comprising one or more processors (e.g., processor 117) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120.

[0036] In some embodiments, local memory 119 may include memory registers that store memory pointers, retrieved data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1 The instance memory subsystem 110 in the present disclosure is described as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115 and may actually rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0037] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may handle other operations, such as wear leveling, garbage collection, error detection and error correction (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130, and translate responses associated with the memory device 130 into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and an address circuitry (e.g., row decoder and column decoder) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0039] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) may externally manage memory device 130 (e.g., perform media management operations on memory device 130). In some embodiments, memory subsystem 110 is a managed memory device, which is the original memory device 130 having on-die control logic (e.g., local controller 132) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

[0040] Split Protocol Control (SPC) component 113 enables a split protocol approach for the memory subsystem 110 (e.g., an NVMe SSD device) with enhanced persistent memory region (PMR) access. More specifically, storage element 137 may be implemented on memory device 130, which corresponds to a non-volatile memory device (e.g., an NVMe SSD block storage element), and PMR 145 may be implemented on memory device 140. For example, memory device 140 may include a volatile memory device (e.g., DRAM), and PMR 145 may be implemented as a power-protected area on the volatile memory device. As another example, memory device 140 may include a non-volatile memory device (e.g., MRAM), and PMR 145 may be implemented on the non-volatile memory device. Upon receiving a host command, SPC component 113 can configure memory subsystem 110 to have a configuration specifying a first interface standard for exposing storage element 137 at a first port and a second interface standard for exposing PMR 145 at a second port. The second interface standard implements one or more alternative protocols supported by the first interface standard. In one embodiment, the first interface standard is PCIe and the second interface standard is CXL, and the one or more alternative protocols supported by the first interface standard (e.g., PCIe) include at least one of the CXL.io protocol and the CXL.mem protocol or the CXL.cache protocol. The CXL.io protocol is supported to allow protocol setup, configuration, and management. Other aspects of the CXL.io protocol are not required because memory management will be implemented via the PCIe end. SPC component 113 can then initiate a reboot of memory subsystem 110 (if necessary) and perform at least one system operation (e.g., at least one error management operation) as a reboot may be required to implement the configuration. In some embodiments, memory subsystem controller 115 includes at least a portion of SPC component 113. In some embodiments, SPC component 113 is part of host system 120, an application, or an operating system. In other embodiments, local media controller 135 includes at least a portion of SPC component 113 and is configured to perform the functions described herein. Further details regarding the operation of SPC component 113 are described below.

[0041] Figure 2 This is a flowchart illustrating an example method 200 of a split protocol approach for an enhanced persistent memory region (PMR) access-enabled device, implemented according to some embodiments of this disclosure. Method 200 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 200 is performed by… Figure 1The SPC component 113 is executed. Although shown in a specific order or sequence, the order of processes may be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are merely examples, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0042] At operation 210, the processing logic boots a system comprising a first memory device and a second memory device, including a non-volatile memory device, to have a first configuration associated with a first interface standard. More specifically, the first configuration corresponds to a plurality of data transfer channels (“channels”) in slots corresponding to the first interface standard. In one embodiment, the first interface standard is PCIe. However, this embodiment should not be considered limiting, and the first interface standard may be any suitable interface standard according to the embodiments described herein. In some embodiments, the first memory device comprises NAND flash. The second memory device may be any suitable means for supporting persistent memory regions (PMR). In some embodiments, the second memory device comprises a volatile memory device. For example, the volatile memory device may comprise DRAM, which may correspond to DDR. In some embodiments, the second memory device comprises a second non-volatile memory device. For example, the second non-volatile memory device may comprise MRAM or other suitable non-volatile memory devices. In some embodiments, the system comprises an NVMe SSD device.

[0043] At operation 220, the processing logic receives a host command to configure the system to have a second configuration having a first interface standard at a first port for exposing storage elements implemented on a non-volatile memory device and a second interface standard at a second port for exposing persistent memory regions (PMRs) implemented on a second memory device. For example, in an embodiment where the second memory device includes a volatile memory device, the PMR may be implemented as a power-protected area on the volatile memory device. In an embodiment where the system includes an NVMe SSD device, the storage element may be an NVMe block storage element.

[0044] The second interface standard implements one or more alternative protocols supported by the first interface standard. For example, the second interface standard may be CXL, and the one or more alternative protocols may include at least one of the CXL.io protocol and the CXL.mem protocol or the CXL.cache protocol. The choice of the CXL.mem protocol and / or the CXL.cache protocol may depend on the desired implementation. However, this embodiment should not be considered limiting, and the second interface standard may be any suitable interface standard according to the embodiments described herein.

[0045] A power-protected memory (PMR) device can be implemented as a power-protected environment on a volatile memory device using any suitable mechanism according to the embodiments described herein. For example, a PMR can be implemented as a power-protected environment on a volatile memory device by employing a spare capacitor. Such a spare capacitor can store charge that can be used to enable the PMR to write data in response to power loss events. Reference will be made below. Figure 5 As will be described in further detail, the system can initiate a capacitor (CAP) check to assess the deterioration of the spare capacitor.

[0046] At operation 230, the processing logic configures the system according to the second configuration. For example, if the firmware is under control, the firmware can configure the system by mapping the required memory space from its internal memory to a PMR partition. The memory space can be a contiguous segment of memory simply characterized by internal memory offsets and lengths, and this will only be exposed to the system as a memory offset, since the base address will be provided by the Extensible Firmware Interface (EFI) and the bootloader.

[0047] More specifically, the system can reconfigure itself as a multi-port system, where each of the multiple ports has its own negotiation protocol. Here, all ports can be configured independently and / or simultaneously. A reboot may be required after configuration.

[0048] An example of a multi-port system is a dual-port system. To perform system reconfiguration in this example, a first portion of a channel can be assigned to a first interface standard at the first port, and a second portion of a channel can be assigned to a second interface standard at the second port (e.g., the first and second portions each correspond to half of the channel). For example, if the first configuration corresponds to four channels in a PCIe slot (i.e., PCIe ×4) at the port, then the first and second portions could each contain the two channels assigned to the corresponding ports in the first and second ports. This configuration change may require a reboot.

[0049] At operation 240, the processing logic initiates a reboot after configuring the system. A reboot may be necessary to rescan the device after a configuration change, and in some embodiments, a reboot is not required. For example, the system may appear as a multi-port system (e.g., a two-port system) after rebooting with connections to the corresponding portions of the first and second parts of the channel.

[0050] Following operation 230 (and any necessary reboot at operation 240), the second interface standard can discover its connectivity. For example, in an embodiment where the second interface standard is CXL, the CXL.io protocol can be used to discover capabilities and detect memory regions that support CXL.mem and / or CXL.cache. The EFI and operating system (OS) can map adjacent regions within cacheable memory maps (e.g., input-output memory management unit (IOMMU) maps). Therefore, the system can be configured to allocate segments of PMRs marked as cacheable memory visible through the second interface standard and detect segments of PMRs as internal memory ranges shared through the second interface standard.

[0051] At operation 250, the processing logic performs at least one system operation based on the configuration. In one embodiment, the at least one system operation may include at least one error management operation. Examples of error management operations include protocol error management and data error management. In some embodiments, the at least one system operation is performed after an optional reboot.

[0052] Protocol errors can be, for example, errors that occur in response to attempts to access system memory. Implementing protocol error management may involve receiving and reporting protocol errors via a second interface standard (e.g., CXL.io).

[0053] Data errors can be, for example, errors that occur when a first interface standard end (e.g., the SSD end) attempts to place or receive data from a second interface standard end (e.g., the CXL end). In data error management, data errors will not be exposed to the second interface standard end. Instead, performing data error management may include: receiving data management errors, processing data management errors by the storage element, and reporting data management errors through a reporting agency associated with the storage element. This ensures separate data flow paths (via the second interface standard if necessary) and control paths (via the first interface standard end).

[0054] Additionally, it may be necessary to track the poisoning status of each “line” (e.g., 64 B) of the PMR. The poisoning status can be maintained via power cycling and may require some form of memory cleaning (e.g., “patrol cleaning”), depending on the memory technology used in the PMR.

[0055] Figure 3 This is a block diagram of a system 300 that can implement a split protocol approach for an enhanced persistent memory region (PMR) access enabled device according to some embodiments of this disclosure. For example, system 300 can be used to implement the above-referenced... Figure 2 The operation of the described method.

[0056] As shown, system 300 may include multiple nodes (e.g., host systems) 310-1, 320-2, ..., 310-N and multiple devices 320-1, 320-2, ..., 320-M. Each of devices 320-1 to 320-M may include any suitable device according to the embodiments described herein. In some embodiments, devices 320-1 to 320-M include one or more NVMe SSD devices (e.g., ... Figure 1 One or more memory subsystems 110 Figure 2 (one or more systems).

[0057] Each of nodes 310-1 to 310-N includes a first interface standard (FIS) component and a second interface standard (SIS) component. More specifically, node 310-1 includes FIS component 312-1 and SIS component 314-1, node 310-2 includes FIS component 312-2 and SIS component 314-2, and node 310-N includes FIS component 312-N and SIS component 314-N. Similar to nodes 310-1 to 310-N, each of devices 320-1 to 320-M includes both an FIS component and a SIS component. More specifically, device 320-1 includes FIS component 322-1 and SIS component 324-1, device 320-2 includes FIS component 322-2 and SIS component 324-2, and device 320-M includes FIS component 322-M and SIS component 324-M.

[0058] The SIS can implement one or more alternative protocols supported by a first interface standard. In one embodiment, the FIS is PCIe and the SIS is CXL, and the one or more alternative protocols may include at least one of the CXL.io protocol and the CXL.mem protocol or the CXL.cache protocol. The choice of the CXL.mem protocol and / or the CXL.cache protocol may depend on the desired implementation. However, this embodiment should not be considered limiting, and the FIS and / or SIS may each be any suitable interface standard according to the embodiments described herein.

[0059] Each of the FIS and SIS components is operatively coupled to the corresponding FIS switch 330 or SIS switch 340. More specifically, FIS components 312-1 to 312-N and 322-1 to 322-M are operatively coupled to FIS switch 330, and SIS components 314-1 to 314-N and 324-1 to 324-M are operatively coupled to SIS switch 340.

[0060] When exposing a PMR using CXL.mem, several factors can be considered to ensure proper PMR operation and performance resulting from exposing the PMR via the CXL.mem protocol. One consideration is startup and shutdown. For example, since PMRs are persistent, specific startup and shutdown solutions can be provided to synchronize the "state" with the host. The host may be unaware of things that cause the PMR to be "not ready" or unavailable, such as power loss or memory degradation. Therefore, mechanisms can be provided, according to the embodiments described herein, to notify or transmit a specific PMR state or readiness to the host. More specifically, a specific status register indicating "% ready" can be defined, where a scale from 0% to 100% not only gives an indication of "not ready" but also a linear estimate of how long until "ready". Notification of changes in the state of this register can be accomplished via asynchronous event notification (AEN), a mechanism defined as part of, for example, the NVMe specification. Host applications using PMR capabilities can therefore observe the PMR readiness register at the start of the day and at any AEN, acting as a gatekeeper for any PMR operation that would otherwise risk data loss. It should be noted that boot time and PMR readiness time can vary depending on the PMR size. To ensure integrity and synchronization with the host, memory region hashing can be used. For example, the host can maintain its own hash and, upon reaching 100% readiness, compare it with the device version hashed. The hash can also be stored in the system's storage (e.g., NAND) end (e.g., SSD) (or even on another storage device). PMR readiness or availability time can be estimated based on the actions required to bring the PMR to a ready or available state.

[0061] Another consideration is AEN. AEN itself does not communicate directly with applications utilizing PMR. In practice, AEN typically notifies the memory drive that a memory happens to be attached. Since the PMR application is not a memory drive, thin drives in the host's memory stack that communicate with the PMR application can be used to manage the delivery of such events using an AEN mechanism (e.g., by employing a device mapper). More specifically, thin drives can detect relevant AEN events associated with PMR and send the relevant AEN events to the appropriate PMR driver.

[0062] Another consideration is the ability to degrade. For example, in the case of power loss, it is important to have a mechanism that provides sufficient time to write any data not yet committed to non-volatile memory. For example, as referenced above… Figure 2As described, a backup capacitor can be used to store energy to enable data writing in the event of power loss. In embodiments where PMR is implemented as a power-protected system on a volatile memory device (e.g., DRAM), a mechanism such as a capacitor can be relied upon to enable data writing to non-volatile memory (e.g., NAND flash) in the event of power loss. However, capacitors can degrade over time, thus adversely affecting their ability to provide data write support during power loss events. To ensure proper PMR operation, periodic capacitor checks (“CAP checks”) can be employed. Such CAP checks verify the presence of sufficient energy in the event of power loss, allowing the device enough time to ensure that data currently stored in volatile memory (e.g., DRAM) can be successfully written to non-volatile memory (e.g., NAND flash). Reference will be made below. Figure 5 Describe other details regarding the CAP check.

[0063] Multiple operating levels or modes can be defined to align with CAP conditions. For example, these modes could include a partially degraded PMR capacity reduction mode (i.e., reducing the amount of PMR memory used) and a read-only mode (e.g., when the PMR can no longer be protected by capacitors). This event can be reported to the host via AEN and managed by the same thin-film driver described above. Therefore, AEN notifications enable the host to adjust the amount of memory being used, completely stop using memory, spare memory, etc.

[0064] As mentioned above, there may be situations where degradation occurs, necessitating adjustments to the PMR size in conjunction with the host. Examples of such situations include, but are not limited to, capacitor degradation, reduced capacity of non-volatile memory (e.g., NAND) and volatile memory (e.g., DRAM), and / or high error rates that cannot be addressed using error correction codes (ECC). To address such situations, the mechanism can specify the PMR size based on the severity of the situation. More specifically, the mechanism may include registers. For example, if the device has lost the ability to reliably protect, for example, 50% of the existing PMR, then read-only PMR ranges (previously stored in non-volatile memory and still accessible) and another range that still supports read / write operations can be specified. In severe cases, the ranges may be entirely read-only or even "offline."

[0065] Another consideration is performance metric customization. For example, in some cases, it may be useful to set up PMR regions with customized performance metrics for different applications with different priorities. To achieve this, control registers can be defined along with protocol agreements between the host and the device to enable regions (e.g., address ranges) with performance metrics. Examples of performance metrics include, but are not limited to, "maximum performance / throughput" (e.g., if a region is marked as maximum performance / throughput, then sustained access is allowed to achieve maximum throughput), "lowest latency" (e.g., if a region is marked as lowest latency, then the region can prioritize accesses), "read-only" (e.g., if a region is marked as read-only, then it is ensured that data has been written to non-volatile memory (e.g., NAND flash) and no writes are allowed), and "balanced performance."

[0066] Another consideration related to performance degradation is "dirty PMR lines," where the content has changed since the last refresh from non-volatile memory (e.g., NAND flash). Associated with degraded operating modes that reduce the ability to protect PMRs, additional metadata can be associated with each PMR "line," indicating whether the line is "dirty." If the metadata indicates a "dirty PMR line," then the host modifies the content in some way. "Dirty PMR lines" can become a burden in the case of asynchronous power loss (APL). However, by tracking the percentage of "dirty" PMR lines and the time required to write "dirty" lines to NAND, the operation of PMRs in a degraded state can be extended. For example, if there are 1,000 managed PMR lines, but only 500 are processed, then the number of unresolved dirty lines cannot exceed 500.

[0067] Figure 4 This is a block diagram of example system 400. As shown, system 400 includes a processor 410 operatively coupled to a plurality of DDRs, including DDR 412-1 and DDR 412-2. System 400 further includes a memory buffer 420 operatively coupled to a plurality of memories, including memories 422-1 to 422-4. Processor 410 and memory buffer 420 communicate via link 430. Memory buffer 420 may include means enabled with enhanced PMR access, such as... Figure 3 The devices 320-1 to 320-M. For example, link 430 may run a split protocol scheme implementing a first interface protocol (e.g., PCIe) and a second interface protocol (e.g., CXL), and memory buffer 420 may contain storage elements visible via, for example, PCIe and PMRs visible via, for example, the CXL.mem protocol or the CXL.cache protocol. However, such embodiments should not be considered limiting.

[0068] In this illustrative embodiment, system 400 implements memory buffer 420 to perform one or more persistent memory applications. However, this implementation is merely exemplary, and the apparatus enabled with enhanced PMR access as described herein can be implemented in any suitable context.

[0069] Figure 5 This describes an example power system 500 according to some embodiments of the present disclosure. As shown, the power system 500 includes a host connector assembly 510, a power management assembly 520, and a subsystem assembly 530, such as... Figure 1 Subsystem 110, which is enabled with enhanced persistent memory area (PMR) access.

[0070] In some embodiments, host connector assembly 510 is an NVMe host connector. Power management assembly 520 is associated with storage voltage (Vstrg) and may include a power management integrated circuit (PMIC) sub-component and an inrush / backup sub-component. Subsystem assembly 530 may include controller assembly 532 (e.g., an application-specific integrated circuit (ASIC) controller). Power management assembly 520 may be located via, for example, an integrated circuit (I... 2 C) The protocol is operatively coupled to controller component 532. Subsystem component 530 may further include NAND 534, DDR 536, and PMR 538. Controller component 532 is operatively coupled to NAND 534 and DDR 536. In some embodiments, subsystem component 530 includes an NVMe SSD device.

[0071] Components 510 to 530 can communicate with each other to enable capacitor (CAP) checks or tests to ensure proper operation of PMR 538, as referenced above. Figure 2 and 3 As described. More specifically, controller component 532 may periodically communicate with power management component 520 to trigger a CAP check, receive the result of the CAP check, and determine the availability or status of PMR 538 based on the result. For example, during a CAP check, a capacitor may be discharged from a first pin connected to the capacitor for energy storage and release to a second pin connected to the external resistor for CAP testing via an external resistor. A transistor (e.g., a field-effect transistor (FET)) may be connected to the second pin and a third pin to ground. When the CAP test start register bit is set (e.g., via I... 2(C-interface), the second pin can be grounded via a transistor for energy discharge. More specifically, power supply can be stopped at an initial time, at which the capacitor can begin discharging from an initial voltage and an internal timer begins counting. The internal timer can maintain the count until the stored voltage hits a threshold at the end time when the internal timer can stop counting and the end voltage can be measured. Therefore, the discharge time can be measured as the difference between the initial time and the end time, and the voltage discharge can be measured as the difference between the initial voltage and the end voltage.

[0072] Figure 6 This describes an example machine of computer system 600, within which an instruction set for causing the machine to perform any one or more of the methods discussed herein can be executed. In some embodiments, computer system 600 may correspond to a host system (e.g., Figure 1 The host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110), or may be used to perform controller operations (e.g., executing an operating system to perform operations corresponding to...). Figure 1 (Operation of SPC component 113). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a peer machine in a peer-to-peer (or distributed) network environment or as a server or client machine in a cloud computing infrastructure or environment, or within the capacity of a server or client machine in a client-server network environment.

[0073] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular telephone, network device, server, network router, switch, or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should be understood to include any set of machines that individually or collectively execute one or more sets of instructions to perform any one or more of the methods discussed herein.

[0074] Example computer system 600 includes processing devices 602 that communicate with each other via bus 630, main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM), static memory 606 (e.g., flash memory, static random access memory (SRAM), etc.) and data storage system 618.

[0075] Processing device 602 represents one or more general-purpose processing devices, such as microprocessors, central processing units, etc. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets. Processing device 602 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, etc. Processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. Computer system 600 may further include a network interface device 608 communicating via network 620.

[0076] Data storage system 618 may include machine-readable storage medium 624 (also referred to as computer-readable medium) on which one or more instruction sets 626 or software embodying any one or more of the methods or functions described herein are stored. Instructions 626 may also reside wholly or at least partially within main memory 604 and / or processing device 602 during execution by computer system 600, which also constitute machine-readable storage medium. Machine-readable storage medium 624, data storage system 618, and / or main memory 604 may correspond to... Figure 1 The memory subsystem 110.

[0077] In one embodiment, instruction 626 includes implementing a component corresponding to the SPC component (e.g., Figure 1 The SPC component 113) contains functional instructions. Although the machine-readable storage medium 624 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions executable by a machine and causing the machine to perform any one or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0078] Some parts of the previously described descriptions have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are, and are generally considered, a self-consistent sequence of operations that produce the desired result. An operation is one that requires physical manipulation of physical quantities. These quantities are usually, but not necessarily, in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. Sometimes, primarily for general reasons, it has proven convenient to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, etc.

[0079] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure can refer to the actions and processes of a computer system or similar electronic computing device that manipulate and transform data represented as physical (electronic) quantities within the registers and memories of a computer system into other data similarly represented as physical quantities within the computer system's memory or registers or other such information storage systems.

[0080] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such computer programs may be stored in computer-readable storage media, such as, but not limited to, any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0081] The algorithms and demonstrations presented herein are inherently independent of any particular computer or other device. Various general-purpose systems can be used with the programs taught herein, or it may be convenient to construct more specialized devices to perform the methods. The structures of various such systems will be presented as described below. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0082] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that can be used to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism for storing information in a machine-readable (e.g., computer-readable) form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine-readable (e.g., computer-readable) storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0083] In the foregoing description, embodiments of this disclosure have been described with reference to specific examples thereof. It will be apparent that various modifications can be made to this disclosure without departing from the broader spirit and scope of the embodiments set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative rather than restrictive sense.

Claims

1. A memory system comprising: An apparatus operatively coupled to a first switch for implementing a first interface standard and a second switch for implementing a second interface standard different from the first interface standard, wherein the second interface standard implements Compute High-Speed ​​Link (CXL), wherein the first interface standard supports one or more alternative protocols implemented by the second interface standard, and wherein the apparatus comprises: A non-volatile memory device that implements storage elements; A volatile memory device, implemented as a persistent memory region (PMR), wherein the PMR serves as a power-protected area of ​​the volatile memory device; and A processor, operably coupled to the non-volatile memory device and the volatile memory device, performs operations including: Receive host commands to configure the memory system to have a configuration that specifies a first interface standard at a first port for exposing the memory elements and a second interface standard at a second port for exposing the PMR; and Configuring the memory system according to the aforementioned configuration includes: The storage element is exposed by specifying the first interface standard at the first port; The PMR is exposed by specifying the second interface standard at the second port; and The allocation is marked as a segment of the PMR that is visible through the second interface standard as a cacheable memory, wherein the segment of the PMR is detected as an internal memory range shared through the second interface standard.

2. The memory system of claim 1, wherein the non-volatile memory device comprises a non-volatile memory high-speed solid-state drive (NVMe SSD), and the storage element is an NVMe block storage element.

3. The memory system of claim 1, wherein the first interface standard is PCIe (Peripheral Component Interconnect), and wherein the one or more alternative protocols include at least one of CXL.io protocol and CXL.mem protocol or CXL.cache protocol.

4. The memory system of claim 1, wherein the operation further comprises, prior to receiving the host command, booting the memory system with a plurality of channels in slots corresponding to the first interface standard, and wherein the configuration of the memory system further comprises, at the first port, assigning a first portion of the plurality of channels to the first interface standard, and at the second port, assigning a second portion of the plurality of channels to the second interface standard.

5. The memory system of claim 1, wherein the operation further comprises performing at least one system operation based on the configuration, and wherein the execution of the at least one system operation further comprises performing at least one of the following: Receive and report protocol errors via the second interface standard; or A data management error is received, the data management error is processed by the storage element, and the data management error is reported by a reporting agency associated with the storage element, thereby supporting separate control paths and data flow paths.

6. A method for operating a memory system, comprising: The processor receives a host command to configure the memory system to have a configuration that specifies a first interface standard at a first port for exposing storage elements and a second interface standard at a second port for exposing persistent memory regions (PMRs) and implementing compute high-speed links (CXLs), wherein the storage elements are implemented on non-volatile memory devices of the memory system and the PMRs are implemented on volatile memory devices of the memory system that are power protected areas of the volatile memory devices, wherein the second interface standard is different from the first interface standard, wherein the first interface standard supports one or more alternative protocols implemented by the second interface standard, and wherein the memory system is operatively coupled to a first switch for implementing the first interface standard and a second switch for implementing the second interface standard. as well as The memory system is configured by the processor according to the configuration, including: The storage element is exposed by specifying the first interface standard at the first port; The PMR is exposed by specifying the second interface standard at the second port; and The allocation is marked as a segment of the PMR that is visible through the second interface standard as a cacheable memory, wherein the segment of the PMR is detected as an internal memory range shared through the second interface standard.

7. The method of claim 6, wherein the non-volatile memory device comprises a non-volatile memory high-speed solid-state drive (NVMe SSD), and the storage element is an NVMe block storage element.

8. The method of claim 6, wherein the first interface standard is PCIe for peripheral component interconnection, and wherein the one or more alternative protocols include at least one of CXL.io protocol and CXL.mem protocol or CXL.cache protocol.

9. The method of claim 6, further comprising, prior to receiving the host command, having the processor bootstrap the memory system with a plurality of channels in a slot corresponding to the first interface standard, wherein the configuration of the memory system further comprises assigning a first portion of the plurality of channels to the first interface standard at the first port, and assigning a second portion of the plurality of channels to the second interface standard at the second port.

10. The method of claim 6, further comprising performing at least one system operation by a processor, wherein the execution of the at least one system operation includes performing at least one of the following: Receive and report protocol errors via the second interface standard; or A data management error is received, the data management error is processed by the storage element, and the data management error is reported by a reporting agency associated with the storage element, thereby supporting separate control paths and data flow paths.

11. A non-transitory computer-readable storage medium including instructions that, when executed by a processor, cause the processor to perform operations including: A system that guides multiple channels in a slot corresponding to a first interface standard, the system including a non-volatile memory device and a volatile memory device implementing storage elements to have a first configuration associated with the first interface standard, wherein the volatile memory device implements a persistent memory region (PMR) as a power protected area of ​​the volatile memory device; The system receives a host command to configure itself in a second configuration having a first interface standard at a first port for exposing the storage element and a second interface standard at a second port for exposing the PMR using a compute high-speed link (CXL) implementation, wherein the second interface standard differs from the first interface standard, wherein the first interface standard supports one or more alternative protocols implemented by the second interface standard, and wherein the system is operatively coupled to a first switch implementing the first interface standard and a second switch implementing the second interface standard. The system is configured according to the second configuration, which includes: The storage element is exposed by specifying the first interface standard at the first port; The PMR is exposed by specifying the second interface standard at the second port; and The allocation is marked as a segment of the PMR that is visible through the second interface standard as a cacheable memory, wherein the segment of the PMR is detected as an internal memory range shared through the second interface standard.

12. The non-transitory computer-readable storage medium of claim 11, wherein the non-volatile memory device comprises a non-volatile memory high-speed solid-state drive (NVMe SSD), and the storage element is an NVMe block storage element.

13. The non-transitory computer-readable storage medium of claim 11, wherein the first interface standard is Peripheral Component Interconnect High Speed ​​PCIe, and wherein the one or more alternative protocols include at least one of the CXL.io protocol and the CXL.mem protocol or the CXL.cache protocol.

14. The non-transitory computer-readable storage medium of claim 11, wherein the configuration of the system further comprises assigning a first portion of the plurality of channels to the first interface standard at the first port, and assigning a second portion of the plurality of channels to the second interface standard at the second port.

15. The non-transitory computer-readable storage medium of claim 11, wherein the operation further comprises performing at least one system operation, and wherein the performance of the at least one system operation comprises performing at least one of the following: Receive and report protocol errors via the second interface standard; or A data management error is received, the data management error is processed by the storage element, and the data management error is reported by a reporting agency associated with the storage element, thereby supporting separate control paths and data flow paths.

Images