Semiconductor device
By introducing impurity diffusion barrier patterns and doped polysilicon patterns into vertical channel transistors, the floating body effect and leakage current problems are solved, and excellent electrical characteristics of highly integrated semiconductor devices are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SAMSUNG ELECTRONICS CO LTD
- Filing Date
- 2021-10-20
- Publication Date
- 2026-07-03
AI Technical Summary
In the prior art, vertical channel transistors suffer from floating body effect and leakage current problems when manufacturing highly integrated semiconductor devices, which affect the operating characteristics of the devices.
The design employs impurity diffusion blocking patterns and impurity-doped polysilicon gate insulating patterns to prevent impurity diffusion in the polysilicon pattern, reduce the floating body effect, and improve the control capability of the channel region by optimizing the layout of the gate insulating pattern and conductive pattern.
It effectively reduces the floating body effect in vertical channel transistors, maintains the target threshold voltage, reduces leakage current, and improves the electrical characteristics and overall performance of semiconductor devices.
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Figure CN114649333B_ABST
Abstract
Description
[0001] Cross-references to related applications
[0002] This application claims priority to Korean Patent Application No. 10-2020-0178360, filed on December 18, 2020 with the Korean Intellectual Property Office (KIPO), the entire contents of which are incorporated herein by reference. Technical Field
[0003] This invention relates to a semiconductor device. More specifically, it relates to a semiconductor device including a vertical channel transistor. Background Technology
[0004] To fabricate highly integrated semiconductor devices, vertical channel transistors are incorporated, each having a vertical channel extending in a direction perpendicular to the substrate surface. Vertical channel transistors can be used as select transistors in memory cells, enabling highly integrated memory devices. Summary of the Invention
[0005] An embodiment provides a semiconductor device including a vertical channel transistor.
[0006] According to some embodiments, a semiconductor device is provided, comprising a plurality of semiconductor structures on a substrate, a first conductive pattern, a first impurity region, a gate insulating pattern, a second conductive pattern, and a second impurity region. Each semiconductor structure includes a first semiconductor pattern having a linear shape extending along a first direction and a second semiconductor pattern projecting vertically from the upper surface of the first semiconductor pattern. The semiconductor structures are spaced apart from each other along a first direction perpendicular to a second direction. The first conductive pattern is formed in a first trench between the first semiconductor patterns. The first conductive pattern extends along the first direction. A first impurity region is formed in an opening in the first semiconductor pattern adjacent to a first sidewall of the second semiconductor pattern. The first impurity region includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities. A gate insulating pattern is formed on the first sidewall of each second semiconductor pattern. The second conductive pattern is formed on the gate insulating pattern and extends along the second direction. A second impurity region is formed on each second semiconductor pattern.
[0007] According to some embodiments, a semiconductor device is provided, comprising a plurality of semiconductor structures disposed on a substrate, a first conductive pattern, a first insulating pattern, a first impurity region, a gate insulating pattern, a second conductive pattern, a second conductive pattern, and a second impurity region. Each semiconductor structure includes a first semiconductor pattern having a linear shape extending along a first direction and a second semiconductor pattern projecting vertically from the upper surface of the first semiconductor pattern. The semiconductor structures are spaced apart from each other along a first direction perpendicular to a second direction. The first conductive pattern is formed in a first trench between the first semiconductor patterns. The first conductive pattern extends along the first direction. The first insulating pattern is formed in the first trench between the first semiconductor patterns. The first insulating pattern contacts the sidewall of the first conductive pattern. The first conductive pattern extends along the first direction. A first impurity region extends from a position spaced apart from the lower portion of the first sidewall of the second semiconductor pattern to a position overlapping a portion of the lower surface of the second semiconductor pattern. The first impurity region includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities. A gate insulating pattern is formed on the first sidewall of each second semiconductor pattern. The second conductive pattern extends along the second direction on the gate insulating pattern. The sidewall of the first impurity region and the sidewall of the first conductive pattern are in contact with each other in each second semiconductor pattern.
[0008] According to some embodiments, a semiconductor device is provided, comprising a semiconductor structure disposed on a substrate, a first impurity region, a gate insulating pattern, a second conductive pattern, and a second impurity region. The semiconductor structure includes a first semiconductor pattern having a linear shape extending along a first direction and a second semiconductor pattern projecting vertically from the upper surface of the first semiconductor pattern. The first impurity region extends from a location spaced apart from the lower portion of a first sidewall of the second semiconductor pattern to a location overlapping a portion of the lower surface of the second semiconductor pattern. The first impurity region includes an impurity diffusion barrier pattern and an impurity-doped polysilicon pattern. The gate insulating pattern is formed on the first sidewall of the second semiconductor pattern. The second conductive pattern is formed on the gate insulating pattern. The second impurity region is formed on the second semiconductor pattern. The impurity diffusion barrier pattern surrounds the sidewalls and bottom of the polysilicon pattern.
[0009] In a semiconductor device according to some embodiments, a first impurity region located below a second semiconductor pattern includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities. The impurity diffusion barrier pattern prevents the diffusion of impurities doped in the polysilicon pattern. Therefore, the floating body effect in the vertical transistor is reduced, and the semiconductor device exhibits excellent operating characteristics. Attached Figure Description
[0010] Figure 1 This is a perspective view of a semiconductor device according to some embodiments.
[0011] Figure 2This is a cross-sectional view of a semiconductor device according to some embodiments.
[0012] Figure 3 These are cross-sectional views and energy bands of a vertical transistor in a semiconductor device according to some embodiments.
[0013] Figure 4 This is a cross-sectional view and band structure of a vertical transistor including a first impurity region containing diffused impurities, used for comparison with this embodiment.
[0014] Figures 5 to 19 These are perspective and cross-sectional views of methods for manufacturing semiconductor devices according to some embodiments.
[0015] Figure 20 This is a perspective view of a semiconductor device according to some embodiments.
[0016] Figure 21 This is a cross-sectional view of a semiconductor device according to some embodiments.
[0017] Figure 22 This is a perspective view of a semiconductor device according to some embodiments.
[0018] Figure 23 This is a cross-sectional view of a semiconductor device according to some embodiments. Detailed Implementation
[0019] Figure 1 This is a perspective view of a semiconductor device according to some embodiments. Figure 2 This is a cross-sectional view of a semiconductor device according to some embodiments.
[0020] In some embodiments, the semiconductor device is a DRAM device. Figure 1 In this example, capacitors are omitted to reduce the complexity of the drawing. Figure 2 It shows along Figure 1 The cross-sectional view taken by lines AA′ and BB′.
[0021] Reference Figure 1 and 2 In some embodiments, the semiconductor structure 114 is formed on the semiconductor substrate 100.
[0022] In some embodiments, the semiconductor structure 114 is formed by etching a portion of an empty semiconductor substrate. Therefore, the semiconductor substrate 100 and the semiconductor structure 114 comprise substantially the same semiconductor material, and include, for example, single-crystal silicon. In some embodiments, at least a portion of the semiconductor structure 114 is formed by an epitaxial growth process.
[0023] In some embodiments, the semiconductor structure 114 includes a first semiconductor pattern 114a and a second semiconductor pattern 114b. The first semiconductor pattern 114a has a linear shape extending along a first direction. The second semiconductor pattern 114b is formed on the first semiconductor pattern 114a. Each second semiconductor pattern 114b has a columnar shape protruding from the upper surface of the first semiconductor pattern 114a in a third direction perpendicular to the upper surface of the first semiconductor pattern 114a.
[0024] In some embodiments, a plurality of first semiconductor patterns 114a are spaced apart from each other in a second direction perpendicular to the first direction. Therefore, a first trench is formed between the first semiconductor patterns 114a, and the first trench extends along the first direction.
[0025] In some embodiments, a second semiconductor pattern 114b is disposed on each of the first semiconductor patterns 114a and is uniformly spaced apart from each other. The second semiconductor patterns 114b are arranged in each of the first and second directions. Therefore, the second semiconductor patterns 114b are arranged in a grid shape. In some embodiments, the semiconductor structure 114 is doped with p-type impurities.
[0026] In some embodiments, each second semiconductor pattern 114b is a channel region of a vertical channel transistor. A vertical channel transistor is formed on each second semiconductor pattern 114b.
[0027] In some embodiments, a first conductive pattern 110 and a first insulating pattern 108 are formed in a first trench. The first conductive pattern 110 and the first insulating pattern 108 extend along a first direction. The first conductive pattern 110 and the first insulating pattern 108 are adjacent to each other in a second direction. A second insulating pattern 106 is further formed covering a portion of the sidewalls and bottom of the first conductive pattern 110.
[0028] In some embodiments, a second insulating pattern 106 and a first conductive pattern 110 are formed on a first sidewall of a first trench. A first insulating pattern 108 is formed on a second sidewall facing the first sidewall of the first trench. The first conductive pattern 110 is an embedded bit line.
[0029] In some embodiments, the first conductive pattern 110 includes, for example, a blocking metal pattern 110a and a metal pattern 110b. In various perspective views, the second insulating pattern, the blocking metal pattern, and the metal pattern are omitted to reduce the complexity of the drawing.
[0030] In some embodiments, the blocking metal pattern 110a includes one or more of, for example, Ti, Ta, TiN, TaN, or WN. The metal pattern 110b includes one or more of, for example, W, Al, Cu, Ru, Mo, Pt, Ni, Co, TiAl, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, or CoSi.
[0031] In some embodiments, the upper surfaces of the first conductive pattern 110 and the first insulating pattern 108 are coplanar with the upper surface of the first semiconductor pattern 114a. Alternatively, the upper surfaces of the first conductive pattern 110 and the first insulating pattern 108 are lower than the upper surface of the first semiconductor pattern 114a.
[0032] In some embodiments, the first opening 118 (see...) Figure 9 The first opening 118 is formed in the portion of the first semiconductor pattern 114a adjacent to the first sidewall of the second semiconductor pattern 114b in the first direction. The first opening 118 is located in the portion corresponding to the first impurity region of the vertical channel transistor.
[0033] In some embodiments, the first opening 118 has an isolation shape. A first conductive pattern 110 is exposed in a second direction by a first sidewall of the first opening 118. A first insulating pattern 108 is exposed by a second sidewall facing the first sidewall of the first opening 118. That is, a second insulating pattern 106 on one sidewall of the first conductive pattern 110 is selectively removed to expose a blocking metal pattern 110a in the first conductive pattern 110 on the first sidewall of the first opening 118. The first opening 118 extends from a first semiconductor pattern 114a adjacent to a first sidewall of a second semiconductor pattern 114b to a portion of the first semiconductor pattern 114a below the second semiconductor pattern 114b, thus the first opening 118 has an undercut shape.
[0034] In some embodiments, the impurity diffusion barrier pattern 120 is conformally formed on the sidewalls and bottom of the first opening 118.
[0035] In some embodiments, a first polysilicon pattern 122 filling the first opening 118 is formed on the impurity diffusion barrier pattern 120. The first polysilicon pattern 122 is doped with impurities. For example, the first polysilicon pattern 122 is doped with n-type impurities. The impurity diffusion barrier pattern 120 and the first polysilicon pattern 122 serve as a first impurity region 124 serving as the source / drain region of a vertical channel transistor. The first impurity region 124 extends from a location spaced apart from the lower portion of the first sidewall of the second semiconductor pattern 114b, which serves as the channel region of the vertical channel transistor, to a location overlapping a portion of the lower surface of the second semiconductor pattern 114b.
[0036] In some embodiments, the impurity diffusion barrier pattern 120 surrounds the sidewalls and bottom of the first polysilicon pattern 122. The impurity diffusion barrier pattern 120 includes a material that prevents impurity diffusion. The impurity diffusion barrier pattern 120 prevents impurities doped in the first polysilicon pattern 122 from diffusing into the first semiconductor pattern 114a and the second semiconductor pattern 114b adjacent to the first polysilicon pattern 122.
[0037] In some embodiments, the first impurity region 124 and the first conductive pattern 110 are adjacent to each other in a second direction. The sidewall of the first impurity region 124 contacts the sidewall of the first conductive pattern 110.
[0038] Specifically, in some embodiments, the impurity diffusion barrier pattern 120 of the first impurity region 124 contacts the barrier metal pattern 110a of the first conductive pattern 110 in a second direction. The first polysilicon pattern 122 is electrically connected to the first conductive pattern 110 through the impurity diffusion barrier pattern 120. Therefore, the impurity diffusion barrier pattern 120 comprises a low-resistance conductive material. The impurity diffusion barrier pattern 120 may include a material having low contact resistance with the first conductive pattern 110.
[0039] In some embodiments, the impurity diffusion barrier pattern 120 includes graphene. When the impurity diffusion barrier pattern 120 includes graphene, the impurity diffusion barrier pattern 120 can prevent impurities from diffusing from the first polycrystalline silicon pattern 122, and the impurity diffusion barrier pattern 120 including graphene has low resistance.
[0040] In some embodiments, to prevent impurity diffusion and reduce contact resistance with the first conductive pattern, the graphene of the impurity diffusion blocking pattern 120 has a thickness of about 0.1 nm to about 0.5 nm. In some embodiments, the graphene has a thickness of about 0.2 nm to about 0.4 nm. However, the embodiments are not limited thereto, and the thickness of the graphene may vary in other embodiments.
[0041] In some embodiments, a first impurity region 124 is formed in a first opening 118, and the first impurity region 124 does not extend into the first semiconductor pattern 114a adjacent to the first opening 118. Therefore, the first impurity region 124 is defined by the first opening 118.
[0042] In some embodiments, the first opening 118 overlaps only with a portion of the lower surface of the second semiconductor pattern 114b, and not with the entire lower surface of the second semiconductor pattern 114b.
[0043] In some embodiments, a first insulating interlayer 130 is formed, which covers the first conductive pattern 110, the semiconductor structure 114, the first insulating pattern 108, and the first impurity region 124. The first insulating interlayer 130 includes, for example, silicon oxide.
[0044] In some embodiments, the second trench 132 (see Figure 15 The second trench 132 is formed in the first insulating interlayer 130 and extends in the second direction.
[0045] In some embodiments, the first sidewall of the second semiconductor pattern 114b is exposed by the first sidewall of the second trench 132. The second semiconductor pattern 114b is not exposed by the second sidewall facing the first sidewall of the second trench 132, and the first insulating interlayer 130 is exposed by the second sidewall of the second trench 132. The upper portion of the first impurity region 124 is exposed by the bottom of the second trench 132.
[0046] In some embodiments, a gate insulating pattern 134 is conformally formed on the sidewalls and bottom of the second trench 132. The gate insulating pattern 134 contacts the first sidewall of the second semiconductor pattern 114b and covers the upper portion of the first impurity region 124.
[0047] In some embodiments, the gate insulating pattern 134 comprises silicon oxide. In some embodiments, the gate insulating pattern 134 comprises a metal oxide having a high dielectric constant. The metal oxide may be, for example, one of HfO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, ZrO2, Al2O3, titanium oxide, or tantalum oxide.
[0048] In some embodiments, a second conductive pattern 136 filling the second trench 132 is formed on the gate insulating pattern 134 and between portions of the gate insulating pattern 134 covering the sidewalls of the second trench 132. The second conductive pattern 136 serves as the gate electrode of a vertical channel transistor. The second conductive pattern 136 extends along a second direction and serves as a word line.
[0049] In some embodiments, the second conductive pattern 136 comprises at least one of a metal, a conductive metal nitride, a conductive metal silicide, or a conductive metal oxide. For example, the second conductive pattern 136 comprises at least one of W, Ti, Ta, TiN, TaN, WN, Al, Cu, Ru, Mo, Pt, Ni, Co, NbN, TiAl, TiAlN, TiSi, TiSiN, TaSi, TaSiN, RuTiN, NiSi, CoSi, IrOx, or RuO. In some embodiments, the second conductive pattern 136 comprises polycrystalline silicon doped with impurities.
[0050] In some embodiments, the uppermost surface of the gate insulating pattern 134 and the second conductive pattern 136 is coplanar with the uppermost surface of the second semiconductor pattern 114b.
[0051] In some embodiments, a second polysilicon pattern 140 is formed on the uppermost surface of the second semiconductor pattern 114b. The second polysilicon pattern 140 is doped with impurities of the same conductivity type as the first polysilicon pattern 122. For example, the second polysilicon pattern 140 is doped with n-type impurities. The second polysilicon pattern 140 is a second impurity region used as the source / drain region of a vertical channel transistor, and therefore the second polysilicon pattern 140 and the second impurity region are represented by the same reference numerals.
[0052] In some embodiments, a second insulating interlayer 150 is formed on both sides of the second polysilicon pattern 140. The second insulating interlayer 150 is formed on the first insulating interlayer 130, the gate insulating pattern 134, and the second conductive pattern 136.
[0053] In some embodiments, capacitor 166 is formed on second polysilicon pattern 140.
[0054] In some embodiments, capacitor 166 includes a lower electrode 160, a dielectric layer 162, and an upper electrode 164. The lower electrode 160 may have a cylindrical shape or a hollow cylindrical shape.
[0055] As described above, a vertical channel transistor according to some embodiments is formed on a semiconductor structure 114. The vertical channel transistor includes a first impurity region 124, a second impurity region 140, a gate insulating pattern 134, and a second conductive pattern 136.
[0056] Figure 3 yes Figure 1 The diagram shows a cross-sectional view and energy band of a vertical transistor in a semiconductor device. Figure 4 This is a cross-sectional view and band structure of a vertical transistor including a first impurity region containing diffused impurities, used for comparison with this embodiment.
[0057] Figure 3 The band structure includes the line EE′ on the right side of the cross-sectional view on the left, and Figure 4 The band structure on the left includes the line FF′ on the right side of the cross-sectional view.
[0058] Reference Figure 3 In some embodiments, the first impurity region 124 overlaps only a portion of the lower surface of the second semiconductor pattern 114b. That is, a portion of the lower surface of the second semiconductor pattern 114b contacts the first impurity region 124. The first semiconductor pattern 114a is connected to the lower surface of the second semiconductor pattern 114b and is disposed on one side of the first impurity region 124.
[0059] Therefore, in some embodiments, the second semiconductor pattern 114b, which serves as the channel region for a vertical channel transistor, is not completely isolated by the first impurity region 124 and the second impurity region 140. A portion of the lower surface of the second semiconductor pattern 114b is connected to the first semiconductor pattern 114a.
[0060] In some embodiments, when the vertical channel transistor is operating, an inversion layer, i.e., a channel, is formed at the second semiconductor pattern 114b between the first impurity region 124 and the second impurity region 140. Figure 2 Region I in the diagram). The portion of the second semiconductor pattern 114b that does not form an inversion layer is connected to the first semiconductor pattern 114a.
[0061] In some embodiments, no energy barrier is generated between the second semiconductor pattern 114b and the first semiconductor pattern 114a connected thereto, thereby reducing the number of holes accumulated in the channel region. Therefore, the target threshold voltage of the vertical channel transistor can be maintained, and the leakage current in the vertical channel transistor can be reduced.
[0062] Reference Figure 4 For comparison with this embodiment, a portion of the first semiconductor pattern 114a is doped with impurities to form a first impurity region 123. In this case, the impurities in the first impurity region 123 can diffuse into the first semiconductor pattern 114a adjacent to the first impurity region 123. Therefore, the first impurity region 123 overlaps with the entire lower surface of the second semiconductor pattern 114b. That is, the lower surface of the second semiconductor pattern 114b contacts the entire upper surface of the first impurity region 123. Therefore, the second semiconductor pattern 114b, which serves as the channel region of the vertical channel transistor, is completely isolated by the first impurity region 123 and the second impurity region 140. In this case, an energy barrier is generated between the channel region 114b and the first impurity region 123, and between the channel region 114b and the second impurity region 140, in the vertical channel transistor. Therefore, holes do not escape from the channel region due to the band gap, and holes accumulate in the channel region. That is, a floating body effect occurs in the vertical transistor. Holes accumulate in the channel region, lowering the threshold voltage of the vertical transistor and generating leakage current in the channel region.
[0063] As described above, the semiconductor device according to this embodiment includes a vertical channel transistor with excellent electrical characteristics. The contact resistance between the first impurity region of the vertical channel transistor and the first conductive pattern serving as a bit line is reduced. Therefore, the semiconductor device has excellent electrical characteristics.
[0064] Figures 5 to 19 This describes the manufacturing process. Figure 1 and Figure 2 Perspective and cross-sectional views of the method for the semiconductor device shown.
[0065] Figures 5 to 7 , Figure 9 , Figure 11 , Figure 12 , Figure 14 , Figure 15 , Figure 16 and Figure 18 It is a perspective view, and Figure 8 , 10 13, 17 and 19 are cross-sectional views.
[0066] Figure 8 Including along Figure 7 Cross-sectional views of lines CC′ and BB′. Figure 10 , 13 17 and 19 include cross-sectional views along lines AA′ and BB′ in each perspective view.
[0067] Reference Figure 5 In some embodiments, p-type impurities are lightly doped into the upper surface of the semiconductor substrate 100. A first etch mask having a linear shape extending along a first direction is formed on the semiconductor substrate 100, and then the semiconductor substrate is dry-etched using the first etch mask to form a first trench 102. The semiconductor substrate 100 is a single-crystal silicon substrate.
[0068] In some embodiments, each first trench 102 has a first depth. The first trench 102 extends along a first direction. Preliminary semiconductor patterns 104 extending in the first direction are formed between adjacent first trenches 102. A plurality of preliminary semiconductor patterns 104 are repeatedly spaced apart in a second direction perpendicular to the first direction, wherein the first trenches are formed between adjacent preliminary semiconductor patterns 104.
[0069] Reference Figure 6 In some embodiments, a first insulating layer is formed to fill the first trench 102, and a portion of the first insulating layer is etched to form a preliminary first insulating pattern. A first sidewall of the preliminary first insulating pattern extends in a first direction and contacts a sidewall of the preliminary semiconductor pattern 104. A gap extending in the first direction is formed between a second sidewall facing the first sidewall of the preliminary first insulating pattern and the preliminary semiconductor pattern 104.
[0070] In some embodiments, a second insulating layer is conformally formed on the surface of the gap. The second insulating layer comprises, for example, silicon oxide.
[0071] In some embodiments, a first conductive layer is formed on a second insulating layer. For example, a barrier metal layer is conformally formed on the second insulating layer, and a metal layer is formed on the barrier metal layer.
[0072] Subsequently, in some embodiments, the upper portions of the first insulating layer, the second insulating layer, and the conductive layer are etched to form a first insulating pattern 108 and a second insulating pattern 106 that fill the lower portion of the first trench (see...). Figure 8 The etching process includes an etch-back process and a first conductive pattern 110. The first conductive pattern 110 includes a barrier metal pattern 110a (see...). Figure 8 ) and metal pattern 110b (see Figure 8 In the perspective view, the second insulating pattern, the blocking metal pattern, and the metal pattern are omitted to reduce the complexity of the drawing.
[0073] In some embodiments, the first conductive pattern 110 extends along a first direction and serves as an embedded bit line. The second insulating pattern 106 covers the sidewalls and bottom of the first conductive pattern 110.
[0074] In some embodiments, the initial semiconductor pattern 104 protrudes between the first conductive pattern 110 and the first insulating pattern 108.
[0075] Reference Figure 7 and Figure 8 In some embodiments, a second etch mask having a line shape extending in a second direction is formed on the first conductive pattern 110 and the preliminary semiconductor pattern 104. The preliminary semiconductor pattern 104 is etched using the second etch mask to form a semiconductor structure 114. In the etching process for forming the semiconductor structure 114, the etching depth of the preliminary semiconductor pattern 104 is a second depth lower than the first depth.
[0076] Reference Figure 7 and Figure 8 In some embodiments, the semiconductor structure 114 includes a first semiconductor pattern 114a extending in a first direction and a plurality of second semiconductor patterns 114b having a columnar shape and projecting upward from the upper surface of the first semiconductor pattern 114a. The second semiconductor patterns 114b are formed on the first semiconductor pattern 114a and are spaced apart from each other. The second semiconductor patterns 114b are arranged in a grid pattern in each of the first and second directions.
[0077] In some embodiments, a first semiconductor pattern 114a is formed between a first trench filled with a first conductive pattern 110 and a first insulating pattern 108. In some embodiments, the upper surfaces of the first conductive pattern 110 and the first insulating pattern 108 are substantially coplanar with the upper surface of the first semiconductor pattern 114a. Alternatively, the upper surfaces of the first conductive pattern 110 and the first insulating pattern 108 are lower than the upper surface of the first semiconductor pattern 114a.
[0078] Reference Figure 9 and Figure 10 In some embodiments, a third etch mask is formed that exposes the portion of the first semiconductor pattern 114a and the second semiconductor pattern 114b adjacent to each other in a first direction. The third etch mask is used to form a first impurity region, i.e., a polysilicon pattern of the lower impurity region, which serves as a unit transistor.
[0079] In some embodiments, a portion of the first semiconductor pattern 114a is etched using a third etch mask to form a first opening 118. The first opening 118 is isolated. A first conductive pattern 110 is exposed in a second direction by a first sidewall of the first opening 118. A first insulating pattern 108 is exposed by a second sidewall facing the first sidewall of the first opening 118.
[0080] That is, in some embodiments, the second insulating pattern 106 on the sidewall of the first conductive pattern 110 is removed, such that the blocking metal pattern 110a of the first conductive pattern 110 is exposed by the first sidewall of the first opening 118. The first opening 118 is formed to have an undercut shape extending below a portion of the lower surface of the second semiconductor pattern 114b to the first semiconductor pattern 114a.
[0081] Reference Figures 11 to 13 In some embodiments, an impurity diffusion barrier layer is conformally formed on the sidewalls and bottom of the first opening 118. In some embodiments, the impurity diffusion barrier layer comprises a graphene layer. The graphene layer is formed by a chemical vapor deposition process. The graphene layer is conductive. The graphene layer prevents impurity diffusion.
[0082] In some embodiments, a first semiconductor layer doped with impurities is formed on an impurity diffusion barrier layer. In some embodiments, a first polysilicon layer doped with impurities is formed on an impurity diffusion barrier layer. For example, the first polysilicon layer is doped with an n-type impurity. In some embodiments, the first polysilicon layer is deposited by an in-situ doping process.
[0083] In some embodiments, the upper portion of the impurity diffusion barrier layer and the first polysilicon layer is etched to form an impurity diffusion barrier pattern 120 and a first polysilicon pattern 122 that fill the first opening 118.
[0084] In some embodiments, the impurity diffusion barrier pattern 120 surrounds the sidewalls and bottom of the first polysilicon pattern 122. The impurity diffusion barrier pattern 120 prevents impurities doped into the first polysilicon pattern 122 from diffusing into the first semiconductor pattern 114a and the second semiconductor pattern 114b adjacent to the first polysilicon pattern 122. The impurity diffusion barrier pattern 120 and the first polysilicon pattern 122 form a first impurity region 124 that serves as the source / drain of a vertical channel transistor.
[0085] In some embodiments, the first impurity region 124 and the first conductive pattern 110 are electrically connected to each other when the sidewall of the first impurity region 124 and the first conductive pattern 110 are in contact with each other. Specifically, the impurity diffusion barrier pattern 120 of the first impurity region 124 contacts the barrier metal pattern 110a of the first conductive pattern 110 in a second direction. In this case, the impurity diffusion barrier pattern 120 is formed of graphene having low resistance and reducing the contact resistance between the impurity diffusion barrier pattern 120 and the barrier metal pattern 110a. That is, the resistance of the bit line contact is reduced.
[0086] Reference Figure 14 In some embodiments, a first insulating interlayer 130 is formed covering the first conductive pattern 110, the semiconductor structure 114, the first insulating pattern 108, and the first impurity region 124.
[0087] Reference Figure 15 In some embodiments, a fourth etch mask having a linear shape extending in a second direction is formed on the first insulating interlayer 130. Subsequently, the first insulating interlayer 130 is etched using the fourth etch mask to form a second trench 132 extending in the second direction.
[0088] In some embodiments, the first sidewall of the second semiconductor pattern 114b is exposed by the first sidewall of the second trench 132. The second semiconductor pattern 114b is not exposed by the second sidewall facing the first sidewall of the second trench 132, and the first insulating interlayer 130 is exposed by the second sidewall of the second trench 132. The bottom of the second trench 132 exposes the upper portion of the first impurity region 124.
[0089] Reference Figure 16 and 17 In some embodiments, a gate insulating layer is conformally formed on the surface of the second trench 132 and the upper surface of the first insulating interlayer 130. Therefore, the gate insulating layer contacts the first sidewall of the second semiconductor pattern 114b and covers the upper portion of the first impurity region 124. A second conductive layer is formed on the gate insulating layer that completely fills the second trench 132.
[0090] Subsequently, in some embodiments, the gate insulating layer, the second conductive layer, and the first insulating interlayer 130 are planarized until the upper surface of the second semiconductor pattern 114b is exposed to form the gate insulating pattern and the second conductive pattern 136 in the second semiconductor pattern 114b.
[0091] In some embodiments, the second conductive pattern 136 serves as a gate electrode. The second conductive pattern 136 extends along a second direction and serves as a word line.
[0092] Reference Figure 18 and 19In some embodiments, a second semiconductor layer doped with impurities is formed on the second semiconductor pattern 114b, the gate insulating pattern 134, the second conductive pattern 136, and the first insulating interlayer 130. In some embodiments, the second semiconductor layer comprises a polysilicon layer doped with impurities. The second semiconductor layer is referred to as the second polysilicon layer. The impurities doped in the second polysilicon layer have the same conductivity type as the impurities doped in the first polysilicon pattern 122. For example, the second polysilicon layer is doped with n-type impurities.
[0093] In some embodiments, the second polysilicon layer is patterned to form a second polysilicon pattern 140 on the second semiconductor pattern 114b. Each second polysilicon pattern 140 is isolated.
[0094] In some embodiments, the second polysilicon pattern 140 serves as a second impurity region for a vertical channel transistor.
[0095] Refer again Figure 2 In some embodiments, capacitor 166 is formed on a second polysilicon pattern 140. Capacitor 166 includes a lower electrode 160, a dielectric layer 162, and an upper electrode 164. The lower electrode 160 has a pillar shape or a hollow cylindrical shape.
[0096] As described above, in some embodiments, a semiconductor device including a vertical channel transistor can be fabricated. A first impurity region 124 of the vertical channel transistor includes a first polysilicon pattern 122 and an impurity diffusion barrier pattern 120 surrounding the surface of the first polysilicon pattern 122. The impurity diffusion barrier pattern 120 prevents impurities doped in the first polysilicon pattern 122 from diffusing into a first semiconductor pattern 114a and a second semiconductor pattern 114b adjacent to the first polysilicon pattern 122. If the first impurity region overlaps the entire lower surface of the second semiconductor pattern, a floating body effect can occur in the vertical channel transistor. That is, the diffusion of impurities doped in the first polysilicon pattern can produce a floating body effect in the vertical channel transistor. However, in the vertical channel transistor according to some embodiments, the floating body effect is mitigated by the impurity diffusion barrier pattern 120. In the vertical channel transistor according to some embodiments, a target threshold voltage can be maintained, and leakage current can be reduced.
[0097] Figure 20 This is a perspective view of a semiconductor device according to some embodiments. Figure 21 yes Figure 20 The diagram shows a cross-sectional view of the semiconductor device.
[0098] Figure 21 Including along Figure 20 Cross-sectional views of lines AA′ and BB′.
[0099] Apart from the second impurity region, Figure 20 and21 The semiconductor device shown is Figure 1 and 2 The semiconductor devices shown are essentially the same. Therefore, repeated descriptions are omitted.
[0100] Reference Figure 20 and 21 In some embodiments, the upper portion of the second semiconductor pattern 114b is doped with impurities. The upper portion of the second semiconductor pattern 114b is a second impurity region 142.
[0101] In some embodiments, the second impurity region 142 faces the second conductive pattern 136 in a first direction, with a gate insulating pattern interposed therebetween. The upper surface of the second impurity region 142 is substantially coplanar with the upper surface of the second conductive pattern 136.
[0102] In some embodiments, the upper surface of the second conductive pattern 136 is lower than the upper surface of the second impurity region 142.
[0103] In some embodiments, a second insulating interlayer 150 is formed on a first insulating interlayer 130, a gate insulating pattern 134, a second conductive pattern 136, and a second semiconductor pattern 114b. A contact plug 152 penetrates the second insulating interlayer 150 and contacts a second impurity region 142.
[0104] In some embodiments, a capacitor 166 is formed on a contact plug 152.
[0105] Figure 22 This is a perspective view of a semiconductor device according to some embodiments. Figure 23 This is a cross-sectional view of a semiconductor device according to some embodiments.
[0106] Figure 23 It is along Figure 22 A cross-sectional view of line DD′.
[0107] In some embodiments, in addition to the location of the first conductive pattern used as an embedded bit line and the contact portion between the first conductive pattern and the first impurity region... Figure 22 and 23 The semiconductor device shown is Figure 1 and 2 The semiconductor devices shown are essentially the same. Therefore, repeated descriptions are omitted.
[0108] Reference Figure 22 and 23 In some embodiments, a first conductive pattern 111 is formed under the semiconductor structure 114. An insulating pattern 154 is located between the semiconductor structure 114 and the upper surface of the first conductive pattern 111.
[0109] In some embodiments, a first impurity region 124 is disposed on a first conductive pattern 111. The upper surface of the first conductive pattern 111 and the lower surface of the first impurity region 124 are in contact with each other. Specifically, an impurity diffusion barrier pattern 120 located at the bottom of the first opening 118 contacts the upper surface of the first conductive pattern 111. Therefore, the contact resistance between the first impurity region 124 and the first conductive pattern 111 is reduced.
[0110] In some embodiments, the first insulating pattern 108a fills the space between the stacked structures, including the first conductive pattern 111 and the semiconductor structure 114.
[0111] The vertical transistor in the semiconductor device according to some embodiments can be used as a select transistor for various memory devices. Furthermore, the semiconductor device according to some embodiments can be used as a memory device in electronic products such as mobile devices, memory cards, or computers.
[0112] The foregoing is illustrative of the embodiments and should not be construed as limiting them. While some embodiments have been described, those skilled in the art will readily understand that various modifications may be made to the embodiments without substantially departing from the novel teachings of the inventive concept. Therefore, all such modifications are intended to be included within the scope of the inventive concept as defined in the claims. Accordingly, it should be understood that the foregoing is illustrative of various embodiments and should not be construed as limiting to the specific embodiments disclosed, and modifications to the disclosed embodiments and other embodiments are intended to be included within the scope of the appended claims.
Claims
1. A semiconductor device, comprising: A plurality of semiconductor structures are disposed on a substrate, wherein each of the plurality of semiconductor structures includes a first semiconductor pattern having a linear shape extending along a first direction, and a second semiconductor pattern protruding from the upper surface of the first semiconductor pattern in a vertical direction, wherein the plurality of semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction; A first conductive pattern is formed in a first trench between the first semiconductor patterns, wherein the first conductive pattern extends along the first direction; A first impurity region is formed in an opening adjacent to the first sidewall of the first semiconductor pattern and the second semiconductor pattern, wherein the first impurity region includes a polysilicon pattern doped with impurities and an impurity diffusion barrier pattern, the impurity diffusion barrier pattern surrounding the sidewall and bottom of the polysilicon pattern to prevent the diffusion of the impurities doped in the polysilicon pattern. A gate insulating pattern is disposed on the first sidewall of each of the second semiconductor patterns; A second conductive pattern extends along the second direction on the gate insulating pattern; and The second impurity region is disposed on each of the second semiconductor patterns.
2. The semiconductor device as claimed in claim 1, wherein, The impurity diffusion barrier pattern includes graphene.
3. The semiconductor device as claimed in claim 1, wherein, The sidewalls of the first impurity region and the sidewalls of the first conductive pattern are in contact with each other.
4. The semiconductor device as claimed in claim 3, wherein, The impurity diffusion blocking pattern in the first impurity region and the sidewalls of the first conductive pattern are in contact with each other.
5. The semiconductor device as claimed in claim 1, wherein, The first impurity region extends from a position spaced apart from the lower portion of the first sidewall of the second semiconductor pattern to a position overlapping a portion of the lower surface of the second semiconductor pattern.
6. The semiconductor device of claim 1, wherein, The first semiconductor pattern is connected to the lower surface of the second semiconductor pattern and is disposed on one side of the first impurity region.
7. The semiconductor device of claim 1, wherein, The second impurity region is formed on the uppermost surface of the second semiconductor pattern, and the second impurity region includes a second polysilicon pattern doped with impurities.
8. The semiconductor device of claim 1, wherein, The second impurity region is the upper part of the second semiconductor pattern that is doped with impurities.
9. The semiconductor device of claim 1, further comprising a first insulating pattern extending along the first direction, wherein, The first insulating pattern contacts the sidewall of the first conductive pattern in the first trench.
10. The semiconductor device of claim 1, further comprising: A capacitor electrically connected to the second impurity region.
11. A semiconductor device, comprising: A plurality of semiconductor structures are disposed on a substrate, wherein each of the plurality of semiconductor structures includes a first semiconductor pattern having a linear shape extending along a first direction, and a second semiconductor pattern protruding from the upper surface of the first semiconductor pattern in a vertical direction, wherein the plurality of semiconductor structures are spaced apart from each other in a second direction perpendicular to the first direction; A first conductive pattern is formed in a first trench between the first semiconductor patterns, wherein the first conductive pattern extends along the first direction; A first insulating pattern is formed in the first trench between the first semiconductor patterns, wherein the first insulating pattern contacts the sidewall of the first conductive pattern and extends along the first direction; A first impurity region extends from a position spaced apart from the lower portion of a first sidewall of the second semiconductor pattern to a position overlapping a portion of the lower surface of the second semiconductor pattern, wherein the first impurity region includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities, and the impurity diffusion barrier pattern surrounds the sidewalls and bottom of the polysilicon pattern to prevent the diffusion of the impurities doped in the polysilicon pattern. A gate insulating pattern is disposed on the first sidewall of each of the second semiconductor patterns; A second conductive pattern extends along the second direction on the gate insulating pattern; and The second impurity region is formed on each of the second semiconductor pattern. The sidewall of the first impurity region is in contact with the sidewall of the first conductive pattern.
12. The semiconductor device of claim 11, wherein, The first impurity region is formed in an opening adjacent to the first sidewall of the first semiconductor pattern and the second semiconductor pattern.
13. The semiconductor device of claim 11, wherein, The impurity diffusion barrier pattern includes graphene.
14. The semiconductor device of claim 11, wherein, The impurity diffusion blocking pattern in the first impurity region and the sidewalls of the first conductive pattern are in contact with each other.
15. The semiconductor device of claim 11, wherein, The first semiconductor pattern is connected to the lower surface of the second semiconductor pattern and is disposed on one side of the first impurity region.
16. A semiconductor device, comprising: A semiconductor structure disposed on a substrate, wherein the semiconductor structure includes a first semiconductor pattern having a linear shape extending along a first direction, and a second semiconductor pattern protruding from the upper surface of the first semiconductor pattern in a vertical direction. A first impurity region extends from a position spaced apart from the lower portion of the first sidewall of the second semiconductor pattern to a position overlapping a portion of the lower surface of the second semiconductor pattern, wherein the first impurity region includes an impurity diffusion barrier pattern and a polysilicon pattern doped with impurities. A gate insulating pattern is disposed on the first sidewall of the second semiconductor pattern; A second conductive pattern is formed on the gate insulating pattern; and A second impurity region is formed on the second semiconductor pattern. The impurity diffusion barrier pattern surrounds the sidewalls and bottom of the polysilicon pattern to prevent the diffusion of impurities doped in the polysilicon pattern.
17. The semiconductor device of claim 16, wherein, The impurity diffusion barrier pattern includes graphene.
18. The semiconductor device of claim 16, wherein, The first impurity region is formed in an opening adjacent to the first sidewall of the first semiconductor pattern and the second semiconductor pattern.