Semiconductor equipment
The semiconductor device integrates metal layers within trenches and insulating films to address the additional process requirement and high resistance issues, facilitating high-speed capacitor operation by simplifying the manufacturing process.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- RENESAS ELECTRONICS CORP
- Filing Date
- 2024-12-23
- Publication Date
- 2026-07-03
AI Technical Summary
The capacitor in existing semiconductor devices requires additional processes to form and has high parasitic resistance due to non-metallic electrodes, hindering high-speed operation.
A semiconductor device design incorporating metal layers within trenches and insulating films, allowing the capacitor to be formed in the same process as the substrate contact, reducing parasitic resistance and enabling high-speed operation.
The design reduces parasitic resistance and simplifies the manufacturing process by integrating the capacitor formation with substrate contact, enabling high-speed capacitor operation without additional steps.
Smart Images
Figure 2026111150000001_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to a semiconductor device.
Background Art
[0002] The semiconductor device disclosed in Japanese Unexamined Patent Application Publication No. 2019-096785 (Patent Document 1) includes a semiconductor substrate, a first insulating film, a second insulating film, and a conductive layer. The semiconductor substrate has a first semiconductor layer forming the lower surface of the semiconductor substrate and a second semiconductor layer formed on the first semiconductor layer and forming the upper surface of the semiconductor substrate. An impurity diffusion layer, which has a conductivity type opposite to that of the first semiconductor layer and the second conductor layer, is formed between the first semiconductor layer and the second semiconductor layer within the semiconductor substrate. A first trench extending from the upper surface of the semiconductor substrate toward the lower surface of the semiconductor substrate is formed within the semiconductor substrate. The first insulating film is formed within the first trench. A second trench extending toward the lower surface of the semiconductor substrate so as to penetrate the first insulating film and reach the first semiconductor layer is formed within the semiconductor substrate and within the first insulating film. The conductive layer is formed within the second trench. The second insulating film is formed between the side surface of the second trench and the conductive layer. The conductive layer is electrically connected to the first semiconductor layer at the bottom surface of the second trench. That is, the conductive layer is a substrate contact.
[0003] The semiconductor device disclosed in Japanese Patent Publication No. 2003-209189 (Patent Document 2) comprises a semiconductor substrate, a polysilicon layer, and a first insulating film. The semiconductor substrate has a first semiconductor layer forming the lower surface of the semiconductor substrate, a second insulating film formed on the first semiconductor layer, and a second semiconductor layer formed on the second insulating film and forming the upper surface of the semiconductor substrate. A trench is formed within the semiconductor substrate, extending from the upper surface to the lower surface of the semiconductor substrate, penetrating the second semiconductor layer and the second insulating film, and reaching the first semiconductor layer. The polysilicon layer is formed within the trench. The first insulating film is formed between the polysilicon layer and the side and bottom surfaces of the trench. The second semiconductor layer, the polysilicon layer, and the first insulating film interposed between the second semiconductor layer and the polysilicon layer form a capacitor. [Prior art documents] [Patent Documents]
[0004] [Patent Document 1] Japanese Patent Publication No. 2019-096785 [Patent Document 2] Japanese Patent Publication No. 2003-209189 [Overview of the Initiative] [Problems that the invention aims to solve]
[0005] The capacitor in the semiconductor device disclosed in Patent Document 2 cannot be formed in the same process as the substrate contact in the semiconductor device disclosed in Patent Document 1. Therefore, an additional process is required to form the capacitor, complicating the manufacturing process. Furthermore, since the electrodes of the capacitor in the semiconductor device disclosed in Patent Document 2 are made of a non-metallic material, i.e., polysilicon, the parasitic resistance of the electrodes is high, making high-speed operation of the capacitor difficult. Other problems and novel features will become clear from the description herein and the accompanying drawings. [Means for solving the problem]
[0006] The semiconductor device according to this disclosure comprises a semiconductor substrate having a bottom surface and an upper surface located opposite the bottom surface, a first insulating film formed on the upper surface, a second insulating film formed on the upper surface, a first metal layer, a second metal layer, a third insulating film, and a fourth insulating film. The semiconductor substrate has a first semiconductor layer forming the bottom surface and a second semiconductor layer formed on the first semiconductor layer and forming the upper surface. The first semiconductor layer has a first impurity diffusion layer formed within the first semiconductor layer and located at the interface between the first semiconductor layer and the second semiconductor layer. The conductivity type of the first semiconductor layer and the conductivity type of the second semiconductor layer is the first conductivity type. The conductivity type of the first impurity diffusion layer is the second conductivity type, opposite to the first conductivity type. A first trench is formed in the semiconductor substrate and the first insulating film, penetrating the first insulating film and extending toward the bottom surface. A second trench is formed in the semiconductor substrate and the second insulating film, penetrating the second insulating film and extending toward the bottom surface so as to reach the first semiconductor layer. A first metal layer is formed within a first trench. A second metal layer is formed within a second trench. A third insulating film is formed between the first metal layer and the side surface of the first trench, and between the first metal layer and the bottom surface of the first trench. A fourth insulating film is formed between the second metal layer and the side surface of the second trench. The second metal layer is electrically connected to the first semiconductor layer at the bottom surface of the second trench. [Effects of the Invention]
[0007] The semiconductor device described herein makes it possible to reduce the parasitic resistance of the capacitor while avoiding complexity in the manufacturing process. [Brief explanation of the drawing]
[0008] [Figure 1] This is a plan view of semiconductor device DEV1. [Figure 2] This is a cross-sectional view of semiconductor device DEV1 in line II-II in Figure 1. [Figure 3] This is a manufacturing process diagram for semiconductor device DEV1. [Figure 4] This is a cross-sectional view illustrating the impurity diffusion layer formation process S1. [Figure 5]It is a cross-sectional view for explaining the epitaxial growth process S2. [Figure 6] It is a cross-sectional view for explaining the impurity diffusion layer formation process S3. [Figure 7] It is a cross-sectional view for explaining the impurity diffusion layer formation process S4. [Figure 8] It is a cross-sectional view for explaining the insulating film formation process S5. [Figure 9] It is a cross-sectional view for explaining the gate insulating film formation process S6. [Figure 10] It is a cross-sectional view for explaining the gate electrode formation process S7. [Figure 11] It is a cross-sectional view for explaining the impurity diffusion layer formation process S8. [Figure 12] It is a cross-sectional view for explaining the sidewall spacer formation process S9. [Figure 13] It is a cross-sectional view for explaining the impurity diffusion layer formation process S10. [Figure 14] It is a cross-sectional view for explaining the interlayer insulating film formation process S11. [Figure 15] It is a cross-sectional view for explaining the trench formation process S12. [Figure 16] It is a cross-sectional view for explaining the interlayer insulating film formation process S13. [Figure 17] It is a cross-sectional view for explaining the etching process S14. [Figure 18] It is a cross-sectional view for explaining the etching process S15. [Figure 19] It is a cross-sectional view for explaining the etching process S16. [Figure 20] It is a cross-sectional view of the semiconductor device DEV2. [Figure 21] It is a manufacturing process diagram of the semiconductor device DEV2. [Figure 22] It is a cross-sectional view for explaining the interlayer insulating film formation process S13 in the manufacturing method of the semiconductor device DEV2. [Figure 23] It is a cross-sectional view for explaining the etching process S18 in the manufacturing method of the semiconductor device DEV2. ] [Figure 24]It is a cross-sectional view for explaining an etching step S19 in a method for manufacturing a semiconductor device DEV2. [Figure 25] It is a cross-sectional view for explaining a polishing step S20 in a method for manufacturing a semiconductor device DEV2. [Figure 26] It is a cross-sectional view for explaining an etching step S21 in a method for manufacturing a semiconductor device DEV2. [Figure 27] It is a cross-sectional view of a semiconductor device DEV3. [Figure 28] It is a cross-sectional view for explaining a gate electrode formation step S7 in a method for manufacturing a semiconductor device DEV3. [Figure 29A] It is a first cross-sectional view for explaining a trench formation step S12 in a method for manufacturing a semiconductor device DEV3. [Figure 29B] It is a second cross-sectional view for explaining a trench formation step S12 in a method for manufacturing a semiconductor device DEV3. [Figure 29C] It is a third cross-sectional view for explaining a trench formation step S12 in a method for manufacturing a semiconductor device DEV3. [Figure 29D] It is a fourth cross-sectional view for explaining a trench formation step S12 in a method for manufacturing a semiconductor device DEV3. [Figure 30] It is a cross-sectional view of a semiconductor device DEV4. [Figure 31] It is a cross-sectional view for explaining an interlayer insulating film formation step S13 in a method for manufacturing a semiconductor device DEV4. [Figure 32] It is a manufacturing process diagram of a semiconductor device DEV4. [Figure 33] It is a cross-sectional view for explaining an etching step S22 in a method for manufacturing a semiconductor device DEV4. [Figure 34] It is a cross-sectional view for explaining an etching step S23 in a method for manufacturing a semiconductor device DEV4. [Figure 35] It is a cross-sectional view for explaining an etching step S24 in a method for manufacturing a semiconductor device DEV4. [Figure 36] It is a plan view of a semiconductor device DEV5. [Figure 37]This is a cross-sectional view of semiconductor device DEV5 at XXXVII-XXXVII in Figure 36. [Figure 38] This is a cross-sectional view of semiconductor device DEV5 in Figure 36, specifically at XXXVIII-XXXVIII. [Figure 39] This is a plan view illustrating the gate electrode formation step S7 in the manufacturing method of semiconductor device DEV5. [Figure 40] This is a first cross-sectional view illustrating the trench formation step S12 in the manufacturing method of semiconductor device DEV5. [Figure 41] This is a second cross-sectional view illustrating the trench formation step S12 in the manufacturing method of the semiconductor device DEV5. [Figure 42] This is a cross-sectional view of semiconductor device DEV6. [Figure 43] This is a manufacturing process diagram for the semiconductor device DEV6. [Figure 44] This is a cross-sectional view of semiconductor device DEV7. [Figure 45] This is a manufacturing process diagram for the semiconductor device DEV7. [Figure 46] This is a cross-sectional view illustrating the etching process S26 in the manufacturing method of the semiconductor device DEV7. [Figure 47] This is a cross-sectional view illustrating the metal layer formation step S27 in the manufacturing method of the semiconductor device DEV7. [Figure 48] This is a cross-sectional view illustrating the interlayer insulating film formation step S28 in the manufacturing method of the semiconductor device DEV7. [Figure 49] This is a cross-sectional view illustrating the planarization step S29 in the manufacturing method of the semiconductor device DEV7. [Figure 50] This is a cross-sectional view illustrating the etching process S30 in the manufacturing method of the semiconductor device DEV7. [Figure 51] This is a cross-sectional view illustrating the etching process S31 in the manufacturing method of the semiconductor device DEV7. [Figure 52] This is a cross-sectional view illustrating the etching process S32 in the manufacturing method of the semiconductor device DEV7. [Modes for carrying out the invention]
[0009] The details of the embodiments will be described with reference to the drawings. In the following drawings, the same or corresponding parts will be denoted by the same reference numerals, and redundant descriptions will not be repeated.
[0010] (First Embodiment) The semiconductor device DEV1 according to the first embodiment will be described.
[0011] <Configuration of Semiconductor Device DEV1> As shown in Figures 1 and 2, the semiconductor device DEV1 has a semiconductor substrate SUB. The semiconductor substrate SUB has a bottom surface F1 and an top surface F2 located on the opposite side of the bottom surface F1. The semiconductor substrate SUB has a semiconductor layer SEL1 forming the bottom surface F1 and a semiconductor layer SEL2 formed on semiconductor layer SEL1 and forming the top surface F2. The semiconductor substrate SUB (semiconductor layer SEL1, semiconductor layer SEL2) is made of, for example, single-crystal silicon. The conductivity type of semiconductor layer SEL1 and semiconductor layer SEL2 is a first conductivity type. The first conductivity type is, for example, p-type.
[0012] The semiconductor layer SEL1 has an impurity diffusion layer IDL1. The impurity diffusion layer IDL1 is formed within the semiconductor layer SEL1 at the interface between semiconductor layer SEL1 and semiconductor layer SEL2, that is, on the upper surface of semiconductor layer SEL1. The conductivity type of the impurity diffusion layer IDL1 is the second conductivity type, which is opposite to the first conductivity type. The second conductivity type is, for example, n-type. The semiconductor layer SEL2 has an impurity diffusion layer IDL2. The impurity diffusion layer IDL2 is formed within the semiconductor layer SEL2 on the upper surface F2 and extends toward the lower surface F1 so as to reach the impurity diffusion layer IDL1. The conductivity type of the impurity diffusion layer IDL2 is the second conductivity type. Note that the dopant concentration in the impurity diffusion layer IDL1 is higher than, for example, the dopant concentration in the impurity diffusion layer IDL2.
[0013] The semiconductor layer SEL2 further comprises a source layer SL, a drain layer DL, and a well layer WEL. The source layer SL is formed on the upper surface F2 within the semiconductor layer SEL2. The drain layer DL is formed on the upper surface F2 within the semiconductor layer SEL2, separated from the source layer SL. The well layer WEL is formed on the upper surface F2 within the semiconductor layer SEL2 so as to surround the source layer SL and the drain layer DL in both plan and cross-sectional views. The conductivity types of the source layer SL and the drain layer DL are opposite to those of the well layer WEL.
[0014] The source layer SL has a first portion SL1 and a second portion SL2. The drain layer DL has a first portion DL1 and a second portion DL2. The first portion SL1 is located between the second portion SL2 and the drain layer DL, and the first portion DL1 is located between the second portion DL2 and the source layer SL. The dopant concentration in the first portion SL1 is lower than the dopant concentration in the second portion SL2, and the dopant concentration in the first portion DL1 is lower than the dopant concentration in the second portion DL2. In other words, the source layer SL and the drain layer DL have an LDD (Lightly Doped Diffusion) structure.
[0015] The semiconductor device DEV1 further has an insulating film IF1. A trench TR1 is formed on the upper surface F2. The trench TR1 extends toward the lower surface F1. The insulating film IF1 is formed within the trench TR1. That is, the insulating film IF1 is formed on the upper surface F2. The impurity diffusion layer IDL2 surrounds the insulating film IF1 in both cross-sectional and plan views. The insulating film IF1 is formed of, for example, silicon oxide.
[0016] The semiconductor device DEV1 further has an insulating film IF2. A trench TR2 is formed on the upper surface F2. The trench TR2 extends toward the lower surface F1. The insulating film IF2 is formed within the trench TR2. That is, the insulating film IF2 is formed on the upper surface F2. The insulating film IF2 is formed of, for example, silicon oxide.
[0017] The semiconductor device DEV1 further has an insulating film IF3. A trench TR3 is formed on the upper surface F2. The trench TR3 extends toward the lower surface F1. The insulating film IF3 is formed within the trench TR3. That is, the insulating film IF3 is formed on the upper surface F2. In a plan view, the insulating film IF3 surrounds the insulating film IF1 with a gap between them. The semiconductor layer SEL2 further has an impurity diffusion layer IDL3. The impurity diffusion layer IDL3 is formed on the upper surface F2 located between the insulating films IF1 and IF3 within the semiconductor layer SEL2. The conductivity type of the impurity diffusion layer IDL3 is the second conductivity type. The dopant concentration in the impurity diffusion layer IDL3 is higher than, for example, the dopant concentration in the impurity diffusion layer IDL2.
[0018] The semiconductor device DEV1 further includes a gate insulating film GI, a gate electrode GE, and a sidewall spacer SWS. The gate insulating film GI is formed on the upper surface F2 located between the source layer SL and the drain layer DL. The gate electrode GE is formed on the gate insulating film GI. The sidewall spacer SWS is formed on the upper surface F2 so as to be in contact with both sides of the gate electrode GE. That is, the sidewall spacer SWS is formed on the first portion SL1 and the first portion DL1. The gate insulating film GI is formed of, for example, silicon oxide. The gate electrode GE is formed of, for example, polysilicon. The sidewall spacer SWS is formed of, for example, silicon nitride. The source layer SL, drain layer DL, well layer WEL, gate insulating film GI, and gate electrode GE constitute a transistor.
[0019] The semiconductor device DEV1 further has an interlayer insulating film ILD1. The interlayer insulating film ILD1 is formed on the upper surface F2 so as to cover insulating films IF1, IF2, IF3, gate electrode GE, and sidewall spacer SWS. The interlayer insulating film ILD1 has a first layer ILD1a and a second layer ILD1b formed on the first layer ILD1a. The first layer ILD1a is formed of, for example, silicon nitride. The second layer ILD1b is formed of, for example, silicon oxide. The interlayer insulating film ILD1 has an upper surface F3.
[0020] Trench TR4 is formed within the interlayer insulating film ILD1, insulating film IF1, and semiconductor substrate SUB. Trench TR5 is also formed within the interlayer insulating film ILD1, insulating film IF2, and semiconductor substrate SUB. Trench TR4 extends toward the bottom surface F1 so as to penetrate the interlayer insulating films ILD1 and IF1 and reach the semiconductor layer SEL1. Trench TR5 extends toward the bottom surface F1 so as to penetrate the interlayer insulating films ILD1 and IF2 and reach the semiconductor layer SEL1.
[0021] The semiconductor device DEV1 further has an interlayer insulating film ILD2. The interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1. The interlayer insulating film ILD2 is made of, for example, silicon oxide. Through holes TH1 and TH2 are formed within the interlayer insulating film ILD2. Through holes TH1 and TH2 penetrate the interlayer insulating film ILD2. In a plan view, through hole TH1 overlaps with trench TR4, and through hole TH2 overlaps with trench TR5.
[0022] Through-holes TH3, TH4, TH5, and TH6 are formed within the interlayer insulating film ILD1 and ILD2. Through-holes TH3, TH4, TH5, and TH6 penetrate the interlayer insulating films ILD1 and ILD2, respectively. Through-hole TH3 overlaps with the impurity diffusion layer IDL3 in a plan view. Through-hole TH4 overlaps with the source layer SL in a plan view, and through-hole TH5 overlaps with the drain layer DL in a plan view. Through-hole TH6 overlaps with the gate electrode GE in a plan view.
[0023] The insulating film IF1 has a first portion IF1a and a second portion IF1b. The first portion IF1a is located on the outer edge of the insulating film IF1 in a plan view. The second portion IF1b is located inside the first portion IF1a in a plan view. Trench TR4 penetrates the second portion IF1b. The number of trenches TR4 is, for example, multiple. Multiple trenches TR4 are arranged, for example, in a grid pattern in a plan view.
[0024] The semiconductor device DEV1 further comprises a metal layer ML1, a metal layer ML2, an insulating film IF4, and an insulating film IF5. The metal layer ML1 is formed within the trench TR4 and the through hole TH1. The insulating film IF4 is formed between the side and bottom surfaces of the trench TR4 and the metal layer ML1. That is, the metal layer ML1 is electrically insulated from the semiconductor substrate SUB by the insulating film IF4. The metal layer ML2 is formed within the trench TR5 and the through hole TH2. The insulating film IF5 is formed between the side surfaces of the trench TR5 and the metal layer ML2. The metal layer ML2 is electrically connected to the semiconductor layer SEL1 at the bottom surface of the trench TR5. That is, the insulating film IF5 is not formed between the bottom surface of the trench TR5 and the metal layer ML2. The metal layers ML1 and ML2 are made of a metallic material. The metal layers ML1 and ML2 are made of, for example, tungsten. The insulating films IF4 and IF5 are made of, for example, silicon oxide.
[0025] The metal layer ML1, the impurity diffusion layer IDL2, and the insulating film IF4 located between the metal layer ML1 and the impurity diffusion layer IDL2, i.e., the metal layer ML1, the impurity diffusion layer IDL2, and the insulating film IF4 located on the side surface of the trench TR4, constitute a capacitor.
[0026] The semiconductor device DEV1 further has an insulating film IF6. Trench TR6 is formed within the interlayer insulating film ILD1, the insulating film IF3, and the semiconductor substrate SUB. Trench TR6 penetrates the interlayer insulating film ILD1 and the insulating film IF3 and extends toward the lower surface F1 to reach the semiconductor layer SEL1. The insulating film IF6 is formed within trench TR6. A void AG is formed within the insulating film IF6.
[0027] The semiconductor device DEV1 further has a metal layer ML3. The metal layer ML3 is formed within the interlayer insulating film ILD. More specifically, the metal layer ML3 is formed within the through hole TH3. The metal layer ML3 is electrically connected to the impurity diffusion layer IDL3. That is, the metal layer ML3 is electrically connected to the capacitor mentioned above. The metal layer ML3 is formed of, for example, tungsten.
[0028] The semiconductor device DEV1 further includes a metal layer ML4, a metal layer ML5, and a metal layer ML6. Metal layers ML4, ML5, and ML6 are formed within an interlayer insulating film ILD. More specifically, metal layer ML4 is formed within a through-hole TH4, metal layer ML5 is formed within a through-hole TH5, and metal layer ML6 is formed within a through-hole TH6. Metal layer ML4 is electrically connected to the source layer SL, metal layer ML5 is electrically connected to the drain layer DL, and metal layer ML6 is electrically connected to the gate electrode GE. That is, metal layers ML4, ML5, and ML6 are electrically connected to the transistor. Metal layers ML4, ML5, and ML6 are formed of, for example, tungsten.
[0029] <Manufacturing method for semiconductor device DEV1> As shown in Figure 3, the manufacturing method for the semiconductor device DEV1 includes an impurity diffusion layer formation step S1, an epitaxial growth step S2, an impurity diffusion layer formation step S3, an impurity diffusion layer formation step S4, and an insulating film formation step S5.
[0030] As shown in Figure 4, in the impurity diffusion layer formation step S1, an impurity diffusion layer IDL1 is formed within the semiconductor layer SEL2. In the impurity diffusion layer formation step S1, firstly, a semiconductor substrate SUB is prepared. At this point, the semiconductor substrate SUB has only the semiconductor layer SEL1. Secondly, the impurity diffusion layer IDL1 is formed by ion implantation onto the upper surface of the semiconductor layer SEL1. As shown in Figure 5, in the epitaxial growth step S2, the semiconductor layer SEL2 is formed by epitaxial growth on the semiconductor layer SEL1, for example, by the CVD (Chemical Vapor Deposition) method.
[0031] As shown in Figure 6, in the impurity diffusion layer formation step S3, an impurity diffusion layer IDL2 is formed within the semiconductor layer SEL2. In the impurity diffusion layer formation step S3, firstly, ion implantation is performed on the upper surface F2. Secondly, heat treatment is performed on the semiconductor substrate SUB, causing the implanted ions to diffuse toward the lower surface F1, thereby forming the impurity diffusion layer IDL2. As shown in Figure 7, in the impurity diffusion layer formation step S4, ion implantation is performed on the upper surface F2, forming a well layer WEL within the semiconductor layer SEL2.
[0032] As shown in Figure 8, in the insulating film formation step S5, insulating films IF1, IF2, and IF3 are formed on the upper surface F2. In the insulating film formation step S5, firstly, a hard mask is formed on the upper surface F2. Secondly, trenches TR1, TR2, and TR3 are formed on the upper surface F2 by dry etching of the upper surface F2 through the openings in the hard mask. Thirdly, constituent materials such as insulating film IF1 are formed inside trenches TR1, TR2, TR3, and on the hard mask, for example by CVD. Fourthly, the constituent materials such as insulating film IF1 formed outside trenches TR1, TR2, and TR3 are removed, for example by CMP (Chemical Mechanical Polishing) or etch-back. After the formation of insulating films IF1, IF2, and IF3, the hard mask is removed.
[0033] As shown in Figure 3, the manufacturing method for semiconductor device DEV1 further includes a gate insulating film formation step S6, a gate electrode formation step S7, an impurity diffusion layer formation step S8, a sidewall spacer formation step S9, and an impurity diffusion layer formation step S10.
[0034] As shown in Figure 9, in the gate insulating film formation step S6, a gate insulating film GI is formed on the upper surface F2, for example by thermal oxidation. As shown in Figure 10, in the gate electrode formation step S7, a gate electrode GE is formed on the gate insulating film GI. In the gate electrode formation step S7, firstly, the constituent material of the gate electrode GE is formed on the gate insulating film GI, for example by CVD. Secondly, a resist pattern is formed on the constituent material of the gate electrode GE. The resist pattern is formed by coating the constituent material of the gate electrode GE with photoresist and patterning the photoresist with photolithography. Thirdly, dry etching is performed on the constituent material of the gate electrode GE through the openings in the resist pattern.
[0035] As shown in Figure 11, in the impurity diffusion layer formation step S8, ion implantation is performed to form a first portion SL1 and a first portion DL1 on the upper surface F2 within the semiconductor layer SEL2. As shown in Figure 12, in the sidewall spacer formation step S9, a sidewall spacer SWS is formed on the upper surface F2 so as to be in contact with both sides of the gate electrode GE. In the sidewall spacer formation step S9, firstly, the constituent material of the sidewall spacer SWS is formed on the upper surface F2 so as to cover the gate electrode GE, gate insulating film GI, insulating film IF1, insulating film IF2 and insulating film IF3. Secondly, etch-back is performed on the constituent material of the sidewall spacer SWS.
[0036] As shown in Figure 13, in the impurity diffusion layer formation step S10, ion implantation is performed, thereby forming a second portion SL2, a second portion DL2, and an impurity diffusion layer IDL3 on the upper surface F2 within the semiconductor layer SEL2.
[0037] As shown in Figure 3, the method for manufacturing the semiconductor device DEV1 further includes an interlayer insulating film formation step S11, a trench formation step S12, an interlayer insulating film formation step S13, an etching step S14, an etching step S15, an etching step S16, and a metal layer formation step S17.
[0038] As shown in Figure 14, in the interlayer insulating film formation step S11, an interlayer insulating film ILD1, that is, a first layer ILD1a and a second layer ILD1b, is formed. In the interlayer insulating film formation step S11, firstly, the first layer ILD1a is formed on the upper surface F2, for example by CVD, so as to cover insulating film IF1, insulating film IF2, insulating film IF3, gate electrode GE and sidewall spacer SWS. Secondly, the second layer ILD1b is formed on the first layer ILD1a, for example by CVD.
[0039] As shown in Figure 15, in the trench formation step S12, trench TR4 is formed by dry etching the interlayer insulating film ILD1, insulating film IF1, and semiconductor substrate SUB through the openings in the resist pattern formed on the interlayer insulating film ILD1. At the same time, trench TR5 is formed by dry etching the interlayer insulating film ILD1, insulating film IF2, and semiconductor substrate SUB through the openings in the resist pattern formed on the interlayer insulating film ILD1. Furthermore, trench TR6 is formed by dry etching the interlayer insulating film ILD1, insulating film IF3, and semiconductor substrate SUB through the openings in the resist pattern formed on the interlayer insulating film ILD1.
[0040] As shown in Figure 16, in the interlayer insulating film formation step S13, an interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1. At this time, the interlayer insulating film ILD2 is also formed in trenches TR4, TR5, and TR6. In the interlayer insulating film formation step S13, firstly, the constituent material of the interlayer insulating film ILD2 is formed on the interlayer insulating film ILD1, in trenches TR4, TR5, and TR6, for example by CVD. Secondly, the upper surface of the constituent material of the interlayer insulating film ILD2 is planarized, for example by CMP.
[0041] Furthermore, the interlayer insulating film ILD2 formed in trench TR4 becomes insulating film IF4, the interlayer insulating film ILD2 formed in trench TR5 becomes insulating film IF5, and the interlayer insulating film ILD2 formed in trench TR5 becomes insulating film IF6.
[0042] As shown in Figure 17, in etching step S14, a through hole TH2 is formed in the interlayer insulating film ILD2. In etching step S14, firstly, a hard mask HM1 is formed on the interlayer insulating film ILD2. The hard mask HM1 has openings in positions that overlap with trenches TR1, TR2, impurity diffusion layer IDL3, source layer SL, drain layer DL, and gate electrode GE in a plan view. The hard mask HM1 is formed of, for example, silicon nitride. Secondly, a resist pattern RP is formed on the hard mask HM1. The resist pattern RP has openings in positions that overlap with trench TR2 in a plan view. That is, the openings of the resist pattern RP and the openings of the hard mask HM1 overlap with each other only in positions that overlap with trench TR2 in a plan view. Thirdly, the through hole TH2 is formed by dry etching of the interlayer insulating film ILD2 through the openings of the resist pattern RP and the openings of the hard mask HM1. In addition, the insulating film IF5 located on the bottom surface of trench TR5 is also removed by this dry etching. After the etching process S14 is completed, the resist pattern RP is removed.
[0043] As shown in Figure 18, in etching step S15, the interlayer insulating film ILD2 and the second layer ILD1b are dry-etched through the openings in the hard mask HM1, forming through-holes TH1, TH3, TH4, TH5, and TH6. As shown in Figure 19, in etching step S16, the first layer ILD1a is dry-etched through through-holes TH3, TH4, TH5, and TH6. During this dry etching, the hard mask HM1 is also removed.
[0044] In the metal layer formation process S17, metal layer ML1 is formed in trench TR4 and through hole TH1, and metal layer ML2 is formed in trench TR5 and through hole TH2. Also in the metal layer formation process S17, metal layer ML3 is formed in through hole TH3, metal layer ML4 is formed in through hole TH4, metal layer ML5 is formed in through hole TH5, and metal layer ML6 is formed in through hole TH6. In the metal layer formation process S17, firstly, constituent materials such as metal layer ML1 are formed in each trench, each through hole, and on the interlayer insulating film ILD2, for example by CVD. Secondly, constituent materials such as metal layer ML1 formed outside each trench and each through hole are removed, for example by CMP. As a result, the structure of the semiconductor device DEV1 shown in Figures 1 and 2 is formed.
[0045] <Effects of Semiconductor Device DEV1> In semiconductor device DEV1, the capacitor is composed of a metal layer ML1, an impurity diffusion layer IDL2, and an insulating film IF4. Therefore, compared to a case where one electrode of the capacitor is formed from a non-metallic material such as polysilicon instead of the metal layer ML1, the parasitic resistance of the capacitor is reduced in semiconductor device DEV1. As a result, semiconductor device DEV1 enables high-speed operation of the capacitor.
[0046] In semiconductor device DEV1, substrate contact is made by a metal layer ML2 formed in a trench TR2. In semiconductor device DEV1, the capacitor described above, more specifically the metal layer ML1 and the insulating film IF4, can be formed by the process of forming the structure for this substrate contact. Thus, semiconductor device DEV1 makes it possible to form a capacitor capable of high-speed operation without additional processes.
[0047] <Example 1> As shown in Figure 20, in the semiconductor device DEV2 according to a modification of the first embodiment, the width of trench TR4 is greater than the widths of trench TR5 and trench TR6.
[0048] As shown in Figure 21, the manufacturing method of semiconductor device DEV2 includes etching steps S18, S19, polishing step S20, and S21 instead of etching steps S14, S15, and S16. As shown in Figure 22, after the interlayer insulating film formation step S13 is completed, an interlayer insulating film ILD2 having voids AG is formed in the trench TR4. The upper end of the voids AG formed in the trench TR4 is located closer to the upper surface F3 than that of semiconductor device DEV1. Furthermore, the upper end of the voids AG formed in the trench TR4 is located closer to the upper surface F3 than the upper ends of the voids AG formed in the trench TR5 and the upper ends of the voids AG formed in the trench TR6. Note that the position of the upper end of the voids AG becomes closer to the upper surface F3 as the width of the trench TR4 increases.
[0049] As shown in Figure 23, in etching step S18, through holes TH3, TH4, TH5, and TH6 are formed in the interlayer insulating film ILD2 and the second layer ILD1b. In etching step S18, firstly, a resist pattern RP1 is formed on the interlayer insulating film ILD2. The resist pattern RP1 has openings in positions that overlap with the impurity diffusion layer IDL3 in a plan view, positions that overlap with the source layer SL in a plan view, positions that overlap with the drain layer DL, and positions that overlap with the gate electrode GE. Secondly, dry etching is performed on the interlayer insulating film ILD2 and the second layer ILD1b through the openings in the resist pattern RP1. After etching step S18, the resist pattern RP1 is removed.
[0050] As shown in Figure 24, in etching step S19, through holes TH2 are formed in the interlayer insulating film ILD2. In etching step S19, firstly, a resist pattern RP2 is formed on the interlayer insulating film ILD2. The resist pattern RP2 has openings in positions that overlap with the trench TR5 in a plan view. The resist pattern RP2 is also formed in through holes TH3, TH4, TH5, and TH6. Secondly, dry etching of the interlayer insulating film ILD2 is performed through the openings in the resist pattern RP2. At this time, the insulating film IF5 located on the bottom surface of the trench TR5 is also removed. After etching step S19, the resist pattern RP2 is removed.
[0051] As shown in Figure 25, in polishing step S20, the upper surface F3 is polished using the CMP method. As a result, the upper end of the void AG formed in the trench TR4 reaches the upper surface F3, and the upper end of the void AG formed in the trench TR4 becomes the through hole TH1. As shown in Figure 26, in etching step S21, the first layer ILD1a is dry-etched through the through holes TH3, TH4, TH5, and TH6. After etching step S21, metal layer formation step S17 is performed to form the structure of the semiconductor device DEV2 shown in Figure 20.
[0052] In semiconductor device DEV2, the cross-sectional area of the metal layer ML1 is larger compared to semiconductor device DEV1, which further reduces the resistance of the metal layer ML1 and enables the capacitor to operate at an even faster speed. In addition, the manufacturing method for semiconductor device DEV2 can be further simplified compared to the manufacturing method for semiconductor device DEV1.
[0053] <Modification 2> As shown in Figure 27, in semiconductor device DEV3 according to a modification of the first embodiment, the bottom surface of trench TR4 is located within the impurity diffusion layer IDL1. That is, in semiconductor device DEV3, the distance between the bottom surface of trench TR4 and the bottom surface F1 is greater than the distance between the bottom surface of trench TR5 and the bottom surface F1.
[0054] As shown in Figure 28, in the manufacturing method of semiconductor device DEV3, a hard mask HM2 is formed on the insulating film IF1 in the gate electrode formation step S7. The hard mask HM2 is made of polysilicon, similar to the gate electrode GE. As shown in Figures 29A, 29B, 29C, and 29D, in the manufacturing method of semiconductor device DEV3, the dry etching in the trench formation step S12 is performed in four stages. As shown in Figure 29A, the first stage of dry etching is performed until trench TR5 penetrates the insulating film IF2 and trench TR6 penetrates the insulating film IF3. At this time, the first stage of dry etching is stopped by the hard mask HM2, so the bottom surface of trench TR4 is located on the hard mask HM2.
[0055] As shown in Figure 29B, in the second stage of dry etching, the etching of the hard mask HM2 causes trench TR4 to penetrate the hard mask HM2, and trench TR4 reaches the insulating film IF1. The second stage of dry etching also progresses into the semiconductor substrate SUB, and trenches TR5 and TR6 are further excavated. As shown in Figure 29C, in the third stage of dry etching, trench TR4 penetrates the insulating film IF1 and reaches the semiconductor substrate SUB. Since the third stage of dry etching does not progress into the semiconductor substrate SUB, trenches TR5 and TR6 are not excavated.
[0056] As shown in Figure 29D, the fourth stage of dry etching progresses the dry etching of the semiconductor substrate SUB, and trenches TR4, TR5, and TR6 are further excavated. In this way, the depth of trench TR4 becomes smaller than the depths of trenches TR5 and TR6, and the structure of semiconductor device DEV3 shown in Figure 27 is formed.
[0057] In semiconductor device DEV1, depending on the voltage applied to the metal layer ML1, an inversion layer may form in the semiconductor layer SEL1 opposite the metal layer ML1, with the insulating film IF4 in between. This inversion capacitance causes fluctuations in the capacitor's capacitance. In semiconductor device DEV3, since the bottom surface of the trench TR4 is located within the impurity diffusion layer IDL1, the fluctuations in capacitor capacitance caused by the formation of such an inversion layer can be suppressed.
[0058] (Second Embodiment) The semiconductor device DEV4 according to the second embodiment will now be described. Here, the differences from the semiconductor device DEV1 will be mainly explained.
[0059] <Configuration of semiconductor device DEV4> As shown in Figure 30, the semiconductor device DEV4 has an insulating film IF4 consisting of a first layer IF4a, a second layer IF4b, and a third layer IF4c. The second layer IF4b is formed on the first layer IF4a, and the third layer IF4c is formed on the second layer IF4b. The first layer IF4a and the third layer IF4c are made of silicon oxide, and the second layer IF4b is made of silicon nitride. In other words, in the semiconductor device DEV4, the insulating film IF4 is formed of an ONO (Oxide-Nitride-Oxide) film.
[0060] In semiconductor device DEV4, the interlayer insulating film ILD2 has a first layer ILD2a, a second layer ILD2b formed on the first layer ILD2a, and a third layer ILD2c formed on the second layer ILD2b. The first layer ILD2a and the third layer ILD2c are made of silicon oxide, and the second layer ILD2b is made of silicon nitride. In semiconductor device DEV4, the insulating films IF5 and IF6 each also have a first layer made of silicon oxide, a second layer made of silicon nitride formed on the first layer, and a third layer made of silicon oxide formed on the second layer.
[0061] <Manufacturing method for semiconductor device DEV4> As shown in Figure 31, in the manufacturing method of semiconductor device DEV4, in the interlayer insulating film formation step S13, the constituent materials of the first layer ILD2a, the second layer ILD2b, and the third layer ILD2c are sequentially formed on the interlayer insulating film ILD1. The first layer ILD2a and the second layer ILD2b are formed, for example, by the ALD (Atomic Layer Deposition) method. The third layer ILD2c is formed, for example, by the CVD method. The constituent materials of the first layer ILD2a, the second layer ILD2b, and the third layer ILD2c are also sequentially formed in trench TR4, trench TR5, and trench TR6. As shown in Figure 32, the manufacturing method of semiconductor device DEV4 has etching steps S22, S23, and S24 instead of etching steps S14, S15, and S16.
[0062] As shown in Figure 33, in etching step S22, through holes TH2, TH3, TH4, TH5, and TH6 are formed in the third layer ILD2c and the second layer ILD2b. In etching step S22, firstly, a hard mask HM1 is formed on the interlayer insulating film ILD2.
[0063] Secondly, a resist pattern RP is formed on the hard mask HM1. The resist pattern RP has openings in positions that overlap with the trench TR5 in a plan view, the impurity diffusion layer IDL3 in a plan view, the source layer SL in a plan view, the drain layer DL in a plan view, and the gate electrode GE in a plan view. In other words, the openings of the resist pattern RP and the openings of the hard mask HM1 overlap with each other in positions that overlap with the trench TR5 in a plan view, the impurity diffusion layer IDL3 in a plan view, the source layer SL in a plan view, the drain layer DL in a plan view, and the gate electrode GE in a plan view.
[0064] Thirdly, dry etching is performed on the third layer ILD2c and the second layer ILD2b through the openings in the resist pattern RP and the hard mask HM1. This forms through holes TH2, TH3, TH4, TH5, and TH6. This dry etching also removes the second and third layers of the insulating film IF5 located on the bottom surface of the trench TR5. After the etching process S22 is completed, the resist pattern RP is removed.
[0065] As shown in Figure 34, in etching step S23, through-holes TH1 are formed by dry etching of the third layer ILD2c through the openings in the hard mask HM1. At the same time, dry etching of the first layer of insulating film IF5 located on the bottom surface of the trench TR5 is performed through through-holes TH2, and dry etching of the first layer ILD2a and the second layer ILD1b is also performed through through-holes TH3, TH4, TH5, and TH6.
[0066] As shown in Figure 35, in etching step S24, dry etching is performed on the first layer ILD1a through through holes TH3, TH4, TH5, and TH6. Following etching step S24, metal layer formation step S17 is performed to form the structure of semiconductor device DEV4 shown in Figure 30.
[0067] <Effects of Semiconductor Device DEV4> In semiconductor device DEV4, the insulating film IF4 is formed of an ONO film. The ONO film has a higher dielectric constant than a single layer of silicon oxide. Therefore, semiconductor device DEV4 can further increase the capacitance of the capacitor, which is composed of a metal layer ML1, an impurity diffusion layer IDL2, and an insulating film IF4.
[0068] (Third embodiment) The semiconductor device DEV5 according to the third embodiment will be described. Here, the differences from the semiconductor device DEV4 will be mainly explained.
[0069] <Configuration of Semiconductor Device DEV5> As shown in Figures 36 and 38, the semiconductor device DEV5 has a hard mask HM3. The hard mask HM3 is formed on the first portion IF1a and the second portion IF1b. The hard mask HM3 only needs to be formed on at least the first portion IF1a. However, as shown in Figure 37, the hard mask HM3 is not formed between two adjacent trenches TR4. The hard mask HM3 is formed of polysilicon, similar to the gate electrode GE.
[0070] <Manufacturing method for semiconductor device DEV5> In the manufacturing method of the semiconductor device DEV5, a hard mask HM3 is formed in addition to the gate electrode GE in the gate electrode formation step S7. As shown in Figure 39, the hard mask HM3 is formed so as to divide the upper surface of the insulating film IF1 into a grid of multiple rectangular regions in a plan view.
[0071] As shown in Figure 40, in the manufacturing method of semiconductor device DEV5, in the trench formation step S12, firstly, dry etching of the interlayer insulating film ILD1 is performed through the openings of the resist pattern RP3 formed on the interlayer insulating film ILD1. After the hard mask HM3 is exposed from the interlayer insulating film ILD1, dry etching of the interlayer insulating film ILD1 and insulating film IF1 is performed through the openings of the hard mask HM3. This forms trench TR4. At this time, trenches TR5 and TR6 are also formed by dry etching of the interlayer insulating film ILD1 and insulating film IF2 and dry etching of the interlayer insulating film ILD1 and insulating film IF3 through the openings of the resist pattern RP3.
[0072] Secondly, as shown in Figure 41, dry etching is performed on the semiconductor substrate SUB through trenches TR4, TR5, and TR6, causing trenches TR4, TR5, and TR6 to be further excavated. At this time, the hard mask HM3 located between two adjacent trenches TR4 is removed because it is not covered by the interlayer insulating film ILD1, but the hard mask HM3 located on the first portion IF1a remains because it is covered by the interlayer insulating film ILD1. Subsequently, the same process as for the manufacturing method of semiconductor device DEV4 is performed to form the structure of semiconductor device DEV5 shown in Figures 36 to 38.
[0073] <Effects of the DEV5 semiconductor device> In semiconductor device DEV5, trenches TR4 are formed using a hard mask HM3. Since the hard mask HM3 is made of polysilicon, it is easy to ensure a selectivity ratio with the constituent materials of the interlayer insulating film ILD1 and insulating film IF1, and it does not easily shrink during dry etching. Therefore, the distance between two adjacent trenches TR4 can be shortened, and the number of capacitors that can be placed per unit area can be increased. In addition, when the trenches TR4 penetrate the interlayer insulating film ILD1 and insulating film IF1 and dry etching is performed on the semiconductor substrate SUB through the trenches TR4, the hard mask HM3 is also removed, so the hard mask HM3 does not ultimately remain on the second part IF1b. Furthermore, since the hard mask HM3 can be formed at the same time as the gate electrode GE is formed, no additional process is required to form the hard mask HM3.
[0074] <Variation> As shown in Figure 42, in the semiconductor device DEV6 according to a modification of the third embodiment, the semiconductor layer SEL2 may further have an impurity diffusion layer IDL4 formed on the side surface of the trench TR4 within the semiconductor layer SEL2. The conductivity type of the impurity diffusion layer IDL4 is the second conductivity type. The dopant concentration in the impurity diffusion layer IDL4 is higher than the dopant concentration in the impurity diffusion layer IDL2. Therefore, in the semiconductor device DEV6, capacitance fluctuations of the capacitor associated with the formation of the inversion layer can be further suppressed.
[0075] As shown in Figure 43, the manufacturing method of the semiconductor device DEV6 includes an impurity diffusion layer formation step S25. The impurity diffusion layer formation step S25 is performed after the trench formation step S12 and before the interlayer insulating film formation step S13. In the impurity diffusion layer formation step S25, an impurity diffusion layer IDL4 can be formed on the side surface of the trench TR4 within the semiconductor layer SEL2 by performing ion implantation from a direction inclined with respect to the normal direction of the upper surface F2.
[0076] (Fourth Embodiment) The semiconductor device DEV7 according to the fourth embodiment will be described.
[0077] <Configuration of semiconductor device DEV7> As shown in Figure 44, the semiconductor device DEV7 further comprises a metal layer ML7 and an insulating film IF7. In the semiconductor device DEV7, the insulating film IF1 has a first layer IF4a and a second layer IF4b, but does not have a third layer IF4c. In the semiconductor device DEV7, the metal layer ML7 and the insulating film IF7 are formed between the metal layer ML1 and the insulating film IF4. The metal layer ML7 is formed on the insulating film IF4, and the insulating film IF7 is formed between the metal layer ML7 and the metal layer ML1.
[0078] The insulating film IF7 has a first layer IF7a, a second layer IF7b, and a third layer IF7c. The first layer IF7a and the third layer IF7c are formed of, for example, silicon oxide. The second layer IF7b is formed of, for example, silicon nitride. In other words, the insulating film IF7 is formed of an ONO film. The metal layer ML7 is formed of a metallic material. The metal layer ML7 is formed of, for example, copper, titanium, titanium nitride, etc.
[0079] The semiconductor device DEV7 does not have impurity diffusion layers IDL2 and IDL3. In the semiconductor device DEV7, the metal layer ML1, the metal layer ML7, and the insulating film IF7 formed between the metal layers ML1 and ML7 constitute a capacitor.
[0080] <Manufacturing method for semiconductor device DEV7> As shown in Figure 45, the manufacturing method for semiconductor device DEV7 does not include the impurity diffusion layer formation step S3. In the manufacturing method for semiconductor device DEV7, the impurity diffusion layer IDL3 is not formed in the impurity diffusion layer formation step S10. Except for these points, the manufacturing method for semiconductor device DEV7 is the same as the manufacturing method for semiconductor device DEV5 up to the interlayer insulating film formation step S13.
[0081] The manufacturing method for the semiconductor device DEV7 includes an etching step S26 following the interlayer insulating film formation step S13. As shown in Figure 46, in the etching step S26, firstly, a resist pattern RP4 is formed on the interlayer insulating film ILD2. The resist pattern RP4 has an opening above the second portion IF1b. Secondly, the third layer ILD2c, which is formed above the second portion IF1b and inside the trench TR4, is removed by dry etching through the opening in the resist pattern RP4. As a result, a recess is formed above the second portion IF1b. The second layer ILD2b is exposed from the side and bottom surfaces of this recess, and the second layer ILD2b (second layer IF4b) is also exposed inside the trench TR4.
[0082] In the manufacturing method of the semiconductor device DEV7, a metal layer formation step S27 is performed after the etching step S26. As shown in Figure 47, in the metal layer formation step S27, a metal layer ML7 is formed on the insulating film IF4 by, for example, sputtering or MOCVD (Metal Organic Chemical Vapor Deposition). At this time, the metal layer ML7 is also formed on the bottom and side surfaces of the recesses, and also on the interlayer insulating film ILD2.
[0083] In the manufacturing method of the semiconductor device DEV7, the interlayer insulating film formation step S28 is performed after the metal layer formation step S27. As shown in Figure 48, in the interlayer insulating film formation step S28, the interlayer insulating film ILD3 is formed on the metal layer ML7. The interlayer insulating film ILD3 has a first layer ILD3a, a second layer ILD3b formed on the first layer ILD3a, and a third layer ILD3c formed on the second layer ILD3b. The first layer ILD3a and the third layer ILD3c are formed of, for example, silicon oxide, and the second layer ILD3b is formed of, for example, silicon nitride. In the interlayer insulating film formation step S28, the first layer ILD3a, the second layer ILD3b, and the third layer ILD3c are formed sequentially. The first layer ILD3a and the second layer ILD3b are formed by, for example, the ALD method, and the third layer ILD3c is formed by, for example, the CVD method.
[0084] In the manufacturing method of semiconductor device DEV7, as shown in Figure 49, a planarization step S29 is performed after the interlayer insulating film formation step S28. In the planarization step S29, the upper surface of the interlayer insulating film ILD3 is planarized, for example by the etch-back method or the CMP method, so that the upper surface of the interlayer insulating film ILD3 becomes flush with the upper surface of the interlayer insulating film ILD2. As a result, the metal layer ML7 and the interlayer insulating film ILD3 that were formed on the upper surface of the interlayer insulating film ILD2 are removed. In the manufacturing method of semiconductor device DEV7, etching steps S30, S31, and S32 are performed sequentially after the planarization step S29.
[0085] As shown in Figure 50, in etching step S30, through holes TH2, TH4, TH5, and TH6 are formed in the third layer ILD2c and the second layer ILD2b. In etching step S30, firstly, a hard mask HM4 is formed on the interlayer insulating film ILD2 and the interlayer insulating film ILD3. The hard mask HM4 has openings in positions that overlap with the trench TR4 in a plan view, positions that overlap with the trench TR5 in a plan view, positions that overlap with the source layer SL in a plan view, positions that overlap with the drain layer DL in a plan view, and positions that overlap with the gate electrode GE in a plan view. The hard mask HM4 also has an opening in a position that overlaps with the bottom surface of the above-mentioned recess in a plan view.
[0086] Secondly, a resist pattern RP5 is formed on the hard mask HM4. The resist pattern RP5 has openings in positions that overlap with the trench TR5 in a plan view, the source layer SL in a plan view, the drain layer DL in a plan view, and the gate electrode GE in a plan view. In other words, the openings of the resist pattern RP5 and the openings of the hard mask HM4 overlap with each other in positions that overlap with the trench TR5 in a plan view, the impurity diffusion layer IDL3 in a plan view, the source layer SL in a plan view, the drain layer DL in a plan view, and the gate electrode GE in a plan view.
[0087] Thirdly, dry etching is performed on the third layer ILD2c and the second layer ILD2b through the openings in the resist pattern RP5 and the hard mask HM4. This forms through holes TH2, TH4, TH5, and TH6. This dry etching also removes the second and third layers of the insulating film IF5 located on the bottom surface of the trench TR5. After the etching process S31 is completed, the resist pattern RP5 is removed.
[0088] As shown in Figure 51, in etching step S31, through holes TH7 are formed by dry etching of the third layer ILD3c through the opening in the hard mask HM4. The through holes TH7 are formed within the third layer ILD3c so as to overlap with the trench TR4 in a plan view. At this time, dry etching is performed on the first layer of the insulating film IF5 located on the bottom surface of the trench TR5 through through holes TH2, and dry etching is also performed on the second layer ILD1b through through holes TH4, TH5, and TH6. In addition, at this time, a through hole TH8 is also formed within the third layer ILD3c so as to overlap with the bottom surface of the recess in a plan view.
[0089] As shown in Figure 52, in etching step S32, dry etching is performed on the first layer ILD1a through through holes TH4, TH5, and TH6. At the same time, dry etching is performed on the first layer ILD3a and the second layer ILD3b through through hole TH8, exposing the metal layer ML7 from the bottom of through hole TH8. The hard mask HM4 is also removed by this dry etching.
[0090] Following the etching process S32, a metal layer formation process S17 is performed. However, in the manufacturing method of the semiconductor device DEV7, the metal layer ML3 is not formed in the metal layer formation process S17, and the metal layer ML8 is formed within the through hole TH8. As a result, the structure of the semiconductor device DEV7 shown in Figure 44 is formed.
[0091] <Effects of the semiconductor device DEV7> In semiconductor device DEV7, both electrodes of the capacitor (metal layer ML1 and metal layer ML7) are formed from metallic material, further reducing parasitic resistance and enabling even faster operation. Furthermore, because both electrodes of the capacitor in semiconductor device DEV7 are formed from metallic material, unlike cases where an impurity diffusion layer is used on one of the capacitor electrodes, there is no change in capacitor capacitance due to the formation of an inversion capacitance.
[0092] Although the present invention has been specifically described above based on embodiments, it goes without saying that the present invention is not limited to the above embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]
[0093] DEV1, DEV2, DEV3, DEV4, DEV5, DEV6, DEV7 Semiconductor device, DL Drain layer, DL1 first part, DL2 second part, F1 bottom surface, F2, F3 top surfaces, GE Gate electrode, GI Gate insulating film, HM1, HM2, HM3, HM4 Hard mask, IDL1, IDL2, IDL3, IDL4 Impurity diffusion layer, IF1, IF2 Insulating film, IF1a first part, IF1b second part, IF3, IF4 Insulating film, IF4a first layer, IF4b second layer, IF4c third layer, IF5, IF6 Insulating film, IF7 Insulating film, IF7a first layer, IF7b second layer, IF7c third layer, ILD1 Interlayer insulating film, ILD1a first layer, ILD1b second layer, ILD2 Interlayer insulating film, ILD2a first layer, ILD2b S11, S20 Polishing process, S21, S22, S23, S24 Etching process, S25 Impurity diffusion layer formation process, S26 Etching process, S27 Metal layer formation process, S28 Interlayer insulating film formation process, S29 Planarization process, S30, S31, S32 Etching process, SEL1 Semiconductor layer, SEL2 Semiconductor layer, SL Source layer, SL1 First part, SL2 Second part, SUB Semiconductor substrate, SWS Sidewall spacer, TH1, TH2, TH3, TH4, TH5, TH6, TH7, TH8 Through holes, TR1, TR2, TR3, TR4, TR5, TR6 Trench.
Claims
1. A semiconductor substrate having a lower surface and an upper surface located on the opposite side of the lower surface, The first insulating film formed on the upper surface, The second insulating film formed on the upper surface, The first metal layer and The second metal layer, The third insulating film and A fourth insulating film is provided, The semiconductor substrate has a first semiconductor layer forming the lower surface and a second semiconductor layer formed on the first semiconductor layer and forming the upper surface. The first semiconductor layer has a first impurity diffusion layer formed within the first semiconductor layer and located at the interface between the first semiconductor layer and the second semiconductor layer. The conductivity type of the first semiconductor layer and the conductivity type of the second semiconductor layer are the first conductivity type, The conductivity type of the first impurity diffusion layer is a second conductivity type opposite to the first conductivity type. Within the semiconductor substrate and the first insulating film, a first trench is formed that penetrates the first insulating film and extends toward the lower surface. A second trench is formed within the semiconductor substrate and the second insulating film, extending toward the lower surface so as to penetrate the second insulating film and reach the first semiconductor layer. The first metal layer is formed in the first trench, The second metal layer is formed in the second trench, The third insulating film is formed between the first metal layer and the side surface of the first trench and between the first metal layer and the bottom surface of the first trench. The fourth insulating film is formed between the second metal layer and the side surface of the second trench, A semiconductor device in which the second metal layer is electrically connected to the first semiconductor layer at the bottom surface of the second trench.
2. The second semiconductor layer has a second impurity diffusion layer formed within the second semiconductor layer, extending from the upper surface to the first impurity diffusion layer, and surrounding the first insulating film in both plan and cross-sectional views. The conductivity type of the second impurity diffusion layer is the second conductivity type, The semiconductor device according to claim 1, wherein the second impurity diffusion layer, the third insulating film, and the first metal layer constitute a capacitor.
3. The semiconductor device according to claim 2, further comprising a third metal layer electrically connected to the second impurity diffusion layer.
4. The semiconductor device according to claim 2, wherein the bottom surface of the first trench is located within the first semiconductor layer.
5. The semiconductor device according to claim 2, wherein the bottom surface of the first trench is located within the first impurity diffusion layer.
6. The fifth insulating film formed on the upper surface, Further comprising a sixth insulating film, The fifth insulating film surrounds the first insulating film with a gap between them in a plan view. A third trench is formed within the semiconductor substrate and the fifth insulating film, extending toward the lower surface so as to penetrate the fifth insulating film and reach the first semiconductor layer. The sixth insulating film is formed in the third trench, The semiconductor device according to claim 2, wherein a cavity is formed within the sixth insulating film.
7. The semiconductor device according to claim 6, wherein the width of the first trench is greater than the widths of the second trench and the third trench.
8. The third insulating film comprises a first layer formed on the side surface and the bottom surface of the first trench, a second layer formed on the first layer, and a third layer formed between the second layer and the first metal layer. The first and third layers are formed of silicon oxide, The semiconductor device according to claim 2, wherein the second layer is formed of silicon nitride.
9. The third insulating film has, in a plan view, a first portion located at the outer edge of the third insulating film and a second portion located inside the first portion. The semiconductor device according to claim 2, wherein the first trench penetrates the second portion.
10. The semiconductor device according to claim 9, further comprising a hard mask formed on the first portion.
11. Gate insulating film and, Equipped with an additional terminal, The second semiconductor layer has a source layer formed on its upper surface and a drain layer formed on its upper surface, separated from the source layer. The gate insulating film is formed on the upper surface located between the source layer and the drain layer. The gate electrode is formed on the gate insulating film, The semiconductor device according to claim 10, wherein the gate electrode and the hard mask are formed of polysilicon.
12. The second semiconductor layer further comprises a third impurity diffusion layer formed within the second semiconductor layer and located on the side surface of the first trench. The conductivity type of the third impurity diffusion layer is the second conductivity type, The semiconductor device according to claim 9, wherein the dopant concentration in the third impurity diffusion layer is higher than the dopant concentration in the second impurity diffusion layer.
13. The semiconductor device according to claim 2, wherein the first metal layer and the second metal layer are formed of tungsten.
14. The fourth metal layer, Further comprising a seventh insulating film, The fourth metal layer and the seventh insulating film are formed between the first insulating film and the first metal layer. The semiconductor device according to claim 1, wherein the seventh insulating film is formed between the first metal layer and the fourth metal layer.
15. The semiconductor device according to claim 14, wherein the first metal layer, the fourth metal layer, and the seventh insulating film constitute a capacitor.