Semiconductor device and method of forming the same

Abstract

The present invention discloses a semiconductor device and a method for forming the same. The semiconductor device includes a substrate, a plurality of bit lines, a plurality of bit line contacts, a gate structure, a first oxide interface layer, and a second oxide interface layer. The bit line is arranged on the substrate, and the bit line contact is located below a portion of the bit line. The gate structure is arranged on the substrate, and the bit line and the gate structure respectively include a semiconductor layer, a barrier layer, a conductive layer, and a cap layer stacked in sequence. The first oxide interface layer is arranged between the bit line contact and the semiconductor layer of the bit line. The second oxide interface layer is arranged in the semiconductor layer of the gate, and the top surface of the first oxide interface layer is higher than the top surface of the second oxide interface layer. In this way, the bit line and the bit line contact can have better structural reliability, so that the semiconductor device can achieve more optimized component performance.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for forming the same, and in particular to a semiconductor storage device and a method for forming the same. Background Art

[0002] As various electronic products develop towards miniaturization, the design of semiconductor storage devices must also meet the requirements of high integration and high density. For dynamic random access memory (DRAM) with a recessed gate structure, since it can obtain a longer carrier channel length in the same semiconductor substrate to reduce the leakage of the capacitor structure, it has gradually replaced the dynamic random access memory with only a planar gate structure under the current mainstream development trend.

[0003] Generally speaking, a dynamic random access memory with a recessed gate structure is composed of a large number of memory cells gathered to form an array area for storing information, and each memory cell can be composed of a transistor component and a capacitor component connected in series to receive voltage information from a word line (WL) and a bit line (BL). In response to product requirements, the density of memory cells in the array area must be continuously improved, resulting in increasing difficulty and complexity in related manufacturing processes and designs. Therefore, the existing technology needs to be further improved to effectively improve the performance and reliability of related storage devices. Summary of the invention

[0004] One object of the present invention is to provide a semiconductor device and a method for forming the same, which forms a bit line and gate structure with a composite semiconductor layer, thereby improving the structural reliability of the bit line and the bit line contact, so that the semiconductor device can achieve more optimized component performance.

[0005] To achieve the above-mentioned purpose, one embodiment of the present invention provides a semiconductor device, which includes a substrate, a plurality of bit lines, a plurality of bit line contacts, a gate structure, a first oxide interface layer and a second oxide interface layer. The bit line is arranged on the substrate. The contact is arranged in the substrate and is located below a portion of the bit line. The gate structure is arranged on the substrate, wherein the bit line and the gate structure respectively include a semiconductor layer, a barrier layer, a conductive layer and a cap layer stacked in sequence. The first oxide interface layer is arranged between the bit line contact and the semiconductor layer of the bit line. The second oxide interface layer is arranged in the semiconductor layer of the gate structure, wherein the topmost surface of the first oxide interface layer is higher than the topmost surface of the second oxide interface layer.

[0006] To achieve the above-mentioned purpose, one embodiment of the present invention provides a method for forming a semiconductor device, which includes the following steps. First, a substrate is provided, and a plurality of bit lines are formed on the substrate. Then, a plurality of bit line contacts are formed in the substrate, which are located below part of the bit lines. Next, a gate structure is formed on the substrate, wherein the bit line and the gate structure include a semiconductor layer, a barrier layer, a conductive layer and a cap layer stacked in sequence. Furthermore, a first oxide interface layer is formed between the bit line contact and the semiconductor layer of the bit line, and a second oxide interface layer is formed in the semiconductor layer of the gate structure, wherein the topmost surface of the first oxide interface layer is higher than the topmost surface of the second oxide interface layer.

[0007] To achieve the above-mentioned purpose, one embodiment of the present invention provides a semiconductor device, which includes a substrate, a plurality of bit lines, a plurality of bit line contacts, a gate structure, and an oxidized interface layer. The bit line is disposed on the substrate. The contact is disposed in the substrate and is located below a portion of the bit line. The gate structure is disposed on the substrate, wherein the bit line and the gate structure respectively include a semiconductor layer, a barrier layer, a conductive layer, and a cap layer stacked in sequence. The oxidized interface layer is disposed between the bit line contact and the semiconductor layer of the bit line. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The accompanying drawings provide a deeper understanding of the embodiments of the present invention and are incorporated into this specification and become a part thereof. These drawings and descriptions are used to illustrate the principles of some embodiments. It should be noted that all drawings are schematic diagrams, and the relative sizes and proportions have been adjusted for the purpose of illustration and drawing convenience. The same symbols represent corresponding or similar features in different embodiments.

[0009] Figures 1 to 5 Schematic diagram of the steps of a method for forming a semiconductor device in a first embodiment of the present invention, wherein:

[0010] Figure 1 is a schematic top view of a semiconductor device after word lines are formed;

[0011] Figure 2 for Figure 1 Schematic diagram of the cross section along the tangent line A-A' and the tangent line B-B';

[0012] Figure 3 is a schematic cross-sectional view of a semiconductor device after a bit line contact opening is formed;

[0013] Figure 4 is a schematic cross-sectional view of a semiconductor device after a bit line contact is formed; and

[0014] Figure 5It is a cross-sectional schematic diagram of a semiconductor device after forming a bit line and a gate stack layer.

[0015] Figures 6 to 10 Schematic diagram of the steps of a method for forming a semiconductor device in a second embodiment of the present invention, wherein:

[0016] Figure 6 is a schematic cross-sectional view of a semiconductor device after an etching process;

[0017] Figure 7 is a schematic cross-sectional view of a semiconductor device after forming a second semiconductor layer;

[0018] Figure 8 is a schematic cross-sectional view of a semiconductor device after forming a bit line and a gate stack layer;

[0019] Fig. 9 is a schematic top view of a semiconductor device after a patterning process is performed; and

[0020] Fig.10 for Fig. 9 Schematic cross-sectional view along the tangent line AA' and the tangent line BB'.

[0021] Fig.11 FIG. 4 is a schematic diagram of steps of a method for forming a semiconductor device according to a third embodiment of the present invention.

[0022] Fig.12 Schematic diagram of the steps of a method for forming a semiconductor device in a fourth embodiment of the present invention.

[0023] The reference numerals are described as follows:

[0024] 100, 300, 400, 500 Semiconductor devices

[0025] 100a Storage area

[0026] 100b Surrounding area

[0027] 110 Substrate

[0028] 112 Shallow Trench Isolation

[0029] 114, 116 Active area

[0030] 118 Ditch

[0031] 120 buried gate structure

[0032] 122 Dielectric layer

[0033] 124 Gate dielectric layer

[0034] 126 Gate

[0035] 128 Covering

[0036] 130 Insulation layer

[0037] 132 Oxide layer

[0038] 134 Nitride layer

[0039] 136 Oxide layer

[0040] 126 Sacrificial Layer

[0041] 142 first semiconductor layer

[0042] 144 Protective layer

[0043] 146 Contact opening

[0044] 162 contacts

[0045] 162a Stoma

[0046] 162b Protrusion

[0047] 164 Barrier

[0048] 166 Conductive layer

[0049] 168 Covering

[0050] 250 Mask layer

[0051] 260, 460 bit lines

[0052] 262, 362, 462 bit line contacts

[0053] 262a Top

[0054] 263a, 363a, first oxide interface layer

[0055] 263b Second oxide interface layer

[0056] 264, 364, 464 Second semiconductor layer

[0057] 266 Barrier Layer

[0058] 268 Conductive layer

[0059] 270 Covering

[0060] 280, 480 gate structure

[0061] 282 Semiconductor layer

[0062] 362a Air hole

[0063] 463a Oxidation interface layer

[0064] D1 Direction

[0065] H1, H2 Height DETAILED DESCRIPTION

[0066] In order to enable those skilled in the art to further understand the present invention, the following lists the preferred embodiments of the present invention, and with the accompanying drawings, describes in detail the components and effects of the present invention. It should be noted that the following embodiments can replace, reorganize, and mix the features of several different embodiments to complete other embodiments without departing from the spirit of the present invention.

[0067] Please refer to Figures 1 to 5 , which is a schematic diagram of the steps of the method for forming the semiconductor device 100 in the first embodiment of the present invention, wherein: Figure 1 is a schematic top view of the semiconductor device 100 at a formation stage, Figures 2 to 5 1 and 2 are cross-sectional views of the semiconductor device 100 at different stages of formation. Figure 1 and Figure 2 As shown, a substrate 110 is provided, such as a silicon substrate, a silicon-containing substrate (such as SiC, SiGe, etc.) or a silicon-on-insulator (SOI) substrate, etc. At least two regions are defined on the substrate 110, such as a storage region 110a with a relatively high component density and a peripheral region 110b with a relatively low component density. Preferably, the peripheral region 110b is, for example, arranged around the storage region 110a, but not limited thereto. In addition, at least one shallow trench isolation (STI) 112 is formed in the substrate 110 to define a plurality of active areas (AA) 114, 116 on the substrate 110, and all the active areas 114, 116 can be surrounded by the shallow trench isolation 112, such as Figure 1 In one embodiment, the shallow trench isolation 112 is formed by, for example, first forming a plurality of trenches (not shown) in the substrate 110 by etching, and then filling the trenches with an insulating material (such as silicon oxide or silicon oxynitride, etc.), but the present invention is not limited thereto.

[0068] In the present embodiment, the active regions 114 in the storage region 110a have, for example, a relatively small width and a set pitch, and the active regions 114 extend, for example, in parallel with each other along the same direction D1, wherein the direction D1 intersects and is not perpendicular to the y direction or the x direction; and the active regions 116 in the peripheral region 110b have, for example, a relatively large width and a set pitch, and the active regions 116 extend, for example, in parallel with each other along the x direction and are arranged in sequence, such as Figure 1 As shown, but not limited to.

[0069] A plurality of gate structures may also be formed in the storage region 110a of the substrate 110, such as buried gate structures 120, which extend in parallel to each other along the y direction and are staggered with each active region 114. In the present embodiment, the method for forming the buried gate structure 120 includes but is not limited to the following steps. First, a plurality of trenches 118 extending in parallel to each other and spaced apart from each other along the y direction are formed in the substrate 110. Then, a dielectric layer 122 covering the entire surface of each trench 118, a gate dielectric layer 124 covering the lower half surface of each trench 118, a gate 126 filling the lower half of each trench 118, and a cap layer 128 filling the upper half of each trench 118 are sequentially formed. In this way, the surface of the cap layer 128 can be flush with the top surface of the substrate 110, such as Figure 2 As shown, the buried gate structure 120 in the substrate 110 can be used as a buried word line (WL) of the semiconductor device 100 to receive or transmit a voltage signal of each memory cell (not shown).

[0070] like Figure 3As shown, an insulating layer 130, a first semiconductor layer 142 and a protective layer 144 are sequentially formed on a substrate 110, covering the storage area 110a and the peripheral area 110b of the substrate 110, wherein the first semiconductor layer 142 includes, for example, semiconductor materials such as doped silicon, doped phosphorus or silicon phosphorus (SiP), preferably doped silicon, and the insulating layer 130 preferably has a composite layer structure, for example, including an oxide layer 132-nitride layer 134-oxide layer 136 (oxide-nitride-oxide, ONO) structure, but not limited thereto. Then, a plurality of contact openings 146 are formed in the storage area 110a, penetrating the protective layer 144, the first semiconductor layer 142 and the insulating layer 130 and exposing a portion of the active area 114, wherein the formation method of the contact openings 146 includes but is not limited to the following steps. First, a mask structure (not shown) is formed on the substrate 110, for example, including a sacrificial layer (not shown, for example, including an organic dielectric layer), a silicon-containing hard mask (not shown, SHB) and a patterned photoresist layer (not shown) stacked in sequence on the protective layer 144, wherein the patterned photoresist layer has at least one pattern that can be used to define the contact opening 146. Through the etching process of the patterned photoresist layer, a plurality of contact openings 146 can be formed in the insulating layer 130, the first semiconductor layer 142 and the protective layer 144, respectively located in each active area 114. It should be noted that each contact opening 146 is, for example, formed between two adjacent word lines (i.e., the buried gate structure 120), so that a portion of the active area 114 (i.e., the substrate 110) can be exposed from the bottom of the contact opening 146, such as Figure 3 Then, the mask structure is completely removed.

[0071] like Figure 4As shown, deposition and back etching processes are sequentially performed on the substrate 110 to form the contact 162 in the contact opening 146. Specifically, for example, a chemical vapor deposition (CVD) process is first performed to form a conductor layer (not shown) on the protective layer 144 and further fill the contact opening 146, wherein the conductor layer, for example, includes semiconductor materials such as doped silicon, doped phosphorus or silicon phosphorus, preferably includes the same semiconductor material as the first semiconductor layer 142 (such as doped silicon), but not limited thereto. Then, a dry etching process is performed to completely remove the conductor layer on the protective layer 144 to expose the protective layer 144 below, further partially remove the conductor layer in the contact opening 146, and then completely remove the protective layer 144 to form the contact 162 and expose the first semiconductor layer 142 below the protective layer 144. It should be noted that the semiconductor material of the conductor layer itself has a poor hole-filling ability. Therefore, the portion of the conductor layer that fills the contact opening 146 is prone to residual air and form voids, and the portion is more likely to present a slightly depressed top surface (not shown). In this case, the slightly depressed top surface is prone to derive a loading effect in the subsequent back-etching process, so that the conductor layer near the side wall of the contact opening 146 may have a relatively slow etching rate, while the conductor layer near the center of the contact opening 146 may have a relatively fast etching rate. In this way, multiple voids may be formed in the contact 162, such as Figure 4 The air hole 162a shown in FIG. 1 is formed on both sides of the contact 162, and relatively high protrusions 162b can be formed, such as Figure 4 shown.

[0072] Then, if Figure 5As shown, a barrier layer 164, a conductive layer 166, and a cap layer 168 are sequentially formed on the first semiconductor layer 142 to cover the storage region 110a and the peripheral region 110b of the substrate 110 as a whole. The barrier layer 164 formed in the storage region 110a directly contacts the contact 162 and the first semiconductor layer 142, while the barrier layer 164 formed in the peripheral region 110b directly contacts the first semiconductor layer 142. In one embodiment, the barrier layer 164 includes, for example, tantalum and / or tantalum nitride, titanium and / or titanium nitride, the conductive layer 166 includes, for example, a low-resistance metal such as aluminum (Al), titanium (Ti), copper (Cu), or tungsten (W), and the cap layer 168 includes, for example, a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto. Subsequently, a patterning process may be performed to pattern the first semiconductor layer 142, the barrier layer 164, the conductive layer 166, and the cap layer 168 stacked in sequence, so as to form a plurality of bit lines (not shown) arranged in parallel along the x-direction in the storage area 110a, and at the same time form a plurality of gate structures (not shown) arranged along the y-direction in the peripheral area 110b, so that each of the bit lines and each of the gate structures may respectively include a patterned semiconductor layer (not shown), a patterned barrier layer (not shown), a patterned conductive layer (not shown), and a patterned cap layer (not shown) stacked in sequence from bottom to top. In this way, each of the bit lines arranged above the substrate 110 can be electrically connected to the source / drain region (not shown) of the transistor device (not shown) in the substrate 110 through the contact 162 below, and is isolated from the buried word line (i.e., the buried gate structure 120) in the substrate 110 by the insulating layer 130 on the substrate 110.

[0073] Thus, the semiconductor device 100 in the first embodiment of the present invention can be formed. The formation method of this embodiment is to first form a fully covered first semiconductor layer 142, define a contact opening 146 through the first semiconductor layer 142, and then form a contact 162 in the contact opening 146. Then, a barrier layer 164, a conductive layer 166, and a cap layer 168 stacked from bottom to top can be sequentially formed on the first semiconductor layer 142, and the first semiconductor layer 142, the barrier layer 164, the conductive layer 166, and the cap layer 168 stacked sequentially by patterning are formed to form the bit line and the gate structure on the storage area 110a and the peripheral area 110b, respectively. Therefore, the semiconductor device 100 with good performance can be formed under the premise of simplifying the overall manufacturing process.

[0074] In addition, those skilled in the art should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and its formation method of the present invention may also have other aspects, not limited to the above. For example, according to the semiconductor device and its formation method in other embodiments, the air hole 162a in the contact 162 in the first embodiment and / or the protrusion 162b on the contact 162 may also be further removed to improve the structural reliability of the contact 162. Other embodiments or variations of the semiconductor device and its formation method in the present invention will be further described below. And to simplify the description, the following description mainly describes the differences between the embodiments in detail, and will not repeat the same parts. In addition, the same components in each embodiment of the present invention are marked with the same reference numerals to facilitate mutual comparison between the embodiments.

[0075] Please refer to Figures 6 to 10 , which is a schematic diagram of the steps of a method for forming a semiconductor device 300 in a second embodiment of the present invention, wherein: Figures 6 to 8 are cross-sectional views of the semiconductor device 300 at different formation stages. Fig. 9 is a schematic top view of the semiconductor device 300 at a formation stage, Fig.10 for Fig. 9 The front-end steps of the forming method of this embodiment are substantially the same as those of the first embodiment described above. Figures 1 to 4 The main difference between the forming method of this embodiment and the forming method of the first embodiment is that the gate structure 280 of this embodiment has a composite semiconductor layer.

[0076] like Figure 6 As shown, in the formation of Figure 4 After the semiconductor device shown in FIG. 1 is formed, a mask layer 250 is additionally formed on the substrate 110 to cover the first semiconductor layer 142 in the peripheral region 110b and expose the first semiconductor layer 142 in the storage region 110a. Then, an etching process is performed through the mask layer 250 to completely remove the first semiconductor layer 142 in the storage region 110a and partially remove the contact 162. In this operation, along with the partially removed contact 162, the pore 162a originally formed in the contact 162 can also be removed, forming a structure as shown in FIG. Figure 6 The bit line contact 262 shown has a top surface 262a flush with the top surface of the insulating layer 130 (ie, the top surface of the oxide layer 136), wherein the bit line contact 262 comprises a semiconductor material such as doped silicon, doped phosphorus, or silicon-phosphorus, preferably doped silicon, but not limited thereto.

[0077] like Figure 7As shown, a second semiconductor layer 264 is formed on the substrate 110, covering the storage region 110a and the peripheral region 110b of the substrate 110, wherein the second semiconductor layer 264 includes, for example, semiconductor materials such as doped silicon, doped phosphorus, or silicon-phosphorus, and preferably includes the same material as the contact 262 and the first semiconductor layer 142 (such as doped silicon), but is not limited thereto. It should be noted that the second semiconductor layer 264 formed in the storage region 110a is in direct contact with the insulating layer 130 and the bit line contact 262 below, while the second semiconductor layer 264 formed in the peripheral region 110b is in direct contact with the first semiconductor layer 142. Thus, although the second semiconductor layer 264 and the bit line contact 262 contacting the bottom, and the second semiconductor layer 264 and the first semiconductor layer 142 contacting the bottom all include the same semiconductor material (such as doped silicon), the semiconductor material is easily oxidized during operation, so that a first oxidized interface layer 263a and a second oxidized interface layer 263b can be formed between the second semiconductor layer 264 and the bit line contact 262 contacting the bottom, and between the second semiconductor layer 264 and the first semiconductor layer 142 contacting the bottom, respectively. Figure 7 As shown. In addition, it should be noted that the thickness of the first oxidation interface layer 263a and the second oxidation interface layer 263b is very thin, only about 0.01 to 1 angstrom, and will not affect the electrical connection between the second semiconductor layer 264 and the bit line contact 262 below, and the second semiconductor layer 264 and the first semiconductor layer 142 below. Among them, the heights H1 and H2 of the first oxidation interface layer 263a and the second oxidation interface layer 263b in the direction vertical to the substrate 110 are obviously different, and the height H2 of the second oxidation interface layer 263b is greater than the height H1 of the first oxidation interface layer 263a, so that the top surface of the second oxidation interface layer 263b is higher than the top surface of the first oxidation interface layer 263a.

[0078] like Figure 8 As shown, a barrier layer 266, a conductive layer 268, and a cap layer 270 are sequentially formed on the second semiconductor layer 264 to cover the storage region 110a and the peripheral region 110b of the substrate 110 as a whole. The barrier layer 266, for example, comprises tantalum and / or tantalum nitride, titanium and / or titanium nitride, the conductive layer 268, for example, comprises a low-resistance metal such as aluminum, titanium, copper, or tungsten, and the cap layer 270, for example, comprises a dielectric material such as silicon oxide, silicon nitride, or silicon oxynitride, but is not limited thereto.

[0079] Then, if Fig. 9 and Fig.10As shown, photolithography and etching processes are performed to pattern the second semiconductor layer 264, barrier layer 266, conductive layer 268, and cap layer 270 stacked in sequence in the storage area 110a into a plurality of bit lines 260 arranged in parallel along the x-direction. At the same time, the first semiconductor layer 142, second semiconductor layer 264, barrier layer 266, conductive layer 268, and cap layer 270 stacked in sequence in the peripheral area 110b are patterned into a plurality of gate structures 280 arranged in parallel along the y-direction. Wherein, each bit line 260 extending in the x-direction may be interlaced with each active region 114 in the storage region 110a and a buried word line (i.e., a buried gate structure 120) in the substrate 110, so that each bit line 260 disposed above the substrate 110 may be electrically connected to a source / drain region (not shown) of a transistor device (not shown) in the substrate 110 through a contact 262 extending deep into the substrate 110 below, and may be isolated from the buried word line in the substrate 110 by the insulating layer 130 on the substrate 110. Thus, each bit line 260 includes a semiconductor layer (including only the second semiconductor layer 264), a barrier layer 266, a conductive layer 268, and a cap layer 270 stacked in sequence from bottom to top, and a first oxidized interface layer 263a is formed between the semiconductor layer and the bit line contact 262 below, and each gate structure 280 includes a semiconductor layer 282, a barrier layer 266, a conductive layer 268, and a cap layer 270 stacked in sequence from bottom to top, wherein the semiconductor layer 282 of the gate structure 280 further includes a first semiconductor layer 142 and a second semiconductor layer 264 stacked in sequence, and a second oxidized interface layer 263b is formed between the first semiconductor layer 142 and the second semiconductor layer 264, as shown in FIG. Fig. 9 and Fig.10As shown. Moreover, the barrier layer 266 of each bit line 260 and the barrier layer 266 of each gate structure 280 have the same material, the conductive layer 268 of each bit line 260 and the conductive layer 268 of each gate structure 280 have the same material, and the cap layer 270 of each bit line 260 and the cap layer 270 of each gate structure 280 also have the same material, while the top surface of the cap layer 270 of each bit line 260 and each gate structure 280 are not at the same height. It should be particularly noted that an insulating layer 130 is disposed below each gate structure 280. In one embodiment, the insulating layer 130 can be used as a gate dielectric layer, so that the insulating layer 130 and the gate structure 280 thereon can together form a transistor device. In another embodiment, the nitride layer 134 in the insulating layer 130 may also serve as a charge trapping layer, so that the insulating layer 130 and the gate structure 280 thereon may together form a silicon-oxide-nitride-oxide-silicon flash memory device (SONOS flash memory device), but the present invention is not limited thereto.

[0080] Thus, the semiconductor device 300 in the second embodiment of the present invention is completed. According to the formation method of this embodiment, the first semiconductor layer 142 in the storage area 110a is first removed by an etching process, and the pores 162a in the contact 162 are removed at the same time, and then the second semiconductor layer 264 is additionally formed. In other words, the formation method of this embodiment uses a two-stage deposition process to form the bit line contact 262 and the semiconductor layer (including only the second semiconductor layer 264) of the same material in the bit line 260, and at the same time, the composite semiconductor layer 282 of the same material in the gate structure 280 is formed (including the first semiconductor layer 142 and the second semiconductor layer 264 stacked in sequence). In this way, a first oxide interface layer 263a can be formed between the semiconductor layer of the bit line 260 and the bit line contact 262, and a second oxide interface layer 263b can be formed in the composite semiconductor layer 282 of the gate structure 280. This will not only not affect the conductive effect of each bit line 260, each bit line contact 262 or each gate structure 280, but also reduce the negative impact of the pores on the bit line contact 262, thereby improving the structural reliability of the semiconductor device 300 and enhancing its device performance.

[0081] Please refer to Fig.11, which is a schematic diagram of the steps of the method for forming the semiconductor device 400 in the third embodiment of the present invention. The front-end steps of the method for forming the present embodiment are substantially the same as those of the second embodiment, and are not repeated here. The main difference between the method for forming the present embodiment and the method for forming the second embodiment is that the second semiconductor layer 364 of the present embodiment is further filled into the air hole 362a exposed on the surface of the bit line contact 362.

[0082] Specifically, the forming method of this embodiment is to perform the etching process (such as the etching process in the second embodiment) Figure 6 When the second semiconductor layer 364 is formed, only the pores 162a that are relatively close to the surface of the contact 162 are removed, and the pores 362a that are relatively lower are exposed. Figure 7 ), the second semiconductor layer 364 covering the storage area 110a can be further filled into the exposed pores 362a to fill the pores 362a. In addition, in this embodiment, a first oxidized interface layer 363a can be formed between the second semiconductor layer 364 and the bit line contact 362 below, and a portion of the first oxidized interface layer 363a can be formed on the surface of the pores 362a and the whole is non-linear, such as Fig.11 shown.

[0083] Therefore, the formation method of this embodiment also uses a two-stage deposition process to form the bit line contact 362 and the semiconductor layer (i.e., the second semiconductor layer 364) of the same material in the bit line 260, and at the same time, to form the composite semiconductor layer 282 of the same material in the gate structure 280 (including the first semiconductor layer 142 and the second semiconductor layer 364 stacked in sequence). In addition, in this embodiment, the second semiconductor layer 364 formed in the storage area 110a can be filled with the air hole 362a, so that the first oxide dielectric layer 363a formed between the bit line contact 362 and the semiconductor layer can be non-linear, which will not affect the conductive effect of each bit line 260, each bit line contact 362 or each gate structure 280, and can also reduce the negative impact of the air hole on the bit line contact 262, thereby improving the structural reliability of the semiconductor device 300 and enhancing its device performance.

[0084] Please refer to Fig.12, which is a schematic diagram of the steps of the method for forming the semiconductor device 500 in the fourth embodiment of the present invention. The front-end steps of the method for forming the present embodiment are substantially the same as those of the second embodiment, and are not described in detail here. The main difference between the method for forming the present embodiment and the method for forming the second embodiment is that each gate structure 480 or each bit line 460 of the present embodiment includes a semiconductor layer (only the second semiconductor layer 464), a barrier layer 266, a conductive layer 268, and a cap layer 270 stacked in sequence from bottom to top, wherein only the semiconductor layer of the bit line 460 and the bit line contact 462 below are further formed with an oxide interface layer 463a.

[0085] Specifically, the forming method of this embodiment is to perform the etching process (such as the etching process in the second embodiment) Figure 6 When the first semiconductor layer 142 in the storage area 110a and the peripheral area 110b is removed at the same time, the air hole 162a in the contact 162 is completely removed. In this way, when the second semiconductor layer 464 (as shown in the second embodiment) is subsequently formed, Figure 7 ), the second semiconductor layer 464 may directly cover the insulating layer 130. The second semiconductor layer 464 formed in the storage region 110a may directly contact the bit line contact 462 below, and an oxidized interface layer 463a may be further formed between the second semiconductor layer 464 formed in the storage region 110a and the bit line contact 462, as shown in FIG. Fig.12 It should be noted that the thickness of the oxide interface layer 463a is very thin, only about 0.01 to 1 angstrom, and will not affect the electrical connection between the second semiconductor layer 464 and the bit line contact 462 below.

[0086] Thus, the semiconductor device 500 in the fourth embodiment of the present invention is completed. According to the formation method of this embodiment, the first semiconductor layer 142 is completely removed by an etching process, the pores 162a in the contact 162 are removed, and then the second semiconductor layer 464 is additionally formed. In other words, the formation method of this embodiment can omit the setting of the mask layer 250 in the aforementioned embodiment, and also use a two-stage deposition process to form the bit line contact 462 and the semiconductor layer (i.e., the second semiconductor layer 464) of the same material in the bit line 460, and at the same time, form the semiconductor layer (i.e., the second semiconductor layer 464) in the gate structure 480. In this way, only the oxide interface layer 463a is formed between the semiconductor layer of the bit line 460 and the bit line contact 462, and the top surfaces of the cap layer 270 of the gate structure 480 of this embodiment and the cap layer 270 of each bit line 460 can also be at the same height. Under this configuration, not only will the conductivity of each bit line 460 or each bit line contact 462 not be affected, but the negative impact of the pores on the bit line contact 462 can also be reduced, thereby improving the structural reliability of the semiconductor device 500 and enhancing its device performance, while simplifying the manufacturing process of the semiconductor device 500.

[0087] Those skilled in the art should be able to easily understand that, in order to meet the actual product requirements, the semiconductor device and its formation method of the present invention may also have other aspects, not limited to the above. For example, in other embodiments, the etching process may be used to partially remove the storage area 110a and the peripheral area 110b in response to the relative position of the pores 162a in the contact 162, so as to remove the pores 162a in the contact 162, and then form an additional second semiconductor layer. In this way, a first oxide interface layer can also be formed between the semiconductor layer of the bit line (including only the first semiconductor layer) and the bit line contact, and a second oxide interface layer can be formed in the composite semiconductor layer of the gate structure (including the first semiconductor layer and the second semiconductor layer stacked in sequence), and the first oxide interface layer can be as high as the second oxide interface layer. In this way, the structural reliability of the semiconductor device can be improved and its device performance can be enhanced while simplifying the manufacturing process of the semiconductor device.

[0088] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that include: substrate; a plurality of active regions on a substrate, wherein the active regions are isolated by shallow trenches; A plurality of bit lines are disposed on the substrate; A plurality of bit line contacts are disposed in the substrate and below a portion of the bit lines, wherein the bit line contacts are in contact with the active region; A gate structure is disposed on the substrate, wherein the bit line and the gate structure respectively include a semiconductor layer, a barrier layer, a conductive layer and a cap layer stacked in sequence; A first oxide interface layer is disposed between a top surface of a corresponding bit line contact below the bit line and a bottom surface of the semiconductor layer of the bit line; and The second oxidized interface layer is disposed in the semiconductor layer of the gate structure, wherein the top surface of the second oxidized interface layer is higher than the top surface of the first oxidized interface layer.

2. The semiconductor device according to claim 1, wherein: The bit line contact and the semiconductor layer of the bit line include the same material.

3. The semiconductor device according to claim 1, wherein: The semiconductor layer of the gate structure includes a first semiconductor layer and a second semiconductor layer stacked in sequence, and the second oxide interface layer is arranged between the first semiconductor layer and the second semiconductor layer.

4. The semiconductor device according to claim 3, wherein: The first semiconductor layer and the second semiconductor layer include the same material.

5. The semiconductor device according to claim 1, wherein: The substrate includes a storage area and a peripheral area. The gate structure and the second oxidized interface layer are arranged in the peripheral area. The bit line, the bit line contact and the first oxidized interface layer are arranged in the storage area.

6. The semiconductor device according to claim 1, wherein: The bit line contact includes a plurality of air holes, and the semiconductor layer of the bit line fills the air holes.

7. The semiconductor device according to claim 6, wherein: The first oxidized interface layer includes a non-planar top surface.

8. The semiconductor device according to claim 1, wherein: The cap layer of the gate structure and the cap layer of the bit line are made of the same material, and top surfaces of the cap layer of the gate structure and the cap layer of the bit line are not at the same height.

9. A method for forming a semiconductor device, characterized in that Include: providing a substrate; forming a plurality of bit lines on the substrate; forming a plurality of bit line contacts in the substrate, located below portions of the bit lines; forming a gate structure on the substrate, wherein the bit line and the gate structure include a semiconductor layer, a barrier layer, a conductive layer and a cap layer stacked in sequence; forming a first oxide interface layer between a top surface of a corresponding bit line contact below the bit line and a bottom surface of the semiconductor layer of the bit line; and A second oxide interface layer is formed in the semiconductor layer of the gate structure, wherein the top surface of the first oxide interface layer is higher than the top surface of the second oxide interface layer.

10. The method for forming a semiconductor device according to claim 9, wherein: Also includes: forming a plurality of buried gate structures in the substrate; A first semiconductor layer is formed on the substrate, wherein a plurality of contact openings are formed in the first semiconductor layer and are respectively located between two adjacent buried gate structures; forming a conductor layer on the substrate, filling the contact opening and covering the first semiconductor layer; as well as Performing an etch-back process to remove the conductor layer covering the first semiconductor layer, wherein the conductor layer filling the contact openings forms a plurality of contacts; as well as An etching process is performed to partially remove the first semiconductor layer and the contact to form the bit line contact.

11. The method for forming a semiconductor device according to claim 10, wherein: Also includes: After the etching process, a second semiconductor layer is formed to cover the first semiconductor layer, wherein the semiconductor layer of the gate structure includes the first semiconductor layer and the second semiconductor layer stacked in sequence.

12. The method for forming a semiconductor device according to claim 11, wherein: The first oxidation interface layer and the second oxidation interface layer are formed after the etching process and before the second semiconductor layer is formed.

13. The method for forming a semiconductor device according to claim 11, wherein: The conductor layer includes a plurality of pores located in the contact opening.

14. The method for forming a semiconductor device according to claim 13, wherein: After the etching process, a portion of the pores is exposed from the surface of the bit line contact, and the second semiconductor layer fills up the portion of the pores.

15. The method for forming a semiconductor device according to claim 13, wherein: After the etching back process, the air holes are completely removed.

16. The method for forming a semiconductor device according to claim 9, wherein: The substrate includes a storage region and a peripheral region. The gate structure and the second oxidized interface layer are formed in the peripheral region. The bit line, the bit line contact and the first oxidized interface layer are formed in the storage region.

17. A semiconductor device, characterized in that include: substrate; a plurality of active regions on a substrate, wherein the active regions are isolated by shallow trenches; A plurality of bit lines are disposed on the substrate; A plurality of bit line contacts are disposed in the substrate and below a portion of the bit lines, wherein the bit line contacts are in contact with the active region; A gate structure is disposed on the substrate, wherein the bit line and the gate structure respectively include a semiconductor layer, a barrier layer, a conductive layer and a cap layer stacked in sequence; as well as An oxidation interface layer is disposed between a top surface of a corresponding bit line contact below the bit line and a bottom surface of the semiconductor layer of the bit line.

18. The semiconductor device according to claim 17, wherein: The bit line contact, the semiconductor layer of the gate structure and the semiconductor layer of the bit line include the same material.

19. The semiconductor device according to claim 17, wherein: The substrate includes a storage area and a peripheral area. The gate structure is arranged in the peripheral area. The bit line, the bit line contact and the oxidation interface layer are arranged in the storage area.

20. The semiconductor device according to claim 17, wherein: The cap layer of the gate structure and the cap layer of the bit line are made of the same material, and top surfaces of the cap layer of the gate structure and the cap layer of the bit line are at the same height.

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