Parallel precoding for downlink transmission

Abstract

Parallel precoding for downlink transmission is disclosed, and in particular, devices, systems and techniques for parallel determination of precoding weights for fifth generation (5G) new radio (NR) downlink transmissions are disclosed. In at least one embodiment, a parallel processor includes one or more circuits for performing precoding on a 5G downlink signal using two or more processing threads in parallel.

Description

Technical Field

[0001] At least one embodiment relates to processing resources for processing wireless communications for precoding. For example, at least one embodiment relates to a parallel processor or computing system for generating precoding weights for downlink signal transmission of wireless communication information according to various new techniques described herein. Background Art

[0002] Processing wireless communication signals and data for precoding consumes significant computing resources and time. Methods for processing wireless communication signals and data can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Figure 1 is a block diagram illustrating a fifth generation (5G) signal processing environment including a distributed unit for performing precoding according to at least one embodiment;

[0004] Figure 2 A multi-element antenna transmitting downlink signals according to at least one embodiment is shown;

[0005] Figure 3 is a block diagram illustrating a fifth generation (5G) signal processing environment according to at least one embodiment;

[0006] Figure 4 is a block diagram illustrating aspects of a precoding technique according to at least one embodiment;

[0007] Figure 5 A flow chart illustrating a technique for generating precoding weights according to at least one embodiment is shown;

[0008] Figure 6 A flowchart illustrating a technique for generating precoding weights according to at least one embodiment includes performing factorization of an augmented matrix;

[0009] Figure 7 An example data center system is shown in accordance with at least one embodiment;

[0010] Figure 8A An example of an autonomous vehicle according to at least one embodiment is shown;

[0011] Figure 8B According to at least one embodiment, Figure 8A Examples of camera positions and fields of view for autonomous vehicles;

[0012] Figure 8C According to at least one embodiment Figure 8A A block diagram of an example system architecture for an autonomous vehicle;

[0013] Figure 8D is a diagram illustrating a method for one or more cloud-based servers and Figure 8A A diagram of a system for communicating between autonomous vehicles;

[0014] Figure 9 is a block diagram illustrating a computer system according to at least one embodiment;

[0015] Figure 10 is a block diagram illustrating a computer system according to at least one embodiment;

[0016] Figure 11 A computer system according to at least one embodiment is shown;

[0017] Figure 12 A computer system according to at least one embodiment is shown;

[0018] Figure 13A A computer system according to at least one embodiment is shown;

[0019] Figure 13B A computer system according to at least one embodiment is shown;

[0020] Figure 13C A computer system according to at least one embodiment is shown;

[0021] Figure 13D A computer system according to at least one embodiment is shown;

[0022] Figure 13E and Figure 13F illustrates a shared programming model according to at least one embodiment;

[0023] Figure 14 An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0024] Figure 15A and Figure 15B An exemplary integrated circuit and associated graphics processor are shown in accordance with at least one embodiment;

[0025] Figure 16A and Figure 16B Additional exemplary graphics processor logic is shown in accordance with at least one embodiment;

[0026] Figure 17 A computer system according to at least one embodiment is shown;

[0027] Figure 18A A parallel processor according to at least one embodiment is shown;

[0028] Figure 18B shows a partition unit according to at least one embodiment;

[0029] Figure 18C illustrates a processing cluster according to at least one embodiment;

[0030] Figure 18D A graphics multiprocessor is shown in accordance with at least one embodiment;

[0031] Figure 19 A multi-graphics processing unit (GPU) system is shown in accordance with at least one embodiment;

[0032] Figure 20 A graphics processor according to at least one embodiment is shown;

[0033] Figure 21 is a block diagram illustrating a processor microarchitecture for a processor according to at least one embodiment;

[0034] Figure 22 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0035] Figure 23 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0036] Figure 24 illustrates at least a portion of a graphics processor according to one or more embodiments;

[0037] Figure 25 is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0038] Figure 26 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0039] Figure 27A and Figure 27B Thread execution logic including an array of processing elements of a graphics processor core is shown in accordance with at least one embodiment;

[0040] Figure 28 illustrates a parallel processing unit ("PPU") in accordance with at least one embodiment;

[0041] Figure 29 illustrates a general processing cluster ("GPC") in accordance with at least one embodiment;

[0042] Figure 30 illustrates a memory partitioning unit of a parallel processing unit ("PPU") according to at least one embodiment;

[0043] Figure 31 A streaming multiprocessor is shown in accordance with at least one embodiment;

[0044] Figure 32 A network for communicating data within a 5G wireless communication network is shown in accordance with at least one embodiment;

[0045] Figure 33 illustrates a network architecture for a 5G LTE wireless network according to at least one embodiment;

[0046] Figure 34 is a diagram illustrating some basic functionality of a mobile telecommunications network / system operating according to LTE and 5G principles, according to at least one embodiment;

[0047] Figure 35 illustrates a radio access network that may be part of a 5G network architecture in accordance with at least one embodiment;

[0048] Figure 36 An example illustration of a 5G mobile communication system in which multiple different types of devices are used is provided according to at least one embodiment;

[0049] Figure 37 An example high-level system according to at least one embodiment is shown;

[0050] Figure 38 shows the architecture of a network system according to at least one embodiment;

[0051] Figure 39 illustrates example components of a device according to at least one embodiment;

[0052] Figure 40 illustrates an example interface for a baseband circuit according to at least one embodiment;

[0053] Figure 41 An example of an uplink channel according to at least one embodiment is shown;

[0054] Figure 42 shows the architecture of a network system according to at least one embodiment;

[0055] Figure 43 illustrates a control plane protocol stack according to at least one embodiment;

[0056] Figure 44 illustrates a user plane protocol stack according to at least one embodiment;

[0057] Figure 45 illustrates components of a core network according to at least one embodiment; and

[0058] Figure 46Components of a system supporting network functions virtualization (NFV) are shown in accordance with at least one embodiment. DETAILED DESCRIPTION

[0059] Figure 1 1 is a block diagram illustrating a fifth generation (5G) new radio (NR) signal processing environment 100 according to at least one embodiment, including a distributed unit 102 for performing precoding at block 104. In at least one embodiment, the precoding at block 104 includes online calculation of matrices. In at least one embodiment, the online calculation of matrices at block 104 is referred to as digital beamforming. In at least one embodiment, performing precoding at block 104 includes calculating beamforming cancellation (BFC) coefficients. In at least one embodiment, calculating BFC coefficients is referred to as beamforming weight calculation (BWC). In at least one embodiment, BFC coefficients are referred to as BFC weights, precoding weights, and / or precoder weights. In at least one embodiment, BFC coefficients are referred to as weights for digital beamforming or spatial filtering. In at least one embodiment, BFC coefficients are referred to as beamforming coefficients or weights. In at least one embodiment, the distributed unit 102 is in signal communication with a remote radio head (RRH) 106 (e.g., via an optical fiber link 108). In at least one embodiment, the RRH 106 is referred to as a remote unit. In at least one embodiment, some other type of radio frequency (RF) communication device and / or system (eg, a gNodeB) performs at least one function described with respect to the RRH 106 .

[0060] In at least one embodiment, distributed unit 102 includes blocks and / or performs actions on a first side of dashed line 110, and RRH 106 includes blocks and / or performs actions on a second side of dashed line 110. In one embodiment, uplink (UL) actions performed on the first side of dashed line 112 are performed at a sounding reference signal (SRS) rate. In at least one embodiment, the UL actions performed on the first side of dashed line 112 are performed for an SRS. In at least one embodiment, the SRS is a pilot signal. In at least one embodiment, downlink (DL) actions performed on the second side of dashed line 112 are performed at a slot rate. In at least one embodiment, it should be understood that at least one action shown and / or described as being performed at the SRS rate or the slot rate may be performed at a different rate than shown and / or described.

[0061] In at least one embodiment, at least one function described with respect to distributed unit 102 (e.g., precoding at block 104) is performed in a cloud environment based at least in part on generating precoding weights using a parallel processing device. In at least one embodiment, at least one function described with respect to distributed unit 102 (e.g., precoding at block 104) is not performed in a cloud environment (e.g., at an edge location associated with RRH 106) based at least in part on using at least one parallel processing device (e.g., at least one GPU) included in distributed unit 102.

[0062] In at least one embodiment, the distributed unit 102 receives compressed UL SRS frequency-domain (FD) symbol in-phase / quadrature (I / Q) samples from the RRH 106 and performs I / Q sample decompression at block 114. In one embodiment, the distributed unit 102 performs SRS channel estimation at an SRS channel estimator block 116 based at least in part on the decompressed I / Q samples. In at least one embodiment, the SRS channel estimates are passed to an SRS channel estimate bank 118 of the distributed unit 102, which converts from the UL SRS rate to the DL slot rate. In at least one embodiment, the SRS channel estimates are generated at the SRS rate and written to the SRS channel estimate bank. In at least one embodiment, a subset of the SRS channel estimates from the SRS channel estimate bank is consumed at the DL slot rate. In at least one embodiment, the distributed unit 102 generates precoding weights at block 104 based at least in part on the downlink channel estimates from the SRS channel estimate bank 118. In at least one embodiment, based at least in part on a downlink channel estimation matrix (e.g., having values ​​corresponding to downlink channel estimates from SRS channel estimation library 118), distributed unit 102 generates precoding weights at block 104. In at least one embodiment, based at least in part on BFC configuration information, distributed unit 102 also generates precoding weights at block 104. In at least one embodiment, it should be understood that at least one action shown and / or described as being performed by RRH 106 and / or distributed unit 102 is performed by another device (e.g., channel estimation at block 116 is performed by RRH 106 rather than distributed unit 102).

[0063] In at least one embodiment, the distributed unit 102 generates precoding weights (e.g., as described with respect to FIG) at block 104 based at least in part on using a linear precoding scheme (such as a regularized zero forcing (RZF) algorithm) on a graphics processing unit (GPU). Figure 4In at least one embodiment, RZF precoding is referred to as minimum mean square error (MMSE) precoding. In at least one embodiment, the RZF algorithm is expressed as: in represents the QAM symbol vector to be precoded, represents the RZF precoding vector, represents the RZF precoder coefficient matrix (eg, including precoding weights), H DL represents the estimate of the DL channel coupling matrix, Λ represents the diagonal matrix capturing the noise power, A scalar representing the normalization of coefficients, In at least one embodiment, the precoding weights (eg, BFC weights) generated at block 104 are compressed by the distributed unit 102 at coefficient compression block 120 .

[0064] In at least one embodiment, the distributed unit 102 sends compressed BFC weights to the RRH 106 (e.g., via optical fiber 108). In at least one embodiment, the distributed unit 102 sends information to be transmitted (e.g., to at least one user equipment (UE) device, such as a bit stream from a DL physical (PHY) channel processing and I / Q compression block 122) to the RRH 106. In at least one embodiment, the bit stream to be transmitted to one or more UEs is processed by the DL PHY to generate I / Q samples, which are compressed and sent to the RRH via fronthaul. In at least one embodiment, the distributed unit 102 sends compressed DL frequency-domain (FD) I / Q samples from block 122 to the RRH 106, representing the information to be transmitted to the at least one UE device. In at least one embodiment, the RRH 106 applies precoding weights (e.g., BFC coefficients) to the compressed DL FD I / Q samples at block 124. In at least one embodiment, the RRH 106 applying the precoding weights at block 124 includes generating beamforming signals to control the antenna array. In at least one embodiment, the RRH 106 applying the precoding weights at block 124 includes generating a beamformed signal for transmission. In at least one embodiment, the generated beamformed signal is transmitted from an antenna array. In at least one embodiment, the RRH 106 creates a radiation pattern by adjusting the amplitude and phase of a signal from each radiating element of an antenna (e.g., an antenna array) based at least in part on multiplying each user's signal by the precoding weights. In at least one embodiment, the RRH 106 transmits a beamformed signal (e.g., for massive multiple-input multiple-output (MIMO) and / or millimeter-wave (mmWave) fifth-generation (5G) wireless New Radio (NR) technology) based at least in part on applying the precoding weights generated by the distributed unit 102 at block 104.

[0065] Figure 2 An antenna array is shown transmitting downlink signals in a wireless communication environment 200 according to at least one embodiment. In at least one embodiment, antenna array 202 transmits downlink signals to a corresponding group of user equipment (UE) devices 206 using beam groups 204. In at least one embodiment, antenna array 202 is an 8x8 flat panel antenna array having 64 antennas. In at least one embodiment, each antenna of antenna array 202 is dual polarized (e.g., -45 degrees and +45 degrees). In at least one embodiment, the beams in beam groups 204 are based at least in part on precoding weights (e.g., Figure 1In at least one embodiment, the RRH 106 includes an antenna array 202. In at least one embodiment, the antenna array 202 forms beam groups 204 to perform spatial multiplexing.

[0066] In at least one embodiment, it should be understood that beam group 204 includes at least one sidelobe, which is not shown for clarity. In at least one embodiment, antenna array 202 implements spatial multiplexing gain for spatial separation of users and / or beams (e.g., in a multi-user multiple input multiple output (MU-MIMO) environment). In at least one embodiment, antenna array 202 implements spatial multiplexing gain to increase system throughput and / or improve spectral efficiency for serving multiple spatial streams simultaneously and / or on the same frequency. In at least one embodiment, antenna array 202 implements spatial multiplexing gain by transmitting independent data signals from each antenna.

[0067] In at least one embodiment, antenna array 208 is an 8x8 flat panel antenna array having 64 antennas. In at least one embodiment, each antenna of antenna array 208 is dual polarized (e.g., -45 degrees and +45 degrees). In at least one embodiment, antenna array 208 uses beamforming to generate array gain to transmit a beamformed signal 210 in a specific direction to UE device 212 to transmit a downlink signal. In at least one embodiment, beamformed signal 210 includes a main lobe directed toward UE device 212 and at least one side lobe. In at least one embodiment, RRH 106 includes at least one of antenna array 202 and / or antenna array 208. In at least one embodiment, antenna array 202 and antenna array 208 are the same antenna array, but are coupled to each other. Figure 2 1 and 2 to illustrate spatial multiplexing gain for antenna array 202 and array gain for antenna array 208. In at least one embodiment, antenna array 202 and antenna array 208 are the same antenna array, and digital beamforming is used to transmit using spatial multiplexing gain (MU-MIMO), array gain (SU-MIMO), or diversity gain. In at least one embodiment, RRH 106 uses beamforming to generate beamformed signals from antenna array 202 and / or antenna array 208 based at least in part on applying precoding weights at block 124. In at least one embodiment, one or more of antenna array 202 and / or antenna array 208 have a different number of antenna elements and / or configuration (e.g., a size and / or shape other than an 8x8 array) and / or a different polarization configuration (polarizations other than -45 degrees and +45 degrees for the antennas in the antenna array).

[0068] In at least one embodiment, antenna array 208 uses array gain to steer signals in a desired direction. In at least one embodiment, array gain is referred to as beamforming gain. In at least one embodiment, antenna array 208 uses multiple antennas of antenna array 208 to improve signal directivity in a desired direction. In at least one embodiment, antenna array 208 improves link budget and / or reduces transmit power due to the use of array gain. In at least one embodiment, at least one of antenna array 202 and / or antenna array 208 uses spatial diversity gain to combat multipath fading. In at least one embodiment, for spatial diversity gain using diversity transmission and reception, the amount of received signal improvement depends on the statistical independence of signal fading characteristics and circuit interruptions and failures on different diversity paths. In at least one embodiment, the use of spatial diversity gain improves reliability, quality, and / or reduces the probability of wireless link outage.

[0069] Figure 3 is a block diagram illustrating a fifth generation (5G) new radio (NR) signal processing environment 300 including precoding 302 according to at least one embodiment. In at least one embodiment, precoding 302 is referred to as beamforming. In at least one embodiment, precoding 302 is performed in a parallel manner, e.g., with respect to Figure 1-2 and / or Figure 4-6 In at least one embodiment, precoding 302 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processors or components thereof described and / or illustrated herein. In at least one embodiment, distributed unit 102 performs precoding 302.

[0070] In at least one embodiment, at least some of the 5G NR signal processing environment 300 is included in a virtual radio access network (vRAN). In at least one embodiment, the 5G NR signal processing environment 300 includes a 5G vRAN stack 306 having a lower physical (PHY) layer 308, an upper PHY layer 310, a media access control (MAC) layer 312, a radio link control (RLC) layer 314, and a packet data convergence protocol (PDCP) layer 316. In at least one embodiment, the lower PHY layer 308 and the upper PHY layer 310 are referred to as PHY layers rather than being separately referenced. In at least one embodiment, the 5G vRAN stack 306 communicates with at least one user equipment (UE) 318 (shown as UE1 through UEn) via a radio frequency (RF) layer 320 and a wireless channel 322. In at least one embodiment, the 5G vRAN stack 106 communicates with a 5G packet core 324 using Internet Protocol (IP) packets.

[0071] In at least one embodiment, the lower PHY layer 308 and the upper PHY layer 310 include signal processing components 326, shown in an expanded block diagram between an analog-to-digital converter (ADC) / digital-to-analog converter (DAC) 328 and a MAC layer 312. In at least one embodiment, the uplink path 330 includes orthogonal frequency division multiplexing (OFDM) demodulation 332, receiver (Rx) beamforming 334, channel estimation 336, channel equalization 338, scrambling demodulation 339, derate matching 340, low-density parity check (LDPC) decoding 341, and transport block cyclic redundancy check (CRC) 342. In at least one embodiment, the downlink path 344 includes CRC segmentation 346, LDPC encoding 348, rate matching 350, scrambling modulation 352, precoding 302, transmit (Tx) beamforming 356, and OFDM modulation 358. In at least one embodiment, the downlink PHY layer operates as a virtual network function (VNF). In at least one embodiment, the VNF running the downlink PHY layer runs in a cluster computing environment. In at least one embodiment, the downlink PHY layer processes data associated with a multiple-input multiple-output (MIMO) layer.

[0072] In at least one embodiment, the RRH 106 includes an RF layer 320. In at least one embodiment, the RF layer 320 includes the antenna array 202 and / or the antenna array 208. In at least one embodiment, the UE 318 corresponds to the UE device 206 and / or the UE device 212. In at least one embodiment, at least one aspect of the downlink path 344 including the precoding 302 is performed in a software defined radio environment (e.g., using at least one GPU of the distributed unit 102). In at least one embodiment, the downlink path 344 is delay sensitive and, as described with respect to FIG. Figure 1 Frame 104, Figure 4 Precoding technology 400, Figure 5 TECH 500 and / or Figure 6 Precoding 302 may be performed as described in at least one of the techniques 600 to provide advantages over conventional techniques by reducing latency and / or providing other computational, time, power, and / or other resource utilization improvements.

[0073] Figure 4 is a block diagram illustrating aspects of a precoding technique 400 according to at least one embodiment. In at least one embodiment, the precoding technique 400 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processor or component described and / or illustrated herein. In at least one embodiment, the precoding technique 400 is performed by Figure 1In at least one embodiment, at least one aspect of the precoding technique 400 is performed by the distributed unit 102. Figure 3 302 of FIG. In at least one embodiment, one or more circuits of a parallel processor perform precoding technique 400 on a 5G downlink signal in parallel using two or more processing threads. In at least one embodiment, precoding technique 400 includes generating a Gram matrix 402, an identity matrix 404, and downlink channel estimation information 406. In at least one embodiment, Gram matrix 402 is an enhanced Gram matrix. In at least one embodiment, precoding technique 400 includes storing Gram matrix 402 in a first portion of augmented matrix 408. In at least one embodiment, precoding technique 400 includes storing identity matrix 404 in a second portion of augmented matrix 408. In one embodiment, precoding technique 400 includes storing downlink channel estimation information 406 in a third portion of augmented matrix 408. In at least one embodiment, portions of augmented matrix 408 are not shown to scale for clarity. In at least one embodiment, the Gram matrix 402 , the identity matrix 404 , and the downlink channel estimation matrix including the downlink channel estimation information 406 are tiled in the augmented matrix 408 .

[0074] In at least one embodiment, the Gram matrix 402 is composed of The enhanced Gram matrix represented by H DL is an estimate of the DL channel coupling matrix, It is H DL is the conjugate transposed matrix of , and Λ is a diagonal matrix that captures the noise power. In at least one embodiment, the Gram matrix 402 is stored in the augmented matrix 408 as a 16x16 matrix. In at least one embodiment, the identity matrix 404 is stored in the augmented matrix 408 as a 16x16 matrix. In at least one embodiment, the identity matrix 404 stored in the augmented matrix 408 is represented as I. In at least one embodiment, the downlink channel estimation information 406 is stored in the augmented matrix 408 as a 16x64 matrix. In at least one embodiment, the downlink channel estimation information 406 stored in the augmented matrix 408 is represented as H DL In at least one embodiment, the augmented matrix 408 is represented as [G|I|H DL ].

[0075] In at least one embodiment, the precoding technique 400 includes, at block 410, encoding the G, I, and H DLIn at least one embodiment, the precoding technique 400 includes generating an intermediate matrix 412 based at least in part on performing the lower upper decomposition at block 410. In at least one embodiment, in each iteration of the LU decomposition, threads in a thread block (e.g., running on a GPU or other parallel processor) perform a joint lower upper (LU) decomposition on the augmented matrix 408 of G and I and H. DL Gaussian elimination is performed on all columns of . In at least one embodiment, the intermediate matrix 412 is represented as [U|L -1 |M], where U = L\G and M = L\H DL In at least one embodiment, U = L -1 G is derived from the LU decomposition of G, where G = LU and M = L -1 H DL In at least one embodiment, the lower-upper decomposition performed at block 410 is performed in-place relative to the augmented matrix 408, such that the intermediate matrix 412 is generated in the same memory location as the augmented matrix 408. In at least one embodiment, portions of the intermediate matrix 412 are not shown to scale for clarity.

[0076] In at least one embodiment, the precoding technique 400 includes generating the precoding weights as a coefficient matrix W RZF =M H (D -1 L -1 ), where D = diag(U). In at least one embodiment, augmented matrix 408 is referred to as a first augmented matrix, intermediate matrix 412 is referred to as a second augmented matrix, and generating precoding weights includes generating a conjugate transposed matrix M of a first portion of the second augmented matrix (e.g., matrix M). H , and a conjugate transposed matrix M generated at least in part based on H Perform matrix multiplication (e.g., M H Multiply by (D -1 L -1 )). In at least one embodiment, the precoding technique 400 includes storing the generated precoding weights in one or more memories. In at least one embodiment, one or more circuits of a parallel processor use two or more processing threads in parallel to process (e.g., perform LU decomposition at block 410) a plurality of matrices (e.g., matrices G, I, and H combined into augmented matrix 408) combined into a memory location. DL) generates precoding weights. In at least one embodiment, although augmented matrix 408, intermediate matrix 412, and their components are shown and described as having specific sizes and / or shapes, it should be understood that in other embodiments they may have different sizes and / or shapes.

[0077] In at least one embodiment, the augmented matrix 408 and the intermediate matrix 412 are stored in shared memory. In at least one embodiment, the shared memory is a high-speed user-controlled memory. In at least one embodiment, the shared memory is the shared memory available to the streaming multiprocessor (SM) of the GPU. In at least one embodiment, the shared memory is limited (e.g., up to 96KB per SM of a particular GPU), and the amount of shared memory used affects the occupancy rate (e.g., the ratio of active thread blocks to the total number of thread blocks supported on the SM). In at least one embodiment, the precoding technique 400 overwrites the augmented matrix (e.g., augmented matrix 408) with the intermediate matrix (e.g., intermediate matrix 412) in the shared memory so that the calculation occurs in place (e.g., the output replaces the input). In at least one embodiment, the shared memory overlay improves the efficiency of shared memory usage and improves the occupancy rate by reusing the shared memory.

[0078] In at least one embodiment, the precoding technique 400 is performed using a parallel processor (e.g., a GPU or a parallel processing unit (PPU)). In at least one embodiment, the precoding weights generated by the precoding technique 400 are referred to as transmit precoder weights. In at least one embodiment, the precoding technique 400 generates the transmit precoder weights based at least in part on a linear precoding scheme (such as an RZF algorithm). In at least one embodiment, the transmit precoder weights generated by the precoding technique 400 are referred to as transmit precoder weights. Indicates that In at least one embodiment, since G is Hermitian symmetric, it has an LDL (Cholesky) decomposition Therefore, in at least one embodiment, In at least one embodiment, A = [G | I | H DL ] indicates that by tiling the matrices G, I, H DL The obtained augmented matrix (e.g., augmented matrix 408). In at least one embodiment, technique 400 includes applying LU decomposition to A (e.g., at block 410) such that Where U = L -1 G is derived from the LU decomposition of G, G=LU, and M=L -1 H DLTherefore, in at least one embodiment, W RZF =M H (D -1 L -1 ), where D = diag(U).

[0079] In at least one embodiment, generating precoding weights based at least in part on the precoding technique 400 results in an improvement over using a method involving Explicit inversion of This approach offers advantages over traditional methods that employ direct computations of G, as explicit inversion compromises numerical precision and is not easily parallelizable. In at least one embodiment, the generation of precoding weights based at least in part on precoding technique 400 leverages the Hermitian symmetry of G to restructure the computational steps, augment the matrix, and apply a parallel (LU) decomposition algorithm. In at least one embodiment, the generation of precoding weights based at least in part on precoding technique 400 avoids explicit computation of the inverse of G, providing better numerical precision than traditional methods. In at least one embodiment, the generation of precoding weights based at least in part on precoding technique 400 eliminates the need for forward or backward substitution, which offers advantages over traditional methods, as these forward and backward substitutions are iterative in nature and not easily parallelizable. In at least one embodiment, the net benefit of eliminating these steps is an acceleration of the precoder weight calculation. In at least one embodiment, the generation of precoding weights based at least in part on precoding technique 400 achieves parallelization by applying a joint LU decomposition to a wider augmented matrix obtained by tiling the matrices together. In at least one embodiment, generating precoding weights based at least in part on precoding technique 400 converts higher cost full matrix multiplications into lower cost triangular or diagonal matrix multiplications.

[0080] Figure 5 A flow chart of a technique 500 for generating precoding weights according to at least one embodiment is shown. In at least one embodiment, the technique 500 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processor or component thereof described and / or shown herein. In at least one embodiment, multiple threads of at least one thread block perform at least one aspect of the technique 500 in parallel. In at least one embodiment, Figure 1 The distributed unit 102 performs at least one aspect of the technique 500 .

[0081] In at least one embodiment, at block 502, technique 500 includes determining uplink channel information based at least in part on a sensed uplink channel. In at least one embodiment, at block 504, technique 500 includes estimating a downlink channel (e.g., at a predetermined time) based at least in part on the determined uplink channel. Figure 1 SRS channel estimation is performed at block 116 of . In at least one embodiment, the uplink channel is estimated using the SRS pilot, and the downlink channel is derived from the uplink channel using the reciprocity principle. In at least one embodiment, at block 506, technique 500 includes generating precoding weights (e.g., based at least in part on precoding technique 400) using two or more processing threads in parallel. In at least one embodiment, at block 508, technique 500 includes performing other actions. In at least one embodiment, performing other actions at block 508 includes storing the generated precoding weights in at least one memory. In at least one embodiment, performing other actions at block 508 includes compressing the generated precoding weights. In at least one embodiment, performing other actions at block 508 includes sending the generated precoding weights to an RRH (e.g., RRH 106).

[0082] Figure 6 A flow chart of a technique 600 for generating precoding weights according to at least one embodiment is shown, including performing a decomposition of an augmented matrix. In at least one embodiment, the technique 600 is performed by at least one circuit, at least one system, at least one processor, at least one graphics processing unit, at least one parallel processor, and / or at least some other processor or component thereof described and / or shown herein. In at least one embodiment, multiple threads of at least one thread block perform at least one aspect of the technique 600 in parallel. In at least one embodiment, Figure 1 The distributed unit 102 performs at least one aspect of the technique 600 .

[0083] In at least one embodiment, technique 600 includes, at block 602, storing an augmented matrix (e.g., augmented matrix 408). In at least one embodiment, technique 600 includes, at block 604, performing a decomposition of the augmented matrix to generate an intermediate matrix (e.g., performing LU decomposition 410 to generate intermediate matrix 412). In at least one embodiment, technique 600 includes, at block 606, generating precoding weights based at least in part on the intermediate matrix (e.g., based at least in part on precoding technique 400). In at least one embodiment, technique 600 includes, at block 608, performing other actions. In at least one embodiment, performing other actions at block 608 includes storing the generated precoding weights in at least one memory. In at least one embodiment, performing other actions at block 608 includes transmitting the generated precoding weights to an RRH (e.g., RRH 106). In at least one embodiment, performing other actions at block 608 includes compressing the generated precoding weights.

[0084] Data Center

[0085] Figure 7 An example data center 700 is shown in which at least one embodiment may be used. In at least one embodiment, the data center 700 includes a data center infrastructure layer 710, a framework layer 720, a software layer 730, and an application layer 740.

[0086] In at least one embodiment, Figure 7 As shown, the data center infrastructure layer 710 may include a resource coordinator 712, grouped computing resources 714, and node computing resources ("node CRs") 716(1)-716(N), where "N" represents any integer, positive integer. In at least one embodiment, the node CRs 716(1)-716(N) may include, but are not limited to, any number of central processing units ("CPUs") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory devices (e.g., dynamic read-only memories), storage devices (e.g., solid-state drives or disk drives), network input / output ("NW I / O") devices, network switches, virtual machines ("VMs"), power modules, and cooling modules. In at least one embodiment, one or more of the node CRs 716(1)-716(N) may be servers having one or more of the above-mentioned computing resources.

[0087] In at least one embodiment, the grouped computing resources 714 may include separate groups of node CRs housed in one or more racks (not shown), or may include many racks (also not shown) housed in data centers at various geographic locations. In at least one embodiment, the separate groups of node CRs within the grouped computing resources 714 may include computing, networking, memory, or storage resources that may be configured or allocated to support groupings of one or more workloads. In at least one embodiment, several node CRs comprising a CPU or processor may be grouped in one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0088] In at least one embodiment, resource coordinator 712 may configure or otherwise control one or more nodes CR 716(1)-716(N) and / or grouped computing resources 714. In at least one embodiment, resource coordinator 712 may comprise a software design infrastructure ("SDI") management entity for data center 700. In at least one embodiment, resource coordinator 712 may comprise hardware, software, or some combination thereof.

[0089] In at least one embodiment, Figure 7 As shown, the framework layer 720 includes a job scheduler 732, a configuration manager 734, a resource manager 736, and a distributed file system 738. In at least one embodiment, the framework layer 720 may include a framework that supports the software 732 of the software layer 730 and / or one or more applications 742 of the application layer 740. In at least one embodiment, the software 732 or the application 742 may include web-based service software or applications, such as those provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 720 may be, but is not limited to, a free and open source software web application framework such as Apache Spark that can utilize the distributed file system 738 for large-scale data processing (e.g., "big data"). TM(hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 732 may include a Spark driver to facilitate scheduling of workloads supported by the various layers of the data center 700. In at least one embodiment, the configuration manager 734 may be capable of configuring the various layers, such as the software layer 730 and the framework layer 720 including Spark and a distributed file system 738 for supporting large-scale data processing. In at least one embodiment, the resource manager 736 may be capable of managing the mapping or allocation of clustered or grouped computing resources used to support the distributed file system 738 and the job scheduler 732. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 714 on the data center infrastructure layer 710. In at least one embodiment, the resource manager 736 may coordinate with the resource coordinator 712 to manage these mapped or allocated computing resources.

[0090] In at least one embodiment, the software 732 included in the software layer 730 may include software used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. In at least one embodiment, the one or more types of software may include, but are not limited to, Internet web page search software, email virus scanning software, database software, and streaming video content software.

[0091] In at least one embodiment, the one or more applications 742 included in the application layer 740 may include one or more types of applications used by at least a portion of the node CRs 716(1)-716(N), the grouped computing resources 714, and / or the distributed file system 738 of the framework layer 720. In at least one embodiment, the one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, and machine learning applications, including training or inference software, machine learning framework software (e.g., PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0092] In at least one embodiment, any of configuration manager 734, resource manager 736, and resource coordinator 712 can implement any number and type of self-modification actions based on any number and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modification actions can relieve a data center operator of data center 700 from making potentially poor configuration decisions and can avoid underutilized and / or poorly performing portions of the data center.

[0093] In at least one embodiment, data center 700 may include tools, services, software, or other resources to train one or more machine learning models or use one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture using the software and computing resources described above with respect to data center 700. In at least one embodiment, using the weight parameters calculated using one or more training techniques described herein, a trained machine learning model corresponding to one or more neural networks may be used to infer or predict information using the resources described above with respect to data center 700.

[0094] In at least one embodiment, a data center can use a CPU, application-specific integrated circuit (ASIC), GPU, FPGA, or other hardware to use the above resources to perform training and / or reasoning. In addition, one or more of the above software and / or hardware resources can be configured as a service to allow users to train or perform information reasoning, such as image recognition, speech recognition, or other artificial intelligence services.

[0095] In at least one embodiment, Figure 7 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, at least one of the grouped computing resources 714 and the node CR 716 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of a parallel processor. In at least one embodiment, at least one of the grouped computing resources 714 and the node CR 716 is configured to generate precoding weights using two or more parallel processing threads by processing at least a plurality of matrices combined into a memory location. In at least one embodiment, at least one of the grouped computing resources 714 and the node CR 716 performs at least one aspect described with respect to the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0096] Figure 8A An example of an autonomous vehicle 800 according to at least one embodiment is shown. In at least one embodiment, autonomous vehicle 800 (alternatively referred to herein as "vehicle 800") can be, but is not limited to, a passenger vehicle, such as a car, truck, bus, and / or another type of vehicle that can accommodate one or more passengers. In at least one embodiment, vehicle 800 can be a semi-tractor-trailer for hauling cargo. In at least one embodiment, vehicle 800 can be an aircraft, a robotic vehicle, or another type of vehicle.

[0097] Automated driving vehicles may be described according to the levels of automation defined by the National Highway Traffic Safety Administration ("NHTSA") and the Society of Automotive Engineers ("SAE") under the U.S. Department of Transportation, "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, dated June 15, 2018, Standard No. J3016-201609, dated September 30, 2016, and previous and future versions of this standard). In one or more embodiments, the vehicle 800 may be capable of functioning according to one or more of the levels 1 to 5 of automated driving. For example, in at least one embodiment, the vehicle 800 may be capable of conditional automation (Level 3), high automation (Level 4), and / or full automation (Level 5), depending on the embodiment.

[0098] In at least one embodiment, vehicle 800 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 800 may include, but is not limited to, a propulsion system 850, such as an internal combustion engine, a hybrid power plant, an all-electric engine, and / or another type of propulsion system. In at least one embodiment, propulsion system 850 may be connected to a drive train of vehicle 800, which may include, but is not limited to, a transmission, to enable propulsion of vehicle 800. In at least one embodiment, propulsion system 850 may be controlled in response to receiving a signal from throttle / accelerator 852.

[0099] In at least one embodiment, when the propulsion system 850 is operating (e.g., when the vehicle is traveling), a steering system 854 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 800 (e.g., along a desired path or route). In at least one embodiment, the steering system 854 may receive signals from a steering actuator 856. In at least one embodiment, a steering wheel may be optional for fully automated (Level 5) functionality. In at least one embodiment, a brake sensor system 846 may be used to operate the vehicle brakes in response to signals received from a brake actuator 848 and / or brake sensors.

[0100] In at least one embodiment, the controller 836 may include, but is not limited to, one or more system-on-chips ("SoCs") ( Figure 8A) and / or a graphics processing unit ("GPU") provides signals (e.g., representing commands) to one or more components and / or systems of vehicle 800. For example, in at least one embodiment, controller 836 can send signals to operate vehicle brakes via brake actuator 848, operate steering system 854 via one or more steering actuators 856, and operate propulsion system 850 via one or more throttles / accelerators 852. In at least one embodiment, one or more controllers 836 may include one or more onboard (e.g., integrated) computing devices (e.g., supercomputers) that process sensor signals and output operational commands (e.g., signals representing commands) to implement autonomous driving and / or assist the driver in driving vehicle 800. In at least one embodiment, one or more controllers 836 may include a first controller 836 for autonomous driving functionality, a second controller 836 for functional safety functionality, a third controller 836 for artificial intelligence functionality (e.g., computer vision), a fourth controller 836 for infotainment functionality, a fifth controller 836 for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller 836 may handle two or more of the above functions, two or more controllers 836 may handle a single function, and / or any combination thereof.

[0101] In at least one embodiment, the one or more controllers 836 provide signals for controlling one or more components and / or systems of the vehicle 800 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data can be received from sensors such as, but not limited to, one or more global navigation satellite system ("GNSS") sensors 858 (e.g., one or more global positioning system sensors), one or more RADAR sensors 860, one or more ultrasonic sensors 862, one or more LIDAR sensors 864, one or more inertial measurement unit (IMU) sensors 866 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 896, one or more stereo cameras 868, one or more wide-angle cameras 870 (e.g., fisheye cameras), one or more infrared cameras 872, one or more surround cameras 874 (e.g., 360-degree cameras), long-range cameras (e.g., infrared cameras), and / or a plurality of other sensors. Figure 8A Not shown), mid-range camera ( Figure 8A), one or more speed sensors 844 (e.g., for measuring the speed of the vehicle 800), one or more vibration sensors 842, one or more steering sensors 840, one or more brake sensors (e.g., as part of a brake sensor system 846), and / or other sensor types are received.

[0102] In at least one embodiment, one or more controllers 836 may receive input (e.g., represented by input data) from a dashboard 832 of the vehicle 800 and provide output (e.g., represented by output data, display data, etc.) via a human machine interface ("HMI") display 834, an audible annunciator, a speaker, and / or other components of the vehicle 800. In at least one embodiment, the output may include information such as vehicle speed, velocity, time, map data (e.g., high definition map ( Figure 8A ), location data (e.g., the location of the vehicle 800, such as on a map), directions, the locations of other vehicles (e.g., occupancy barriers), information about objects and the states of objects sensed by the one or more controllers 836, etc. For example, in at least one embodiment, the HMI display 834 can display information about the presence of one or more objects (e.g., road signs, warning signs, traffic light changes, etc.) and / or information about driving maneuvers the vehicle has, is, or will make (e.g., changing lanes now, taking exit 34B in two miles, etc.).

[0103] In at least one embodiment, the vehicle 800 further includes a network interface 824 that can communicate over one or more networks using one or more wireless antennas 826 and / or one or more modems. For example, in at least one embodiment, the network interface 824 may be capable of communicating over Long Term Evolution ("LTE"), Wideband Code Division Multiple Access ("WCDMA"), Universal Mobile Telecommunications System ("UMTS"), Global System for Mobile Communications ("GSM"), IMT-CDMA Multi-Carrier ("CDMA2000") networks, etc. In at least one embodiment, the one or more wireless antennas 826 can also use one or more local area networks (e.g., Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low power wide area networks (hereinafter referred to as "LPWAN") (e.g., protocols such as LoRaWAN, SigFox, etc.) to enable communication between objects in the environment (e.g., vehicles, mobile devices).

[0104] In at least one embodiment, Figure 2The beamformed signals transmitted by the antenna array 202 and / or the antenna array 208 may be transmitted to the vehicle 800, as described with respect to Figure 1-6 At least one of the described can be used to provide vehicle 800 with information for its autonomous operation, such as weather data, navigation data, road condition data, and / or can be used to provide a remote operator with the ability to remotely control vehicle 800.

[0105] Figure 8B According to at least one embodiment, Figure 8A An example of camera locations and fields of view for an autonomous vehicle 800 is shown. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located in different locations on the vehicle 800.

[0106] In at least one embodiment, the camera type used for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 800. In at least one embodiment, one or more cameras may operate at Automotive Safety Integrity Level (“ASIL”) B and / or other ASILs. In at least one embodiment, the camera type may have any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, another type of shutter, or a combination thereof. In at least one embodiment, the color filter array may include a red-clear-clear (“RCCC”) filter array, a red-clear-clear-blue (“RCCB”) filter array, a red-blue-green-clear (“RBGC”) filter array, a Foveon X3 filter array, a Bayer sensor (“RGGB”) filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a clear pixel camera, such as one having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to increase photosensitivity.

[0107] In at least one embodiment, one or more cameras can be used to perform advanced driver assistance system ("ADAS") functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-function mono camera can be installed to provide functions including lane departure warning, traffic sign assistance, and intelligent headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can simultaneously record and provide image data (e.g., video).

[0108] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional ("3D") printed) assembly, so as to cut out stray light and reflections from within the car (e.g., reflections from the dashboard reflecting in the windshield mirror) that might interfere with the camera's ability to capture image data. With respect to the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be custom 3D printed so that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side-view cameras, one or more cameras can also be integrated into the four pillars at each corner of the car.

[0109] In at least one embodiment, a camera (e.g., a forward-facing camera) having a field of view that includes a portion of the environment in front of the vehicle 800 can be used for surround vision and, with the assistance of one or more controllers 836 and / or control SoCs, to help identify the forward path and obstacles, thereby providing information that is critical for generating an occupancy grid and / or determining a preferred vehicle path. In at least one embodiment, a forward-facing camera can be used to perform many of the same ADAS functions as LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, a forward-facing camera can also be used for ADAS functions and systems, including but not limited to lane departure warning ("LDW"), automatic cruise control ("ACC"), and / or other functions (e.g., traffic sign recognition).

[0110] In at least one embodiment, various cameras can be used in a forward-facing configuration, including, for example, a monocular camera platform including a CMOS ("Complementary Metal Oxide Semiconductor") color imager. In at least one embodiment, a wide-angle camera 870 can be used to sense objects entering from the periphery (e.g., pedestrians, people crossing the road, or bicycles). Although Figure 8B Only one wide-angle camera 870 is shown in the figure, however, in other embodiments, any number (including zero) of wide-angle cameras can be present on the vehicle 800. In at least one embodiment, any number of remote cameras 898 (e.g., a remote stereo camera pair) can be used for depth-based object detection, particularly for objects for which a neural network has not yet been trained. In at least one embodiment, the remote cameras 898 can also be used for object detection and classification, as well as basic object tracking.

[0111] In at least one embodiment, any number of stereo cameras 868 may also be included in the forward configuration. In at least one embodiment, one or more stereo cameras 868 may include an integrated control unit including a scalable processing unit that may provide programmable logic ("FPGA") and a multi-core microprocessor with a controller area network ("CAN") or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit may be used to generate a 3D map of the environment of the vehicle 800, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 868 may include, but are not limited to, a compact stereo vision sensor, which may include, but are not limited to, two camera lenses (one on each side) and an image processing chip that may measure the distance from the vehicle 800 to the target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 868 may be used in addition to those described herein.

[0112] In at least one embodiment, a camera having a field of view of a portion of the environment including the sides of the vehicle 800 (e.g., a side-view camera) can be used for surround viewing to provide information for creating and updating occupancy grids and generating side collision warnings. For example, in at least one embodiment, the surround camera 874 (e.g., Figure 8B Four surround cameras 874 (shown) can be positioned on the vehicle 800. In at least one embodiment, the one or more surround cameras 874 can include, but are not limited to, any number and combination of wide-angle cameras 870, one or more fish-eye lenses, one or more 360-degree cameras, and / or the like. For example, in at least one embodiment, four fish-eye lens cameras can be located on the front, rear, and sides of the vehicle 800. In at least one embodiment, the vehicle 800 can use three surround cameras 874 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward-facing camera) as a fourth surround-view camera.

[0113] In at least one embodiment, a camera having a field of view that includes a portion of the environment behind the vehicle 800 (e.g., a rearview camera) can be used for parking assistance, surround view, rear collision warning, and creating and updating occupancy grids. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward-facing cameras (e.g., long-range camera 898 and / or one or more mid-range cameras 876, one or more stereo cameras 868, one or more infrared cameras 872, etc.), as described herein.

[0114] In at least one embodiment, Figure 2 The beamformed signals transmitted by the antenna array 202 and / or the antenna array 208 may be transmitted to the vehicle 800, as described with respect to Figure 1-6 At least one of the described can be used to provide vehicle 800 with information for its autonomous operation, such as weather data, navigation data, road condition data, and / or can be used to provide a remote operator with the ability to remotely control vehicle 800.

[0115] Figure 8C According to at least one embodiment, Figure 8A A block diagram of an example system architecture for an autonomous vehicle 800 is provided. In at least one embodiment, Figure 8C Each of one or more components, one or more features, and one or more systems of vehicle 800 is shown as being connected via bus 802. In at least one embodiment, bus 802 may include, but is not limited to, a CAN data interface (alternatively referred to herein as a "CAN bus"). In at least one embodiment, CAN may be a network internal to vehicle 800 that facilitates control of various features and functions of vehicle 800, such as brake actuation, acceleration, braking, steering, wipers, and the like. In one embodiment, bus 802 may be configured with dozens or even hundreds of nodes, each with its own unique identifier (e.g., a CAN ID). In at least one embodiment, bus 802 may be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle status indicators. In at least one embodiment, bus 802 may be an ASIL B compliant CAN bus.

[0116] In at least one embodiment, FlexRay and / or Ethernet may be used in addition to or in addition to CAN. In at least one embodiment, there may be any number of buses 802, including, but not limited to, zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using other protocols. In at least one embodiment, two or more buses 802 may be used to perform different functions and / or for redundancy. For example, a first bus 802 may be used for collision avoidance, and a second bus 802 may be used for actuation control. In at least one embodiment, each bus 802 may communicate with any component of the vehicle 800, and two or more buses 802 may communicate with the same component. In at least one embodiment, each of any number of system-on-chips ("SoCs") 804, each of one or more controllers 836, and / or each computer within the vehicle may have access to the same input data (e.g., input from sensors in the vehicle 800) and may be connected to a common bus, such as a CAN bus.

[0117] In at least one embodiment, the vehicle 800 may include one or more controllers 836, such as those described herein with respect to Figure 8A In at least one embodiment, the controller 836 can be used for a variety of functions. In at least one embodiment, the controller 836 can be coupled to any of the various other components and systems of the vehicle 800 and can be used to control the vehicle 800, the artificial intelligence of the vehicle 800, the infotainment and / or other functions of the vehicle 800.

[0118] In at least one embodiment, the vehicle 800 may include any number of SoCs 804. Each of the SoCs 804 may include, but is not limited to, a central processing unit ("CPU(s)") 806, a graphics processing unit ("GPU(s")) 808, one or more processors 810, one or more caches 812, one or more accelerators 814, one or more data stores 816, and / or other components and features not shown. In at least one embodiment, the one or more SoCs 804 may be used to control the vehicle 800 in various platforms and systems. For example, in at least one embodiment, the one or more SoCs 804 may be combined in a system (e.g., a system of the vehicle 800) with a high-definition ("HD") map 822 that may be downloaded from one or more servers (e.g., a system of the vehicle 800) via a network interface 824. Figure 8C ) to obtain map refreshes and / or updates.

[0119] In at least one embodiment, one or more CPUs 806 may include a CPU cluster or CPU complex (alternatively referred to herein as a "CCPLEX"). In at least one embodiment, one or more CPUs 806 may include multiple cores and / or a level 2 ("L2") cache. For example, in at least one embodiment, one or more CPUs 806 may include eight cores in a mutually coupled multiprocessor configuration. In at least one embodiment, one or more CPUs 806 may include four dual-core clusters, each with a dedicated L2 cache (e.g., a 2MB L2 cache). In at least one embodiment, one or more CPUs 806 (e.g., CCPLEX) may be configured to support simultaneous cluster operations such that any combination of clusters of one or more CPUs 806 may be active at any given time.

[0120] In at least one embodiment, one or more CPUs 806 can implement power management functionality including, but not limited to, one or more of the following features: automatic clock gating of various hardware modules when idle to conserve dynamic power; clock gating of each core when the core is not actively executing instructions due to executing a wait-for-interrupt ("WFI") / wait-for-event ("WFE") instruction; each core can be independently powered; each core cluster can be independently clock gated when all cores are clock gated or power gated; and / or each core cluster can be independently power gated when all cores are power gated. In at least one embodiment, one or more CPUs 806 can further implement an enhanced algorithm for managing power states, wherein allowed power states and expected wakeup times are specified, and hardware / microcode determines the optimal power state for the core, cluster, and CCPLEX input. In at least one embodiment, the processing core can support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0121] In at least one embodiment, one or more GPUs 808 may include an integrated GPU (or alternatively referred to herein as an "iGPU"). In at least one embodiment, one or more GPUs 808 may be programmable and may be efficient for parallel workloads. In at least one embodiment, one or more GPUs 808 may use an enhanced tensor instruction set. In one embodiment, one or more GPUs 808 may include one or more streaming microprocessors, each of which may include a level 1 ("L1") cache (e.g., an L1 cache with at least 96KB of storage capacity), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with 512KB of storage capacity). In at least one embodiment, one or more GPUs 808 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 808 may use a computing application programming interface (API). In at least one embodiment, one or more GPUs 808 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA).

[0122] In at least one embodiment, one or more GPUs 808 can be power-optimized for optimal performance in automotive and embedded use cases. For example, in one embodiment, one or more GPUs 808 can be fabricated on fin field-effect transistors (“FinFETs”). In at least one embodiment, each streaming microprocessor can include multiple mixed-precision processing cores partitioned into multiple blocks. For example, but not limited to, 64 PF32 cores and 32 PF64 cores can be partitioned into four processing blocks. In at least one embodiment, each processing block can be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA Tensor Cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a warp scheduler, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor can include independent parallel integer and floating-point data paths to provide efficient execution of workloads that mix compute and addressing operations. In at least one embodiment, the streaming microprocessor can include independent thread scheduling capabilities to enable finer-grained synchronization and collaboration between parallel threads. In at least one embodiment, a streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0123] In at least one embodiment, one or more GPUs 808 may include high bandwidth memory ("HBM") and / or a 16GB HBM2 memory subsystem to provide a peak memory bandwidth of approximately 900 GB / s in some examples. In at least one embodiment, synchronous graphics random access memory ("SGRAM"), such as graphics double data rate type five synchronous random access memory ("GDDR5"), may be used in addition to or in lieu of HBM memory.

[0124] In at least one embodiment, the one or more GPUs 808 may include unified memory technology. In at least one embodiment, address translation services ("ATS") support may be used to allow the one or more GPUs 808 to directly access the one or more CPU 806 page tables. In at least one embodiment, when the one or more GPU 808 memory management units ("MMUs") experience a miss, an address translation request may be sent to the one or more CPUs 806. In response, in at least one embodiment, the one or more CPUs 806 may look up the virtual-to-physical mapping of the address in its page table and transmit the translation back to the one or more GPUs 808. In at least one embodiment, unified memory technology may allow a single unified virtual address space to be used for memory for both the one or more CPUs 806 and the one or more GPUs 808, thereby simplifying programming the one or more GPUs 808 and porting applications to the one or more GPUs 808.

[0125] In at least one embodiment, one or more GPUs 808 may include any number of access counters that can track the frequency with which one or more GPUs 808 access the memory of other processors. In at least one embodiment, the one or more access counters can help ensure that memory pages are moved to the physical memory of the processor that accesses the page most frequently, thereby improving the efficiency of memory ranges shared between processors.

[0126] In at least one embodiment, one or more SoCs 804 may include any number of caches 812, including those described herein. For example, in at least one embodiment, one or more caches 812 may include a level 3 ("L3") cache available to one or more CPUs 806 and one or more GPUs 808 (e.g., connected to CPUs 806 and GPUs 808). In at least one embodiment, one or more caches 812 may include a write-back cache that can track the state of a line, for example, by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, the L3 cache may include 4MB or more, depending on the embodiment, although smaller cache sizes may be used.

[0127] In at least one embodiment, one or more SoCs 804 may include one or more accelerators 814 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 804 may include a hardware acceleration cluster that may include optimized hardware accelerators and / or large on-chip memory. In at least one embodiment, large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other calculations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 808 and offload some tasks of one or more GPUs 808 (e.g., freeing up more cycles of one or more GPUs 808 to perform other tasks). In at least one embodiment, one or more accelerators 814 may be used for target workloads that are sufficiently stable to withstand acceleration testing (e.g., perception, convolutional neural networks ("CNN"), recurrent neural networks ("RNN"), etc.). In at least one embodiment, the CNN may include a region-based or region-based convolutional neural network ("RCNN") and a fast RCNN (e.g., as used for object detection) or other types of CNN.

[0128] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators ("DLAs"). One or more DLAs may include, but are not limited to, one or more Tensor Processing Units ("TPUs"), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNN, RCNN, etc.). One or more DLAs may be further optimized for a specific set of neural network types and floating-point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU, and often significantly exceeds the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including single-instance convolution functions that support, for example, INT8, INT16, and FP16 data types for features and weights, as well as post-processor functions. In at least one embodiment, one or more DLAs can quickly and efficiently execute neural networks, particularly CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection and recognition and detection using data from microphone 896; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for safety and / or security-related events.

[0129] In at least one embodiment, a DLA can perform any function of one or more GPUs 808, and by using an inference accelerator, for example, a designer can target any function to one or more DLAs or one or more GPUs 808. For example, in at least one embodiment, a designer can focus CNN processing and floating-point operations on one or more DLAs and leave other functions to one or more GPUs 808 and / or other one or more accelerators 814.

[0130] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) may include a programmable vision accelerator ("PVA"), which may be referred to herein alternatively as a computer vision accelerator. In at least one embodiment, one or more PVAs may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems ("ADAS") 838, autonomous driving, augmented reality ("AR") applications, and / or virtual reality ("VR") applications. In at least one embodiment, one or more PVAs may strike a balance between performance and flexibility. For example, in at least one embodiment, each of the one or more PVAs may include, for example, but not limited to, any number of reduced instruction set computer ("RISC") cores, direct memory access ("DMA"), and / or any number of vector processors.

[0131] In at least one embodiment, the RISC core can interact with an image sensor (e.g., an image sensor of any camera described herein), an image signal processor, and the like. In at least one embodiment, each RISC core can include any amount of memory. In at least one embodiment, the RISC core can use any of a variety of protocols, depending on the embodiment. In at least one embodiment, the RISC core can execute a real-time operating system ("RTOS"). In at least one embodiment, the RISC core can be implemented using one or more integrated circuit devices, application specific integrated circuits ("ASICs"), and / or memory devices. For example, in at least one embodiment, the RISC core can include an instruction cache and / or tightly coupled RAM.

[0132] In at least one embodiment, the DMA can enable components of the PVA to access system memory independently of the one or more CPUs 806. In at least one embodiment, the DMA can support any number of features for providing optimizations to the PVA, including, but not limited to, support for multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include, but are not limited to, block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0133] In at least one embodiment, the vector processor can be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA can include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core can include a processor subsystem, a DMA engine (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem can serve as the main processing engine of the PVA and can include a vector processing unit ("VPU"), an instruction cache, and / or a vector memory (e.g., "VMEM"). In at least one embodiment, the VPU core can include a digital signal processor, such as a single instruction multiple data ("SIMD"), a very long instruction word ("VLIW") digital signal processor. In at least one embodiment, the combination of SIMD and VLIW can increase throughput and speed.

[0134] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to a dedicated memory. As a result, in at least one embodiment, each vector processor may be configured to execute independently of the other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to exploit data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute the same computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may execute different computer vision algorithms simultaneously on the same image, or even execute different algorithms on sequenced images or portions of images. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA, among other things. In at least one embodiment, the PVAs may include additional error correction code ("ECC") memory to enhance overall system security.

[0135] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) may include an on-chip computer vision network and static random access memory ("SRAM") to provide high bandwidth, low latency SRAM to the one or more accelerators 814. In at least one embodiment, the on-chip memory may include at least 4MB of SRAM, including, for example, but not limited to, eight field-configurable memory blocks that are accessible to both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an advanced peripheral bus ("APB") interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone network that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone network may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0136] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and DLA provide ready and valid signals before transmitting any control signals / addresses / data. In at least one embodiment, the interface may provide separate phases and separate channels for sending control signals / addresses / data, as well as burst-type communication for continuous data transmission. In at least one embodiment, the interface may comply with the International Organization for Standardization ("ISO") 26262 or International Electrotechnical Commission ("IEC") 61508 standards, although other standards and protocols may be used.

[0137] In at least one embodiment, one or more SoCs 804 may include a real-time gaze tracking hardware accelerator. In at least one embodiment, the real-time gaze tracking hardware accelerator may be used to quickly and efficiently determine the position and range of objects (e.g., within a world model) to generate real-time visual simulations for use in RADAR signal interpretation, for sound propagation synthesis and / or analysis, for simulation of SONAR systems, for general wave propagation simulations, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0138] In at least one embodiment, one or more accelerators 814 (e.g., a hardware acceleration cluster) have a wide range of uses for autonomous driving. In at least one embodiment, the PVA can be a programmable vision accelerator that is used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of the PVA at low power and low latency are well matched to the algorithmic domain that requires predictable processing. In other words, the PVA performs well in semi-intensive or intensive conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, an autonomous vehicle, such as in vehicle 800, may be designed to run classic computer vision algorithms because they can be efficient at object detection and integer math operations.

[0139] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, a semi-global matching-based algorithm may be used in some examples, although this is not meant to be limiting. In at least one embodiment, applications for Level 3-5 autonomous driving use dynamic estimation / stereo matching during operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on input from two monocular cameras.

[0140] In at least one embodiment, the PVA can be used to perform dense optical flow. For example, in at least one embodiment, the PVA can process raw RADAR data (e.g., using a 4D Fast Fourier Transform) to provide processed RADAR data. In at least one embodiment, the PVA is used for time-of-flight depth processing, for example, by processing raw time-of-flight data to provide processed time-of-flight data.

[0141] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example, but not limited to, a neural network that outputs a confidence score for each object detection. In at least one embodiment, the confidence score can be expressed or interpreted as a probability, or as providing a relative "weight" of each detection relative to other detections. In at least one embodiment, the confidence score enables the system to make further decisions about which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence score and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, a false positive detection will cause the vehicle to automatically perform emergency braking, which is obviously undesirable. In at least one embodiment, a highly confident detection can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing the confidence score. In at least one embodiment, the neural network may take as its input at least some subset of parameters, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), outputs of one or more IMU sensors 866 associated with vehicle 800 heading, distance, 3D position estimates of objects obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 864 or one or more RADAR sensors 860), etc.

[0142] In at least one embodiment, one or more SoCs 804 (e.g., a hardware acceleration cluster) may include one or more data stores 816 (e.g., memory). In at least one embodiment, the one or more data stores 816 may be on-chip memory of the one or more SoCs 804, which may store neural networks to be executed on one or more GPUs 808 and / or DLAs. In at least one embodiment, the one or more data stores 816 may have a capacity large enough to store multiple instances of the neural network for redundancy and safety. In at least one embodiment, the one or more data stores 812 may include an L2 or L3 cache.

[0143] In at least one embodiment, one or more SoCs 804 may include any number of processors 810 (e.g., embedded processors). In at least one embodiment, one or more processors 810 may include a boot and power management processor, which may be a dedicated processor and subsystem to handle boot power and management functions and related security implementations. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 804 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, one or more SoCs 804 thermal and temperature sensor management, and / or one or more SoCs 804 power state management. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 804 may use the ring oscillator to detect the temperature of one or more CPUs 806, one or more GPUs 808, and / or one or more accelerators 814. In at least one embodiment, if the temperature is determined to exceed a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 804 into a lower power consumption state and / or place the vehicle 800 into a driver's safe parking pattern (e.g., bringing the vehicle 800 to a safe stop).

[0144] In at least one embodiment, one or more processors 810 may further include a set of embedded processors that can be used as an audio processing engine. In at least one embodiment, the audio processing engine can be an audio subsystem that can provide full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0145] In at least one embodiment, one or more processors 810 may further include an always-on processor engine. In at least one embodiment, the automatic processing engine may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the processors on the always-on processor engine may include, but are not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0146] In at least one embodiment, one or more processors 810 may further include a safety cluster engine, which may include, but is not limited to, a dedicated processor subsystem for handling safety management of automotive applications. In at least one embodiment, the safety cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In safety mode, in at least one embodiment, the two or more cores may operate in lockstep mode and may function as a single core with comparison logic to detect any differences between their operations. In at least one embodiment, one or more processors 810 may further include a real-time camera engine, which may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 810 may further include a high dynamic range signal processor, which may include, but is not limited to, an image signal processor, which is a hardware engine that is part of the camera processing pipeline.

[0147] In at least one embodiment, one or more processors 810 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required by the video playback application to produce the final video, thereby generating the final image for the player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 870, one or more surround cameras 874, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, the in-cabin monitoring camera sensors are preferably monitored by a neural network running on another instance of the SoC 804, the neural network being configured to identify cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular service and place calls, dictate emails, change the vehicle's destination, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode, but are otherwise disabled.

[0148] In at least one embodiment, the video image compositor may include enhanced temporal noise reduction for simultaneous spatial and temporal noise reduction. For example, in at least one embodiment, where motion occurs in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of information provided by adjacent frames. In at least one embodiment, where an image or portion of an image does not include motion, the temporal noise reduction performed by the video image compositor may use information from previous images to reduce noise in the current image.

[0149] In at least one embodiment, the video image compositor can also be configured to perform stereoscopic rectification on the input stereoscopic lens frames. In at least one embodiment, the video image compositor can also be used for user interface composition when using an operating system desktop, without requiring one or more GPUs 808 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 808 are powered and actively performing 3D rendering, the video image compositor can be used to offload one or more GPUs 808 to improve performance and responsiveness.

[0150] In at least one embodiment, one or more of the SoCs 804 may further include a Mobile Industry Processor Interface ("MIPI") camera serial interface for receiving video and input from a camera, a high-speed interface, and / or a video input block that may be used for a camera and associated pixel input functionality. In at least one embodiment, one or more of the SoCs 804 may further include an input / output controller that may be controlled by software and may be used to receive I / O signals that are not assigned to a specific role.

[0151] In at least one embodiment, one or more of the SoCs 804 may further include a wide range of peripheral interfaces to enable communication with peripheral devices, audio encoders / decoders (“codecs”), power management, and / or other devices. The one or more SoCs 804 may be configured to process data from cameras (e.g., via Gigabit multimedia serial links and Ethernet connections), sensors (e.g., one or more LIDAR sensors 864, one or more RADAR sensors 860, etc., which may be connected via Ethernet), data from the bus 802 (e.g., vehicle 800 speed, steering wheel position, etc.), data from one or more GNSS sensors 858 (e.g., via Ethernet bus or CAN bus connections), and the like. In at least one embodiment, one or more of the SoCs 804 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and may be used to offload the one or more CPUs 806 from routine data management tasks.

[0152] In at least one embodiment, one or more SoCs 804 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing a comprehensive functional safety architecture that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, providing a platform that can provide a flexible and reliable driving software stack and deep learning tools. In at least one embodiment, one or more SoCs 804 can be faster and more reliable than conventional systems, and even more energy and space efficient. For example, in at least one embodiment, one or more accelerators 814, when combined with one or more CPUs 806, one or more GPUs 808, and one or more data storage devices 816, can provide a fast and efficient platform for Level 3-5 autonomous driving vehicles.

[0153] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high-level programming language (e.g., the C programming language) to execute a variety of processing algorithms on a variety of visual data. However, in at least one embodiment, CPUs generally cannot meet the performance requirements of many computer vision applications, such as those related to execution time and power consumption. In at least one embodiment, many CPUs are unable to execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual Level 3-5 autonomous driving vehicles.

[0154] The embodiments described herein allow for the simultaneous and / or sequential execution of multiple neural networks and for the results to be combined to achieve Level 3-5 autonomous driving functionality. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 820) may include text and word recognition, allowing the supercomputer to read and understand traffic signs, including signs for which the neural network has not been specifically trained. In at least one embodiment, the DLA may also include a neural network capable of recognizing, interpreting, and providing semantic understanding of the symbols and passing this semantic understanding to a path planning module running on the CPU Complex.

[0155] In at least one embodiment, for Level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign consisting of "Caution: flashing lights indicate icy conditions" along with connected lights can be interpreted independently or collectively by multiple neural networks. In at least one embodiment, the sign itself can be identified as a traffic sign by a first deployed neural network (e.g., a trained neural network), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executing on a CPU Complex) that icy conditions exist when flashing lights are detected. In at least one embodiment, flashing lights can be identified by operating a third deployed neural network over multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, for example within the DLA and / or on one or more GPUs 808.

[0156] In at least one embodiment, a CNN for facial recognition and vehicle owner identification can use data from the camera sensor to identify the presence of an authorized driver and / or owner of the vehicle 800. In at least one embodiment, an always-on sensor processor engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and, in security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 804 provide protection against theft and / or carjacking.

[0157] In at least one embodiment, a CNN for emergency vehicle detection and identification can use data from microphone 896 to detect and identify emergency vehicle sirens. In at least one embodiment, one or more SoCs 804 use the CNN to classify environmental and urban sounds, as well as classify visual data. In at least one embodiment, the CNN running on the DLA is trained to identify the relative approaching speed of the emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to identify emergency vehicles for the area in which the vehicle is operating, as identified by one or more GNSS sensors 858. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while when operating in the United States, the CNN will seek to identify only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used with the assistance of one or more ultrasonic sensors 862 to execute emergency vehicle safety routines, slow the vehicle, pull over, stop the vehicle, and / or idle the vehicle until the emergency vehicle passes.

[0158] In at least one embodiment, the vehicle 800 may include one or more CPUs 818 (e.g., one or more discrete CPUs or one or more dCPUs) that may be coupled to the one or more SoCs 804 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, the one or more CPUs 818 may include an X86 processor, such as one or more CPUs 818. The one or more CPUs 818 may be used to perform any of a variety of functions, including, for example, arbitrating potentially inconsistent results between ADAS sensors and the one or more SoCs 804, and / or monitoring the status and health of the one or more controllers 836 and / or an infotainment system-on-chip ("Infotainment SoC") 830.

[0159] In at least one embodiment, the vehicle 800 may include one or more GPUs 820 (e.g., one or more discrete GPUs or one or more dGPUs) that may be coupled to the one or more SoCs 804 via a high-speed interconnect (e.g., NVIDIA's NVLINK). In at least one embodiment, the one or more GPUs 820 may provide additional artificial intelligence functionality, such as by executing redundant and / or different neural networks, and may be used to train and / or update the neural networks based at least in part on input (e.g., sensor data) from sensors of the vehicle 800.

[0160] In at least one embodiment, vehicle 800 may further include a network interface 824, which may include, but is not limited to, one or more wireless antennas 826 (e.g., one or more wireless antennas 826 for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 824 may be used to enable wireless connectivity with other vehicles and / or computing devices (e.g., a passenger's client device) via the internet with a cloud (e.g., using a server and / or other network devices). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 800 and the other vehicle, and / or an indirect link may be established (e.g., via a network and the internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 800 with information about vehicles in its vicinity (e.g., vehicles in front of, to the sides of, and / or behind vehicle 800). In at least one embodiment, this functionality may be part of the cooperative adaptive cruise control functionality of vehicle 800.

[0161] In at least one embodiment, the network interface 824 may include a SoC that provides modulation and demodulation functionality and enables one or more controllers 836 to communicate over a wireless network. In at least one embodiment, the network interface 824 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by well-known processes and / or using a superheterodyne process. In at least one embodiment, the radio frequency front end functionality may be provided by a separate chip. In at least one embodiment, the network interface may include wireless functionality for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0162] In at least one embodiment, the vehicle 800 may further include one or more data stores 828, which may include, but are not limited to, off-chip (e.g., one or more SoCs 804) storage. In at least one embodiment, the one or more data stores 828 may include, but are not limited to, one or more storage elements including RAM, SRAM, dynamic random access memory ("DRAM"), video random access memory ("VRAM"), flash memory, a hard disk, and / or other components and / or devices that can store at least one bit of data.

[0163] In at least one embodiment, the vehicle 800 may further include one or more GNSS sensors 858 (e.g., GPS and / or assisted GPS sensors) to assist with mapping, perception, occupancy raster generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 858 may be used, including, for example, but not limited to, GPS connected to a serial interface (e.g., RS-232) bridge using a USB connector with Ethernet.

[0164] In at least one embodiment, the vehicle 800 may further include one or more RADAR sensors 860. One or more RADAR sensors 860 may be used by the vehicle 800 for remote vehicle detection, even in darkness and / or in adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. One or more RADAR sensors 860 may use the CAN bus and / or bus 802 (e.g., to transmit data generated by one or more RADAR sensors 860) for control and access to object tracking data, and in some examples may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example, but not limited to, one or more of the RADAR sensors 860 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more RADAR sensors 860 are pulse Doppler RADAR sensors.

[0165] In at least one embodiment, one or more RADAR sensors 860 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR can be used for adaptive cruise control functionality. In at least one embodiment, the long-range RADAR system can provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250m). In at least one embodiment, one or more RADAR sensors 860 can help distinguish between static objects and moving objects and can be used by the ADAS system 838 for emergency brake assistance and forward collision warning. In at least one embodiment, the one or more sensors 860 included in the long-range RADAR system may include, but are not limited to, a single-base multi-mode RADAR with multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, having six antennas, with the central four antennas, can create a focused beam pattern designed to record the surroundings of the vehicle 800 at higher speeds with minimal interference from traffic in adjacent lanes. In at least one embodiment, the additional two antennas can extend the field of view, allowing for quick detection of vehicles entering or leaving the vehicle's 800 lane.

[0166] In at least one embodiment, as an example, a medium-range RADAR system may include, for example, a range of up to 160m (front) or 80m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 860 designed to be mounted on both ends of the rear bumper. When mounted on both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can generate two light beams that continuously monitor the rear of the vehicle and nearby blind spots. In at least one embodiment, the short-range RADAR system can be used in the ADAS system 838 for blind spot detection and / or lane change assistance.

[0167] In at least one embodiment, the vehicle 800 may further include one or more ultrasonic sensors 862. In at least one embodiment, one or more ultrasonic sensors 862, which may be positioned on the front, rear, and / or sides of the vehicle 800, may be used for parking assistance and / or for creating and updating occupancy barriers. In at least one embodiment, a variety of ultrasonic sensors 862 may be used, and different ultrasonic sensors 862 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 862 may operate at an ASIL B functional safety level.

[0168] In at least one embodiment, the vehicle 800 can include one or more LIDAR sensors 864. The one or more LIDAR sensors 864 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, the one or more LIDAR sensors 864 can be functional safety level ASIL B. In at least one embodiment, the vehicle 800 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 864 that can use Ethernet (e.g., provide data to a Gigabit Ethernet switch).

[0169] In at least one embodiment, the one or more LIDAR sensors 864 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 864 may, for example, have an advertised range of approximately 100 meters, an accuracy of 2-3 cm, and support a 100 Mbps Ethernet connection. In at least one embodiment, one or more non-obtrusive LIDAR sensors 864 may be used. In such an embodiment, the one or more LIDAR sensors 864 may be implemented as small devices embedded in the front, rear, sides, and / or corners of the vehicle 800. In at least one embodiment, the one or more LIDAR sensors 864 may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and have a range of 200 meters. In at least one embodiment, the forward-facing one or more LIDAR sensors 864 may be configured for a horizontal field of view between 45 and 135 degrees.

[0170] In at least one embodiment, LIDAR technology (such as 3D flash LIDAR) may also be used. 3D flash LIDAR uses a laser flash as a transmission source to illuminate approximately 200 meters around vehicle 800. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light at each pixel, which in turn corresponds to the range from vehicle 800 to the object. In at least one embodiment, flash LIDAR can enable the generation of a highly accurate and distortion-free image of the surrounding environment with each laser flash. In at least one embodiment, four flash LIDAR sensors can be deployed, one on each side of vehicle 800. In at least one embodiment, a 3D flash LIDAR system includes, but is not limited to, a solid-state 3D line-of-sight array LIDAR camera with no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device can use 5 nanosecond Class I (eye-safe) laser pulses per frame and can capture the reflected laser light in the form of a 3D range point cloud and co-registered intensity data.

[0171] In at least one embodiment, the vehicle 800 may also include one or more IMU sensors 866. In at least one embodiment, the one or more IMU sensors 866 may be located at the center of the rear axle of the vehicle 800. In at least one embodiment, the one or more IMU sensors 866 may include, for example, but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, the one or more IMU sensors 866 may include, but not limited to, accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, the one or more IMU sensors 866 may include, but not limited to, accelerometers, gyroscopes, and magnetometers.

[0172] In at least one embodiment, the one or more IMU sensors 866 can be implemented as a miniature, high-performance GPS-aided inertial navigation system ("GPS / INS") that combines microelectromechanical system ("MEMS") inertial sensors, a high-sensitivity GPS receiver, and advanced Kalman filtering algorithms to provide estimates of position, velocity, and attitude; in at least one embodiment, the one or more IMU sensors 866 can enable the vehicle 800 to estimate heading without input from a magnetic sensor by directly observing and correlating velocity changes from GPS to the one or more IMU sensors 866. In at least one embodiment, the one or more IMU sensors 866 and the one or more GNSS sensors 858 can be combined in a single integrated unit.

[0173] In at least one embodiment, the vehicle 800 can include one or more microphones 896 positioned within and / or around the vehicle 800. In at least one embodiment, the one or more microphones 896 can be used for emergency vehicle detection and identification, among other things.

[0174] In at least one embodiment, the vehicle 800 may further include any number of camera types, including one or more stereo cameras 868, one or more wide angle cameras 870, one or more infrared cameras 872, one or more surround cameras 874, one or more long range cameras 898, one or more mid range cameras 876, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of the vehicle 800. In at least one embodiment, the type of camera used depends on the vehicle 800. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around the vehicle 800. In at least one embodiment, the number of cameras deployed may vary depending on the embodiment. For example, in at least one embodiment, the vehicle 800 may include six cameras, seven cameras, ten cameras, twelve cameras, or another number of cameras. In at least one embodiment, the cameras may, by way of example but not limitation, support Gigabit Multimedia Serial Link ("GMSL") and / or Gigabit Ethernet. In at least one embodiment, the present disclosure previously referred to herein may provide a plurality of cameras. Figure 8A and Figure 8B Each camera can be described in more detail.

[0175] In at least one embodiment, the vehicle 800 can further include one or more vibration sensors 842. In at least one embodiment, the one or more vibration sensors 842 can measure vibrations of a component (e.g., an axle) of the vehicle 800. For example, in at least one embodiment, changes in vibration can indicate changes in the road surface. In at least one embodiment, when two or more vibration sensors 842 are used, the difference between the vibrations can be used to determine friction or slippage in the road surface (e.g., when there is a vibration difference between a powered drive shaft and a freely rotating shaft).

[0176] In at least one embodiment, the vehicle 800 may include an ADAS system 838. The ADAS system 838 may include, but is not limited to, an SoC. In at least one embodiment, the ADAS system 838 may include, but is not limited to, any number of autonomous / adaptive / automatic cruise control ("ACC") systems, cooperative adaptive cruise control ("CACC") systems, forward collision warning ("FCW") systems, automatic emergency braking ("AEB") systems, lane departure warning ("LDW") systems, lane keeping assist ("LKA") systems, blind spot alert ("BSW") systems, rear cross traffic alert ("RCTW") systems, collision warning ("CW") systems, lane centering ("LC") systems, and / or other systems, features, and / or functions, and combinations thereof.

[0177] In at least one embodiment, the ACC system may utilize one or more RADAR sensors 860, one or more LIDAR sensors 864, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to the vehicle immediately ahead of the vehicle 800 and automatically adjusts the speed of the vehicle 800 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 800 change lanes when necessary. In at least one embodiment, lateral ACC is associated with other ADAS applications, such as LC and CW.

[0178] In at least one embodiment, the CACC system uses information from other vehicles, which can be received from other vehicles via a wireless link or indirectly via a network connection (e.g., via the Internet) via a network interface 824 and / or one or more wireless antennas 826. In at least one embodiment, the direct link can be provided by a vehicle-to-vehicle ("V2V") communication link, while the indirect link can be provided by an infrastructure-to-vehicle ("I2V") communication link. Generally, the V2V communication concept provides information about the vehicle immediately ahead (e.g., the vehicle immediately ahead of vehicle 800 and in the same lane as it), while the I2V communication concept provides information about traffic further ahead. In at least one embodiment, the CACC system can include one or both of the I2V and V2V information sources. In at least one embodiment, given information about vehicles ahead of vehicle 800, the CACC system can be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0179] In at least one embodiment, the FCW system is designed to warn the driver of hazards so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward-facing camera and / or one or more RADAR sensors 860, coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of audible, visual warnings, vibrations, and / or rapid brake pulses.

[0180] In at least one embodiment, an AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can utilize one or more forward-facing cameras and / or one or more RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, the AEB system typically first warns the driver to take corrective action to avoid the collision, and if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or imminent collision braking.

[0181] In at least one embodiment, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibrations, to alert the driver when the vehicle 800 crosses a lane marking. In at least one embodiment, the LDW system is inactive when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system may utilize a front-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration assembly. In at least one embodiment, a LKA system is a variation of the LDW system. If the vehicle 800 begins to leave the lane, the LKA system provides steering input or braking to correct the vehicle 800.

[0182] In at least one embodiment, the BSW system detects and warns the driver of vehicles in the car's blind spot. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback, such as a display, speaker, and / or vibration component.

[0183] In at least one embodiment, the RCTW system can provide visual, audible, and / or tactile notifications when an object is detected outside the rear camera range while the vehicle 800 is in reverse. In at least one embodiment, the RCTW system includes an AEB system to ensure application of vehicle brakes to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 860 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0184] In at least one embodiment, conventional ADAS systems can be prone to generating false positive results, which can be annoying and distracting to the driver, but are generally not catastrophic because conventional ADAS systems alert the driver and allow the driver to decide whether a safe condition truly exists and take appropriate action. In at least one embodiment, in the event of conflicting results, the vehicle 800 itself decides whether to follow the results of the primary or secondary computer (e.g., the first controller 836 or the second controller 836). For example, in at least one embodiment, the ADAS system 838 can be a backup and / or auxiliary computer that provides perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run redundant software on hardware components to detect failures in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 838 can be provided to a supervisory MCU. In at least one embodiment, if the outputs from the primary and secondary computers conflict, the supervisory MCU determines how to reconcile the conflict to ensure safe operation.

[0185] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU to indicate the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, if the confidence score does not meet the threshold, and if the primary and secondary computers indicate different results (e.g., conflicting), the supervisory MCU can arbitrate between the computers to determine the appropriate result.

[0186] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine, based at least in part on outputs from the primary and secondary computers, conditions under which the secondary computer provides a false alarm. In at least one embodiment, the neural network in the supervisory MCU can learn when the output of the secondary computer can be trusted and when it cannot. For example, in at least one embodiment, when the secondary computer is a RADAR-based FCW system, the neural network in the supervisory MCU can learn when the FCW system identifies a metallic object that is not actually a danger, such as a drain grate or manhole cover, that would trigger an alarm. In at least one embodiment, when the secondary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when a cyclist or pedestrian is present and lane departure is actually the safest action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running a neural network with associated memory. In at least one embodiment, the supervisory MCU can include and / or be included as a component of one or more SoCs 804.

[0187] In at least one embodiment, the ADAS system 838 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of a neural network in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementations and intentional non-identity make the entire system more fault-tolerant, especially for failures caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or bug in the software running on the main computer, and a different software code running on the auxiliary computer provides the same overall result, the supervisory MCU can be more confident that the overall result is correct and that the vulnerability in the software or hardware on the main computer will not cause a significant error.

[0188] In at least one embodiment, the output of the ADAS system 838 can be input into the primary computer's perception module and / or the primary computer's dynamic driving task module. For example, in at least one embodiment, if the ADAS system 838 indicates a forward collision warning due to an object directly ahead, the perception module can use this information when identifying the object. In at least one embodiment, as described herein, the secondary computer can have its own neural network that has been trained to reduce the risk of false positives.

[0189] In at least one embodiment, the vehicle 800 may further include an infotainment SoC 830 (e.g., an in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, the infotainment system 830 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, the infotainment SoC 830 may include, but is not limited to, a combination of hardware and software that can be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., TV, movies, streaming, etc.), phone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total distance covered, brake fuel level, oil level, door open / closed, air filter information, etc.) to the vehicle 800. For example, the infotainment SoC 830 may include a radio, a disk player, a navigation system, a video player, USB and Bluetooth connectivity, a car, an in-vehicle entertainment system, WiFi, steering wheel audio controls, hands-free voice control, a heads-up display ("HUD"), an HMI display 834, a telematics device, a control panel (e.g., for controlling and / or interacting with various components, features, and / or systems), and / or other components. In at least one embodiment, the infotainment SoC 830 may be further configured to provide information (e.g., visual and / or auditory) to a user of the vehicle, such as information from an ADAS system 838, autonomous driving information (such as planned vehicle maneuvers), trajectory, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0190] In at least one embodiment, the infotainment SoC 830 can include any number and type of GPU functionality. In at least one embodiment, the infotainment SoC 830 can communicate with other devices, systems, and / or components of the vehicle 800 via a bus 802 (e.g., a CAN bus, Ethernet, etc.). In at least one embodiment, the infotainment SoC 830 can be coupled to a supervisory MCU so that the infotainment system's GPU can perform some autonomous driving functions in the event of a failure of a primary controller 836 (e.g., the vehicle 800's main computer and / or backup computer). In at least one embodiment, the infotainment SoC 830 can cause the vehicle 800 to enter a driver-to-safety stop mode, as described herein.

[0191] In at least one embodiment, the vehicle 800 may further include an instrument panel 832 (e.g., a digital instrument panel, an electronic instrument panel, a digital instrument panel, etc.). In at least one embodiment, the instrument panel 832 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or a supercomputer). In at least one embodiment, the instrument panel 832 may include, but is not limited to, any number and combination of a set of instruments, such as a speedometer, fuel level, oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine check lights, supplemental restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 830 and the instrument panel 832. In at least one embodiment, the instrument panel 832 may be included as part of the infotainment SoC 830, or vice versa.

[0192] In at least one embodiment, Figure 2 The beamformed signals transmitted by the antenna array 202 and / or the antenna array 208 may be transmitted to the vehicle 800, as described with respect to Figure 1-6 At least one of the described can be used to provide vehicle 800 with information for its autonomous operation, such as weather data, navigation data, road condition data, and / or can be used to provide a remote operator with the ability to remotely control vehicle 800.

[0193] Figure 8D In accordance with at least one embodiment, a cloud-based server and Figure 8A880 and PCIe switch 882. FIGURE 876 is a diagram of a system 876 for communicating between autonomous vehicles 800. In at least one embodiment, system 876 may include, but is not limited to, one or more servers 878, one or more networks 890, and any number and type of vehicles, including vehicle 800. One or more servers 878 may include, but is not limited to, multiple GPUs 884(A)-884(H) (collectively referred to herein as GPUs 884), PCIe switches 882(A)-882(D) (collectively referred to herein as PCIe switches 882), and / or CPUs 880(A)-880(B) (collectively referred to herein as CPUs 880). GPUs 884, CPUs 880, and PCIe switches 882 may be interconnected with high-speed connections, such as, but not limited to, NVLink interfaces 888 developed by NVIDIA and / or PCIe connections 886. GPUs 884 are connected via NVLink and / or NVSwitch SoCs, and GPUs 884 and PCIe switches 882 are connected via PCIe interconnects. In at least one embodiment, although eight GPUs 884, two CPUs 880, and four PCIe switches 882 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 878 may include, but is not limited to, any combination of any number of GPUs 884, CPUs 880, and / or PCIe switches 882. For example, in at least one embodiment, one or more servers 878 may each include eight, sixteen, thirty-two, and / or more GPUs 884.

[0194] In at least one embodiment, one or more servers 878 may receive image data representing an image from a vehicle via one or more networks 890 that depicts unexpected or altered road conditions, such as recently begun road construction. In at least one embodiment, one or more servers 878 may transmit a neural network 892, an updated neural network 892, and / or map information 894, including, but not limited to, information regarding traffic and road conditions, to the vehicle via one or more networks 890. In at least one embodiment, updates to the map information 894 may include, but not limited to, updates to the HD map 822, such as information regarding construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 892, the updated neural network 892, and / or the map information 894 may be generated by new training and / or experience derived from data received from any number of vehicles in the environment, and / or may be based at least on training performed at a data center (e.g., using one or more servers 878 and / or other servers).

[0195] In at least one embodiment, one or more servers 878 can be used to train a machine learning model (e.g., a neural network) based at least in part on the training data. In at least one embodiment, the training data can be generated by the vehicle and / or can be generated in simulation (e.g., using a game engine). In at least one embodiment, any amount of the training data is labeled (e.g., where the associated neural network benefits from supervised learning) and / or undergoes other pre-processing. In at least one embodiment, no amount of the training data is labeled and / or pre-processed (e.g., where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model can be used by the vehicle (e.g., transmitted to the vehicle via one or more networks 890, and / or the machine learning model can be used by one or more servers 878 to remotely monitor the vehicle.

[0196] In at least one embodiment, one or more servers 878 can receive data from the vehicle and apply the data to the latest real-time neural networks for real-time intelligent reasoning. In at least one embodiment, one or more servers 878 can include a deep learning supercomputer and / or a dedicated AI computer powered by one or more GPUs 884, such as the DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 878 can include the deep learning infrastructure of a data center using CPU power.

[0197] In at least one embodiment, the deep learning infrastructure of one or more servers 878 may be capable of fast, real-time inference and may use this capability to assess and verify the health of the processors, software, and / or related hardware in the vehicle 800. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from the vehicle 800, such as an image sequence and / or objects located within that image sequence by the vehicle 800 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify objects and compare them to those identified by the vehicle 800, and if the results do not match and the deep learning infrastructure concludes that the AI ​​in the vehicle 800 is malfunctioning, the one or more servers 878 may send a signal to the vehicle 800 to instruct the vehicle's 800 fail-safe computer to take control, notify passengers, and complete a safe parking maneuver.

[0198] In at least one embodiment, one or more servers 878 may include one or more GPUs 884 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time responses. In at least one embodiment, for example, in situations where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, the hardware structure is used to execute one or more embodiments.

[0199] Computer system

[0200] Figure 9 9 is a block diagram illustrating an exemplary computer system according to at least one embodiment, which may be a system of interconnected devices and components, a system on a chip (SOC), or some combination thereof formed with a processor that may include execution units to execute instructions. In at least one embodiment, in accordance with the present disclosure, such as the embodiments described herein, computer system 900 may include, but is not limited to, components such as processor 902, whose execution units include logic to execute algorithms for processing data. In at least one embodiment, computer system 900 may include a processor such as the Intel® processor 902 available from Intel Corporation of Santa Clara, California. Processor family, Xeon TM 、 XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessor, although other systems (including PCs with other microprocessors, engineering workstations, set-top boxes, etc.) may also be used. In at least one embodiment, computer system 900 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (e.g., UNIX and Linux), embedded software, and / or graphical user interfaces may also be used.

[0201] Embodiments may be used in other devices, such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol (IP) devices, digital cameras, personal digital assistants ("PDAs"), and handheld PCs. In at least one embodiment, the embedded application may include a microcontroller, a digital signal processor ("DSP"), a system on a chip, a network computer ("NetPC"), a set-top box, a network hub, a wide area network ("WAN") switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0202] In at least one embodiment, the computer system 900 may include, but is not limited to, a processor 902, which may include, but is not limited to, one or more execution units 908 to perform machine learning model training and / or reasoning according to the techniques described herein. In at least one embodiment, the system 9 is a single-processor desktop or server system, but in another embodiment, the system 9 may be a multi-processor system. In at least one embodiment, the processor 902 may include, but is not limited to, a complex instruction set computer ("CISC") microprocessor, a reduced instruction set computing ("RISC") microprocessor, a very long instruction word ("VLIW") microprocessor, a processor that implements a combination of instruction sets, or any other processor device, such as a digital signal processor. In at least one embodiment, the processor 902 may be coupled to a processor bus 910 that can transmit data signals between the processor 902 and other components in the computer system 900.

[0203] In at least one embodiment, processor 902 may include, but is not limited to, a level 1 ("L1") internal cache memory ("cache") 904. In at least one embodiment, processor 902 may have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory may reside external to processor 902. Other embodiments may include a combination of internal and external caches, depending on the specific implementation and requirements. In at least one embodiment, register file 906 may store different types of data in various registers, including, but not limited to, integer registers, floating point registers, status registers, and an instruction pointer register.

[0204] In at least one embodiment, an execution unit 908, including but not limited to logic for performing integer and floating-point operations, is also located within the processor 902. In at least one embodiment, the processor 902 may also include a microcode ("ucode") read-only memory ("ROM") for storing microcode for certain macroinstructions. In at least one embodiment, the execution unit 908 may include logic for processing a packed instruction set 909. In at least one embodiment, by including the packed instruction set 909 in the instruction set of a general-purpose processor, along with associated circuitry to execute the instructions, operations used by many multimedia applications may be performed using packed data within the general-purpose processor 902. In one or more embodiments, many multimedia applications may be accelerated and executed more efficiently by using the full width of the processor's data bus to perform operations on the packed data, which may eliminate the need to transfer smaller units of data across the processor's data bus to perform one or more operations one data element at a time.

[0205] In at least one embodiment, execution unit 908 may also be used in a microcontroller, an embedded processor, a graphics device, a DSP, or other types of logic circuits. In at least one embodiment, computer system 900 may include, but is not limited to, memory 920. In at least one embodiment, memory 920 may be implemented as a dynamic random access memory ("DRAM") device, a static random access memory ("SRAM") device, a flash memory device, or other storage device. In at least one embodiment, memory 920 may store instructions 919 and / or data 921 represented by data signals that may be executed by processor 902.

[0206] In at least one embodiment, a system logic chip can be coupled to the processor bus 910 and the memory 920. In at least one embodiment, the system logic chip can include, but is not limited to, a memory controller hub ("MCH") 916, and the processor 902 can communicate with the MCH 916 via the processor bus 910. In at least one embodiment, the MCH 916 can provide a high-bandwidth memory path 918 to the memory 920 for instruction and data storage, as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 916 can initiate data signals between the processor 902, the memory 920, and other components in the computer system 900, and bridge data signals between the processor bus 910, the memory 920, and the system I / O 922. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 916 may be coupled to the memory 920 via a high-bandwidth memory path 918 , and the graphics / video card 912 may be coupled to the MCH 916 via an Accelerated Graphics Port (“AGP”) interconnect 914 .

[0207] In at least one embodiment, the computer system 900 may use a system I / O 922, which is a proprietary hub interface bus, to couple the MCH 916 to an I / O controller hub ("ICH") 930. In at least one embodiment, the ICH 930 may provide a direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 920, the chipset, and the processor 902. Examples may include, but are not limited to, an audio controller 929, a firmware hub ("Flash BIOS") 928, a wireless transceiver 926, a data store 924, a traditional I / O controller 923 including a user input and keyboard interface, a serial expansion port 927 (e.g., a universal serial bus (USB)), and a network controller 934. In at least one embodiment, the data store 924 may include a hard drive, a floppy disk drive, a CD-ROM device, a flash memory device, or other mass storage device.

[0208] In at least one embodiment, Figure 9 The system is shown as comprising interconnected hardware devices or "chips", while in other embodiments, Figure 9 A system on a chip (SoC) may be shown. In at least one embodiment, Figure 9The devices shown in can be interconnected with a proprietary interconnect, a standardized interconnect (eg, PCIe), or some combination thereof. In at least one embodiment, one or more components of system 900 are interconnected using a Compute Express Link (CXL) interconnect.

[0209] In at least one embodiment, Figure 9 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, at least one of the processor 902 and the graphics card 912 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of a parallel processor. In at least one embodiment, at least one of the processor 902 and the graphics card 912 is configured to generate precoding weights in parallel using two or more processing threads by at least processing multiple matrices combined into memory locations. In at least one embodiment, at least one of the processor 902 and the graphics card 912 performs at least one aspect described with respect to the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600. In at least one embodiment, the processor 902 executes a kernel launch function to pass parameters to at least one kernel on the graphics card 912, which generates precoding weights in parallel.

[0210] Figure 10 1 is a block diagram illustrating an electronic device 1000 for utilizing a processor 1010 according to at least one embodiment. In at least one embodiment, the electronic device 1000 may be, for example, but not limited to, a notebook computer, a tower server, a rack server, a blade server, a laptop computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0211] In at least one embodiment, system 1000 may include, but is not limited to, a processor 1010 communicatively coupled to any suitable number or kind of components, peripherals, modules, or devices. In at least one embodiment, processor 1010 is coupled using a bus or interface, such as an I2C bus, a system management bus ("SMBus"), a low pin count (LPC) bus, a serial peripheral interface ("SPI"), a high-definition audio ("HDA") bus, a serial advanced technology attachment ("SATA") bus, a universal serial bus ("USB") (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter ("UART") bus. In at least one embodiment, Figure 10 shows a system comprising interconnected hardware devices or "chips", while in other embodiments, Figure 10 An exemplary system on a chip (SoC) may be shown. In at least one embodiment, Figure 10The devices shown in can be interconnected with proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 10 One or more components of the system are interconnected using Compute Express Link (CXL) interconnect lines.

[0212] In at least one embodiment, Figure 10 It may include a display 1024, a touch screen 1025, a touchpad 1030, a near field communication unit (“NFC”) 1045, a sensor hub 1040, a thermal sensor 1046, a fast chipset (“EC”) 1035, a trusted platform module (“TPM”) 1038, a BIOS / firmware / flash memory (“BIOS, FW Flash”) 1022, a DSP 1060, a drive “SSD or HDD” 1020 (e.g., a solid-state disk (“SSD”) or a hard disk drive (“HDD”)), a wireless local area network unit (“WLAN”) 1050, a Bluetooth unit 1052, a wireless wide area network unit (“WWAN”) 1056, a global positioning system (GPS) 1055, a camera (“USB 3.0 camera”) 1054 (e.g., a USB 3.0 camera), or a low-power double data rate (“LPDDR”) memory unit (“LPDDR3”) 1015 implemented with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0213] In at least one embodiment, other components may be communicatively coupled to processor 1010 via the components described above. In at least one embodiment, accelerometer 1041, ambient light sensor (“ALS”) 1042, compass 1043, and gyroscope 1044 may be communicatively coupled to sensor hub 1040. In at least one embodiment, thermal sensor 1039, fan 1037, keyboard 1046, and touchpad 1030 may be communicatively coupled to EC 1035. In at least one embodiment, speaker 1063, earphone 1064, and microphone (“mic”) 1065 may be communicatively coupled to audio unit (“audio codec and class-D amplifier”) 1064, which in turn may be communicatively coupled to DSP 1060. In at least one embodiment, audio unit 1064 may include, for example, but not limited to, an audio codec / decoder (“codec”) and a class-D amplifier. In at least one embodiment, SIM card (“SIM”) 1057 may be communicatively coupled to WWAN unit 1056. In at least one embodiment, components such as the WLAN unit 1050 and the Bluetooth unit 1052 and the WWAN unit 1056 may be implemented as a next generation form factor (NGFF).

[0214] In at least one embodiment, Figure 10 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, processor 1010 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, processor 1010 is configured to generate precoder weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, processor 1010 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0215] Figure 11 A computer system 1100 is shown in accordance with at least one embodiment. In at least one embodiment, the computer system 1100 is configured to implement the various processes and methods described throughout this disclosure.

[0216] In at least one embodiment, computer system 1100 includes, but is not limited to, at least one central processing unit ("CPU") 1102 connected to a communication bus 1110 implemented using any suitable protocol, such as PCI ("Peripheral Component Interconnect"), Peripheral Component Interconnect Express ("PCI-Express"), AGP ("Accelerated Graphics Port"), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1100 includes, but is not limited to, main memory 1104 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data may be stored in main memory 1104 in the form of random access memory ("RAM"). In at least one embodiment, a network interface subsystem ("network interface") 1122 provides an interface to other computing devices and networks for receiving data from computer system 1100 and transmitting data to other systems.

[0217] In at least one embodiment, computer system 1100 includes, but is not limited to, input device 1108, parallel processing system 1112, and display device 1106, which can be implemented using conventional cathode ray tubes ("CRTs"), liquid crystal displays ("LCDs"), light emitting diodes ("LEDs"), plasma displays, or other suitable display technologies. In at least one embodiment, user input is received from input device 1108 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each of the aforementioned modules can be located on a single semiconductor platform to form a processing system.

[0218] In at least one embodiment, Figure 11 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, at least one of the parallel processing system 1112 and the CPU 1102 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of the parallel processor. In at least one embodiment, at least one of the parallel processing system 1112 and the CPU 1102 is configured to generate precoder weights in parallel using two or more processing threads by at least processing multiple matrices combined into memory locations. In at least one embodiment, at least one of the parallel processing system 1112 and the CPU 1102 performs at least one aspect of the description regarding the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600. In at least one embodiment, the CPU 1102 executes a kernel launch function to pass parameters to at least one kernel on the PPU 1114, which generates precoder weights in parallel.

[0219] Figure 12 A computer system 1200 is shown in accordance with at least one embodiment. In at least one embodiment, computer system 1200 includes, but is not limited to, a computer 1210 and a USB stick 1220. In at least one embodiment, computer 1210 may include, but is not limited to, any number and type of processors (not shown) and memory (not shown). In at least one embodiment, computer 1210 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0220] In at least one embodiment, the USB stick 1220 includes, but is not limited to, a processing unit 1230, a USB interface 1240, and USB interface logic 1250. In at least one embodiment, the processing unit 1230 can be any instruction execution system, device, or device capable of executing instructions. In at least one embodiment, the processing unit 1230 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing core 1230 includes an application-specific integrated circuit ("ASIC") that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing core 1230 is a tensor processing unit ("TPC") that is optimized to perform machine learning inference operations. In at least one embodiment, the processing core 1230 is a vision processing unit ("VPU") that is optimized to perform machine vision and machine learning inference operations.

[0221] In at least one embodiment, USB interface 1240 can be any type of USB connector or USB receptacle. For example, in at least one embodiment, USB interface 1240 is a USB 3.0 Type-C receptacle for data and power. In at least one embodiment, USB interface 1240 is a USB 3.0 Type-A connector. In at least one embodiment, USB interface logic 1250 can include any number and type of logic that enables processing unit 1230 to connect to a device (e.g., computer 1210) via USB connector 1240.

[0222] In at least one embodiment, Figure 12 At least one component shown or described is used to implement the combination Figure 1-6 The techniques and / or functionality described herein are described herein. In at least one embodiment, computer 1210 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, computer 1210 is configured to generate precoder weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, computer 1210 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0223] Figure 13A An exemplary architecture is shown in which multiple GPUs 1310-1313 are communicatively coupled to multiple multi-core processors 1305-1306 via high-speed links 1340-1343 (e.g., buses / point-to-point interconnects, etc.). In one embodiment, high-speed links 1340-1343 support communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. Various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0.

[0224] Furthermore, in one embodiment, two or more GPUs 1310-1313 are interconnected via high-speed links 1329-1330, which may be implemented using the same or different protocols / links as used for high-speed links 1340-1343. Similarly, two or more multi-core processors 1305-1306 may be connected via high-speed link 1328, which may be a symmetric multiprocessor (SMP) bus running at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, the same protocol / links may be used (e.g., via a common interconnect fabric). Figure 13A All communications between the various system components shown in .

[0225] In one embodiment, each multi-core processor 1305-1306 is communicatively coupled to processor memory 1301-1302 via memory interconnects 1326-1327, respectively, and each GPU 1310-1313 is communicatively coupled to GPU memory 1320-1323 via GPU memory interconnects 1350-1353, respectively. Memory interconnects 1326-1327 and 1350-1353 can utilize the same or different memory access technologies. By way of example and not limitation, processor memory 1301-1302 and GPU memory 1320-1323 can be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, some portion of the processor memory 1301-1302 may be volatile memory, while another portion may be non-volatile memory (eg, using a two-level memory (2LM) hierarchy).

[0226] As described herein, although the various processors 1305-1306 and GPUs 1310-1313 may each be physically coupled to a specific memory 1301-1302, 1320-1323, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across the various physical memories. For example, the processor memories 1301-1302 may each contain 64GB of system memory address space, and the GPU memories 1320-1323 may each contain 32GB of system memory address space (resulting in a total addressable memory size of 256GB in this example).

[0227] Figure 13B 13. Additional details are shown for the interconnection between multi-core processor 1307 and graphics acceleration module 1346 according to an exemplary embodiment. Graphics acceleration module 1346 may include one or more GPU chips integrated on a line card that is coupled to processor 1307 via high-speed link 1340. Alternatively, graphics acceleration module 1346 may be integrated on the same package or chip as processor 1307.

[0228] In at least one embodiment, the illustrated processor 1307 includes a plurality of cores 1360A-1360D, each having a translation lookaside buffer 1361A-1361D and one or more caches 1362A-1362D. In at least one embodiment, cores 1360A-1360D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, caches 1362A-1362D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 1356 may be included in caches 1362A-1362D and shared by each group of cores 1360A-1360D. For example, one embodiment of processor 1307 includes 24 cores, each having its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. The processor 1307 and the graphics acceleration module 1346 are connected to the system memory 1314, which may include Figure 13A Processor memory 1301-1302 in.

[0229] Coherence is maintained for data and instructions stored in the various caches 1362A-1362D, 1356, and system memory 1314 via inter-core communication over a coherence bus 1364. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 1364 in response to detecting a read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 1364 to snoop cache accesses.

[0230] In one embodiment, proxy circuitry 1325 communicatively couples graphics acceleration module 1346 to coherence bus 1364, thereby allowing graphics acceleration module 1346 to participate in a cache coherence protocol as a peer of cores 1360A-1360D. In particular, in at least one embodiment, interface 1335 provides connectivity to proxy circuitry 1325 via high-speed link 1340 (e.g., a PCIe bus, NVLink, etc.), and interface 1337 connects graphics acceleration module 1346 to link 1340.

[0231] In one implementation, the accelerator integrated circuit 1336 provides cache management, memory access, context management, and interrupt management services on behalf of the graphics acceleration module's multiple graphics processing engines 1331, 1332, N. The graphics processing engines 1331, 1332, N may each comprise a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 1331, 1332, N may selectively comprise different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In at least one embodiment, the graphics acceleration module 1346 may be a GPU having multiple graphics processing engines 1331-1332, N, or the graphics processing engines 1331-1332, N may be individual GPUs integrated into a common package, line card, or chip.

[0232] In one embodiment, the accelerator integrated circuit 1336 includes a memory management unit (MMU) 1339 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and a memory access protocol for accessing system memory 1314. The MMU 1339 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective-to-physical / real address translations. In one implementation, cache 1338 may store commands and data for efficient access by graphics processing engines 1331-1332, N. In at least one embodiment, data stored in cache 1338 and graphics memory 1333-1334, M is maintained coherently with core caches 1362A-1362D, 1356, and system memory 1314. As previously described, this task may be accomplished via proxy circuitry 1325 acting on behalf of cache 1338 and graphics memory 1333-1334, M (e.g., sending updates related to modifications / accesses of cache lines on processor caches 1362A-1362D, 1356 to cache 1338 and receiving updates from cache 1338).

[0233] A set of registers 1345 stores context data for threads executed by graphics processing engines 1331, 1332, N, and context management circuitry 1348 manages thread contexts. For example, context management circuitry 1348 can perform save and restore operations to save and restore the context of each thread during a context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, context management circuitry 1348 can store current register values ​​to a designated area in memory (e.g., identified by a context pointer) upon a context switch. The register values ​​can then be restored upon returning to the context. In one embodiment, interrupt management circuitry 1347 receives and processes interrupts received from system devices.

[0234] In one implementation, the MMU 1339 converts virtual / effective addresses from the graphics processing engine 1331 into real / physical addresses in the system memory 1314. One embodiment of the accelerator integrated circuit 1336 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1346 and / or other accelerator devices. The graphics accelerator module 1346 can be dedicated to a single application executing on the processor 1307, or can be shared among multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 1331-1332, N are shared with multiple applications or virtual machines (VMs). In at least one embodiment, the resources can be subdivided into "slices" that are allocated to different VMs and / or applications based on processing requirements and priorities associated with the VMs and / or applications.

[0235] In at least one embodiment, accelerator integrated circuit 1336 acts as a bridge to the system for graphics acceleration module 1346 and provides address translation and system memory caching services. Additionally, accelerator integrated circuit 1336 can provide virtualization facilities to the host processor to manage virtualization, interrupts, and memory management for graphics processing engines 1331-1332.

[0236] Because the hardware resources of graphics processing engines 1331-1332, N are explicitly mapped into the real address space seen by host processor 1307, any host processor can directly address these resources using effective address values. In at least one embodiment, one function of accelerator integrated circuit 1336 is to physically separate graphics processing engines 1331-1332, N so that they appear as independent units to the system.

[0237] In at least one embodiment, one or more graphics memories 1333-1334, M are respectively coupled to each graphics processing engine 1331-1332, N. Graphics memories 1333-1334, M store instructions and data, which are processed by each graphics processing engine 1331-1332, N. Graphics memories 1333-1334, M can be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0238] In one embodiment, to reduce data traffic on link 1340, a biasing technique can be used to ensure that the data stored in graphics memories 1333-1334, M is the data most frequently used by graphics processing engines 1331-1332, N, and preferably is not used (at least not frequently) by cores 1360A-1360D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep data needed by the cores (and preferably not graphics processing engines 1331-1332, N) in the cores' caches 1362A-1362D, 1356 and system memory 1314.

[0239] Figure 13C Another exemplary embodiment is shown in which an accelerator integrated circuit 1336 is integrated into the processor 1307. In this embodiment, the graphics processing engines 1331-1332, N communicate directly with the accelerator integrated circuit 1336 via the interface 1337 and the interface 1335 (which may also utilize any form of bus or interface protocol) through the high-speed link 1340. The accelerator integrated circuit 1336 can perform operations related to Figure 13B The operations described above are identical to those described above. However, due to its close proximity to the coherence bus 1364 and caches 1362A-1362D, 1356, higher throughput is possible. One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), which can include a programming model controlled by the accelerator integrated circuit 1336 and a programming model controlled by the graphics acceleration module 1346.

[0240] In at least one embodiment, graphics processing engines 1331-1332, N are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1331-1332, N, thereby providing virtualization within a VM / partition.

[0241] In at least one embodiment, graphics processing engines 1331-1332, N can be shared by multiple VM / application partitions. In at least one embodiment, the sharing model can utilize a hypervisor to virtualize graphics processing engines 1331-1332, N, allowing each operating system to access them. For a single-partition system without a hypervisor, the operating system owns graphics processing engines 1331-1332, N. In at least one embodiment, the operating system can virtualize graphics processing engines 1331-1332, N to provide access to each process or application.

[0242] In at least one embodiment, the graphics acceleration module 1346 or individual graphics processing engines 1331-1332,N use a process handle to select a process element. In one embodiment, the process element is stored in the system memory 1314 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engine 1331-1332,N (i.e., calling system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0243] Figure 13D An exemplary accelerator integrated slice 1390 is shown. As used herein, a "slice" comprises a designated portion of the processing resources of an accelerator integrated circuit 1336. An application is an effective address space 1382 in system memory 1314, which stores process elements 1383. In one embodiment, process elements 1383 are stored in response to GPU calls 1381 from application 1380 executing on processor 1307. Process elements 1383 contain the process state of the corresponding application 1380. A work descriptor (WD) 1384 contained in process element 1383 can be a single job requested by the application, or can contain a pointer to a job queue. In at least one embodiment, WD 1384 is a pointer to a job request queue in the application's address space 1382.

[0244] The graphics acceleration module 1346 and / or the individual graphics processing engines 1331-1332, N can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure for setting process state and sending WD 1384 to the graphics acceleration module 1346 to start a job in a virtualized environment can be included.

[0245] In at least one embodiment, a dedicated process programming model is implementation-specific. In this model, a single process owns either a graphics acceleration module 1346 or an individual graphics processing engine 1331. Since the hypervisor initializes the accelerator integrated circuit for the owning partition when the graphics acceleration module 1346 is owned by a single process, the operating system initializes the accelerator integrated circuit 1336 for the owning process when the graphics acceleration module 1346 is assigned.

[0246] In operation, the WD fetch unit 1391 in the accelerator integrated slice 1390 fetches the next WD 1384, which includes an indication of work to be completed by one or more graphics processing engines in the graphics acceleration module 1346. Data from WD 1384 may be stored in registers 1345 and used by the MMU 1339, interrupt management circuitry 1347, and / or context management circuitry 1348, as shown. For example, one embodiment of the MMU 1339 includes segment / page roaming circuitry for accessing segment / page tables 1386 within the OS virtual address space 1385. The interrupt management circuitry 1347 may process interrupt events 1392 received from the graphics acceleration module 1346. When executing graphics operations, effective addresses 1393 generated by the graphics processing engines 1331-1332, N are converted into real addresses by the MMU 1339.

[0247] In one embodiment, the same set of registers 1345 is replicated for each graphics processing engine 1331-1332, N, and / or graphics acceleration module 1346, and the registers 1345 can be initialized by the hypervisor or operating system. Each of these replicated registers can be included in the accelerator integration slice 1390. Example registers that can be initialized by the hypervisor are shown in Table 1.

[0248]

[0249]

[0250] Example registers that may be initialized by the operating system are shown in Table 2.

[0251]

[0252] In one embodiment, each WD 1384 is specific to a particular graphics acceleration module 1346 and / or graphics processing engine 1331-1332, N. It contains all the information needed for the graphics processing engine 1331-1332, N to complete the work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0253] Figure 13E 1396 , which virtualizes the graphics acceleration module engine for the operating system 1395 .

[0254] In at least one embodiment, the shared programming model allows all processes or a subset of processes from all partitions or a subset of partitions in the system to use the graphics acceleration module 1346. There are two programming models where the graphics acceleration module 1346 is shared by multiple processes and partitions: time-sliced ​​sharing and graphics-directed sharing.

[0255] In this model, the hypervisor 1396 owns the graphics acceleration module 1346 and makes its functionality available to all operating systems 1395. For the graphics acceleration module 1346 to support virtualization through the hypervisor 1396, the graphics acceleration module 1346 may adhere to the following: (1) the application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 1346 must provide a context save and restore mechanism, (2) the graphics acceleration module 1346 guarantees that the application's job requests are completed within a specified amount of time, including any transition errors, or the graphics acceleration module 1346 provides the ability to preempt job processing, and (3) fairness between graphics acceleration module 1346 processes must be ensured when operating in a directed shared programming model.

[0256] In at least one embodiment, an application 1380 is required to make an operating system 1395 system call using a graphics acceleration module 1346 type, a work descriptor (WD), an authority mask register (AMR) value, and a context save / restore region pointer (CSRP). In at least one embodiment, the graphics acceleration module 1346 type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module 1346 type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1346 and can take the form of a graphics acceleration module 1346 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure describing work to be performed by the graphics acceleration module 1346. In one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to that of an application setting the AMR. If the implementation of the accelerator integrated circuit 1336 and graphics acceleration module 1346 does not support the User Authority Mask Override Register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in the hypervisor call. Hypervisor 1396 can optionally apply the current privilege mask overwrite register (AMOR) value before placing the AMR into process element 1383. In at least one embodiment, CSRP is one of registers 1345 that contains the effective address of an area in the application's address space 1382 for graphics acceleration module 1346 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be fixed system memory.

[0257] Upon receiving the system call, the operating system 1395 may verify that the application 1380 has been registered and granted permission to use the graphics acceleration module 1346. The operating system 1395 then calls the hypervisor 1396 using the information shown in Table 3.

[0258]

[0259] Upon receiving the hypervisor call, the hypervisor 1396 verifies that the operating system 1395 has registered and been granted permission to use the graphics acceleration module 1346. The hypervisor 1396 then places the process element 1383 into a linked list of process elements of the corresponding graphics acceleration module 1346 type. The process element may include the information shown in Table 4.

[0260]

[0261] In at least one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 1390 registers 1345 .

[0262] like Figure 13F As shown, in at least one embodiment, a unified memory is used that is addressable via a common virtual memory address space for accessing physical processor memories 1301-1302 and GPU memories 1320-1323. In this implementation, operations executed on GPUs 1310-1313 utilize the same virtual / effective memory address space to access processor memories 1301-1302, and vice versa, thereby simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1301, a second portion is allocated to second processor memory 1302, a third portion is allocated to GPU memory 1320, and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1301-1302 and GPU memories 1320-1323, thereby allowing any processor or GPU to access that memory using a virtual address mapped to any physical memory.

[0263] In one embodiment, bias / coherency management circuitry 1394A-1394E within one or more MMUs 1339A-1339E ensures cache coherency between the caches of one or more host processors (e.g., 1305) and GPUs 1310-1313 and implements biasing techniques that indicate the physical memory where certain types of data should be stored. Figure 13F Multiple instances of bias / coherence management circuits 1394A- 1394E are shown in , but bias / coherence circuits may be implemented within an MMU of one or more host processors 1305 and / or within an accelerator integrated circuit 1336 .

[0264] One embodiment allows GPU attached memory 1320-1323 to be mapped as part of system memory and accessed using shared virtual memory (SVM) technology, but without suffering the performance drawbacks associated with full system cache coherence. In at least one embodiment, the ability to access GPU attached memory 1320-1323 as system memory without the heavy cache coherence overhead provides a favorable operating environment for GPU offloading. This arrangement allows software of the host processor 1305 to set operands and access calculation results without the overhead of traditional I / O DMA data copies. Such traditional copies include driver calls, interrupts, and memory mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access GPU attached memory 1320-1323 without cache coherence overhead can be critical to the execution time of offloaded calculations. For example, in situations with large amounts of streaming write memory traffic, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPUs 1310-1313. In at least one embodiment, efficiency of operand setup, efficiency of result access, and efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0265] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. For example, a bias table can be used, which can be a page-granular structure (e.g., controlled at the granularity of a memory page) that includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in GPUs 1310-1313 (e.g., to cache frequently / recently used entries in the bias table), the bias table can be implemented in the stolen memory range of one or more GPU-attached memories 1320-1323. Alternatively, the entire bias table can be maintained within the GPU.

[0266] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU-attached memory 1320-1323 is accessed, resulting in the following operations. First, local requests from GPUs 1310-1313 whose pages are found in the GPU bias are forwarded directly to the corresponding GPU memory 1320-1323. Local requests from the GPU whose pages are found in the host bias are forwarded to processor 1305 (e.g., via a high-speed link as described above). In one embodiment, requests from processor 1305 that find the requested page in the host processor bias complete a request similar to a normal memory read. Alternatively, requests directed to GPU biased pages can be forwarded to GPUs 1310-1313. In at least one embodiment, if the GPU is not currently using the page, the GPU can subsequently migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed via a software-based mechanism, a hardware-assisted software-based mechanism, or, in limited cases, a purely hardware-based mechanism.

[0267] One mechanism for changing the bias state employs an API call (e.g., OpenCL) that in turn calls the GPU's device driver, which in turn sends a message (or queues a command descriptor) to the GPU, directing the GPU to change the bias state and, in some migrations, to perform a cache flush operation in the host. In at least one embodiment, the cache flush operation is used for migrations from host processor 1305 bias to GPU bias, but not for the reverse migration.

[0268] In one embodiment, cache coherence is maintained by temporarily rendering GPU-biased pages that cannot be cached by host processor 1305. To access these pages, processor 1305 may request access from GPU 1310, which may or may not immediately grant access. Therefore, to reduce communication between processor 1305 and GPU 1310, it is beneficial to ensure that GPU-biased pages are the pages required by the GPU and not the host processor 1305, and vice versa.

[0269] One or more hardware structures are used to implement one or more embodiments.

[0270] In at least one embodiment, Figure 13A -F At least one component shown or described is used to achieve the combination Figure 1-6In at least one embodiment, at least one GPU and / or multi-core processor shown or described with respect to Figures 13A-F is used to perform precoding (e.g., generate precoding weights) in parallel by multiple threads of a parallel processor. In at least one embodiment, at least one GPU (e.g., 1310, 1311, 1312, and / or 1313) is used to generate precoder weights in parallel with two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, with respect to Figure 13A At least one GPU and / or multi-core processor shown or described in FIG. 13 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600. In at least one embodiment, a multi-core processor (e.g., multi-core processor 1305) executes a kernel launch function to pass parameters to at least one kernel on a graphics processor (e.g., GPU 1310), and the at least one kernel generates precoder weights in parallel.

[0271] Figure 14 An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuitry may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0272] Figure 14is a block diagram illustrating an exemplary system on a chip integrated circuit 1400 that can be fabricated using one or more IP cores according to at least one embodiment. In at least one embodiment, integrated circuit 1400 includes one or more application processors 1405 (e.g., CPUs), at least one graphics processor 1410, and may additionally include an image processor 1415 and / or a video processor 1420, any of which may be modular IP cores. In at least one embodiment, integrated circuit 1400 includes peripheral or bus logic, including a USB controller 1425, a UART controller 1430, an SPI / SDIO controller 1435, and an I.sup.2S / I.sup.2C controller 1440. In at least one embodiment, integrated circuit 1400 may include a display device 1445 coupled to one or more of a High-Definition Multimedia Interface (HDMI) controller 1450 and a Mobile Industry Processor Interface (MIPI) display interface 1455. In at least one embodiment, storage may be provided by a flash memory subsystem 1460, including flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1465 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1470 .

[0273] In at least one embodiment, Figure 14 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, the graphics processor 1410 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, the graphics processor 1410 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, the graphics processor 1410 performs at least one aspect described with respect to the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0274] Figure 15A and Figure 15B An exemplary integrated circuit and associated graphics processor according to various embodiments described herein are shown, which can be manufactured using one or more IP cores. In addition to the illustrations, other logic and circuits may be included in at least one embodiment, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0275] Figure 15A and Figure 15Bis a block diagram illustrating an exemplary graphics processor for use within a SoC according to embodiments described herein. Figure 15A An exemplary graphics processor 1510 of a system-on-chip integrated circuit that can be fabricated using one or more IP cores in accordance with at least one embodiment is shown. Figure 15B Another exemplary graphics processor 1540 of a system-on-chip integrated circuit is shown, which may be manufactured using one or more IP cores, in accordance with at least one embodiment. Figure 15A The graphics processor 1510 is a low power graphics processor core. In at least one embodiment, Figure 15B The graphics processor 1540 is a higher performance graphics processor core. In at least one embodiment, each graphics processor 1510, 1540 can be Figure 14 A variant of the graphics processor 1410.

[0276] In at least one embodiment, the graphics processor 1510 includes a vertex processor 1505 and one or more fragment processors 1515A-1515N (e.g., 1515A, 1515B, 1515C, 1515D through 1515N-1 and 1515N). In at least one embodiment, the graphics processor 1510 can execute different shader programs via separate logic, such that the vertex processor 1505 is optimized to perform operations for the vertex shader program, while the one or more fragment processors 1515A-1515N perform fragment (e.g., pixel) shading operations for the fragment or pixel or shader program. In at least one embodiment, the vertex processor 1505 performs the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1515A-1515N use the primitives and vertex data generated by the vertex processor 1505 to generate a frame buffer for display on a display device. In at least one embodiment, one or more fragment processors 1515A-1515N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform similar operations as pixel shader programs provided in the Direct 3D API.

[0277] In at least one embodiment, graphics processor 1510 additionally includes one or more memory management units (MMUs) 1520A-1520B, one or more caches 1525A-1525B, and one or more circuit interconnects 1530A-1530B. In at least one embodiment, one or more MMUs 1520A-1520B provide virtual-to-physical address mapping for graphics processor 1510, including for vertex processor 1505 and / or fragment processors 1515A-1515N, which may reference vertex or image / texture data stored in memory, in addition to vertex or image / texture data stored in one or more caches 1525A-1525B. In at least one embodiment, one or more MMUs 1520A-1520B may synchronize with other MMUs within the system, including with other MMUs. Figure 14 One or more MMUs associated with one or more application processors 1405, graphics processor 1415, and / or video processor 1420 enable each processor 1405-1420 to participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1530A-1530B enable graphics processor 1510 to connect to other IP cores within the SoC via an internal bus of the SoC or via a direct connection.

[0278] In at least one embodiment, graphics processor 1540 includes Figure 15A 1520B, caches 1525A-1525B, and circuit interconnects 1530A-1530B of the graphics processor 1510. In at least one embodiment, the graphics processor 1540 includes one or more shader cores 1555A-1555N (e.g., 1555A, 1555B, 1555C, 1555D, 1555E, 1555F through 1555N-1 and 1555N) that provide a unified shader core architecture where a single core or type or core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1540 includes an inter-core task manager 1545 that acts as a thread dispatcher to dispatch execution threads to one or more shader cores 1555A-1555N and a tiling unit 1558 to accelerate tile-based rendering operations in which rendering operations of a scene are subdivided in image space, for example, to exploit local spatial coherence within a scene or to optimize the use of internal caches.

[0279] In at least one embodiment, Figure 15A and Figure 15B At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, at least one graphics processor 1510 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, at least one graphics processor 1510 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, at least one graphics processor 1510 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0280] Figure 16A and Figure 16B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, Figure 16A Shows that can be included in Figure 14 Graphics core 1600 within graphics processor 1410 of FIG. 1 and, in at least one embodiment, may be such as Figure 15B Unified shader cores 1555A-1555N are shown. Figure 16B A highly parallel, general-purpose graphics processing unit 1630 suitable for deployment on a multi-chip module in at least one embodiment is shown.

[0281] In at least one embodiment, graphics core 1600 includes a shared instruction cache 1602, texture units 1618, and cache / shared memory 1620, which are common to execution resources within graphics core 1600. In at least one embodiment, graphics core 1600 may include multiple slices 1601A-1601N, or partitions of each core, and a graphics processor may include multiple instances of graphics core 1600. Slices 1601A-1601N may include support logic including local instruction caches 1604A-1604N, thread schedulers 1606A-1606N, thread dispatchers 1608A-1608N, and a set of registers 1610A-1610N. In at least one embodiment, slices 1601A-1601N may include a set of additional function units (AFUs 1612A-1612N), floating point units (FPUs 1614A-1614N), integer arithmetic logic units (ALUs 1616A-1616N), address calculation units (ACUs 1613A-1613N), double precision floating point units (DPFPUs 1615A-1615N), and matrix processing units (MPUs 1617A-1617N).

[0282] In at least one embodiment, FPUs 1614A-1614N can perform single-precision (32-bit) and half-precision (16-bit) floating-point operations, while DPFPUs 1615A-1615N perform double-precision (64-bit) floating-point operations. In at least one embodiment, ALUs 1616A-1616N can perform variable-precision integer operations with 8-bit, 16-bit, and 32-bit precision and can be configured for mixed-precision operations. In at least one embodiment, MPUs 1617A-1617N can also be configured for mixed-precision matrix operations, including half-precision floating-point operations and 8-bit integer operations. In at least one embodiment, MPUs 1617-1617N can perform various matrix operations to accelerate machine learning application frameworks, including enabling support for accelerated general matrix-matrix multiplication (GEMM). In at least one embodiment, AFUs 1612A-1612N can perform additional logical operations not supported by floating-point or integer units, including trigonometric operations (e.g., sine, cosine, etc.).

[0283] In at least one embodiment, Figure 16A At least one component shown or described is used to implement the combination Figure 1-6In at least one embodiment, at least one graphics processor 1600 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, at least one graphics processor 1600 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, at least one graphics processor 1600 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0284] Figure 16B A general-purpose processing unit (GPGPU) 1630 is shown in at least one embodiment. It can be configured to enable highly parallel computational operations to be performed by a group of graphics processing units. In at least one embodiment, GPGPU 1630 can be directly linked to other instances of GPGPU 1630 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, GPGPU 1630 includes a host interface 1632 to enable connection to a host processor. In at least one embodiment, host interface 1632 is a PCI Express interface. In at least one embodiment, host interface 1632 can be a vendor-specific communication interface or communication structure. In at least one embodiment, GPGPU 1630 receives commands from the host processor and uses a global scheduler 1634 to assign execution threads associated with those commands to a group of compute clusters 1636A-1636H. In at least one embodiment, compute clusters 1636A-1636H share a cache memory 1638. In at least one embodiment, cache memory 1638 may be used as a higher level cache for cache memory within compute clusters 1636A-1636H.

[0285] In at least one embodiment, GPGPU 1630 includes memory 1644A-1644B coupled to compute clusters 1636A-1636H via a set of memory controllers 1642A-1642B. In at least one embodiment, memory 1644A-1644B may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory.

[0286] In at least one embodiment, computing clusters 1636A-1636H each include a set of graphics cores, e.g. Figure 16AThe graphics core 1600 may include multiple types of integer and floating-point logic units that can perform computational operations at various precision ranges, including precision suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1636A-1636H may be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units may be configured to perform 64-bit floating-point operations.

[0287] In at least one embodiment, multiple instances of GPGPU 1630 can be configured to function as a compute cluster. In at least one embodiment, the communications used by compute clusters 1636A-1636H for synchronization and data exchange vary between embodiments. In at least one embodiment, multiple instances of GPGPU 1630 communicate via host interface 1632. In at least one embodiment, GPGPU 1630 includes an I / O hub 1639 that couples GPGPU 1630 to GPU link 1640, enabling direct connections to other instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of GPGPU 1630. In at least one embodiment, GPU link 1640 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of GPGPU 1630 reside in separate data processing systems and communicate via a network device accessible through host interface 1632. In at least one embodiment, GPU link 1640 may be configured to enable connection to a host processor in addition to or as an alternative to host interface 1632 .

[0288] In at least one embodiment, GPGPU 1630 can be configured to train neural networks. In at least one embodiment, GPGPU 1630 can be used within an inference platform. In at least one embodiment, where GPGPU 1630 is used for inference, the GPGPU can include fewer compute clusters 1636A-1636H than when the GPGPU is used to train a neural network. In at least one embodiment, the memory technology associated with memory 1644A-1644B can differ between the inference and training configurations, with higher-bandwidth memory technology being dedicated to the training configuration. In at least one embodiment, the inference configuration of GPGPU 1630 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions, which can be used during inference operations of a deployed neural network.

[0289] In at least one embodiment, Figure 16B At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, at least one GPGPU 1630 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, at least one GPGPU 1630 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, at least one GPGPU 1630 performs at least one aspect of the description of distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0290] Figure 17 A block diagram of a computer system 1700 is shown, according to at least one embodiment. In at least one embodiment, computer system 1700 includes a processing subsystem 1701 having one or more processors 1702 and a system memory 1704, which communicates via an interconnect path that may include a memory hub 1705. In at least one embodiment, memory hub 1705 may be a separate component within a chipset assembly or may be integrated within one or more processors 1702. In at least one embodiment, memory hub 1705 is coupled to an I / O subsystem 1711 via a communication link 1706. In one embodiment, I / O subsystem 1711 includes an I / O hub 1707, which enables computer system 1700 to receive input from one or more input devices 1708. In at least one embodiment, I / O hub 1707 enables a display controller, which may be included in one or more processors 1702, to provide output to one or more display devices 1710A. In at least one embodiment, the one or more display devices 1710A coupled to the I / O hub 1707 may include local, internal, or embedded display devices.

[0291] In at least one embodiment, the processing subsystem 1701 includes one or more parallel processors 1712 coupled to the memory hub 1705 via a bus or other communication link 1713. In at least one embodiment, the communication link 1713 can be any of a number of standards-based communication link technologies or protocols, such as, but not limited to, PCI Express, or can be a vendor-specific communication interface or communication structure. In at least one embodiment, the one or more parallel processors 1712 form a computationally focused parallel or vector processing system, which can include a large number of processing cores and / or processing clusters, such as a multi-integrated core (MIC) processor. In at least one embodiment, the one or more parallel processors 1712 form a graphics processing subsystem that can output pixels to one of one or more display devices 1710A coupled via the I / O hub 1707. In at least one embodiment, the one or more parallel processors 1712 can also include a display controller and display interface (not shown) to enable direct connection to the one or more display devices 1710B.

[0292] In at least one embodiment, a system storage unit 1714 can be connected to the I / O hub 1707 to provide a storage mechanism for the computer system 1700. In at least one embodiment, an I / O switch 1716 can be used to provide an interface mechanism to enable connections between the I / O hub 1707 and other components, such as a network adapter 1718 and / or a wireless network adapter 1717 that can be integrated into the platform, as well as various other devices that can be added via one or more add-in devices 1720. In at least one embodiment, the network adapter 1718 can be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1719 can include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0293] In at least one embodiment, computer system 1700 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, etc., which may also be connected to I / O hub 1707. In at least one embodiment, interconnection may be achieved using any suitable protocol, such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol. Figure 17 Communication paths for various components in a chip, such as NV-Link high-speed interconnect or interconnect protocol.

[0294] In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for graphics and video processing, including, for example, video output circuitry, and constitute a graphics processing unit (GPU). In at least one embodiment, one or more parallel processors 1712 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of computer system 1700 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1712, memory hub 1705, processor 1702, and I / O hub 1707 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of computer system 1700 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of computer system 1700 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules to form a modular computer system.

[0295] In at least one embodiment, Figure 17 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, at least one of processor 1702 and parallel processor 1712 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of the parallel processor. In at least one embodiment, at least one of processor 1702 and parallel processor 1712 is configured to generate precoder weights in parallel using two or more processing threads by processing at least a plurality of matrices combined into a memory location. In at least one embodiment, at least one of processor 1702 and parallel processor 1712 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600. In at least one embodiment, processor 1702 executes a kernel launch function that passes parameters to at least one kernel on at least one parallel processor 1712, and the at least one kernel generates precoder weights in parallel.

[0296] processor

[0297] Figure 18A 1800 is shown in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 1800 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). In at least one embodiment, the parallel processor 1800 is shown in accordance with an exemplary embodiment. Figure 17A variation of the one or more parallel processors 1712 is shown.

[0298] In at least one embodiment, parallel processor 1800 includes parallel processing unit 1802. In at least one embodiment, parallel processing unit 1802 includes an I / O unit 1804 that enables communication with other devices, including other instances of parallel processing unit 1802. In at least one embodiment, I / O unit 1804 can be directly connected to other devices. In at least one embodiment, I / O unit 1804 connects to other devices using a hub or switch interface (e.g., memory hub 1705). In at least one embodiment, the connection between memory hub 1705 and I / O unit 1804 forms communication link 1713. In at least one embodiment, I / O unit 1804 is connected to a host interface 1806 and a memory crossbar switch 1816, where host interface 1806 receives commands for performing processing operations, and memory crossbar switch 1816 receives commands for performing memory operations.

[0299] In at least one embodiment, when host interface 1806 receives command buffers via I / O unit 1804, host interface 1806 can direct work operations to execute those commands to front end 1808. In at least one embodiment, front end 1808 is coupled to scheduler 1810, which is configured to distribute commands or other work items to processing cluster array 1812. In at least one embodiment, scheduler 1810 ensures that processing cluster array 1812 is properly configured and in a valid state before distributing tasks to processing cluster array 1812. In at least one embodiment, scheduler 1810 is implemented via firmware logic executing on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 1810 can be configured to perform complex scheduling and work distribution operations at both coarse and fine granularity, thereby enabling fast preemption and context switching of threads executing on processing array 1812. In at least one embodiment, host software can authenticate workloads for scheduling on processing array 1812 through one of multiple graphics processing doorbells. In at least one embodiment, the workload may then be automatically distributed across the processing array 1812 by scheduler 1810 logic within a microcontroller that includes scheduler 1810 .

[0300] In at least one embodiment, processing cluster array 1812 may include up to "N" processing clusters (e.g., cluster 1814A, cluster 1814B, through cluster 1814N). In at least one embodiment, each cluster 1814A-1814N of processing cluster array 1812 may execute a large number of concurrent threads. In at least one embodiment, scheduler 1810 may allocate work to clusters 1814A-1814N of processing cluster array 1812 using various scheduling and / or work distribution algorithms, which may vary depending on the workload generated by each program or computation type. In at least one embodiment, scheduling may be handled dynamically by scheduler 1810 or may be assisted in part by compiler logic during the compilation of program logic configured to be executed by processing cluster array 1812. In at least one embodiment, different clusters 1814A-1814N of processing cluster array 1812 may be assigned to process different types of programs or to perform different types of computations.

[0301] In at least one embodiment, processing cluster array 1812 can be configured to perform various types of parallel processing operations. In at least one embodiment, processing cluster array 1812 can be configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, processing cluster array 1812 can include logic to perform processing tasks including filtering video and / or audio data, performing modeling operations including physics operations, and performing data transformations.

[0302] In at least one embodiment, processing cluster array 1812 is configured to perform parallel graphics processing operations. In at least one embodiment, processing cluster array 1812 may include additional logic to support the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, as well as tessellation logic and other vertex processing logic. In at least one embodiment, processing cluster array 1812 may be configured to execute shader programs related to graphics processing, such as, but not limited to, vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, parallel processing units 1802 may transfer data from system memory via I / O units 1804 for processing. In at least one embodiment, during processing, the transferred data may be stored in on-chip memory (e.g., parallel processor memory 1822) and then written back to system memory.

[0303] In at least one embodiment, when parallel processing unit 1802 is used to perform graphics processing, scheduler 1810 can be configured to divide the processing workload into tasks of approximately equal size to better distribute graphics processing operations to multiple clusters 1814A-1814N of processing cluster array 1812. In at least one embodiment, portions of processing cluster array 1812 can be configured to perform different types of processing. For example, in at least one embodiment, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen-space operations to generate a rendered image for display. In at least one embodiment, intermediate data generated by one or more of clusters 1814A-1814N can be stored in a buffer to allow the intermediate data to be transferred between clusters 1814A-1814N for further processing.

[0304] In at least one embodiment, processing cluster array 1812 can receive processing tasks to be executed via scheduler 1810, which receives commands defining the processing tasks from front end 1808. In at least one embodiment, a processing task can include an index of data to be processed, such as surface (patch) data, primitive data, vertex data, and / or pixel data, as well as state parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, scheduler 1810 can be configured to obtain an index corresponding to a task, or can receive the index from front end 1808. In at least one embodiment, front end 1808 can be configured to ensure that processing cluster array 1812 is configured in a valid state before starting a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0305] In at least one embodiment, each of one or more instances of parallel processing unit 1802 can be coupled to parallel processor memory 1822. In at least one embodiment, parallel processor memory 1822 can be accessed via memory crossbar 1816, which can receive memory requests from processing cluster array 1812 and I / O unit 1804. In at least one embodiment, memory crossbar 1816 can access parallel processor memory 1822 via memory interface 1818. In at least one embodiment, memory interface 1818 can include a plurality of partition units (e.g., partition unit 1820A, partition unit 1820B, through partition unit 1820N), each of which can be coupled to a portion of parallel processor memory 1822 (e.g., a memory unit). In at least one embodiment, the plurality of partition units 1820A-1820N are configured to be equal to the number of memory cells, such that the first partition unit 1820A has a corresponding first memory cell 1824A, the second partition unit 1820B has a corresponding memory cell 1824B, and the Nth partition unit 1820N has a corresponding Nth memory cell 1824N. In at least one embodiment, the number of partition units 1820A-1820N may not be equal to the number of memory devices.

[0306] In at least one embodiment, memory units 1824A-1824N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, memory units 1824A-1824N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). In at least one embodiment, render targets such as frame buffers or texture maps may be stored across memory units 1824A-1824N, allowing partition units 1820A-1820N to write portions of each render target in parallel to efficiently use the available bandwidth of parallel processor memory 1822. In at least one embodiment, local instances of parallel processor memory 1822 may be eliminated in favor of a unified memory design utilizing system memory in combination with local cache memory.

[0307] In at least one embodiment, any of the clusters 1814A-1814N in the processing cluster array 1812 can process data to be written to any memory unit 1824A-1824N within the parallel processor memory 1822. In at least one embodiment, the memory crossbar 1816 can be configured to transmit the output of each cluster 1814A-1814N to any partition unit 1820A-1820N or another cluster 1814A-1814N, which can perform other processing operations on the output. In at least one embodiment, each cluster 1814A-1814N can communicate with a memory interface 1818 via the memory crossbar 1816 to read from or write to various external storage devices. In at least one embodiment, memory crossbar 1816 has connections to memory interface 1818 for communicating with I / O unit 1804, and connections to local instances of parallel processor memory 1822, thereby enabling processing units within different processing clusters 1814A-1814N to communicate with system memory or other memory that is not local to parallel processing unit 1802. In at least one embodiment, memory crossbar 1816 may use virtual channels to separate traffic flows between clusters 1814A-1814N and partition units 1820A-1820N.

[0308] In at least one embodiment, multiple instances of parallel processing unit 1802 can be provided on a single add-in card, or multiple add-in cards can be interconnected. In at least one embodiment, different instances of parallel processing unit 1802 can be configured to interoperate with each other, even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example, in at least one embodiment, some instances of parallel processing unit 1802 can include a higher precision floating point unit than other instances. In at least one embodiment, a system incorporating one or more instances of parallel processing unit 1802 or parallel processor 1800 can be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, gaming consoles, and / or embedded systems.

[0309] Figure 18B is a block diagram of a partition unit 1820 according to at least one embodiment. In at least one embodiment, the partition unit 1820 is Figure 18A1820A-1820N. In at least one embodiment, partition unit 1820 includes an L2 cache 1821, a frame buffer interface 1825, and a ROP 1826 (raster operations unit). L2 cache 1821 is a read / write cache that is configured to execute load and store operations received from memory crossbar 1816 and ROP 1826. In at least one embodiment, L2 cache 1821 outputs read misses and urgent writeback requests to frame buffer interface 1825 for processing. In at least one embodiment, updates may also be sent to the frame buffer via frame buffer interface 1825 for processing. In at least one embodiment, frame buffer interface 1825 interacts with one of the memory units in the parallel processor memory, such as memory units 1824A-1824N of FIG. 18A (e.g., within parallel processor memory 1822).

[0310] In at least one embodiment, ROP 1826 is a processing unit that performs raster operations such as stenciling, z-testing, blending, and the like. In at least one embodiment, ROP 1826 then outputs processed graphics data that is stored in graphics memory. In at least one embodiment, ROP 1826 includes compression logic to compress depth or color data written to memory and decompress depth or color data read from memory. In at least one embodiment, the compression logic may be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by ROP 1826 may vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, incremental color compression is performed on the depth and color data on a per-tile basis.

[0311] In at least one embodiment, ROP 1826 is included within each processing cluster (e.g., clusters 1814A-1814N of FIG. 18A ), rather than within partition unit 1820. In at least one embodiment, read and write requests for pixel data are transmitted through memory crossbar 1816 rather than pixel fragment data. In at least one embodiment, processed graphics data may be displayed on a display device such as a graphics card. Figure 17 1702 for further processing, or by Figure 18A One of the processing entities within parallel processor 1800 is routed for further processing.

[0312] Figure 18C is a block diagram of a processing cluster 1814 within a parallel processing unit according to at least one embodiment. In at least one embodiment, a processing cluster is Figure 18AIn at least one embodiment, processing cluster 1814 can be configured to execute many threads in parallel, where the term "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads, which uses a common instruction unit that is configured to issue instructions to a group of processing engines within each processing cluster.

[0313] In at least one embodiment, the operation of the processing cluster 1814 can be controlled by a pipeline manager 1832 that assigns processing tasks to SIMT parallel processors. In at least one embodiment, the pipeline manager 1832 Figure 18A Scheduler 1810 receives instructions and manages the execution of these instructions via graphics multiprocessor 1834 and / or texture unit 1836. In at least one embodiment, graphics multiprocessor 1834 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors with different architectures may be included within processing cluster 1814. In at least one embodiment, one or more instances of graphics multiprocessor 1834 may be included within processing cluster 1814. In at least one embodiment, graphics multiprocessor 1834 may process data, and data crossbar 1840 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, pipeline manager 1832 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via data crossbar 1840.

[0314] In at least one embodiment, each graphics multiprocessor 1834 within a processing cluster 1814 can include the same set of function execution logic (e.g., arithmetic logic unit, load-store unit, etc.). In at least one embodiment, the function execution logic can be configured in a pipelined manner, where new instructions can be issued before previous instructions have completed. In at least one embodiment, the function execution logic supports a variety of operations, including integer and floating-point arithmetic, comparison operations, Boolean operations, shifts, and calculations of various algebraic functions. In at least one embodiment, the same functional unit hardware can be utilized to perform different operations, and any combination of functional units can be present.

[0315] In at least one embodiment, instructions transmitted to processing cluster 1814 constitute threads. In at least one embodiment, a group of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, a thread group executes a program on different input data. In at least one embodiment, each thread within a thread group can be assigned to a different processing engine within graphics multiprocessor 1834. In at least one embodiment, a thread group can include fewer threads than the number of processing engines within graphics multiprocessor 1834. In at least one embodiment, when a thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the processing of a loop within the thread group. In at least one embodiment, a thread group can also include more threads than the number of processing engines within graphics multiprocessor 1834. In at least one embodiment, when a thread group includes more threads than the number of processing engines within graphics multiprocessor 1834, processing can be performed within consecutive clock cycles. In at least one embodiment, multiple thread groups can be executed simultaneously on graphics multiprocessor 1834.

[0316] In at least one embodiment, the graphics multiprocessor 1834 includes internal cache memory to perform load and store operations. In at least one embodiment, the graphics multiprocessor 1834 can abandon the internal cache and use cache memory within the processing cluster 1814 (e.g., L1 cache 1848). In at least one embodiment, each graphics multiprocessor 1834 can also access a partition unit (e.g., Figure 18A L2 cache within partition units 1820A-1820N) of the graphics multiprocessor 1834 is shared across all processing clusters 1814 and can be used to transfer data between threads. In at least one embodiment, graphics multiprocessor 1834 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to parallel processing unit 1802 can be used as global memory. In at least one embodiment, processing cluster 1814 includes multiple instances of graphics multiprocessor 1834, which can share common instructions and data, which can be stored in L1 cache 1848.

[0317] In at least one embodiment, each processing cluster 1814 may include a memory management unit ("MMU") 1845 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of MMU 1845 may reside in Figure 18A1818. In at least one embodiment, the MMU 1845 includes a set of page table entries (PTEs) that are used to map virtual addresses to physical addresses of tiles (more on tiling) and optionally to cache line indices. In at least one embodiment, the MMU 1845 may include an address translation lookaside buffer (TLB) or a cache that may reside within the graphics multiprocessor 1834 or L1 cache or processing cluster 1814. In at least one embodiment, the physical address is processed to assign surface data access locality to allow for efficient request interleaving between partition units. In at least one embodiment, the cache line index may be used to determine whether a request for a cache line is a hit or a miss.

[0318] In at least one embodiment, the processing clusters 1814 can be configured such that each graphics multiprocessor 1834 is coupled to a texture unit 1836 to perform texture mapping operations, which determine texture sample locations, read texture data, and filter texture data. In at least one embodiment, texture data is read from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 1834, and retrieved from an L2 cache, local parallel processor memory, or system memory as needed. In at least one embodiment, each graphics multiprocessor 1834 outputs processed tasks to a data crossbar 1840 to provide the processed tasks to another processing cluster 1814 for further processing or to store the processed tasks in an L2 cache, local parallel processor memory, or system memory via the memory crossbar 1816. In at least one embodiment, a PreROP 1842 (pre-raster operations unit) is configured to receive data from the graphics multiprocessor 1834 and direct the data to a ROP unit, which can communicate with a partitioning unit (e.g., a partitioning unit) as described herein. Figure 18A In at least one embodiment, the PreROP 1842 unit can perform optimizations for color blending, organize pixel color data, and perform address translation.

[0319] In at least one embodiment, Figure 18A -C At least one component shown or described is used to implement the combination Figure 1-6In at least one embodiment, at least one parallel processor 1800 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of the parallel processor. In at least one embodiment, at least one parallel processor 1800 is configured to generate precoder weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, at least one parallel processor 1800 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0320] Figure 18D A graphics multiprocessor 1834 is shown in accordance with at least one embodiment. In at least one embodiment, the graphics multiprocessor 1834 is coupled to a pipeline manager 1832 of a processing cluster 1814. In at least one embodiment, the graphics multiprocessor 1834 has an execution pipeline that includes, but is not limited to, an instruction cache 1852, an instruction unit 1854, an address mapping unit 1856, a register file 1858, one or more general purpose graphics processing unit (GPGPU) cores 1862, and one or more load / store units 1866. The GPGPU cores 1862 and the load / store units 1866 are coupled to a cache memory 1872 and a shared memory 1870 via a memory and cache interconnect 1868.

[0321] In at least one embodiment, instruction cache 1852 receives a stream of instructions to be executed from pipeline manager 1832. In at least one embodiment, instructions are cached in instruction cache 1852 and dispatched for execution by instruction unit 1854. In one embodiment, instruction unit 1854 can dispatch instructions as thread groups (e.g., warps), assigning each thread of the thread group to a different execution unit within GPGPU core 1862. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within the unified address space. In at least one embodiment, address mapping unit 1856 can be used to convert addresses in the unified address space into different memory addresses that can be accessed by load / store unit 1866.

[0322] In at least one embodiment, register file 1858 provides a set of registers for the functional units of graphics multiprocessor 1834. In at least one embodiment, register file 1858 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 1862, load / store unit 1866) connected to graphics multiprocessor 1834. In at least one embodiment, register file 1858 is divided between each functional unit such that a dedicated portion of register file 1858 is allocated to each functional unit. In at least one embodiment, register file 1858 is divided between the different warps being executed by graphics multiprocessor 1834.

[0323] In at least one embodiment, the GPGPU cores 1862 may each include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions for the graphics multiprocessor 1834. The GPGPU cores 1862 may be architecturally similar or may differ in architecture. In at least one embodiment, a first portion of the GPGPU core 1862 includes a single-precision FPU and integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic or enable variable-precision floating-point arithmetic. In at least one embodiment, the graphics multiprocessor 1834 may additionally include one or more fixed-function or special-function units to perform specific functions, such as copying rectangles or pixel blending operations. In at least one embodiment, one or more of the GPGPU cores may also include fixed-function or special-function logic.

[0324] In at least one embodiment, the GPGPU core 1862 includes SIMD logic capable of executing a single instruction on multiple sets of data. In one embodiment, the GPGPU core 1862 can physically execute SIMD4, SIMD8, and SIMD16 instructions, and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core can be generated by a shader compiler at compile time, or automatically generated when executing a program written and compiled for a single program multiple data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model can be executed by a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations can be executed in parallel by a single SIMD8 logic unit.

[0325] In at least one embodiment, the memory and cache interconnect 1868 is an interconnect network that connects each functional unit of the graphics multiprocessor 1834 to the register file 1858 and shared memory 1870. In at least one embodiment, the memory and cache interconnect 1868 is a crossbar interconnect that allows the load / store unit 1866 to perform load and store operations between the shared memory 1870 and the register file 1858. In at least one embodiment, the register file 1858 can operate at the same frequency as the GPGPU core 1862, resulting in very low latency for data transfers between the GPGPU core 1862 and the register file 1858. In at least one embodiment, the shared memory 1870 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 1834. In at least one embodiment, the cache memory 1872 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 1836. In at least one embodiment, the shared memory 1870 can also be used as a program-managed cache. In at least one embodiment, in addition to automatically cached data stored in cache memory 1872, threads executing on GPGPU core 1862 may programmatically store data in shared memory.

[0326] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the GPU can be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., internal to the package or chip). In at least one embodiment, regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0327] In at least one embodiment, Figure 18D At least one component shown or described is used to implement the combination Figure 1-6In at least one embodiment, at least one graphics multiprocessor 1834 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, at least one graphics multiprocessor 1834 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, at least one graphics multiprocessor 1834 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0328] Figure 19 A multi-GPU computing system 1900 is shown, according to at least one embodiment. In at least one embodiment, multi-GPU computing system 1900 may include a processor 1902 coupled to multiple general-purpose graphics processing units (GPGPUs) 1906A-D via a host interface switch 1904. In at least one embodiment, host interface switch 1904 is a PCI Express switch device that couples processor 1902 to a PCI Express bus, through which processor 1902 can communicate with GPGPUs 1906A-D. GPGPUs 1906A-D may be interconnected via a set of high-speed P2P GPU-to-GPU links 1916. In at least one embodiment, GPU-to-GPU links 1916 connect to each of GPGPUs 1906A-D via a dedicated GPU link. In at least one embodiment, P2P GPU links 1916 enable direct communication between each GPGPU 1906A-D without requiring communication through host interface bus 1904 to which processor 1902 is connected. In at least one embodiment, with GPU-to-GPU traffic directed to P2P GPU link 1916, host interface bus 1904 remains available for system memory access or communication with other instances of multi-GPU computing system 1900, e.g., via one or more network devices. While in at least one embodiment, GPGPUs 1906A-D are connected to processor 1902 via host interface switch 1904, in at least one embodiment, processor 1902 includes direct support for P2P GPU link 1916 and can connect directly to GPGPUs 1906A-D.

[0329] In at least one embodiment, Figure 19 At least one component shown or described is used to implement the combination Figure 1-6In at least one embodiment, at least one GPGPU 1906 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of a parallel processor. In at least one embodiment, at least one GPGPU 1906 is configured to generate precoding weights in parallel using two or more processing threads by at least processing multiple matrices combined into memory locations. In at least one embodiment, at least one GPGPU 1906 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600. In at least one embodiment, processor 1902 executes a kernel launch function that passes parameters to at least one kernel on at least one GPGPU 1906, and the at least one kernel generates precoding weights in parallel.

[0330] Figure 20 FIG2 is a block diagram of a graphics processor 2000 according to at least one embodiment. In at least one embodiment, graphics processor 2000 includes a ring interconnect 2002, a pipeline front end 2004, a media engine 2037, and graphics cores 2080A-2080N. In at least one embodiment, ring interconnect 2002 couples graphics processor 2000 to other processing units, including other graphics processors or one or more general-purpose processor cores. In at least one embodiment, graphics processor 2000 is one of many processors integrated within a multi-core processing system.

[0331] In at least one embodiment, graphics processor 2000 receives batches of commands via ring interconnect 2002. In at least one embodiment, the incoming commands are interpreted by command streamer 2003 in pipeline front end 2004. In at least one embodiment, graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via graphics cores 2080A-2080N. In at least one embodiment, for 3D geometry processing commands, command streamer 2003 provides commands to geometry pipeline 2036. In at least one embodiment, for at least some media processing commands, command streamer 2003 provides commands to video front end 2034, which is coupled to media engine 2037. In at least one embodiment, media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing, and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware-accelerated media data encoding and decoding. In at least one embodiment, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080A.

[0332] In at least one embodiment, the graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A-2080N (sometimes referred to as core slices), each of which has multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In at least one embodiment, the graphics processor 2000 can have any number of graphics cores 2080A-2080N. In at least one embodiment, the graphics processor 2000 includes a graphics core 2080A having at least a first sub-core 2050A and a second sub-core 2060A. In at least one embodiment, the graphics processor 2000 is a low-power processor having a single sub-core (e.g., 2050A). In at least one embodiment, the graphics processor 2000 includes multiple graphics cores 2080A-2080N, each of which includes a set of first sub-cores 2050A-2050N and a set of second sub-cores 2060A-2060N. In at least one embodiment, each of the first sub-cores 2050A-2050N includes at least a first set of execution units 2052A-2052N and media / texture samplers 2054A-2054N. In at least one embodiment, each of the second sub-cores 2060A-2060N includes at least a second set of execution units 2062A-2062N and samplers 2064A-2064N. In at least one embodiment, each of the sub-cores 2050A-2050N, 2060A-2060N shares a set of shared resources 2070A-2070N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic.

[0333] In at least one embodiment, Figure 20 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, at least one graphics processor 2000 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, at least one graphics processor 2000 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, at least one graphics processor 2000 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0334] Figure 21is a block diagram illustrating a microarchitecture for a processor 2100, which may include logic circuitry for executing instructions, according to at least one embodiment. In at least one embodiment, the processor 2100 may execute instructions including x86 instructions, ARM instructions, specialized instructions for an application-specific integrated circuit (ASIC), and the like. In at least one embodiment, the processor 2100 may include registers for storing packed data, such as the 64-bit wide MMX registers in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. TM Registers. In at least one embodiment, MMX registers available in integer and floating point form can operate with packed data elements that accompany single instruction multiple data ("SIMD") and streaming SIMD extensions ("SSE") instructions. In at least one embodiment, 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or higher (generally referred to as "SSEx") technology can hold such packed data operands. In at least one embodiment, processor 2110 can execute instructions to accelerate machine learning or deep learning algorithms, training, or inference.

[0335] In at least one embodiment, the processor 2100 includes an in-order front end ("front end") 2101 to fetch instructions for execution and prepare them for later use in the processor pipeline. In at least one embodiment, the front end 2101 may include several units. In at least one embodiment, an instruction prefetcher 2126 retrieves instructions from memory and provides them to an instruction decoder 2128, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2128 decodes the received instructions into one or more so-called "microinstructions" or "micro-operations" (also referred to as "micro-ops" or "micro-instructions") that the machine can execute. In at least one embodiment, the instruction decoder 2128 parses the instructions into an opcode and corresponding data and control fields, which can be used by the microarchitecture to perform the operations according to at least one embodiment. In at least one embodiment, the trace cache 2130 can assemble the decoded microinstructions into a program-ordered sequence or trace in the microinstruction queue 2134 for execution. In at least one embodiment, when trace cache 2130 encounters a complex instruction, microcode ROM 2132 provides the microinstructions necessary to complete the operation.

[0336] In at least one embodiment, some instructions may be converted into a single micro-op, while other instructions may require several micro-ops to complete the entire operation. In at least one embodiment, if more than four micro-ops are required to complete an instruction, the instruction decoder 2128 may access the microcode ROM 2132 to execute the instruction. In at least one embodiment, an instruction may be decoded into a smaller number of micro-ops for processing at the instruction decoder 2128. In at least one embodiment, if multiple micro-ops are required to complete the operation, the instruction may be stored in the microcode ROM 2132. In at least one embodiment, the trace cache 2130 references the entry point programmable logic array ("PLA") to determine the correct micro-op pointer for reading the microcode sequence from the microcode ROM 2132 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2132 completes the micro-op sequencing for the instruction, the front end 2101 of the machine may resume fetching micro-ops from the trace cache 2130.

[0337] In at least one embodiment, an out-of-order execution engine ("OOO engine") 2103 can prepare instructions for execution. In at least one embodiment, the OOO logic has multiple buffers to smooth and reorder the instruction flow to optimize performance as instructions flow down the pipeline and are scheduled for execution. The OOO engine 2103 includes, but is not limited to, an allocator / register renamer 2140, a memory microinstruction queue 2142, an integer / floating-point microinstruction queue 2144, a memory scheduler 2146, a fast scheduler 2102, a slow / general purpose floating-point scheduler ("slow / general purpose FP scheduler") 2104, and a simple floating-point scheduler ("simple FP scheduler") 2106. In at least one embodiment, the fast scheduler 2102, the slow / general purpose floating-point scheduler 2104, and the simple floating-point scheduler 2106 are also collectively referred to as "microinstruction schedulers 2102, 2104, 2106." In at least one embodiment, the allocator / register renamer 2140 allocates the machine buffers and resources required for each microinstruction to execute in sequence. In at least one embodiment, the allocator / register renamer 2140 renames logical registers into entries in the register file. In at least one embodiment, the allocator / register renamer 2140 also allocates an entry for each microinstruction in one of two microinstruction queues: a memory microinstruction queue 2142 for memory operations and an integer / floating-point microinstruction queue 2144 for non-memory operations, preceding the memory scheduler 2146 and the microinstruction schedulers 2102, 2104, and 2106. In at least one embodiment, the microinstruction schedulers 2102, 2104, and 2106 determine when a microinstruction is ready to execute based on the readiness of its dependent input register operand sources and the availability of the execution resource microinstructions that need to be completed. The fast scheduler 2102 of at least one embodiment can schedule every half of the main clock cycle, while the slow / general floating-point scheduler 2104 and the simple floating-point scheduler 2106 can schedule once per main processor clock cycle. In at least one embodiment, microinstruction schedulers 2102, 2104, 2106 arbitrate on dispatch ports to schedule microinstructions for execution.

[0338] In at least one embodiment, execution block 2111 includes, but is not limited to, integer register file / branch network 2108, floating point register file / branch network ("FP register file / branch network") 2110, address generation units ("AGUs") 2112 and 2114, fast arithmetic logic units ("fast ALUs") 2116 and 2118, slow arithmetic logic unit ("slow ALU") 2120, floating point ALU ("FP") 2122, and floating point move unit ("FP move") 2124. In at least one embodiment, integer register file / branch network 2108 and floating point register file / bypass network 2110 are also referred to herein as "register files 2108, 2110." In at least one embodiment, AGUs 2112 and 2114, fast ALUs 2116 and 2118, slow ALU 2120, floating-point ALU 2122, and floating-point move unit 2124 are also referred to herein as "execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124." In at least one embodiment, execution block 2111 may include, but is not limited to, any number (including zero) and type of register files, branch networks, address generation units, and execution units (in any combination).

[0339] In at least one embodiment, register files 2108 and 2110 may be arranged between microinstruction schedulers 2102, 2104, and 2106 and execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124. In at least one embodiment, integer register file / branch network 2108 performs integer operations. In at least one embodiment, floating-point register file / branch network 2110 performs floating-point operations. In at least one embodiment, each of register files 2108 and 2110 may include, but is not limited to, a branch network that can bypass or forward recently completed results that have not yet been written to the register file to new dependent objects. In at least one embodiment, register files 2108 and 2110 can communicate data with each other. In at least one embodiment, integer register file / branch network 2108 may include, but is not limited to, two separate register files: one register file for low-order 32-bit data and a second register file for high-order 32-bit data. In at least one embodiment, floating point register file / branch network 2110 may include, but is not limited to, 128-bit wide entries, as floating point instructions typically have operands that are 64 to 128 bits wide.

[0340] In at least one embodiment, execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124 may execute instructions. In at least one embodiment, register files 2108 and 2110 store integer and floating-point data operand values ​​required for microinstructions to execute. In at least one embodiment, processor 2100 may include, but is not limited to, any number of execution units 2112, 2114, 2116, 2118, 2120, 2122, and 2124, and any combination thereof. In at least one embodiment, floating-point ALU 2122 and floating-point move unit 2124 may perform floating-point, MMX, SIMD, AVX, SSE, or other operations, including specialized machine learning instructions. In at least one embodiment, floating-point ALU 2122 may include, but is not limited to, a 64-bit by 64-bit floating-point divider to perform division, square root, and remainder micro-operations. In at least one embodiment, floating-point hardware may be used to process instructions involving floating-point values. In at least one embodiment, ALU operations can be passed to fast ALUs 2116 and 2118. In at least one embodiment, fast ALUs 2116 and 2118 can perform fast operations with an effective latency of half a clock cycle. In at least one embodiment, most complex integer operations go to slow ALU 2120, as slow ALU 2120 may include, but is not limited to, integer execution hardware for long-latency operations, such as multipliers, shifts, flag logic, and branch processing. In at least one embodiment, memory load / store operations can be performed by ALUs 2112 and 2114. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 can perform integer operations on 64-bit data operands. In at least one embodiment, fast ALU 2116, fast ALU 2118, and slow ALU 2120 can be implemented to support various data bit sizes, including 16, 32, 128, 256, and the like. In at least one embodiment, the floating point ALU 2122 and floating point shift unit 2124 can be implemented to support a range of operands having bits of various widths. In at least one embodiment, the floating point ALU 2122 and floating point shift unit 2124 can operate on 128-bit wide packed data operands in conjunction with SIMD and multimedia instructions.

[0341] In at least one embodiment, microinstruction schedulers 2102, 2104, and 2106 schedule dependent operations before the parent load completes execution. In at least one embodiment, because microinstructions can be speculatively scheduled and executed in processor 2100, processor 2100 may also include logic for handling memory misses. In at least one embodiment, if a data load misses in the data cache, there may be dependent operations running in the pipeline, temporarily preventing the scheduler from having the correct data. In at least one embodiment, a replay mechanism tracks and re-executes instructions that use incorrect data. In at least one embodiment, it may be necessary to replay dependent operations and allow independent operations to complete. In at least one embodiment, the scheduler and replay mechanism of at least one embodiment of the processor may also be designed to capture instruction sequences for text string comparison operations.

[0342] In at least one embodiment, the term "register" may refer to an on-board processor storage location that can be used as part of an instruction to identify an operand. In at least one embodiment, registers may be those that can be used from outside the processor (from a programmer's perspective). In at least one embodiment, registers may not be limited to a particular type of circuit. Instead, in at least one embodiment, registers can store data, provide data, and perform the functions described herein. In at least one embodiment, the registers described herein can be implemented by circuitry within the processor using a variety of different techniques, such as dedicated physical registers, physical registers dynamically allocated using register renaming, a combination of dedicated and dynamically allocated physical registers, and the like. In at least one embodiment, integer registers store 32-bit integer data. The register file of at least one embodiment also includes eight multimedia SIMD registers for packing data.

[0343] In at least one embodiment, Figure 21 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, the at least one processor 2100 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of a parallel processor. In at least one embodiment, the at least one processor 2100 is configured to generate precoder weights in parallel using two or more processing threads by at least processing multiple matrices combined into memory locations. In at least one embodiment, the at least one processor 2100 performs at least one aspect of the description of the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0344] Figure 22A block diagram of a processing system according to at least one embodiment is shown. In at least one embodiment, system 2200 includes one or more processors 2202 and one or more graphics processors 2208, and can be a single-processor desktop system, a multi-processor workstation system, or a server system with a large number of processors 2202 or processor cores 2207. In at least one embodiment, system 2200 is a processing platform incorporated within a system-on-chip (SoC) integrated circuit for use in mobile, handheld, or embedded devices.

[0345] In at least one embodiment, the system 2200 may include or be incorporated into a server-based gaming platform, including a gaming console, a mobile gaming console, a handheld gaming console, or an online gaming console. In at least one embodiment, the system 2200 is a mobile phone, a smartphone, a tablet computing device, or a mobile internet device. In at least one embodiment, the processing system 2200 may also include a device coupled to or integrated into a wearable device, such as a smartwatch wearable device, a smart glasses device, an augmented reality device, or a virtual reality device. In at least one embodiment, the processing system 2200 is a television or set-top box device having one or more processors 2202 and a graphical interface generated by one or more graphics processors 2208.

[0346] In at least one embodiment, one or more processors 2202 each include one or more processor cores 2207 to process instructions that, when executed, perform operations for system and user software. In at least one embodiment, each of the one or more processor cores 2207 is configured to process a specific instruction set 2209. In at least one embodiment, the instruction set 2209 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or be calculated using very long instruction words (VLIW). In at least one embodiment, the processor cores 2207 can each process a different instruction set 2209, which can include instructions that contribute to emulating other instruction sets. In at least one embodiment, the processor cores 2207 can also include other processing devices, such as a digital signal processor (DSP).

[0347] In at least one embodiment, the processor 2202 includes a cache memory 2204. In at least one embodiment, the processor 2202 can have a single internal cache or multiple levels of internal cache. In at least one embodiment, the cache memory is shared among various components of the processor 2202. In at least one embodiment, the processor 2202 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which can be shared among the processor cores 2207 using known cache coherence techniques. In at least one embodiment, the processor 2202 further includes a register file 2206. The processor can include different types of registers (e.g., integer registers, floating point registers, status registers, and an instruction pointer register) for storing different types of data. In at least one embodiment, the register file 2206 can include general purpose registers or other registers.

[0348] In at least one embodiment, one or more processors 2202 are coupled to one or more interface buses 2210 to transmit communication signals, such as address, data, or control signals, between the processors 2202 and other components in the system 2200. In at least one embodiment, the interface bus 2210 may be a processor bus, such as a version of a Direct Media Interface (DMI) bus. In at least one embodiment, the interface 2210 is not limited to a DMI bus and may include one or more peripheral component interconnect buses (e.g., PCI, PCI Express), a memory bus, or other types of interface buses. In at least one embodiment, the processor 2202 includes an integrated memory controller 2216 and a platform controller hub 2230. In at least one embodiment, the memory controller 2216 facilitates communication between memory devices and other components of the processing system 2200, while the platform controller hub (PCH) 2230 provides connections to input / output (I / O) devices via a local I / O bus.

[0349] In at least one embodiment, the memory device 2220 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or other suitable memory device for use as processor memory. In at least one embodiment, the memory device 2220 may serve as system memory for the processing system 2200 to store data 2222 and instructions 2221 for use when one or more processors 2202 execute applications or processes. In at least one embodiment, the memory controller 2216 is also coupled to an optional external graphics processor 2212, which may communicate with one or more graphics processors 2208 in the processors 2202 to perform graphics and media operations. In at least one embodiment, a display device 2211 may be connected to the processor 2202. In at least one embodiment, the display device 2211 may include one or more internal display devices, such as in a mobile electronic device or laptop, or an external display device connected via a display interface (e.g., DisplayPort). In at least one embodiment, the display device 2211 may include a head-mounted display (HMD), such as a stereoscopic display device used in virtual reality (VR) applications or augmented reality (AR) applications.

[0350] In at least one embodiment, the platform controller hub 2230 enables peripheral devices to connect to the storage device 2220 and the processor 2202 via a high-speed I / O bus. In at least one embodiment, the I / O peripherals include, but are not limited to, an audio controller 2246, a network controller 2234, a firmware interface 2228, a wireless transceiver 2226, a touch sensor 2225, and a data storage device 2224 (e.g., a hard drive, flash memory, etc.). In at least one embodiment, the data storage device 2224 can be connected via a storage interface (e.g., SATA) or via a peripheral bus, such as a peripheral component interconnect bus (e.g., PCI, PCIe). In at least one embodiment, the touch sensor 2225 can include a touch screen sensor, a pressure sensor, or a fingerprint sensor. In at least one embodiment, the wireless transceiver 2226 can be a Wi-Fi transceiver, a Bluetooth transceiver, or a mobile network transceiver, such as a 3G, 4G, or Long Term Evolution (LTE) transceiver. In at least one embodiment, the firmware interface 2228 enables communication with the system firmware and can be, for example, a Unified Extensible Firmware Interface (UEFI). In at least one embodiment, a network controller 2234 can enable network connectivity to a wired network. In at least one embodiment, a high-performance network controller (not shown) is coupled to the interface bus 2210. In at least one embodiment, the audio controller 2246 is a multi-channel high-definition audio controller. In at least one embodiment, the processing system 2200 includes an optional legacy I / O controller 2240 for coupling legacy (e.g., Personal System 2 (PS / 2)) devices to the system 2200. In at least one embodiment, the platform controller hub 2230 can also be connected to one or more universal serial bus (USB) controllers 2242 that connect input devices such as a keyboard and mouse 2243 combination, a camera 2244, or other USB input devices.

[0351] In at least one embodiment, instances of the memory controller 2216 and the platform controller hub 2230 may be integrated into a discrete external graphics processor, such as the external graphics processor 2212. In at least one embodiment, the platform controller hub 2230 and / or the memory controller 2216 may be external to one or more processors 2202. For example, in at least one embodiment, the system 2200 may include an external memory controller 2216 and a platform controller hub 2230, which may be configured as a memory controller hub and a peripheral controller hub in a system chipset that communicates with the processor 2202.

[0352] In at least one embodiment, Figure 22 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, the at least one graphics processor 2208 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of a parallel processor. In at least one embodiment, the at least one graphics processor 2208 is configured to generate precoding weights in parallel using two or more processing threads by at least processing multiple matrices combined into memory locations. In at least one embodiment, the at least one graphics processor 2208 performs at least one aspect of the description regarding the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600. In at least one embodiment, the processor core 2207 executes a kernel launch function that passes parameters to at least one kernel on the at least one graphics processor 2208, and the at least one kernel generates precoding weights in parallel.

[0353] Figure 23 is a block diagram of a processor 2300 having one or more processor cores 2302A-2302N, an integrated memory controller 2314, and an integrated graphics processor 2308, in accordance with at least one embodiment. In at least one embodiment, the processor 2300 may include additional cores, up to and including the additional core 2302N represented by the dashed box. In at least one embodiment, each processor core 2302A-2302N includes one or more internal cache units 2304A-2304N. In at least one embodiment, each processor core may also have access to one or more shared cache units 2306.

[0354] In at least one embodiment, the internal cache units 2304A-2304N and the shared cache unit 2306 represent a cache memory hierarchy within the processor 2300. In at least one embodiment, the cache memory units 2304A-2304N may include at least one level of instruction and data cache within each processor core and one or more levels of cache in a shared mid-level cache, such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache, where the highest level of cache before external memory is categorized as LLC. In at least one embodiment, cache coherence logic maintains coherence between the various cache units 2306 and 2304A-2304N.

[0355] In at least one embodiment, the processor 2300 may also include a set of one or more bus controller units 2316 and a system agent core 2310. In at least one embodiment, the one or more bus controller units 2316 manage a set of peripheral buses, such as one or more PCI or PCIe buses. In at least one embodiment, the system agent core 2310 provides management functions for various processor components. In at least one embodiment, the system agent core 2310 includes one or more integrated memory controllers 2314 to manage access to various external memory devices (not shown).

[0356] In at least one embodiment, one or more processor cores 2302A-2302N include support for simultaneous multithreading. In at least one embodiment, system agent core 2310 includes components for coordinating and operating cores 2302A-2302N during multithreaded processing. In at least one embodiment, system agent core 2310 may additionally include a power control unit (PCU) that includes logic and components for regulating one or more power states of processor cores 2302A-2302N and graphics processor 2308.

[0357] In at least one embodiment, the processor 2300 also includes a graphics processor 2308 for performing graphics processing operations. In at least one embodiment, the graphics processor 2308 is coupled to a shared cache unit 2306 and a system agent core 2310 including one or more integrated memory controllers 2314. In at least one embodiment, the system agent core 2310 also includes a display controller 2311 for driving the graphics processor output to one or more coupled displays. In at least one embodiment, the display controller 2311 may also be a separate module coupled to the graphics processor 2308 via at least one interconnect, or may be integrated within the graphics processor 2308.

[0358] In at least one embodiment, a ring-based interconnect 2312 is used to couple the internal components of processor 2300. In at least one embodiment, alternative interconnects may be used, such as point-to-point interconnects, switched interconnects, or other technologies. In at least one embodiment, graphics processor 2308 is coupled to ring interconnect 2312 via I / O link 2313.

[0359] In at least one embodiment, I / O link 2313 represents at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and a high-performance embedded memory module 2318 (e.g., an eDRAM module). In at least one embodiment, each of processor cores 2302A-2302N and graphics processor 2308 uses embedded memory module 2318 as a shared last-level cache.

[0360] In at least one embodiment, the processor cores 2302A-2302N are homogeneous cores that execute a common instruction set architecture. In at least one embodiment, the processor cores 2302A-2302N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more processor cores 2302A-2302N execute a common instruction set, while one or more other processor cores 2302A-2302N execute a subset of the common instruction set or a different instruction set. In at least one embodiment, the processor cores 2302A-2302N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively high power consumption are coupled with one or more power cores with lower power consumption. In at least one embodiment, the processor 2300 can be implemented on one or more chips or as a SoC integrated circuit.

[0361] In at least one embodiment, Figure 23 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, the at least one graphics processor 2308 is configured to perform precoding (e.g., generating precoding weights) in parallel by multiple threads of a parallel processor. In at least one embodiment, the at least one graphics processor 2308 is configured to generate precoding weights in parallel using two or more processing threads by at least processing multiple matrices combined into a memory location. In at least one embodiment, the at least one graphics processor 2308 performs at least one aspect described with respect to the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600. In at least one embodiment, the at least one processor core 2302 executes a kernel launch function that passes parameters to at least one kernel on the at least one graphics processor 2308, and the at least one kernel generates precoding weights in parallel.

[0362] Figure 242 is a block diagram of a graphics processor 2400, which may be a discrete graphics processing unit or a graphics processor integrated with multiple processing cores. In at least one embodiment, the graphics processor 2400 communicates with registers on the graphics processor 2400 and commands placed in memory via a memory-mapped I / O interface. In at least one embodiment, the graphics processor 2400 includes a memory interface 2414 for accessing memory. In at least one embodiment, the memory interface 2414 is an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0363] In at least one embodiment, the graphics processor 2400 also includes a display controller 2402 for driving display output data to a display device 2420. In at least one embodiment, the display controller 2402 includes hardware for one or more overlay planes of the display device 2420 and a combination of multiple layers of video or user interface elements. In at least one embodiment, the display device 2420 can be an internal or external display device. In at least one embodiment, the display device 2420 is a head-mounted display device, such as a virtual reality (VR) display device or an augmented reality (AR) display device. In at least one embodiment, the graphics processor 2400 includes a video codec engine 2406 to encode, decode, or transcode media to, from, or between one or more media coding formats, including but not limited to Moving Picture Experts Group (MPEG) formats (e.g., MPEG-2), Advanced Video Coding (AVC) formats (e.g., H.264 / MPEG-4 AVC, and Society of Motion Picture and Television Engineers (SMPTE) 421M / VC-1), and Joint Photographic Experts Group (JPEG) formats (e.g., JPEG) and Motion JPEG (MJPEG) formats.

[0364] In at least one embodiment, graphics processor 2400 includes a block image transfer (BLIT) engine 2404 to perform two-dimensional (2D) rasterizer operations, including, for example, bit-boundary block transfers. However, in at least one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 2410. In at least one embodiment, GPE 2410 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0365] In at least one embodiment, the GPE 2410 includes a 3D pipeline 2412 for performing 3D operations, such as rendering three-dimensional images and scenes, using processing functions that operate on 3D primitive shapes (e.g., rectangles, triangles, etc.). The 3D pipeline 2412 includes programmable and fixed-function elements that perform various tasks and / or spawn execution threads to the 3D / media subsystem 2415. While the 3D pipeline 2412 can be used to perform media operations, in at least one embodiment, the GPE 2410 also includes a media pipeline 2416 for performing media operations, such as video post-processing and image enhancement.

[0366] In at least one embodiment, the media pipeline 2416 includes fixed-function or programmable logic units for performing one or more specialized media operations, such as video decode acceleration, video deinterlacing, and video encode acceleration, in place of or on behalf of the video codec engine 2406. In at least one embodiment, the media pipeline 2416 also includes a thread spawning unit for spawning threads for execution on the 3D / media subsystem 2415. In at least one embodiment, the spawned threads perform computations for the media operations on one or more graphics execution units included in the 3D / media subsystem 2415.

[0367] In at least one embodiment, the 3D / media subsystem 2415 includes logic for executing threads generated by the 3D pipeline 2412 and the media pipeline 2416. In at least one embodiment, the 3D pipeline 2412 and the media pipeline 2416 send thread execution requests to the 3D / media subsystem 2415, which includes thread dispatch logic for arbitrating and dispatching the various requests to available thread execution resources. In at least one embodiment, the execution resources include an array of graphics execution units for processing 3D and media threads. In at least one embodiment, the 3D / media subsystem 2415 includes one or more internal caches for thread instructions and data. In at least one embodiment, the subsystem 2415 also includes shared memory, including registers and addressable memory, to share data between threads and store output data.

[0368] In at least one embodiment, Figure 24 At least one component shown or described is used to implement the combination Figure 1-6In at least one embodiment, the at least one graphics processor 2400 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, the at least one graphics processor 2400 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, the at least one graphics processor 2400 performs at least one aspect of the description of the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0369] Figure 25 is a block diagram of a graphics processing engine 2510 of a graphics processor according to at least one embodiment. In at least one embodiment, the graphics processing engine (GPE) 2510 is Figure 24 . In at least one embodiment, media pipeline 2516 is optional and may not be explicitly included in GPE 2510. In at least one embodiment, separate media and / or graphics processors are coupled to GPE 2510.

[0370] In at least one embodiment, GPE 2510 is coupled to or includes a command streamer 2503, which provides a command stream to the 3D pipeline 2512 and / or the media pipeline 2516. In at least one embodiment, command streamer 2503 is coupled to a memory, which may be system memory, or one or more of an internal cache memory and a shared cache memory. In at least one embodiment, command streamer 2503 receives commands from the memory and sends the commands to the 3D pipeline 2512 and / or the media pipeline 2516. In at least one embodiment, the commands are instructions, primitives, or micro-operations retrieved from a ring buffer that stores commands for the 3D pipeline 2512 and the media pipeline 2516. In at least one embodiment, the ring buffer may also include a batch command buffer that stores batches of multiple commands. In at least one embodiment, commands for 3D pipeline 2512 may also include references to data stored in memory, such as, but not limited to, vertex and geometry data for 3D pipeline 2512 and / or image data and memory objects for media pipeline 2516. In at least one embodiment, 3D pipeline 2512 and media pipeline 2516 process commands and data by executing operations or by dispatching one or more execution threads to graphics core array 2514. In at least one embodiment, graphics core array 2514 includes one or more graphics core blocks (e.g., one or more graphics cores 2515A, one or more graphics cores 2515B), each block including one or more graphics cores. In at least one embodiment, each graphics core includes a set of graphics execution resources, including general-purpose and graphics-specific execution logic for performing graphics and compute operations, as well as fixed-function texture processing and / or machine learning and artificial intelligence acceleration logic.

[0371] In at least one embodiment, the 3D pipeline 2512 includes fixed-function and programmable logic for processing one or more shader programs, such as vertex shaders, geometry shaders, pixel shaders, fragment shaders, compute shaders, or other shader programs, by processing instructions and dispatching execution threads to the graphics core array 2514. In at least one embodiment, the graphics core array 2514 provides a unified execution resource block for processing shader programs. In at least one embodiment, the multi-purpose execution logic (e.g., execution units) within the graphics cores 2515A-2515B of the graphics core array 2514 includes support for various 3D API shader languages ​​and can execute multiple simultaneous execution threads associated with multiple shaders.

[0372] In at least one embodiment, graphics core array 2514 also includes execution logic for performing media functions, such as video and / or image processing. In at least one embodiment, in addition to graphics processing operations, the execution units also include general logic that can be programmed to perform parallel general computing operations.

[0373] In at least one embodiment, output data generated by threads executing on graphics core array 2514 can be output to memory in unified return buffer (URB) 2518. In at least one embodiment, URB 2518 can store data for multiple threads. In at least one embodiment, URB 2518 can be used to send data between different threads executing on graphics core array 2514. In at least one embodiment, URB 2518 can also be used for synchronization between threads on graphics core array 2514 and fixed-function logic within shared function logic 2520.

[0374] In at least one embodiment, graphics core array 2514 is scalable such that graphics core array 2514 includes a variable number of graphics cores, each having a variable number of execution units based on the target power and performance level of GPE 2510. In at least one embodiment, execution resources are dynamically scalable such that execution resources can be enabled or disabled as needed.

[0375] In at least one embodiment, graphics core array 2514 is coupled to shared functionality logic 2520, which includes a plurality of resources shared between the graphics cores in graphics core array 2514. In at least one embodiment, the shared functionality performed by shared functionality logic 2520 is embodied in hardware logic that provides specialized, supplemental functionality to graphics core array 2514. In at least one embodiment, shared functionality logic 2520 includes, but is not limited to, samplers 2521, math 2522, and inter-thread communication (ITC) logic 2523. In at least one embodiment, one or more caches 2525 are included in or coupled to shared functionality logic 2520.

[0376] In at least one embodiment, if the demand for a dedicated function is insufficient to be contained within graphics core array 2514, shared functions are used. In at least one embodiment, a single instance of a dedicated function is used within shared function logic 2520 and shared among other execution resources within graphics core array 2514. In at least one embodiment, a specific shared function may be included within shared function logic 2520 within graphics core array 2514, with the specific shared function being included within shared function logic 2516, which is used extensively by graphics core array 2514. In at least one embodiment, shared function logic 2516 within graphics core array 2514 may include some or all of the logic within shared function logic 2520. In at least one embodiment, all logic elements within shared function logic 2520 may be replicated within shared function logic 2516 within graphics core array 2514. In at least one embodiment, shared function logic 2520 is eliminated in favor of shared function logic 2516 within graphics core array 2514.

[0377] In at least one embodiment, Figure 25 At least one component shown or described is used to implement the combination Figure 1-6 In at least one embodiment, the at least one graphics processor 2510 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, the at least one graphics processor 2510 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, the at least one graphics processor 2510 performs at least one aspect of the description of the distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0378] Figure 26 is a block diagram of the hardware logic of a graphics processor core 2600 according to at least one embodiment described herein. In at least one embodiment, graphics processor core 2600 is included within a graphics core array. In at least one embodiment, graphics processor core 2600 (sometimes referred to as a core slice) can be one or more graphics cores within a modular graphics processor. In at least one embodiment, graphics processor core 2600 is an example of one graphics core slice, and the graphics processors described herein can include multiple graphics core slices based on target power and performance envelopes. In at least one embodiment, each graphics core 2600 can include a fixed function block 2630 coupled to multiple sub-cores 2601A-2601F, also referred to as sub-slices, which include modular blocks of general-purpose and fixed-function logic.

[0379] In at least one embodiment, fixed function block 2630 includes geometry and fixed function pipelines 2636, which may be shared by all sub-cores in graphics processor 2600, for example, in lower performance and / or lower power graphics processor implementations. In at least one embodiment, geometry and fixed function pipelines 2636 include a 3D fixed function pipeline, a video front end unit, a thread spawner and thread dispatcher, and a unified return buffer manager that manages a unified return buffer.

[0380] In at least one fixed embodiment, fixed function block 2630 also includes a graphics SoC interface 2637, a graphics microcontroller 2638, and a media pipeline 2639. Graphics SoC interface 2637 provides an interface between graphics core 2600 and other processor cores in the on-chip integrated circuit system. In at least one embodiment, graphics microcontroller 2638 is a programmable subprocessor that can be configured to manage various functions of graphics processor 2600, including thread dispatching, scheduling, and preemption. In at least one embodiment, media pipeline 2639 includes logic that facilitates decoding, encoding, pre-processing, and / or post-processing of multimedia data, including image and video data. In at least one embodiment, media pipeline 2639 implements media operations via requests to computational or sampling logic within sub-cores 2601-2601F.

[0381] In at least one embodiment, the SoC interface 2637 enables the graphics core 2600 to communicate with a general-purpose application processor core (e.g., a CPU) and / or other components within the SoC, including memory hierarchy elements such as a shared last-level cache, system RAM, and / or embedded on-chip or packaged DRAM. In at least one embodiment, the SoC interface 2637 may also enable communication with fixed-function devices within the SoC (e.g., a camera imaging pipeline) and enable the use and / or implementation of global memory atomics that can be shared between the graphics core 2600 and the CPU within the SoC. In at least one embodiment, the SoC interface 2637 may also implement power management controls for the graphics core 2600 and enable interfaces between the clock domain of the graphics core 2600 and other clock domains within the SoC. In at least one embodiment, the SoC interface 2637 enables the reception of command buffers from a command stream converter and a global thread dispatcher, which are configured to provide commands and instructions to each of one or more graphics cores within the graphics processor. In at least one embodiment, commands and instructions may be dispatched to the media pipeline 2639 when media operations are to be performed, or to the geometry and fixed function pipelines (e.g., the geometry and fixed function pipeline 2636, and / or the geometry and fixed function pipeline 2614) when graphics processing operations are to be performed.

[0382] In at least one embodiment, the graphics microcontroller 2638 can be configured to perform various scheduling and management tasks for the graphics core 2600. In at least one embodiment, the graphics microcontroller 2638 can perform graphics and / or compute workload scheduling on the various graphics parallel engines within the execution unit (EU) arrays 2602A-2602F, 2604A-2604F in the sub-cores 2601A-2601F. In at least one embodiment, host software executing on a CPU core of a SoC including the graphics core 2600 can submit a workload to one of multiple graphics processor doorbells, which invokes scheduling operations on the appropriate graphics engine. In at least one embodiment, scheduling operations include determining which workload to run next, submitting the workload to the command stream converter, preempting existing workloads running on the engine, monitoring the progress of the workload, and notifying the host software when the workload is complete. In at least one embodiment, graphics microcontroller 2638 may also facilitate low power or idle states for graphics core 2600, thereby providing graphics core 2600 with the ability to save and restore registers across low power state transitions within graphics core 2600 independent of the operating system and / or graphics driver software on the system.

[0383] In at least one embodiment, graphics core 2600 may have up to N modular sub-cores, more or less than the sub-cores 2601A-2601F shown. For each set of N sub-cores, in at least one embodiment, graphics core 2600 may also include shared function logic 2610, shared and / or cache memory 2612, geometry / fixed function pipelines 2614, and additional fixed function logic 2616 to accelerate various graphics and compute processing operations. In at least one embodiment, shared function logic 2610 may include logic units (e.g., samplers, math, and / or inter-thread communication logic) that may be shared by each of the N sub-cores within graphics core 2600. In at least one embodiment, shared and / or cache memory 2612 may be the last level cache for the N sub-cores 2601A-2601F within graphics core 2600 and may also serve as shared memory accessible by multiple sub-cores. In at least one embodiment, geometry / fixed function pipeline 2614 may be included in place of geometry / fixed function pipeline 2636 within fixed function block 2630 and may include the same or similar logic units.

[0384] In at least one embodiment, graphics core 2600 includes additional fixed-function logic 2616, which may include various fixed-function acceleration logic for use by graphics core 2600. In at least one embodiment, additional fixed-function logic 2616 includes an additional geometry pipeline for use in position-only shading. In position-only shading, there are at least two geometry pipelines, and the full geometry pipeline and culling pipeline within geometry and fixed-function pipelines 2614, 2636 are the additional geometry pipelines that may be included in additional fixed-function logic 2616. In at least one embodiment, the culling pipeline is a modified version of the full geometry pipeline. In at least one embodiment, the full pipeline and the culling pipeline can execute different instances of an application, each with a separate context. In at least one embodiment, position-only shading can hide long culling runs for discarded triangles, allowing shading to complete earlier in some cases. For example, in at least one embodiment, the culling pipeline logic in the additional fixed function logic 2616 can execute position shaders in parallel with the main application and generally generate critical results faster than the full pipeline because the culling pipeline obtains and masks the position attributes of the vertices without having to perform rasterization and render the pixels to the frame buffer. In at least one embodiment, the culling pipeline can use the generated critical results to calculate visibility information for all triangles, regardless of whether those triangles are culled. In at least one embodiment, the full pipeline (which in this case may be called a replay pipeline) can consume visibility information to skip culled triangles to mask only visible triangles that are ultimately passed to the rasterization stage.

[0385] In at least one embodiment, the additional fixed-function logic 2616 may also include machine learning acceleration logic, such as fixed-function matrix multiplication logic, to implement optimizations including for machine learning training or inference.

[0386] In at least one embodiment, each graphics sub-core 2601A-2601F includes a set of execution resources that can be used to perform graphics, media, and compute operations in response to requests from the graphics pipeline, media pipeline, or shader programs. In at least one embodiment, the graphics sub-core 2601A-2601F includes multiple EU arrays 2602A-2602F, 2604A-2604F, thread dispatch and inter-thread communication (TD / IC) logic 2603A-2603F, 3D (e.g., texture) samplers 2605A-2605F, media samplers 2606A-2606F, shader processors 2607A-2607F, and shared local memory (SLM) 2608A-2608F. In at least one embodiment, EU arrays 2602A-2602F, 2604A-2604F each include multiple execution units, which are general-purpose graphics processing units capable of servicing graphics, media, or compute operations and executing floating-point and integer / fixed-point logic operations, including graphics, media, or compute shader programs. In at least one embodiment, TD / IC logic 2603A-2603F performs local thread dispatch and thread control operations for execution units within a sub-core and facilitates communication between threads executing on execution units within a sub-core. In at least one embodiment, 3D samplers 2605A-2605F can read texture or other 3D graphics-related data into memory. In at least one embodiment, 3D samplers can read texture data differently based on the configured sampling state and texture format associated with a given texture. In at least one embodiment, media samplers 2606A-2606F can perform similar read operations based on the type and format associated with the media data. In at least one embodiment, each graphics sub-core 2601A-2601F may alternatively include a unified 3D and media sampler. In at least one embodiment, threads executing on execution units within each sub-core 2601A-2601F may utilize shared local memory 2608A-2608F within each sub-core, enabling threads executing within a thread group to execute using a common pool of on-chip memory.

[0387] In at least one embodiment, Figure 26 At least one component shown or described is used to implement the combination Figure 1-6In at least one embodiment, at least one graphics processor core 2600 is configured to perform precoding (e.g., generating precoding weights) in parallel using multiple threads of a parallel processor. In at least one embodiment, at least one graphics processor core 2600 is configured to generate precoding weights in parallel using two or more processing threads by processing at least multiple matrices combined into memory locations. In at least one embodiment, at least one graphics processor core 2600 performs at least one aspect described with respect to distributed unit 102, precoding 302, precoding technique 400, technique 500, and / or technique 600.

[0388] Figure 27A and Figure 27B Thread execution logic 2700 is shown for an array of processing elements comprising a graphics processor core, in accordance with at least one embodiment. Figure 27A At least one embodiment is shown in which thread execution logic 2700 is used. Figure 27B Illustrative internal details of an execution unit are shown in accordance with at least one embodiment.

[0389] like Figure 27A As shown in FIG, in at least one embodiment, thread execution logic 2700 includes a shader processor 2702, a thread dispatcher 2704, an instruction cache 2706, a scalable execution unit array including a plurality of execution units 2708A-2708N, a sampler 2710, a data cache 2712, and a data port 2714. In at least one embodiment, the scalable execution unit array can be dynamically scaled by enabling or disabling one or more execution units (e.g., any one of execution units 2708A, 2708B, 2708C, 2708D, through 2708N-1 and 2708N), for example, based on the computational requirements of the workload. In at least one embodiment, the scalable execution units are interconnected via an interconnect structure that links to each execution unit. In at least one embodiment, thread execution logic 2700 includes one or more connections to a memory (such as system memory or cache memory) through instruction cache 2706, data port 2714, sampler 2710, and one or more of execution units 2708A-2708N. In at least one embodiment, each execution unit (e.g., 2708A) is an independent programmable general-purpose computing unit capable of executing multiple simultaneous hardware threads while processing multiple data elements in parallel for each thread. In at least one embodiment, the array of execution units 2708A-2708N is scalable to include any number of individual execution units.

[0390] In at least one embodiment, execution units 2708A-2708N are primarily used to execute shader programs. In at least one embodiment, shader processor 2702 can process various shader programs and dispatch execution threads associated with the shader programs via thread dispatcher 2704. In at least one embodiment, thread dispatcher 2704 includes logic for arbitrating thread initialization requests from graphics and media pipelines and instantiating requested threads on one or more execution units in execution units 2708A-2708N. For example, in at least one embodiment, the geometry pipeline can dispatch vertex, tessellation, or geometry shaders to thread execution logic for processing. In at least one embodiment, thread dispatcher 2704 can also handle runtime thread generation requests from executing shader programs.

[0391] In at least one embodiment, execution units 2708A-2708N support an instruction set that includes native support for many standard 3D graphics shader instructions, enabling shader programs from graphics libraries such as Direct3D and OpenGL to execute with minimal translation. In at least one embodiment, the execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general-purpose processing (e.g., compute and media shaders). In at least one embodiment, each execution unit 2708A-2708N includes one or more arithmetic logic units (ALUs) capable of multi-issue single instruction, multiple data (SIMD) and multi-threaded operation, enabling an efficient execution environment despite higher latency memory accesses. In at least one embodiment, each hardware thread within each execution unit has a dedicated high-bandwidth register file and associated independent thread state. In at least one embodiment, execution is multiple issues per clock to the pipeline, which is capable of integer, single-precision, and double-precision floating-point operations, SIMD branching functions, logical operations, transcendental operations, and other operations. In at least one embodiment, while waiting for data from memory or one of the shared functions, dependency logic within execution units 2708A-2708N causes the waiting thread to sleep until the requested data is returned. In at least one embodiment, while the waiting thread is sleeping, hardware resources can be dedicated to processing other threads. For example, in at least one embodiment, during the delay associated with vertex shader operations, the execution unit can perform operations on a pixel shader, a fragment shader, or another type of shader program (including a different vertex shader).

[0392] In at least one embodiment, each of execution units 2708A-2708N operates on an array of data elements. In at least one embodiment, the number of data elements is the "execution size" or number of lanes of an instruction. In at least one embodiment, an execution lane is the logic used to perform data element access, masking, and flow control within an instruction. In at least one embodiment, the number of lanes can be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) used for a particular graphics processor. In at least one embodiment, execution units 2708A-2708N support integer and floating point data types.

[0393] In at least one embodiment, the execution unit instruction set includes SIMD instructions. In at least one embodiment, various data elements can be stored in registers as packed data types, and the execution unit will process various elements based on the data size of those elements. For example, in at least one embodiment, when a 256-bit wide vector is operated, 256 bits of the vector are stored in registers, and the execution unit operates on the vector as four separate 64-bit packed data elements (quad word (QW) size data elements), eight separate 32-bit packed data elements (double word (DW) size data elements), sixteen separate 16-bit packed data elements (word (W) size data elements) or thirty-two separate 8-bit data elements (byte (B) size data elements). However, in at least one embodiment, different vector widths and register sizes are possible.

[0394] In at least one embodiment, one or more execution units can be combined into fused execution units 2709A-2709N with thread control logic (2707A-2707N) that typically fuse EUs. In at least one embodiment, multiple EUs can be fused into a single EU group. In at least one embodiment, the number of EUs in a fused EU group can be configured to execute separate SIMD hardware threads. The number of EUs in a fused EU group may vary depending on the various embodiments. In at least one embodiment, each EU can execute various SIMD widths, including but not limited to SIMD8, SIMD16, and SIMD32. In at least one embodiment, each fused graphics execution unit 2709A-2709N includes at least two execution units. For example, in at least one embodiment, the fused execution unit 2709A includes a first EU 2708A, a second EU 2708B, and thread control logic 2707A shared by the first EU 2708A and the second EU 2708B. In at least one embodiment, thread control logic 2707A controls threads executing on fused graphics execution unit 2709A, allowing each EU within fused execution units 2709A-2709N to execute using a common instruction pointer register.

[0395] In at least one embodiment, one or more internal instruction caches (e.g., 2706) are included in thread execution logic 2700 to cache thread instructions for the execution units. In at least one embodiment, one or more data caches (e.g., 2712) are included to cache thread data during thread execution. In at least one embodiment, a sampler 2710 is included to provide texture sampling for 3D operations and media sampling for media operations. In at least one embodiment, sampler 2710 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution units.

[0396] During execution, in at least one embodiment, the graphics and media pipeline sends thread initiation requests to thread execution logic 2700 via thread spawning and dispatching logic. In at least one embodiment, once a set of geometric objects has been processed and rasterized into pixel data, pixel processor logic (e.g., pixel shader logic, fragment shader logic, etc.) within shader processor 2702 is invoked to further calculate output information and cause the results to be written to output surfaces (e.g., color buffer, depth buffer, stencil buffer, etc.). In at least one embodiment, the pixel shader or frag...

Claims

1. A parallel processor, comprising: One or more circuits for performing precoding on a fifth generation (5G) downlink signal in parallel using two or more processing threads, wherein the two or more processing threads are used to generate precoder weights by at least processing an augmented matrix comprising a plurality of tiled matrices.

2. The parallel processor according to claim 1, wherein: The two or more processing threads are used to generate the precoder weights by at least processing a plurality of matrices combined into memory locations.

3. The parallel processor according to claim 2, wherein: The plurality of matrices includes a downlink channel estimation matrix.

4. The parallel processor according to claim 2, wherein: The two or more processing threads are used to perform decomposition of an augmented matrix including the plurality of matrices.

5. The parallel processor of claim 4, wherein: The decomposition is a bottom-up decomposition.

6. The parallel processor of claim 5, wherein: The two or more processing threads are used to store an intermediate matrix generated by lower-up decomposition of the augmented matrix in the memory location.

7. The parallel processor of claim 6, wherein: The two or more processing threads are used to generate the precoder weights based at least in part on the intermediate matrix.

8. The parallel processor of claim 2, wherein: The two or more processing threads are used to send the precoder weights to a remote radio head.

9. A system comprising: one or more processors for performing precoding on a fifth generation (5G) downlink signal using two or more processing threads in parallel to generate at least precoder weights; as well as one or more memories for storing the precoder weights; The two or more processing threads are configured to generate the precoder weights by at least processing a plurality of matrices combined into a memory location, wherein the plurality of matrices include a downlink channel estimation matrix and an identity matrix.

10. The system of claim 9, wherein: The plurality of matrices are combined into an augmented matrix in the memory location, and the two or more processing threads are used to perform a decomposition of the augmented matrix.

11. The system of claim 10, wherein: The decomposition is a bottom-up decomposition.

12. The system of claim 10, wherein: The two or more processing threads are used to store an intermediate matrix generated by decomposition of the augmented matrix in the memory location.

13. The system of claim 12, wherein: The two or more processing threads are used to generate the precoder weights based at least in part on the intermediate matrix.

14. The system of claim 9, wherein: The two or more processing threads are used to compress the precoder weights.

15. A machine-readable medium having stored thereon a set of instructions which, if executed, cause a parallel processor to at least: performing precoding on a fifth generation (5G) downlink signal using two or more processing threads in parallel, in, The two or more processing threads are used to generate precoder weights by at least processing a plurality of matrices combined into a memory location, wherein the plurality of matrices are combined into an augmented matrix in the memory location.

16. The machine-readable medium of claim 15, wherein: The plurality of matrices include a downlink channel estimation matrix and an enhanced Gram matrix.

17. The machine-readable medium of claim 16, wherein: The enhanced Gram matrix is ​​based at least in part on a downlink channel estimate matrix and a conjugate transpose of the downlink channel estimate matrix.

18. The machine-readable medium of claim 15, wherein: The two or more processing threads are used to generate an intermediate matrix based at least in part on performing a bottom-up decomposition of the augmented matrix.

19. The machine-readable medium of claim 18, wherein: The two or more processing threads are used to generate the precoder weights based at least in part on the intermediate matrix.

20. The machine-readable medium of claim 19, wherein: The augmented matrix is ​​a first augmented matrix, the intermediate matrix is ​​a second augmented matrix, and the two or more processing threads are used to generate the precoder weights based at least in part on generating a conjugate transposed matrix of a first portion of the second augmented matrix and performing a matrix multiplication operation based at least in part on the generated conjugate transposed matrix.

21. A precoding method, comprising: Precoding a fifth generation (5G) downlink signal is performed in parallel using two or more processing threads, wherein the two or more processing threads are used to generate precoder weights by at least processing multiple matrices combined into a memory location, wherein the memory location is a shared memory location accessible to a parallel processor running the two or more processing threads.

22. The method of claim 21, wherein: The plurality of matrices include a downlink channel estimation matrix, an enhanced Gram matrix, and an identity matrix.

23. The method of claim 21, wherein: The plurality of matrices are combined into an augmented matrix in the memory location, and the two or more processing threads are used to generate an intermediate matrix and store the intermediate matrix in the memory location.

24. The method of claim 23, wherein: The two or more processing threads are used to generate the intermediate matrix by performing a decomposition of the augmented matrix.

25. The method of claim 21, further comprising: compressing the precoder weights; as well as The compressed precoder weights are sent to the remote radio head.

26. The method of claim 21, wherein: The two or more processing threads are executed on a graphics processing unit (GPU).

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