I2C communication method, system, device and medium

Abstract

The present invention discloses an I2C communication method, comprising the following steps: a data sender reads a first encryption key in a register and inserts false data into the data to be transmitted using the first encryption key; the data sender sends the data to be transmitted with the false data to a data receiver according to the I2C bus communication rule; the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted. The present invention also discloses a system, a computer device, and a readable storage medium. The scheme proposed by the present invention can perform out-of-order transmission of the data to be transmitted, that is, fill false data between the real data, and delete the false data at the data receiving end to obtain the complete data to be transmitted, thereby preventing the data from being stolen.

Description

Technical Field

[0001] The present invention relates to the I2C field, and in particular to an I2C communication method, system, device and storage medium. Background Art

[0002] I2C (Inter-Integrated Circuit) bus is a two-wire serial bus developed by PHILIPS, used to connect microcontrollers and their peripherals. It is a bus standard widely used in the field of microelectronic communication control. It is a special form of synchronous communication with the advantages of fewer interface lines, simple control method, small device package, and higher communication rate.

[0003] I2C transfers information between devices connected to the bus through the serial data (SDA) line and the serial clock (SCL) line. Each device is identified by a unique address and can act as a transmitter or receiver (depending on the function of the device). The host is the device that initializes the data transfer on the bus and generates the clock signal that allows the transfer. At this time, any addressed device is considered a slave.

[0004] Normally, the I2C link is relatively simple, with one master and multiple slaves. Due to its slow speed and the large number of devices mounted on the same link, data communication is subject to great risks. Common risks include invading the slave devices on the link through technical means and physically connecting the I2C link. In this way, even if the transmitted data is encrypted using traditional encryption methods, the data packets can be obtained by other slave devices on the link, and then decrypted by decryption means, thereby stealing the communication data.

[0005] Therefore, due to the I2C data transmission method and the easy acquisition of data packets, it is impossible to guarantee that the data is truly safe and reliable. Moreover, since the logic of I2C devices is generally simple and difficult to carry complex encryption algorithms, a safe and reliable I2C communication method is needed. Summary of the invention

[0006] In view of this, in order to overcome at least one aspect of the above problems, an embodiment of the present invention proposes an I2C communication method, comprising the following steps:

[0007] The data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted;

[0008] The data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules;

[0009] The data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.

[0010] In some embodiments, it also includes:

[0011] The data sender obtains a second encryption key and uses the second encryption key to encrypt the communication data to obtain the data to be transmitted;

[0012] The data receiver obtains the second encryption key and uses the second encryption key to decrypt the real data to obtain the communication data.

[0013] In some embodiments, it also includes:

[0014] Get configuration parameters;

[0015] Determine whether to encrypt and the encryption level based on configuration parameters;

[0016] In response to encryption being determined according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level and written into the register as a first encryption key.

[0017] In some embodiments, the data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted, further comprising:

[0018] In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted;

[0019] In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

[0020] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0021] adjusting a response time threshold of the data receiver;

[0022] Get the generated random number;

[0023] The clock of the corresponding bit is stretched according to the random number to extend the clock length corresponding to the bit data, wherein the extended time length is less than the time threshold.

[0024] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0025] Get the generated random number;

[0026] The start and end signals are sent before sending the data corresponding to the random number, and the data corresponding to the random number is sent after sending the end signal.

[0027] In some embodiments, it also includes:

[0028] In response to the data receiving party receiving the end signal, determining whether the number of bits of the currently received data is a preset number of bits;

[0029] In response to the number of bits of the currently received data not being the preset number of bits, the end signal is ignored to continue receiving the next bit of data.

[0030] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides an I2C communication system, including:

[0031] an encryption module configured to enable a data sender to read a first encryption key in a register and insert false data into data to be transmitted using the first encryption key;

[0032] A sending module, configured to enable the data sender to send the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules;

[0033] The decryption module is configured to enable the data receiver to read the first encryption key in the register and extract real data from the received data according to the first encryption key to obtain the data to be transmitted.

[0034] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer device, including:

[0035] at least one processor; and

[0036] A memory storing a computer program executable on the processor, wherein the processor executes the following steps when executing the program:

[0037] The data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted;

[0038] The data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules;

[0039] The data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.

[0040] In some embodiments, it also includes:

[0041] The data sender obtains a second encryption key and uses the second encryption key to encrypt the communication data to obtain the data to be transmitted;

[0042] The data receiver obtains the second encryption key and uses the second encryption key to decrypt the real data to obtain the communication data.

[0043] In some embodiments, it also includes:

[0044] Get configuration parameters;

[0045] Determine whether to encrypt and the encryption level based on configuration parameters;

[0046] In response to encryption being determined according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level and written into the register as a first encryption key.

[0047] In some embodiments, the data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted, further comprising:

[0048] In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted;

[0049] In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

[0050] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0051] adjusting a response time threshold of the data receiver;

[0052] Get the generated random number;

[0053] The clock of the corresponding bit is stretched according to the random number to extend the clock length corresponding to the bit data, wherein the extended time length is less than the time threshold.

[0054] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0055] Get the generated random number;

[0056] The start and end signals are sent before sending the data corresponding to the random number, and the data corresponding to the random number is sent after sending the end signal.

[0057] In some embodiments, it also includes:

[0058] In response to the data receiving party receiving the end signal, determining whether the number of bits of the currently received data is a preset number of bits;

[0059] In response to the number of bits of the currently received data not being the preset number of bits, the end signal is ignored to continue receiving the next bit of data.

[0060] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the following steps are performed:

[0061] The data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted;

[0062] The data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules;

[0063] The data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.

[0064] In some embodiments, it also includes:

[0065] The data sender obtains a second encryption key and uses the second encryption key to encrypt the communication data to obtain the data to be transmitted;

[0066] The data receiver obtains the second encryption key and uses the second encryption key to decrypt the real data to obtain the communication data.

[0067] In some embodiments, it also includes:

[0068] Get configuration parameters;

[0069] Determine whether to encrypt and the encryption level based on configuration parameters;

[0070] In response to encryption being determined according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level and written into the register as a first encryption key.

[0071] In some embodiments, the data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted, further comprising:

[0072] In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted;

[0073] In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

[0074] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0075] adjusting a response time threshold of the data receiver;

[0076] Get the generated random number;

[0077] The clock of the corresponding bit is stretched according to the random number to extend the clock length corresponding to the bit data, wherein the extended time length is less than the time threshold.

[0078] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0079] Get the generated random number;

[0080] The start and end signals are sent before sending the data corresponding to the random number, and the data corresponding to the random number is sent after sending the end signal.

[0081] In some embodiments, it also includes:

[0082] In response to the data receiving party receiving the end signal, determining whether the number of bits of the currently received data is a preset number of bits;

[0083] In response to the number of bits of the currently received data not being the preset number of bits, the end signal is ignored to continue receiving the next bit of data.

[0084] The present invention has one of the following beneficial technical effects: the scheme proposed in the present invention can transmit the data to be transmitted out of order, that is, fill false data between real data, and delete the false data at the data receiving end to obtain the complete data to be transmitted, thereby preventing the data from being stolen. BRIEF DESCRIPTION OF THE DRAWINGS

[0085] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.

[0086] Figure 1 A schematic diagram of a flow chart of an I2C communication method provided by an embodiment of the present invention;

[0087] Figure 2 The I2C link structure provided by the embodiment of the present invention is intended;

[0088] Figure 3 A schematic diagram of stretching a clock corresponding to one bit of data;

[0089] Figure 4 This is a schematic diagram of generating a short Start / Stop signal before one of the data bits;

[0090] Figure 5 A schematic diagram of the structure of an I2C communication system according to an embodiment of the present invention;

[0091] Figure 6 A schematic diagram of the structure of a computer device provided by an embodiment of the present invention;

[0092] Figure 7 A schematic diagram of the structure of a computer-readable storage medium provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0093] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0094] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.

[0095] In the embodiment of the present invention, the Master is a master device, that is, a party that initiates communication in I2C communication, and the Slave is a slave device, that is, a party that receives communication in the I2C bus.

[0096] According to one aspect of the present invention, an embodiment of the present invention provides an I2C communication method, such as Figure 1 As shown, it may include the steps of:

[0097] S1, a data sender reads a first encryption key in a register and uses the first encryption key to insert false data into the data to be transmitted;

[0098] S2, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules;

[0099] S3, the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.

[0100] The solution proposed in the present invention can transmit the data to be transmitted out of order, that is, fill false data between real data, and delete the false data at the data receiving end to obtain the complete data to be transmitted, so that the data receiving end that does not have the secret key cannot obtain the complete data packet, thereby preventing the data from being stolen.

[0101] In some embodiments, when data is read, the reading process of I2C is:

[0102] 1.Master sends I2C addr (7bit) and w operation 1 (1bit), and waits for ACK;

[0103] 2.Slave sends ACK;

[0104] 3.Master sends regaddr (8 bits) and waits for ACK;

[0105] 4.Slave sends ACK;

[0106] 5.Master initiates START;

[0107] 6.Master sends I2Caddr (7bit) and r operation 1 (1bit), and waits for ACK;

[0108] 7.Slave sends ACK;

[0109] 8.Slave sends data (8 bits), which is the value in the register;

[0110] 9.Master sends ACK;

[0111] 10. Steps 8 and 9 can be repeated multiple times, that is, multiple registers are read sequentially.

[0112] Therefore, the master device can act as a data receiver and the slave device can act as a data transmitter.

[0113] When writing data, the writing process of I2C is:

[0114] 1.Master initiates START

[0115] 2.Master sends I2Caddr (7bit) and w operation 0 (1bit), waiting for ACK

[0116] 3.Slave sends ACK

[0117] 4.Master sends regaddr (8 bits) and waits for ACK

[0118] 5.Slave sends ACK

[0119] 6.Master sends data (8 bits), that is, the data to be written into the register, and waits for ACK

[0120] 7.Slave sends ACK

[0121] 8. Steps 6 and 7 can be repeated multiple times, that is, write multiple registers in sequence

[0122] 9.Master initiates STOP

[0123] Therefore, the master device can act as a data transmitter and the slave device can act as a data receiver.

[0124] In some embodiments, it also includes:

[0125] The data sender obtains a second encryption key and uses the second encryption key to encrypt the communication data to obtain the data to be transmitted;

[0126] The data receiver obtains the second encryption key and uses the second encryption key to decrypt the real data to obtain the communication data.

[0127] Specifically, the communication data can be encrypted with the first key before transmission, and then the encrypted data can be filled with false data using the second key. In this way, even if the data to be transmitted is stolen, the real data packet cannot be obtained because the data to be transmitted is filled with false data.

[0128] In some embodiments, it also includes:

[0129] Get configuration parameters;

[0130] Determine whether to encrypt and the encryption level based on configuration parameters;

[0131] In response to encryption being determined according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level and written into the register as a first encryption key.

[0132] Specifically, Figure 2 As shown, the master device and the slave device can be connected to the encryption unit through a link other than I2C. The encryption unit includes a key processing unit, a key generator, and a configuration unit. The key generator can be a secure and trusted device such as TCM or TPM of the server. The configuration unit contains some basic functions such as whether the encryption function is turned on or off and the encryption level. The key processing unit is responsible for processing the data into data that conforms to I2C communication. After initialization, the key generator generates a set of random numbers, assuming that there are 16 bits, assuming that it is 0100 0000 1101 1011. The key processing unit will read the configuration parameters of the configuration unit to determine whether the encryption function is turned on and the encryption level. Assuming that the configuration item is to turn on the encryption function, the encryption level is a choice of two, that is, one of the two numbers is selected. Then the key processing unit will intercept the first half of the data of the key generator, that is, 01100000. After processing, the data is stored in the register and can be read by the I2C master device and slave device.

[0133] In some embodiments, the data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted, further comprising:

[0134] In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted;

[0135] In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

[0136] Specifically, the main device encrypts and transmits the data according to the data sent by the encryption unit.

[0137] For example, if the data to be transmitted is 11110101, the value of each bit of the secret key is 0 or 1, which means the first or last bit is real data. If the first bit of the secret key is 0, the first bit of the transmitted data is real data. If the second bit of the secret key is 1, the fourth bit of the transmitted data is real data. Similarly, the data stream transmitted by I2C is 1X X1 X1 1X 0X 1X 0X1X, and X will be randomly filled with fake data.

[0138] When the slave device with the address of 0101011 receives a write request from the master device, the received data is decrypted according to the secret key. The received data is 1011 0110 0011 0110. The data is processed using the secret key to obtain the data 011110101.

[0139] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0140] adjusting a response time threshold of the data receiver;

[0141] Get the generated random number;

[0142] The clock of the corresponding bit is stretched according to the random number to extend the clock length corresponding to the bit data, wherein the extended time length is less than the time threshold.

[0143] Specifically, the clock can be disrupted to increase the clock length of the response signal. Since I2C transmits 8 bits of data each time, a random number is set each time to randomly stretch the clock corresponding to one bit of data, for example Figure 3 As shown, the clock of the 12th bit of data (equivalent to the 3rd bit of data at one time) is stretched, so that other slave devices cannot receive data because they do not extend the response time threshold.

[0144] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0145] Get the generated random number;

[0146] The start and end signals are sent before sending the data corresponding to the random number, and the data corresponding to the random number is sent after sending the end signal.

[0147] In some embodiments, it also includes:

[0148] In response to the data receiving party receiving the end signal, determining whether the number of bits of the currently received data is a preset number of bits;

[0149] In response to the number of bits of the currently received data not being the preset number of bits, the end signal is ignored to continue receiving the next bit of data.

[0150] Specifically, a Start / Stop signal is generated for the data line, and the slave device with encryption and decryption function will automatically filter out the short Start / Stop signal during the communication process, while the normal slave device will be disturbed. A random number can be generated each time, and the start and end signals are sent before sending the data corresponding to the random number, so that other slave devices cannot ignore the short Start / Stop signal and are disturbed. The communicating slave device can automatically filter out the Start / Stop signal because the received data does not reach the preset number of bits. For example, Figure 4 As shown in FIG. 1 , a Start / Stop signal is generated before the 12th bit of data (equivalent to the 3rd bit of data at one time), so that other slave devices will be disturbed.

[0151] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides an I2C communication system 400, such as Figure 5 As shown, including:

[0152] The encryption module 401 is configured to enable the data sender to read the first encryption key in the register and insert false data into the data to be transmitted using the first encryption key;

[0153] The sending module 402 is configured to enable the data sender to send the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules;

[0154] The decryption module 403 is configured to enable the data receiver to read the first encryption key in the register and extract real data from the received data according to the first encryption key to obtain the data to be transmitted.

[0155] In some embodiments, a second encryption model is further included, configured to:

[0156] The data sender obtains a second encryption key and uses the second encryption key to encrypt the communication data to obtain the data to be transmitted;

[0157] The data receiver obtains the second encryption key and uses the second encryption key to decrypt the real data to obtain the communication data.

[0158] In some embodiments, an initialization module is further included, configured to:

[0159] Get configuration parameters;

[0160] Determine whether to encrypt and the encryption level based on configuration parameters;

[0161] In response to encryption being determined according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level and written into the register as a first encryption key.

[0162] In some embodiments, the encryption module 401 is further configured to:

[0163] In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted;

[0164] In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

[0165] In some embodiments, the sending module 402 is further configured to:

[0166] adjusting a response time threshold of the data receiver;

[0167] Get the generated random number;

[0168] The clock of the corresponding bit is stretched according to the random number to extend the clock length corresponding to the bit data, wherein the extended time length is less than the time threshold.

[0169] In some embodiments, the sending module 402 is further configured to:

[0170] Get the generated random number;

[0171] The start and end signals are sent before sending the data corresponding to the random number, and the data corresponding to the random number is sent after sending the end signal.

[0172] In some embodiments, the sending module 402 is further configured to:

[0173] In response to the data receiving party receiving the end signal, determining whether the number of bits of the currently received data is a preset number of bits;

[0174] In response to the number of bits of the currently received data not being the preset number of bits, the end signal is ignored to continue receiving the next bit of data.

[0175] Based on the same inventive concept, according to another aspect of the present invention, Figure 6 As shown, an embodiment of the present invention further provides a computer device 501, including:

[0176] at least one processor 520; and

[0177] The memory 510 stores a computer program 511 that can be run on the processor. When the processor 520 executes the program, the following steps are performed:

[0178] S1, a data sender reads a first encryption key in a register and uses the first encryption key to insert false data into the data to be transmitted;

[0179] S2, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules;

[0180] S3, the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.

[0181] In some embodiments, it also includes:

[0182] The data sender obtains a second encryption key and uses the second encryption key to encrypt the communication data to obtain the data to be transmitted;

[0183] The data receiver obtains the second encryption key and uses the second encryption key to decrypt the real data to obtain the communication data.

[0184] In some embodiments, it also includes:

[0185] Get configuration parameters;

[0186] Determine whether to encrypt and the encryption level based on configuration parameters;

[0187] In response to encryption being determined according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level and written into the register as a first encryption key.

[0188] In some embodiments, the data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted, further comprising:

[0189] In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted;

[0190] In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

[0191] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0192] adjusting a response time threshold of the data receiver;

[0193] Get the generated random number;

[0194] The clock of the corresponding bit is stretched according to the random number to extend the clock length corresponding to the bit data, wherein the extended time length is less than the time threshold.

[0195] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0196] Get the generated random number;

[0197] The start and end signals are sent before sending the data corresponding to the random number, and the data corresponding to the random number is sent after sending the end signal.

[0198] In some embodiments, it also includes:

[0199] In response to the data receiving party receiving the end signal, determining whether the number of bits of the currently received data is a preset number of bits;

[0200] In response to the number of bits of the currently received data not being the preset number of bits, the end signal is ignored to continue receiving the next bit of data.

[0201] Based on the same inventive concept, according to another aspect of the present invention, Figure 7 As shown, an embodiment of the present invention further provides a computer-readable storage medium 601, wherein the computer-readable storage medium 601 stores computer program instructions 610, and when the computer program instructions 610 are executed by a processor, the following steps are performed:

[0202] S1, a data sender reads a first encryption key in a register and uses the first encryption key to insert false data into the data to be transmitted;

[0203] S2, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules;

[0204] S3, the data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted.

[0205] In some embodiments, it also includes:

[0206] The data sender obtains a second encryption key and uses the second encryption key to encrypt the communication data to obtain the data to be transmitted;

[0207] The data receiver obtains the second encryption key and uses the second encryption key to decrypt the real data to obtain the communication data.

[0208] In some embodiments, it also includes:

[0209] Get configuration parameters;

[0210] Determine whether to encrypt and the encryption level based on configuration parameters;

[0211] In response to encryption being determined according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level and written into the register as a first encryption key.

[0212] In some embodiments, the data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted, further comprising:

[0213] In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted;

[0214] In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

[0215] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0216] adjusting a response time threshold of the data receiver;

[0217] Get the generated random number;

[0218] The clock of the corresponding bit is stretched according to the random number to extend the clock length corresponding to the bit data, wherein the extended time length is less than the time threshold.

[0219] In some embodiments, the data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising:

[0220] Get the generated random number;

[0221] The start and end signals are sent before sending the data corresponding to the random number, and the data corresponding to the random number is sent after sending the end signal.

[0222] In some embodiments, it also includes:

[0223] In response to the data receiving party receiving the end signal, determining whether the number of bits of the currently received data is a preset number of bits;

[0224] In response to the number of bits of the currently received data not being the preset number of bits, the end signal is ignored to continue receiving the next bit of data.

[0225] Finally, it should be noted that a person skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be implemented by instructing related hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods.

[0226] Furthermore, it should be appreciated that the computer-readable storage medium (eg, memory) herein may be either a volatile memory or a nonvolatile memory, or may include both volatile and nonvolatile memory.

[0227] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.

[0228] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope disclosed in the embodiments of the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.

[0229] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.

[0230] The serial numbers of the embodiments disclosed in the above embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0231] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware or by instructing related hardware through a program, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0232] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the embodiments of the present invention as above, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.

Claims

1. An I2C communication method, characterized in that: The following steps are involved: The data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted; The data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules; The data receiver reads the first encryption key in the register and extracts real data from the received data according to the first encryption key to obtain the data to be transmitted; The data sender reads the first encryption key in the register and uses the first encryption key to insert false data into the data to be transmitted, further comprising: In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted; In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

2. The method according to claim 1, characterized in that Also includes: The data sender obtains a second encryption key and uses the second encryption key to encrypt the communication data to obtain the data to be transmitted; The data receiver obtains the second encryption key and uses the second encryption key to decrypt the real data to obtain the communication data.

3. The method according to claim 1, characterized in that Also includes: Get configuration parameters; Determine whether to encrypt and the encryption level based on configuration parameters; In response to encryption being determined according to the configuration parameters, a corresponding portion is selected from the generated initial key according to the encryption level and written into the register as a first encryption key.

4. The method according to claim 1, characterized in that The data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising: adjusting a response time threshold of the data receiver; Get the generated random number; The clock of the corresponding bit is stretched according to the random number to extend the clock length corresponding to the bit data, wherein the extended time length is less than the time threshold.

5. The method according to claim 1, characterized in that The data sender sends the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules, further comprising: Get the generated random number; The start and end signals are sent before sending the data corresponding to the random number, and the data corresponding to the random number is sent after sending the end signal.

6. The method according to claim 5, characterized in that Also includes: In response to the data receiving party receiving the end signal, determining whether the number of bits of the currently received data is a preset number of bits; In response to the number of bits of the currently received data not being the preset number of bits, the end signal is ignored to continue receiving the next bit of data.

7. An I2C communication system, characterized in that: include: an encryption module configured to enable a data sender to read a first encryption key in a register and insert false data into data to be transmitted using the first encryption key; A sending module, configured to enable the data sender to send the data to be transmitted together with the false data to the data receiver according to the I2C bus communication rules; a decryption module, configured to enable the data receiver to read the first encryption key in the register and extract real data from the received data according to the first encryption key to obtain the data to be transmitted; The cryptographic module is also configured as: In response to the value of the first encryption key being a first preset value, inserting random false data on the left side of the corresponding bit data of the data to be transmitted; In response to the value of the first encryption key being a second preset value, random false data is inserted at the right side of corresponding bit data of the data to be transmitted.

8. A computer device comprising: at least one processor; as well as A memory storing a computer program executable on the processor, wherein the processor executes the steps of the method according to any one of claims 1 to 6 when executing the program.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 6 are performed.

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