Display device and method for manufacturing the same

Abstract

The display device may include: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas, each of the plurality of pixel areas including a light-emitting area; and pixels disposed in each of the plurality of pixel areas. The pixel may include: a first electrode; a second electrode surrounding the periphery of the first electrode while being spaced apart from the first electrode; a third electrode surrounding the periphery of the second electrode while being spaced apart from the second electrode; a fourth electrode surrounding the periphery of the third electrode while being spaced apart from the third electrode; a plurality of light-emitting elements disposed between the first electrode and the fourth electrode; and a first conductive wire and a second conductive wire disposed under the first electrode to the fourth electrode, and an insulating layer is disposed between the first conductive wire and the second conductive wire and the first electrode to the fourth electrode. The first conductive wire may be electrically connected to the first electrode, and the second conductive wire may be electrically connected to the fourth electrode.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0002] As the interest in information display increases and the demand for using portable information media increases, the demand and commercialization of display devices have become the focus. Summary of the Invention

[0003] Technical Problem

[0004] An object of the present disclosure is to provide a display device having improved light output efficiency and a method of manufacturing the display device.

[0005] Technical Solution

[0006] According to an embodiment of the present disclosure, a display device may include: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas each including an emission area; and pixels disposed in each of the plurality of pixel areas.

[0007] In an embodiment of the present disclosure, a pixel may include: a first electrode; a second electrode spaced apart from the first electrode and surrounding the periphery of the first electrode; a third electrode spaced apart from the second electrode and surrounding the periphery of the second electrode; a fourth electrode spaced apart from the third electrode and surrounding the periphery of the third electrode; a plurality of light-emitting elements disposed between the first electrode and the fourth electrode; and a first conductive wire and a second conductive wire disposed below the first electrode and the fourth electrode, and an insulating layer is disposed between the first conductive wire and the second conductive wire and the first electrode and the fourth electrode. Here, the first conductive wire may be electrically connected to the first electrode, and the second conductive wire may be electrically connected to the fourth electrode.

[0008] In an embodiment of the present disclosure, when viewed in a plan view, each of the second electrode to the fourth electrode may have an annular shape, and the first electrode may have an isolated circular island shape surrounded by the second electrode to the fourth electrode.

[0009] In an embodiment of the present disclosure, the light-emitting element may include: a first light-emitting element disposed between the first electrode and the second electrode; a second light-emitting element disposed between the second electrode and the third electrode; and a third light-emitting element disposed between the third electrode and the fourth electrode.

[0010] In an embodiment of the present disclosure, the first light-emitting element may be disposed between the first electrode and the second electrode along a circumferential direction centered on the first electrode, the second light-emitting element may be disposed between the second electrode and the third electrode along a circumferential direction centered on the second electrode, and the third light-emitting element may be disposed between the third electrode and the fourth electrode along a circumferential direction centered on the third electrode.

[0011] In an embodiment of the present disclosure, the first conductive wire and the second conductive wire may be disposed on the same layer.

[0012] In an embodiment of the present disclosure, the first conductive wire and the second conductive wire may be disposed on different layers.

[0013] In an embodiment of the present disclosure, the insulating layer may include a first insulating layer and a second insulating layer sequentially stacked on a substrate.

[0014] In an embodiment of the present disclosure, the first conductive wire may be disposed on one of the first insulating layer and the second insulating layer, and the second conductive wire may be disposed on the other of the first insulating layer and the second insulating layer.

[0015] In an embodiment of the present disclosure, the pixel may further include: a third conductive wire connected to the second electrode, with an insulating layer disposed between the third conductive wire and the second electrode; and a fourth conductive wire connected to the third electrode, with an insulating layer disposed between the fourth conductive wire and the third electrode. Here, the third conductive wire and the fourth conductive wire may be in a floating state.

[0016] In an embodiment of the present disclosure, the third conductive wire and the fourth conductive wire may be disposed on the same layer as the first conductive wire and the second conductive wire.

[0017] In an embodiment of the present disclosure, the third conductive wire and the fourth conductive wire may be disposed on different layers.

[0018] In an embodiment of the present disclosure, the first light-emitting element may form a first stage connected in parallel between the first electrode and the second electrode, the second light-emitting element may form a second stage connected in parallel between the second electrode and the third electrode, and the third light-emitting element may form a third stage connected in parallel between the third electrode and the fourth electrode.

[0019] In an embodiment of the present disclosure, the pixel may further include: a bank pattern disposed under each of the first electrode to the fourth electrode; and contact electrodes respectively disposed on the first electrode to the fourth electrode.

[0020] In an embodiment of the present disclosure, the second electrode may include a 2-1 electrode surrounding one region of the first electrode and a 2-2 electrode spaced apart from the 2-1 electrode and surrounding another region of the first electrode. The third electrode may include a 3-1 electrode surrounding one region of the second electrode and a 3-2 electrode spaced apart from the 3-1 electrode and surrounding another region of the second electrode.

[0021] In an embodiment of the present disclosure, the 2-2 electrode and the 3-2 electrode may be in a floating state.

[0022] In an embodiment of the present disclosure, the 2-2 electrode may be connected to the second conductive wire, and the 3-2 electrode may be connected to the first conductive wire.

[0023] In an embodiment of the present disclosure, the first conductive wire and the second conductive wire may be disposed on the same layer.

[0024] In an embodiment of the present disclosure, the pixel may further include a pixel circuit portion including at least one transistor electrically connected to the fourth electrode. Here, the first electrode may be the cathode electrode of the pixel, and the fourth electrode may be the anode electrode of the pixel.

[0025] The above display device may be manufactured by providing pixels including a pixel region. The step of providing pixels may include forming a pixel circuit portion and forming a display element portion.

[0026] The step of forming the pixel circuit portion includes: forming at least one transistor and first to fourth conductive wires spaced apart from each other on a substrate; and forming a protective layer on the transistor and the first to fourth conductive wires.

[0027] The step of forming the display element portion may include: forming a first electrode connected to the first conductive wire, a second electrode spaced apart from the first electrode and connected to the second conductive wire, a third electrode spaced apart from the second electrode and connected to the third conductive wire, and a fourth electrode spaced apart from the third electrode and connected to the fourth conductive wire on the protective layer; aligning a plurality of light-emitting elements between the first electrode and the second electrode, between the second electrode and the third electrode, and between the third electrode and the fourth electrode by applying alignment signals corresponding to each of the first to fourth conductive wires; and forming contact electrodes on each of the first to fourth electrodes.

[0028] In an embodiment of the present disclosure, the method may further include removing a part of each of the second conductive wire and the third conductive wire after forming the contact electrodes.

[0029] In an embodiment of the present disclosure, the first electrode may be located at the center of the pixel region, the second electrode may surround the periphery of the first electrode, the third electrode may surround the periphery of the second electrode, and the fourth electrode may surround the periphery of the third electrode.

[0030] Advantageous Effects

[0031] According to an embodiment of the present disclosure, a display device and a method of manufacturing the display device can be provided. The display device and the method of manufacturing the display device can sufficiently ensure an alignment area of a light-emitting element by providing a circular electrode at the center of a pixel area in a pixel area where one pixel is provided and providing at least one annular electrode surrounding the circular electrode, which is advantageous for achieving high resolution and improving light output efficiency.

[0032] The effects according to the embodiments of the present disclosure are not limited to the above-exemplified content, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure.

[0034] Figure 1b is Figure 1a a cross-sectional view of the light-emitting element.

[0035] Figure 2a is a perspective view schematically showing a light-emitting element according to another embodiment of the present disclosure.

[0036] Figure 2b is Figure 2a a cross-sectional view of the light-emitting element.

[0037] Figure 3a is a perspective view schematically showing a light-emitting element according to another embodiment of the present disclosure.

[0038] Figure 3b is Figure 3a a cross-sectional view of the light-emitting element.

[0039] Figure 4a is a perspective view schematically showing a light-emitting element according to still another embodiment of the present disclosure.

[0040] Figure 4b is Figure 4a a cross-sectional view of the light-emitting element.

[0041] Figure 5 is a view showing a display device according to an embodiment of the present disclosure, and particularly a schematic plan view of a display device using any one of the light-emitting elements shown in Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b as a light source.

[0042] Figures 6a to 6e is a circuit diagram showing the electrical connection relationship between components included in one pixel shown in Figure 5 .

[0043] Figures 7a to 7c is a circuit diagram showing the electrical connection relationship between components included in one pixel shown in Figure 5 .

[0044] Figure 8 schematically shows Figure 5 a plan view of one pixel among the pixels shown in

[0045] Fig. 9 is a cross-sectional view taken along line I-I' of Figure 8 .

[0046] Fig.10 is a cross-sectional view taken along line II-II' of Figure 8 .

[0047] Fig.11 is a cross-sectional view corresponding to line II-II' of Fig.10 as an implementation of the first bank shown in Figure 8 .

[0048] Fig.12 is a cross-sectional view corresponding to line II-II' of Fig.10 as an implementation of the display element layer shown in Figure 8 .

[0049] Fig.13 is a cross-sectional view taken along line III-III' and line IV-IV' of Figure 8 .

[0050] Fig.14 is a cross-sectional view corresponding to line I-I' of Fig. 9 as an implementation of the fourth conductive line shown in Figure 8 .

[0051] Fig.15 is a cross-sectional view corresponding to line III-III' and line IV-IV' of Fig.13 as an implementation of the second conductive line shown in Figure 8 .

[0052] Fig.16 is a plan view showing the drive current flowing through a pixel according to an embodiment of the present disclosure, and as an example, shows the flow of the drive current flowing through the pixel of Figure 8 .

[0053] Figures 17a to 17f is a schematic plan view showing the method of manufacturing the pixels shown in Figure 8 .

[0054] Figures 18a to 18h is a sequential illustration of the manufacturing Fig. 9 is a cross-sectional view of the method of manufacturing the pixels shown in

[0055] Fig.19 is a view showing the pixels according to another embodiment Figure 8 , and is a schematic plan view of a pixel including only a partial structure of the display element portion.

[0056] Fig. 20 is a schematic plan view showing the pixels according to still another embodiment.

[0057] Fig.21 is a cross-sectional view taken along the line V-V' of Fig. 20 .

[0058] Fig. 22 is a plan view showing the drive current flowing through the pixels according to an embodiment of the present disclosure, and shows, for example, the flow of the drive current through the pixels of Fig. 20 .

[0059] Fig.23 is a view showing the shape when the light-emitting element is aligned in the pixels of Fig. 20 , and is a schematic plan view of a pixel including only a partial structure of the display element portion. DETAILED DESCRIPTION

[0060] Since the present disclosure can be modified in various ways and has various forms, specific embodiments will be shown in the drawings and described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the specific forms disclosed, and the present disclosure includes all modifications, equivalents, and substitutions within the technical scope of the present disclosure.

[0061] When describing each drawing, like reference numerals are used for like components. In the drawings, for the sake of clarity of the present disclosure, the dimensions of the structures are shown enlarged from the actual dimensions. Terms such as "first", "second", etc. may be used to describe various components, but the components should not be limited by the terms. These terms are only used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present disclosure, the first component may be referred to as the second component, and similarly, the second component may also be referred to as the first component. Unless the context clearly indicates otherwise, the singular expressions include the plural expressions.

[0062] It should be understood that in this application, terms such as "comprising" and "having" are used to specify the presence of features, quantities, steps, operations, components, parts, or combinations thereof described in the specification, but do not exclude the possibility of the pre-existence or addition of one or more other features, quantities, steps, operations, components, parts, or combinations thereof. Additionally, when a part of a layer, film, region, plate, etc. is referred to as being "on" another part, it includes not only the case where this part is "directly on" the other part, but also the case where there is another part between this part and the other part. Further, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming this part on the side or in the downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where this part is "directly under" the other part, but also the case where there is another part between this part and the other part.

[0063] Hereinafter, preferred embodiments of the present disclosure and other matters necessary for those skilled in the art to easily understand the content of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, unless the context clearly indicates otherwise, singular expressions include plural expressions.

[0064] Figure 1a is a perspective view schematically showing a light-emitting element according to an embodiment of the present disclosure, Figure 1b is Figure 1a a cross-sectional view of the light-emitting element of Figure 2a is a perspective view schematically showing a light-emitting element according to another embodiment of the present disclosure, Figure 2b is Figure 2a a cross-sectional view of the light-emitting element of Figure 3a is a perspective view schematically showing a light-emitting element according to another embodiment of the present disclosure, Figure 3b is Figure 3a a cross-sectional view of the light-emitting element of Figure 4a is a perspective view schematically showing a light-emitting element according to yet another embodiment of the present disclosure, and Figure 4b is Figure 4a a cross-sectional view of the light-emitting element of

[0065] For convenience, after describing Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b which show light-emitting elements manufactured by an etching method, Figure 4a and Figure 4b which show light-emitting elements manufactured by a growth method will be described. In the embodiments of the present disclosure, the type and / or shape of the light-emitting element are not limited to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a and Figure 4b the embodiments shown in

[0066] First, referring to Figure 1a , Figure 1b , Figure 2a , Figure 2b , Figure 3a and Figure 3b , the light-emitting element LD may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light-emitting element LD may be implemented as a light-emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0067] According to an embodiment of the present disclosure, the light-emitting element LD extends in one direction. When the extending direction of the light-emitting element LD is referred to as the longitudinal direction, the light-emitting element LD may have one side end and the other side end along the extending direction. Either the first semiconductor layer 11 or the second semiconductor layer 13 may be disposed at one side end of the light-emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 may be disposed at the other side end of the light-emitting element LD.

[0068] The light-emitting element LD may be provided in various shapes. For example, the light-emitting element LD may have a rod shape or a strip shape that is long in the longitudinal direction (i.e., the aspect ratio is greater than 1). In an embodiment of the present disclosure, the length L of the light-emitting element LD in the longitudinal direction may be greater than the diameter D (or the width of the cross section) of the light-emitting element LD. The light-emitting element LD may include, for example, a light-emitting diode that is manufactured to be extremely small to have a diameter D and / or a length L of about the micron scale or the nanometer scale. In an embodiment of the present disclosure, the size of the light-emitting element LD may be changed to meet the required conditions (or design conditions) of an illumination device or a self-luminous display device.

[0069] The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 may include any one of semiconductor materials such as InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include an n-type semiconductor layer doped with a first conductive dopant (such as Si, Ge, or Sn). However, the material constituting the first semiconductor layer 11 is not limited thereto, and various other materials may constitute the first semiconductor layer 11.

[0070] The active layer 12 may be disposed on the first semiconductor layer 11 and may be formed in a single quantum well structure or a multi - quantum well structure. The position of the active layer 12 may be variably changed according to the type of the light - emitting element LD. The active layer 12 may emit light with a wavelength of 400 nm to 900 nm and may have a double - heterostructure. In an embodiment of the present disclosure, a cladding layer (not shown) doped with a conductive dopant may be formed on and / or under the active layer 12. For example, the cladding layer may be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12, and various other materials may constitute the active layer 12.

[0071] When an electric field of a predetermined voltage or higher is applied across the light - emitting element LD, the light - emitting element LD emits light while electron - hole pairs recombine in the active layer 12. By controlling the light emission of the light - emitting element LD using this principle, the light - emitting element LD can be used as a light source for various light - emitting devices including pixels of a display device.

[0072] The second semiconductor layer 13 may be disposed on the active layer 12 and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p - type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p - type semiconductor layer doped with a second conductive dopant such as Mg. However, the material constituting the second semiconductor layer 13 is not limited thereto, and various other materials may constitute the second semiconductor layer 13.

[0073] In an embodiment of the present disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) from each other in the length L direction of the light - emitting element LD. For example, along the length L direction of the light - emitting element LD, the first semiconductor layer 11 may have a relatively wider width (or thicker thickness) than the width (or thickness) of the second semiconductor layer 13. Thus, as Figures 1a to 3b shown, the active layer 12 of the light - emitting element LD may be positioned closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11.

[0074] According to an embodiment of the present disclosure, in addition to the above - mentioned first semiconductor layer 11, active layer 12, and second semiconductor layer 13, the light - emitting element LD may further include an additional electrode 15 disposed on the second semiconductor layer 13. Additionally, according to an embodiment, as Figure 3a and Figure 3b shown, the light - emitting element LD may further include another additional electrode 16 disposed at one end of the first semiconductor layer 11.

[0075] The additional electrodes 15 and 16 may be ohmic contact electrodes, but are not limited thereto, and may be Schottky contact electrodes according to embodiments. The additional electrodes 15 and 16 may include a metal or a metal oxide. For example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), their oxides or alloys, ITO, etc. may be used alone or in combination, but the present disclosure is not limited thereto.

[0076] The materials included in each of the additional electrodes 15 and 16 may be the same as or different from each other. The additional electrodes 15 and 16 may be substantially transparent or translucent. Thus, the light generated by the light-emitting element LD can pass through the additional electrodes 15 and 16 and can be emitted to the outside of the light-emitting element LD. According to an embodiment, when the light generated by the light-emitting element LD does not pass through the additional electrodes 15 and 16 and is emitted to the outside of the light-emitting element LD through a region other than both ends of the light-emitting element LD, the additional electrodes 15 and 16 may include an opaque metal.

[0077] In an embodiment of the present disclosure, the light-emitting element LD may further include an insulating film 14. However, according to an embodiment, the insulating film 14 may be omitted and may be provided to cover only a part of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0078] The insulating film 14 may prevent an electrical short circuit that may occur when the active layer 12 comes into contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, by forming the insulating film 14, the lifetime and efficiency of the light-emitting element LD can be improved by minimizing surface defects of the light-emitting element LD. In addition, when a plurality of light-emitting elements LD are closely arranged, the insulating film 14 may prevent an undesired short circuit that may occur between the light-emitting elements LD. When the active layer 12 can prevent a short circuit with an external conductive material, the presence or absence of the insulating film 14 is not limited.

[0079] As Figure 1a and Figure 1b shown, the insulating film 14 may be provided in a form that completely surrounds the outer circumferential surface of the light-emitting stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15. For ease of description, a part of the insulating film 14 is removed in Figure 1a and the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15 included in the actual light-emitting element LD may be surrounded by the insulating film 14.

[0080] In the above embodiment, the insulating film 14 completely surrounds the outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15, but the present disclosure is not limited thereto.

[0081] According to an embodiment, as Figure 2a and Figure 2b shown, the insulating film 14 may surround the outer circumferential surfaces of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, and may not completely surround the outer circumferential surface of the additional electrode 15 provided on the second semiconductor layer 13, or may surround only a part of the outer circumferential surface of the additional electrode 15 and may not surround the remaining part of the outer circumferential surface of the additional electrode 15. However, the insulating film 14 may expose at least both ends of the light-emitting element LD. For example, the insulating film 14 may expose one end of the first semiconductor layer 11 together with the additional electrode 15 provided at one end side of the second semiconductor layer 13. Additionally, according to an embodiment, as Figure 3a and Figure 3b shown, when the additional electrodes 15 and 16 are provided at both ends of the light-emitting element LD, the insulating film 14 may expose at least one region of each of the additional electrodes 15 and 16. Alternatively, in another embodiment, the insulating film 14 may not be provided.

[0082] According to an embodiment of the present disclosure, the insulating film 14 may include a transparent insulating material. For example, the insulating film 14 may include one or more insulating materials selected from the group consisting of SiO 2 、Si 3 N 4 、Al 2 O 3 and TiO 2 ,but is not limited thereto, and various materials having insulating properties may be used.

[0083] When the insulating film 14 is provided to the light-emitting element LD, a short circuit between the active layer 12 and the first electrode and / or the second electrode (not shown) can be prevented. Additionally, by forming the insulating film 14, the lifetime and efficiency of the light-emitting element LD can be improved by minimizing surface defects of the light-emitting element LD. Additionally, when a plurality of light-emitting elements LD are closely arranged, the insulating film 14 can prevent an undesired short circuit that may occur between the light-emitting elements LD.

[0084] The above-described light-emitting element LD can be used as a light source for various display devices. The light-emitting element LD can be manufactured by a surface treatment process. For example, when a plurality of light-emitting elements LD are mixed in a fluid solution (or solvent) and supplied to each emission region (e.g., the emission region of each pixel or the emission region of each sub-pixel), surface treatment can be performed on each of the light-emitting elements LD so that the light-emitting elements LD can be uniformly ejected instead of being unevenly aggregated in the solution.

[0085] A light-emitting device including the above-described light-emitting element LD can be used in various types of devices (including display devices) that require a light source. For example, when a plurality of light-emitting elements LD are provided in the emission region of each pixel of a display panel, the light-emitting element LD can be used as a light source for each of the pixels. However, the application fields of the light-emitting element LD are not limited to the above examples. For example, the light-emitting element LD can be used in other types of devices (such as lighting devices) that require a light source.

[0086] Next, with reference to Figure 4a and Figure 4b a light-emitting element LD manufactured by a growth method will be described.

[0087] When describing the light-emitting element LD manufactured by the growth method, the present disclosure will be described based on points different from the above-described embodiments, and parts not specifically described in the light-emitting element LD manufactured by the growth method follow the above-described embodiments, and the same reference numerals are given to components similar and / or identical to the components of the above-described embodiments.

[0088] With reference to Figure 4a and Figure 4b , a light-emitting element LD according to an embodiment of the present disclosure may include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to an embodiment, the light-emitting element LD may include a core-shell structured light-emitting pattern 10 including a first semiconductor layer 11 located at the center, an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0089] The light-emitting element LD may be provided in a polygonal horn shape extending in one direction. For example, the light-emitting element LD may be provided in a hexagonal horn shape. When the extending direction of the light-emitting element LD is referred to as the length L direction, the light-emitting element LD may have one end (or lower end) and the other end (or upper end) along the length L direction. A part of one of the first semiconductor layer 11 and the second semiconductor layer 13 may be exposed at one end (or lower end) of the light-emitting element LD, and a part of the other semiconductor layer of the first semiconductor layer 11 and the second semiconductor layer 13 may be exposed at the other end (upper end) of the light-emitting element LD. For example, a part of the first semiconductor layer 11 may be exposed at one end (or lower end) of the light-emitting element LD, and a part of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light-emitting element LD. In this case, when the light-emitting element LD is applied as a light source of a display device, the exposed part of the first semiconductor layer 11 may be in contact with one of the driving electrodes for driving the light-emitting element LD, and the exposed part of the second semiconductor layer 13 may be in contact with the other driving electrode.

[0090] According to an embodiment, when the light-emitting element LD includes the additional electrode 15, a part of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 may be exposed at the other end (or upper end) of the light-emitting element LD. In this case, when the light-emitting element LD is applied as a light source of a display device, the exposed part of the additional electrode 15 may contact another driving electrode and may be electrically connected to the other driving electrode.

[0091] In an embodiment of the present disclosure, the first semiconductor layer 11 may be located at the core (i.e., the center of the light-emitting element LD). The light-emitting element LD may be provided in a shape corresponding to the shape of the first semiconductor layer 11. For example, when the first semiconductor layer 11 has a hexagonal horn shape, the light-emitting element LD and the light-emitting pattern 10 may also have a hexagonal horn shape.

[0092] The active layer 12 may be provided and / or formed in a shape surrounding the outer circumferential surface of the first semiconductor layer 11 in the length L direction of the light-emitting element LD. Specifically, the active layer 12 may be provided and / or formed in a shape surrounding the remaining region except for the other end provided at the lower sides of both ends of the first semiconductor layer 11 in the length L direction of the light-emitting element LD.

[0093] The second semiconductor layer 13 may be provided and / or formed in a shape surrounding the active layer 12 in the length L direction of the light-emitting element LD, and may include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

[0094] In an embodiment of the present disclosure, the light-emitting element LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 may be an ohmic contact electrode or a Schottky contact electrode electrically connected to the second semiconductor layer 13, but is not limited thereto.

[0095] As described above, the light-emitting element LD may be configured to have a hexagonal horn shape in which both ends protrude, and may be implemented as a light-emitting pattern 10 having a core-shell structure including the first semiconductor layer 11 provided at its center, the active layer 12 surrounding the first semiconductor layer 11, the second semiconductor layer 13 surrounding the active layer 12, and the additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 may be provided at one end (or lower end) of the light-emitting element LD having a hexagonal horn shape, and the additional electrode 15 may be provided at the other end (or upper end) of the light-emitting element LD.

[0096] In addition, according to an embodiment, the light-emitting element LD may further include an insulating film 14 disposed on an outer circumferential surface of the light-emitting pattern 10 of the core-shell structure. The insulating film 14 may include a transparent insulating material.

[0097] Figure 5 is a diagram showing a display device according to an embodiment of the present disclosure, and particularly is a schematic plan view of a display device using any one of the light-emitting elements shown in Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a and Figure 4b as a light source.

[0098] In Figure 5 , for convenience, the structure of the display device is briefly shown based on the display area of the display image. However, according to an embodiment, at least one driving circuit unit (e.g., a scan driver, a data driver, etc.) and / or a plurality of signal lines not shown may also be provided in the display device.

[0099] Referring to Figure 1a 、 Figure 1b 、 Figure 2a 、 Figure 2b 、 Figure 3a 、 Figure 3b 、 Figure 4a 、 Figure 4b and Figure 5 , a display device according to an embodiment of the present disclosure may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and including at least one light-emitting element LD, a driver (not shown) disposed on the substrate SUB and driving the pixels PXL, and a line unit (not shown) connecting the pixels PXL and the driver to each other.

[0100] The display device may be classified into a passive matrix type display device and an active matrix type display device according to a method of driving the light-emitting element LD. For example, when the display device is implemented as an active matrix type, each of the pixels PXL may include a driving transistor for controlling the amount of current supplied to the light-emitting element LD, a switching transistor for transmitting a data signal to the driving transistor, and the like.

[0101] Recently, active matrix type display devices that select and light up each pixel PXL have become mainstream in terms of resolution, contrast, and operation speed. However, the present disclosure is not limited thereto, and passive matrix type display devices that perform lighting for each group of pixels PXL may also use components (e.g., a first electrode and a second electrode, etc.) for driving the light-emitting element LD.

[0102] The substrate SUB may include a display area DA and a non-display area NDA.

[0103] According to an embodiment, the display area DA may be disposed in the central area of the display device, and the non-display area NDA may be disposed in the edge area of the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and the positions of the display area DA and the non-display area NDA may be changed.

[0104] The display area DA may be an area where pixels PXL for displaying an image are provided. The non-display area NDA may be an area where a driver for driving the pixels PXL and a part of a line unit connecting the pixels PXL and the driver to each other are provided.

[0105] The display area DA may have various shapes. For example, the display area DA may be set as a polygon having a closed shape including sides formed by straight lines. Additionally, the display area DA may be set as a circular shape and / or an elliptical shape including sides formed by curves. Additionally, the display area DA may be set as various shapes (such as a semi-circular shape, a semi-elliptical shape, etc.) including sides formed by straight lines and curves.

[0106] The non-display area NDA may be disposed at at least one side of the display area DA. In an embodiment of the present disclosure, the non-display area NDA may surround the periphery (or edge) of the display area DA.

[0107] The substrate SUB may include a transparent insulating material and may transmit light.

[0108] The substrate SUB may be a rigid substrate. For example, the rigid substrate may be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0109] Additionally, the substrate SUB may be a flexible substrate. Here, the flexible substrate may be one of a film substrate including a polymer organic material and a plastic substrate. For example, the flexible substrate may include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose, and cellulose acetate propionate.

[0110] However, the material constituting the substrate SUB may be changed differently and may include fiber-reinforced plastic (FRP), etc.

[0111] One area on the substrate SUB can be set as the display area DA to set the pixels PXL, and the remaining area on the substrate SUB can be provided as the non-display area NDA. For example, the substrate SUB can include the display area DA and the non-display area NDA. The display area DA includes a pixel area where each pixel PXL is set, and the non-display area NDA is set around the display area DA.

[0112] Each of the pixels PXL can be set in the display area DA on the substrate SUB. In an embodiment of the present disclosure, the pixels PXL can be arranged in a stripe or pentile array structure in the display area DA, but the present disclosure is not limited thereto.

[0113] Each of the pixels PXL can include at least one light-emitting element LD driven by corresponding scan signals and data signals. The light-emitting element LD can have a size as small as the micron or nanometer level and can be connected in parallel with adjacent light-emitting elements, but the present disclosure is not limited thereto. The light-emitting element LD can constitute the light source of each pixel PXL.

[0114] Each of the pixels PXL can include at least one light source driven by a predetermined signal (e.g., scan signal and data signal) and / or a predetermined power supply (e.g., first driving power supply and second driving power supply). For example, each pixel PXL can include at least one ultra-small light-emitting element LD having a small size of about nanometer to micron level as shown in each of the Figures 1a to 4b embodiments. However, the type of the light-emitting element LD that can be used as the light source of each pixel PXL is not limited thereto.

[0115] In an embodiment of the present disclosure, the color, type, quantity, etc. of the pixels PXL are not particularly limited. For example, the color of the light emitted from each pixel PXL can be changed differently.

[0116] The driver can provide a predetermined signal and a predetermined power supply to each pixel PXL through a line unit, thereby controlling the driving of the pixel PXL. In Figure 5 order to facilitate description, the line unit is omitted.

[0117] The driver can include a scan driver that provides scan signals to the pixels PXL through scan lines, an emission driver that provides emission control signals to the pixels PXL through emission control lines, a data driver that provides data signals to the pixels PXL through data lines, and a timing controller. The timing controller can control the scan driver, the emission driver, and the data driver.

[0118] Figures 6a to 6e is a circuit diagram showing the electrical connection relationship between components included in one pixel shown in Figure 5 according to various embodiments.

[0119] For example, Figures 6a to 6e shows the electrical connection relationship between components included in a pixel PXL that can be applied to an active type display device according to different embodiments. However, the types of components included in the pixel PXL to which the embodiments of the present disclosure can be applied are not limited thereto.

[0120] In Figures 6a to 6e not only the components included in each of the pixels shown in Figure 5 but also the area where the components are provided is referred to as the pixel PXL. According to an embodiment, Figures 6a to 6e each pixel PXL shown in Figure 5 can be any one of the pixel PXLs included in the display device of

[0121] and the pixel PXLs can have substantially the same or similar structures. Figures 1a to 4b 、 Figure 5 and Figures 6a to 6e , a pixel PXL (hereinafter referred to as "pixel") can include a light emitting unit EMU that generates light having a luminance corresponding to a data signal. In addition, the pixel PXL can also selectively include a pixel circuit 144 for driving the light emitting unit EMU.

[0122] According to an embodiment, the light emitting unit EMU can include a plurality of light emitting elements LD connected in parallel between a first power line PL1 to which a first driving power supply VDD is applied and a second power line PL2 to which a second driving power supply VSS is applied. For example, the light emitting unit EMU can include a first electrode EL1 (or "first alignment electrode") connected to the first driving power supply VDD via the pixel circuit 144 and the first power line PL1, a second electrode EL2 (or "second alignment electrode") connected to the second driving power supply VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel in the same direction. In the embodiments of the present disclosure, the first electrode EL1 can be an anode electrode, and the second electrode EL2 can be a cathode electrode.

[0123] In the embodiments of the present disclosure, each of the light emitting elements LD included in the light emitting unit EMU can include a first end connected to the first driving power supply VDD through the first electrode EL1 and a second end connected to the second driving power supply VSS through the second electrode EL2. The first driving power supply VDD and the second driving power supply VSS can have different potentials. For example, the first driving power supply VDD can be set as a high potential power supply, and the second driving power supply VSS can be set as a low potential power supply. At this time, during the light emitting period of the pixel PXL, the potential difference between the first driving power supply VDD and the second driving power supply VSS can be set to be equal to or higher than the threshold voltage of the light emitting element LD.

[0124] As described above, corresponding light-emitting elements LD connected in parallel in the same direction (e.g., the forward direction) between a first electrode EL1 and a second electrode EL2 supplied with voltages of different potentials can constitute corresponding effective light sources. Such effective light sources can be aggregated to form a light-emitting unit EMU of a pixel PXL.

[0125] The light-emitting elements LD of the light-emitting unit EMU can emit light having a luminance corresponding to a driving current supplied through a corresponding pixel circuit 144. For example, the pixel circuit 144 can supply a driving current corresponding to a grayscale value of corresponding frame data to the light-emitting unit EMU during each frame period. The driving current supplied to the light-emitting unit EMU can be shunted and flow to the light-emitting elements LD connected in the same direction. Accordingly, each of the light-emitting elements LD can emit light having a luminance corresponding to the current flowing through the light-emitting element LD, and thus the light-emitting unit EMU can emit light having a luminance corresponding to the driving current.

[0126] Meanwhile, Figures 6a to 6e An embodiment is shown in which the light-emitting elements LD are connected in the same direction between a first driving power source VDD and a second driving power source VSS, but the present disclosure is not limited thereto. According to an embodiment, in addition to the light-emitting elements LD constituting each effective light source, the light-emitting unit EMU may further include at least one ineffective light source. For example, at least one reverse light-emitting element LDr may also be connected between a first electrode EL1 and a second electrode EL2 of the light-emitting unit EMU, as Figure 6d and Figure 6e shown. The reverse light-emitting element LDr may be connected in parallel with the light-emitting elements LD constituting the effective light source between the first electrode EL1 and the second electrode EL2, and may be connected between the first electrode EL1 and the second electrode EL2 in a direction opposite to that of the light-emitting elements LD. Although a predetermined driving voltage (e.g., a driving voltage in the forward direction) is applied between the first electrode EL1 and the second electrode EL2, the reverse light-emitting element LDr remains in an inactive state, and thus current substantially does not flow through the reverse light-emitting element LDr.

[0127] The pixel circuit 144 may be connected to a scan line Si and a data line Dj of a corresponding pixel PXL. For example, when the pixel PXL is provided at the i-th (i is a positive integer) row and the j-th (j is a positive integer) column of a display area DA, the pixel circuit 144 of the pixel PXL may be connected to the i-th scan line Si and the j-th data line Dj of the display area DA. According to an embodiment, the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst, as Figure 6a and Figure 6b shown. However, the structure of the pixel circuit 144 is not limited to the embodiments shown in Figure 6a and Figure 6b shown.

[0128] First, referring to Figure 6a , the pixel circuit 144 may include a first transistor T1, a second transistor T2, and a storage capacitor Cst.

[0129] A first terminal of the second transistor T2 (switching transistor) may be connected to the data line Dj, and a second terminal may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 may be different terminals. For example, when the first terminal is the source electrode, the second terminal may be the drain electrode. In addition, a gate electrode of the second transistor T2 may be connected to the scan line Si.

[0130] When a scan signal that can turn on the second transistor T2 (e.g., a low voltage) is supplied from the scan line Si, the second transistor T2 may turn on to electrically connect the data line Dj and the first node N1 to each other. At this time, the data signal of the corresponding frame is supplied to the data line Dj, so the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged in the storage capacitor Cst.

[0131] A first terminal of the first transistor T1 (driving transistor) may be connected to the first driving power supply VDD, and a second terminal may be electrically connected to a first electrode EL1 of each of the light-emitting elements LD. A gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 controls the amount of driving current supplied to the light-emitting element LD in response to the voltage of the first node N1.

[0132] One electrode of the storage capacitor Cst may be connected to the first driving power supply VDD, and the other electrode may be connected to the first node N1. The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1 and holds the charged voltage until the data signal of the next frame is supplied.

[0133] Figure 6a and Figure 6b each of which shows the pixel circuit 144 including a second transistor T2 for transmitting a data signal to the pixel PXL, a storage capacitor Cst for storing the data signal, and a first transistor T1 for supplying a driving current corresponding to the data signal to the light-emitting element LD.

[0134] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 can be modified and implemented differently. For example, the pixel circuit 144 may further include other circuit elements, such as at least one transistor element (such as a transistor element for compensating the threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling the light emission time of the light emitting element LD) or a boost capacitor for boosting the voltage of the first node N1.

[0135] In addition, in Figure 6a the transistors included in the pixel circuit 144 (e.g., the first transistor T1 and the second transistor T2) are P-type transistors, but the present disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 may be changed to an N-type transistor.

[0136] Next, referring to Figures 1a to 4b 、 Figure 5 and Figure 6b according to an embodiment of the present disclosure, the first transistor T1 and the second transistor T2 may be implemented as N-type transistors. Except for some changes in the connection positions of some components due to the change in the transistor type, Figure 6b the structure or operation of the pixel circuit 144 shown in Figure 6a is the same as the structure or operation of the pixel circuit 144 of

[0137] In an embodiment of the present disclosure, Figure 6b the pixel circuit 144 shown in Figure 6b may include a first transistor T1 and a second transistor T2 formed of N-type transistors and a storage capacitor Cst. When the first transistor T1 and the second transistor T2 are formed of N-type transistors, the light emitting unit EMU may be connected between the first driving power supply VDD and the pixel circuit 144 for stabilizing the storage capacitor Cst that charges a voltage corresponding to the data signal supplied to the first node N1. However, the present disclosure is not limited thereto, and according to an embodiment, Figure 6a and Figure 6b the light emitting unit EMU shown in Figure 6c and Figure 6d may be connected between the pixel circuit 144 and the second driving power supply VSS. In an embodiment of the present disclosure, the structure of the pixel circuit 144 is not limited to the embodiments shown in

[0138] For example, the pixel circuit 144 may be constructed as in the embodiments shown in Figure 6c and Figure 6dAs shown, the pixel circuit 144 can be connected to the scan line Si and the data line Dj of the pixel PXL. For example, when the pixel PXL is set in the i-th row and j-th column of the display area DA, the pixel circuit 144 of the corresponding pixel PXL can be connected to the i-th scan line Si and the j-th data line Dj of the display area DA.

[0139] In addition, according to an embodiment, the pixel circuit 144 can also be connected to at least another scan line. For example, the pixel PXL set in the i-th row of the display area DA can also be connected to the (i - 1)-th scan line Si-1 and / or the (i + 1)-th scan line Si+1. In addition, according to an embodiment, in addition to the first driving power supply VDD and the second driving power supply VSS, the pixel circuit 144 can also be connected to a third power supply. For example, the pixel circuit 144 can also be connected to the initialization power supply Vint.

[0140] The pixel circuit 144 can include a first transistor T1 to a seventh transistor T7 and a storage capacitor Cst.

[0141] One electrode (e.g., the source electrode) of the first transistor T1 (driving transistor) can be connected to the first driving power supply VDD via the fifth transistor T5, and the other electrode (e.g., the drain electrode) can be connected to one end of the light-emitting element LD via the sixth transistor T6. In addition, the gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 controls the driving current flowing between the first driving power supply VDD and the second driving power supply VSS via the light-emitting element LD in response to the voltage of the first node N1.

[0142] The second transistor T2 (switching transistor) can be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. In addition, the gate electrode of the second transistor T2 can be connected to the i-th scan line Si connected to the pixel PXL. When a scan signal supplying a gate-on voltage (e.g., a low voltage) is supplied from the i-th scan line Si, the second transistor T2 can be turned on to electrically connect the j-th data line Dj to the source electrode of the first transistor T1. Therefore, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transmitted to the first transistor T1.

[0143] The third transistor T3 can be connected between the drain electrode of the first transistor T1 and the first node N1. In addition, the gate electrode of the third transistor T3 can be connected to the i-th scan line Si. When a scan signal supplying a gate-on voltage is supplied from the i-th scan line Si, the third transistor T3 can be turned on to electrically connect the drain electrode of the first transistor T1 and the first node N1 to each other.

[0144] The fourth transistor T4 may be connected between the first node N1 and an initialization power supply line to which an initialization power supply Vint is applied. Additionally, a gate electrode of the fourth transistor T4 may be connected to a previous scan line, for example, the (i - 1)-th scan line Si-1. When a scan signal having a gate-on voltage is supplied to the (i - 1)-th scan line Si-1, the fourth transistor T4 may be turned on to transfer the voltage of the initialization power supply Vint to the first node N1. Here, the initialization power supply Vint may have a voltage equal to or less than the lowest voltage of the data signal.

[0145] The fifth transistor T5 may be connected between the first driving power supply VDD and the first transistor T1. Additionally, a gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0146] The sixth transistor T6 may be connected between the first transistor T1 and a second node N2 electrically connected to one end of the light-emitting element LD. Additionally, a gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when an emission control signal having a gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

[0147] The seventh transistor T7 may be connected between one end of the light-emitting element LD and the initialization power supply line. Additionally, a gate electrode of the seventh transistor T7 may be connected to any one of the next scan lines, for example, the (i + 1)-th scan line Si+1. When a scan signal having a gate-on voltage is supplied to the (i + 1)-th scan line Si+1, the seventh transistor T7 may be turned on to supply the voltage of the initialization power supply Vint to one end of the light-emitting element LD.

[0148] The storage capacitor Cst may be connected between the first driving power supply VDD and the first node N1. The storage capacitor Cst may store a data signal supplied to the first node N1 and a voltage corresponding to the threshold voltage of the first transistor T1 during each frame period.

[0149] In Figure 6c and Figure 6d the transistors (e.g., the first transistor T1 to the seventh transistor T7) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 may be changed to an N-type transistor.

[0150] In an embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to Figures 6a to 6d the embodiment shown in Figure 6econfigured as in the embodiment shown.

[0151] As Figure 6e shown, the pixel circuit 144 may also be connected to the control line CLi and the sense line SENj. For example, the pixel circuit 144 of the pixel PXL disposed at the i-th row and j-th column of the display area DA may be connected to the i-th control line CLi and the j-th sense line SENj of the display area DA. In addition to Figure 6a and Figure 6b the first transistor T1 and the second transistor T2 shown in, the above pixel circuit 144 may further include a third transistor T3 and a storage capacitor C OLED , the storage capacitor C OLED is connected to the first electrode EL1 and the second electrode EL2 of the light emitting unit EMU.

[0152] The third transistor T3 is connected between the first transistor T1 and the sense line SENj. For example, one electrode of the third transistor T3 may be connected to a terminal (e.g., the source electrode) of the first transistor T1 connected to the first electrode EL1, and the other electrode of the third transistor T3 may be connected to the sense line SENj. Meanwhile, when the sense line SENj is omitted, the other electrode of the third transistor T3 may be connected to the data line Dj.

[0153] According to an embodiment, the gate electrode of the third transistor T3 is connected to the control line CLi. Meanwhile, when the control line CLi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si. The third transistor T3 may be turned on by a control signal of a gate-on voltage (e.g., high level) supplied to the control line CLi during a predetermined sensing period to electrically connect the sense line SENj and the first transistor T1 to each other.

[0154] According to an embodiment, the sensing period may be a period for extracting characteristic information (e.g., the threshold voltage of the first transistor T1, etc.) of each of the pixels PXL provided in the display area DA. During the above sensing period, the first transistor T1 may be turned on by supplying a predetermined reference voltage that can turn on the first transistor T1 to the first node N1 through the data line Dj and the second transistor T2, or by connecting each pixel PXL to a current source, etc. In addition, by supplying a control signal of a gate-on voltage to the third transistor T3 to turn on the third transistor T3, the first transistor T1 may be connected to the sense line SENj. Therefore, the characteristic information including the threshold voltage of the first transistor T1, etc. of each pixel PXL may be extracted through the sense line SENj. The extracted characteristic information may be used to convert image data, thereby compensating for the characteristic deviation between the pixels PXL. The capacitor C OLED may be provided between the first electrode EL1 and the second electrode EL2.

[0155] Meanwhile, Figure 6e Embodiments are disclosed in which all of the first transistor T1 to the third transistor T3 are N-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the third transistor T3 may be changed to a P-type transistor. Additionally, Figure 6e Embodiments are disclosed in which the light-emitting unit EMU is connected between the pixel circuit 144 and the second driving power source VSS, but the light-emitting unit EMU may also be connected between the first driving power source VDD and the pixel circuit 144.

[0156] Additionally, Figures 6a to 6e Embodiments are shown in which all of the light-emitting elements LD that make up each light-emitting unit EMU are connected in parallel, but the present disclosure is not limited thereto. According to an embodiment, the light-emitting unit EMU may be configured to include at least one series stage, and at least one series stage includes a plurality of light-emitting elements LD connected in parallel with each other. That is, the light-emitting unit EMU may be configured in a series / parallel hybrid structure. This will be described later with reference to Figures 7a to 7c which follows.

[0157] The structure of the pixel PXL to which the present disclosure can be applied is not limited to Figures 6a to 6e the embodiments shown therein, and the corresponding pixel may have various structures. Additionally, in another embodiment of the present disclosure, each pixel PXL may be constructed inside a passive light-emitting display device or the like. In this case, the pixel circuit 144 may be omitted, and each of the two ends of the light-emitting element LD included in the light-emitting unit EMU may be directly connected to each of the scan lines Si-1, Si, Si+1, data lines Dj, the first power supply line PL1 to which the first driving power source VDD is applied, the second power supply line PL2 to which the second driving power source VSS is applied, a predetermined control line, and the like.

[0158] Figures 7a to 7c is a circuit diagram showing the electrical connection relationship of the components included in one pixel shown in Figure 5 according to another embodiment. In Figures 7a to 7c each pixel PXL's light-emitting unit EMU may be configured to include a plurality of series stages connected continuously to each other. When describing Figures 7a to 7c the embodiments, in order to avoid repetitive description, the detailed description of the structures similar or identical to those of Figures 6a to 6e the embodiments (e.g., the pixel circuit 144) will be omitted.

[0159] First, refer to Figure 7a, the light emitting unit EMU may include a plurality of light emitting elements connected in series with each other. For example, the light emitting unit EMU may include a first light emitting element LD1, a second light emitting element LD2, a third light emitting element LD3, and a fourth light emitting element LD4 connected in series in the forward direction between a first driving power supply VDD and a second driving power supply VSS to construct an effective light source. In the following embodiments, at least one random light emitting element among the first light emitting element LD1 to the fourth light emitting element LD4 or the combined first light emitting element LD1 to the fourth light emitting element LD4 may be referred to as the light emitting element LD or a plurality of light emitting elements LD.

[0160] One end of the first light emitting element LD1 (e.g., the second semiconductor layer) may be connected to the first driving power supply VDD through the first electrode EL1, and the other end of the first light emitting element LD1 (e.g., the first semiconductor layer) may be connected to one end of the second light emitting element LD2 (e.g., the second semiconductor layer) through the first intermediate electrode CTE1 connected between the first series stage and the second series stage.

[0161] The one end of the second light emitting element LD2 (e.g., the second semiconductor layer) may be connected to the first intermediate electrode CTE1, and the other end of the second light emitting element LD2 (e.g., the first semiconductor layer) may be connected to one end of the third light emitting element LD3 (e.g., the second semiconductor layer) through the second intermediate electrode CTE2 connected between the second series stage and the third series stage.

[0162] The one end of the third light emitting element LD3 may be connected to the second intermediate electrode CTE2, and the other end of the third light emitting element LD3 (e.g., the first semiconductor layer) may be connected to one end of the fourth light emitting element LD4 (e.g., the second semiconductor layer) through the third intermediate electrode CTE3 connected between the third series stage and the fourth series stage.

[0163] The one end of the fourth light emitting element LD4 may be connected to the third intermediate electrode CTE3, and the other end of the fourth light emitting element LD4 (e.g., the first semiconductor layer) may be connected to the second driving power supply VSS through the second electrode EL2.

[0164] As described above, the first light emitting element LD1 to the fourth light emitting element LD4 may be connected in series between the first electrode EL1 and the second electrode EL2 of the light emitting unit EMU of the pixel PXL.

[0165] In the case of a light-emitting unit EMU having a structure in which light-emitting elements LD are connected in series, compared with a light-emitting unit EMU having a structure in which light-emitting elements LD are connected in parallel, the voltage applied between a first electrode EL1 and a second electrode EL2 can be increased, and the magnitude of the drive current flowing through the light-emitting unit EMU can be decreased. Accordingly, when the light-emitting unit EMU of each pixel PXL is configured as a series structure, the power consumption of the display device can be reduced.

[0166] According to an embodiment, at least one series stage may be provided in a form including a plurality of light-emitting elements LD connected in parallel with each other. In this case, the light-emitting unit EMU of each pixel PXL may be configured in a series / parallel hybrid structure. For example, the light-emitting unit EMU may be configured as shown in Figure 7b and Figure 7c therein.

[0167] Next, referring to Figure 7b and Figure 7c , the light-emitting unit EMU of the pixel PXL may include a plurality of series stages sequentially connected between a first driving power source VDD and a second driving power source VSS. In addition, each series stage may include one or more light-emitting elements LD connected in the forward direction between two electrodes of an electrode pair constituting the corresponding series stage. For example, the light-emitting unit EMU may include first to third series stages SET1 to SET3 sequentially connected between a first driving power source VDD and a second driving power source VSS. Each of the first to third series stages SET1 to SET3 may include two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 of an electrode pair constituting the corresponding series stage, and a plurality of light-emitting elements LD connected in parallel in the forward direction (e.g., in the same direction) between each pair of the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4.

[0168] The first series stage SET1 may include the first electrode EL1 and the 2a electrode EL2a among two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 that form an electrode pair included in the light emitting unit EMU, and may include at least one first light emitting element LD1 connected between the first electrode EL1 and the 2a electrode EL2a. For example, the first series stage SET1 may include the first electrode EL1 connected to the first driving power supply VDD via the pixel circuit 144, the 2a electrode EL2a connected to the second driving power supply VSS, and a plurality of first light emitting elements LD1 connected between the first electrode EL1 and the 2a electrode EL2a. One end (e.g., the second semiconductor layer) of each first light emitting element LD1 is electrically connected to the first electrode EL1 of the first series stage SET1, and the other end (e.g., the first semiconductor layer) thereof is electrically connected to the 2a electrode EL2a of the first series stage SET1. The first light emitting elements LD1 may be connected in parallel between the first electrode EL1 and the 2a electrode EL2a of the first series stage SET1, and may be connected between the first electrode EL1 and the 2a electrode EL2a in the same direction (e.g., the forward direction). According to an embodiment, as Figure 7c shown in, at least one reverse light emitting element LDr may also be connected to the first series stage SET1. The reverse light emitting element LDr may be connected in parallel with the first light emitting elements LD1 that constitute the effective light source between the first electrode EL1 and the 2a electrode EL2a, and may be connected between the first electrode EL1 and the 2a electrode EL2a in a direction opposite to that of the first light emitting elements LD1. For example, the first semiconductor layer of the reverse light emitting element LDr may be connected to the first electrode EL1, and the second semiconductor layer thereof may be connected to the 2a electrode EL2a. Although a predetermined driving voltage (e.g., a driving voltage in the forward direction) is applied between the first electrode EL1 and the 2a electrode EL2a, the reverse light emitting element LDr remains in an inactive state, so that current basically does not flow through the reverse light emitting element LDr.

[0169] The second series stage SET2 may include the 2b electrode EL2b and the 3a electrode EL3a among the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 that form an electrode pair included in the light emitting unit EMU, and may include at least one second light emitting element LD2 connected between the 2b electrode EL2b and the 3a electrode EL3a. For example, the second series stage SET2 may include the 2b electrode EL2b connected to the first driving power supply VDD via the first series stage SET1, the 3a electrode EL3a connected to the second driving power supply VSS, and a plurality of second light emitting elements LD2 connected between the 2b electrode EL2b and the 3a electrode EL3a. One end (e.g., the second semiconductor layer) of each second light emitting element LD2 is electrically connected to the 2b electrode EL2b of the second series stage SET2, and the other end (e.g., the first semiconductor layer) thereof is electrically connected to the 3a electrode EL3a of the second series stage SET2. The second light emitting elements LD2 may be connected in parallel between the 2b electrode EL2b and the 3a electrode EL3a of the second series stage SET2, and may be connected between the first driving power supply VDD and the second driving power supply VSS in the same direction (e.g., the forward direction) through the 2b electrode EL2b and the 3a electrode EL3a. According to an embodiment, as Figure 7c shown, at least one reverse light emitting element LDr may also be connected between the 2b electrode EL2b and the 3a electrode EL3a. The reverse light emitting element LDr may be connected in parallel with the second light emitting elements LD2 that constitute the effective light source between the 2b electrode EL2b and the 3a electrode EL3a, and may be connected between the 2b electrode EL2b and the 3a electrode EL3a in a direction opposite to that of the second light emitting elements LD2. For example, the first semiconductor layer of the reverse light emitting element LDr may be connected to the 2b electrode EL2b, and the second semiconductor layer thereof may be connected to the 3a electrode EL3a.

[0170] In the disclosed embodiment, the 2a electrode EL2a of the first series stage SET1 and the 2b electrode EL2b of the second series stage SET2 may be integrally provided and connected to each other. That is, the 2a electrode EL2a of the first series stage SET1 and the 2b electrode EL2b of the second series stage SET2 may construct the second electrode EL2 that electrically connects the first series stage SET1 and the second series stage SET2 to each other. As described above, when the 2a electrode EL2a of the first series stage SET1 and the 2b electrode EL2b of the second series stage SET2 are integrally provided, the 2a electrode EL2a and the 2b electrode EL2b may be different regions of the second electrode EL2.

[0171] The third series stage SET3 may include the 3b electrode EL3b among the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 that form the electrode pairs included in the light emitting unit EMU, and the fourth electrode EL4, and may include at least one third light emitting element LD3 connected between the 3b electrode EL3b and the fourth electrode EL4. For example, the third series stage SET3 may include the 3b electrode EL3b connected to the first driving power supply VDD via the pixel circuit 144 and the previous series stages (e.g., the first series stage SET1 and the second series stage SET2), the fourth electrode EL4 connected to the second driving power supply VSS, and a plurality of third light emitting elements LD3 connected between the 3b electrode EL3b and the fourth electrode EL4. One end (e.g., the second semiconductor layer) of each third light emitting element LD3 is electrically connected to the 3b electrode EL3b of the third series stage SET3, and the other end (e.g., the first semiconductor layer) is electrically connected to the fourth electrode EL4 of the third series stage SET3. The third light emitting elements LD3 may be connected in parallel between the 3b electrode EL3b and the fourth electrode EL4 of the third series stage SET3, and may be connected between the first driving power supply VDD and the second driving power supply VSS in the same direction (e.g., the forward direction) through the 3b electrode EL3b and the fourth electrode EL4. According to an embodiment, as Figure 7c shown in, at least one reverse light emitting element LDr may also be connected between the 3b electrode EL3b and the fourth electrode EL4. The reverse light emitting element LDr may be connected in parallel with the third light emitting elements LD3 that constitute the effective light source between the 3b electrode EL3b and the fourth electrode EL4, and may be connected between the 3b electrode EL3b and the fourth electrode EL4 in a direction opposite to that of the third light emitting elements LD3. For example, the first semiconductor layer of the reverse light emitting element LDr may be connected to the 3b electrode EL3b, and the second semiconductor layer may be connected to the fourth electrode EL4.

[0172] In the disclosed embodiment, the 3a electrode EL3a of the second series stage SET2 and the 3b electrode EL3b of the third series stage SET3 may be integrally provided and connected to each other. That is, the 3a electrode EL3a of the second series stage SET2 and the 3b electrode EL3b of the third series stage SET3 may constitute a third electrode EL3 that electrically connects the second series stage SET2 and the third series stage SET3 to each other. As described above, when the 3a electrode EL3a of the second series stage SET2 and the 3b electrode EL3b of the third series stage SET3 are integrally provided, the 3a electrode EL3a and the 3b electrode EL3b may be different regions of the third electrode EL3.

[0173] In the above-described embodiment, the first electrode EL1 of the first series stage SET1 may be the anode electrode of the light-emitting unit EMU of each pixel PXL, and the fourth electrode EL4 of the third series stage SET3 may be the cathode electrode of the light-emitting unit EMU.

[0174] As described above, the light-emitting unit EMU of the pixel PXL including the light-emitting elements LD connected in a series / parallel hybrid structure can easily adjust the drive current / voltage conditions according to the product specifications of the application.

[0175] In particular, compared with the light-emitting unit EMU having a structure in which the light-emitting elements LD are connected in parallel, the light-emitting unit EMU of the pixel PXL including the light-emitting elements LD connected in a series / parallel hybrid structure can reduce the drive current. In addition, compared with the light-emitting unit EMU having a structure in which all of the light-emitting elements LD are connected in series, the light-emitting unit EMU of the pixel PXL including the light-emitting elements LD connected in a series / parallel hybrid structure can reduce the drive voltage applied across both ends of the light-emitting unit EMU. In addition, in the case where all of the light-emitting elements LD are connected in series, when at least one of the serially connected light-emitting elements LD is not completely connected in the forward direction (or includes a reverse light-emitting element LDr), the path through which the drive current can flow in the pixel PXL is blocked, resulting in a dark spot defect. On the other hand, in the case where the light-emitting elements LD are connected in a series / parallel hybrid structure, even if some of the light-emitting elements LD are not connected in the forward direction (or include a reverse light-emitting element LDr) or a defect occurs in some of the light-emitting elements LD in each series stage, the drive current can flow through the other light-emitting element LD of the corresponding series stage. Therefore, defects in the pixel PXL can be prevented or reduced.

[0176] Figure 8 schematically shows Figure 5 a plan view of one of the pixels among the pixels shown in Fig. 9 is a cross-sectional view taken along line I-I' of Figure 8 , Fig.10 is a cross-sectional view taken along line II-II' of Figure 8 , Fig.11 is, according to another embodiment, a cross-sectional view corresponding to line II-II' of Fig.10 showing an implementation of the first bank as shown in Figure 8 ; Fig.12 is a cross-sectional view corresponding to line II-II' of Fig.10 showing an implementation of the display element layer as shown in Figure 8 ; Fig.13 is a cross-sectional view taken along lines III-III' and IV-IV' of Figure 8 ; Fig.14 is, according to another embodiment, as Fig. 9 A cross-sectional view corresponding to lines I to I' of the implementation of the fourth conductive wire shown in Figure 8 and Fig.15 is a cross-sectional view corresponding to lines III to III' and lines IV to IV' of the implementation of the second conductive wire shown in Fig.13 according to another embodiment. Figure 8

[0177] Figure 8 The pixel shown in Figures 6a to 6e and Figures 7a to 7c can be any one of the pixels shown in each of Figure 8 For example, the pixel shown in Figure 7a and / or Figure 7c the pixel shown in

[0178] In Figure 8 for convenience, the transistor connected to the light-emitting element and the signal line connected to the transistor are omitted.

[0179] Figures 8 to 15 The structure of a pixel PXL is simplified and shown, such as showing each electrode as a single electrode layer and each insulating layer as a single insulating layer, but the disclosure is not limited thereto.

[0180] In addition, in the disclosed embodiment, "formed and / or provided in the same layer" may mean formed in the same process, and "formed and / or provided in different layers" may mean formed in different processes.

[0181] Referring to Figures 1a to 5 、 Figure 7b 、 Figure 7c and Figures 8 to 15 a display device according to an embodiment may include a substrate SUB, a line unit, and a plurality of pixels PXL.

[0182] The substrate SUB may include a transparent insulating material and may transmit light. The substrate SUB may be a rigid substrate or a flexible substrate. During the manufacturing process of the display device, the material applied to the substrate SUB may preferably have tolerance to high process temperatures (or heat resistance). The substrate SUB may include a display area DA and a non-display area NDA. The display area DA includes at least one pixel area PXA in which pixels PXL are provided, and the non-display area NDA is provided around the display area DA.

[0183] ​The pixels PXL may be arranged in a matrix form and / or a stripe form on the substrate SUB in the display area DA along a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 crossing the first direction DR1, but the disclosure is not limited thereto. According to embodiments, the pixels PXL may be provided in the display area DA on the substrate SUB in various arrangement forms.

[0184] The pixel area PXA in which each pixel PXL is disposed may include an emission area EMA in which light is emitted and a peripheral area surrounding the periphery of the emission area EMA. In the disclosed embodiment, the peripheral area may include a non-emission area in which light is not emitted.

[0185] Each pixel PXL may include a pixel circuit section PCL including a pixel circuit 144 and a display element section DPL including a plurality of light emitting elements LD. The light emitting element LD may be located in an emission area EMA of a pixel area PXA of each pixel PXL.

[0186] The pixel circuit part PCL may include a buffer layer BFL, a pixel circuit 144 including at least one transistor T, and a protective layer PSV. The display element part DPL may include first and second bank patterns BNK1 and BNK2, first to fourth electrodes EL1 to EL4, a light emitting element LD, and a contact electrode CNE.

[0187] For the sake of convenience, the pixel circuit portion PCL is described first, and then the display element portion DPL is described.

[0188] The buffer layer BFL may prevent impurities from diffusing into the transistor T. The buffer layer BFL may be provided as a single layer, but may be provided as a multilayer of at least two layers. When the buffer layer BFL is provided in multiple layers, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted according to the material of the substrate SUB, process conditions, etc.

[0189] The transistor T may include a first transistor T1 as a driving transistor for controlling the amount of driving current supplied to the light emitting element LD and a second transistor T2 as a switching transistor. In an embodiment of the present disclosure, the first transistor T1 may be a reference transistor. Figure 6a , Figure 7b and Figure 7c The first transistor T1 and the second transistor T2 of the pixel circuit 144 described above may be referenced Figure 6a , Figure 7b and Figure 7cThe second transistor T2 of the described pixel circuit 144. In the following embodiments, either one of the first transistor T1 and the second transistor T2 or the combined first transistor T1 and second transistor T2 is referred to as transistor T or transistors T.

[0190] Each of the first transistor T1 and the second transistor T2 may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be either a source electrode or a drain electrode, and the second terminal DE may be the other electrode. For example, when the first terminal SE is the source electrode, the second terminal DE may be the drain electrode.

[0191] The transistor semiconductor pattern SCL may be disposed and / or formed on the buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact region in contact with the first terminal SE and a second contact region in contact with the second terminal DE. The region between the first contact region and the second contact region may be a channel region. The transistor semiconductor pattern SCL may be a semiconductor panel formed of polysilicon, amorphous silicon, an oxide semiconductor, etc. The channel region is a semiconductor pattern without doped impurities and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities.

[0192] The gate electrode GE may be disposed and / or formed on the transistor semiconductor pattern SCL, with a gate insulating layer GI interposed between the gate electrode GE and the transistor semiconductor pattern SCL.

[0193] The corresponding first terminal SE and second terminal DE may be in contact with the first contact region and the second contact region of the transistor semiconductor pattern SCL through contact holes passing through the first interlayer insulating layer ILD1 and the gate insulating layer GI.

[0194] In the above embodiments, the first terminal SE and the second terminal DE of each of the first transistor T1 and the second transistor T2 are described as being electrically connected to separate electrodes of the transistor semiconductor pattern SCL, but the present disclosure is not limited thereto. According to an embodiment, the first terminal SE of each of the first transistor T1 and the second transistor T2 may be one of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL, and the second terminal DE of each of the first transistor T1 and the second transistor T2 may be the other of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. In this case, the second terminal DE of each of the first transistor T1 and the second transistor T2 may be electrically connected to the light-emitting element LD of the corresponding pixel PXL through a separate connection means such as a bridge electrode or a contact electrode.

[0195] In an embodiment of the present disclosure, the transistor T included in the pixel circuit 144 may be formed of an LTPS thin film transistor, but the present disclosure is not limited thereto. The transistor T included in the pixel circuit 144 may be formed of an oxide semiconductor thin film transistor according to an embodiment. Additionally, the case where the transistor T is a thin film transistor having a top gate structure is described as an example, but the present disclosure is not limited thereto. According to an embodiment, the transistor T may be a thin film transistor having a bottom gate structure.

[0196] The second interlayer insulating layer ILD2 may be disposed on the above-described transistor T. The second interlayer insulating layer ILD2 may cover the transistor T. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0197] The protective layer PSV may be disposed on the second interlayer insulating layer ILD2. The protective layer PSV may be provided in a form including an organic insulating layer, an inorganic insulating layer, or an organic insulating layer provided on an inorganic insulating layer. Here, the inorganic insulating layer may include at least one of silicon oxide (SiO x ) and silicon nitride (SiN x ). The organic insulating layer may include an organic insulating material capable of transmitting light. The organic insulating layer may include at least one of acrylic resin (polyacrylate resin), epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0198] Meanwhile, the pixel circuit portion PCL may include first to fourth conductive lines CL1 to CL4.

[0199] Among the first to fourth conductive lines CL1 to CL4, the first conductive line CL1 and the fourth conductive line CL4 may have a strip shape extending in the second direction DR2 (e.g., in the vertical direction) on the substrate SUB, and the second conductive line CL2 and the third conductive line CL3 may have a strip shape extending in the first direction DR1 (e.g., in the horizontal direction) intersecting the second direction DR2 on the substrate SUB. The extending direction and shape of each of the first to fourth conductive lines CL1 to CL4 are not limited to the above embodiment. According to an embodiment, the first conductive line CL1 and the fourth conductive line CL4 may extend in the first direction DR1 or in a direction inclined with respect to the first direction DR1 on the substrate SUB, and the second conductive line CL2 and the third conductive line CL3 may extend in the second direction DR2 or in a direction inclined with respect to the second direction DR2 on the substrate SUB. Additionally, according to an embodiment, the first to fourth conductive lines CL1 to CL4 may extend in the same direction (e.g., in the first direction DR1 and / or the second direction DR2).

[0200] The first conductive line CL1 to the fourth conductive line CL4 may be disposed in the same layer as the first terminal SE and the second terminal DE of each of the first transistor T1 and the second transistor T2, and may include the same material. For example, the first conductive line CL1 to the fourth conductive line CL4 may be disposed and / or formed on the first interlayer insulating layer ILD1.

[0201] The first conductive line CL1 may be disposed and / or formed on the first interlayer insulating layer ILD1. The first conductive line CL1 may be integrally disposed with the second terminal DE of the first transistor T1 to be connected to the second terminal DE of the first transistor T1. When the first conductive line CL1 and the second terminal DE of the first transistor T1 are integrally disposed, the first conductive line CL1 may be regarded as a region of the second terminal DE of the first transistor T1, or the second terminal DE of the first transistor T1 may be regarded as a region of the first conductive line CL1. According to an embodiment, the first conductive line CL1 may be non-integrally disposed with the second terminal DE of the first transistor T1, and may be electrically connected to the second terminal DE of the first transistor T1 through a separate connection method such as a contact hole and a bridge electrode.

[0202] The first conductive line CL1 may be electrically connected to a partial structure (e.g., the first electrode) of the display element unit DPL through a first contact hole CH1 that sequentially passes through the second interlayer insulating layer ILD2 and the protective layer PSV. In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the first conductive line CL1 may transmit a predetermined alignment signal (or alignment voltage) to the first electrode EL1 to allow the first electrode EL1 to function as a first alignment electrode (or first alignment line). Additionally, after the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the first conductive line CL1 may be electrically connected to the first transistor T1 to allow the first electrode EL1 to function as a driving electrode for the light-emitting element LD.

[0203] The second conductive line CL2 may be disposed and / or formed on the first interlayer insulating layer ILD1, and may be spaced apart from the first conductive line CL1 to be electrically and / or physically separated from the first conductive line CL1. The second conductive line CL2 may be electrically connected to a partial structure (e.g., the second electrode EL2) of the display element unit DPL through a second contact hole CH2 that sequentially penetrates the second interlayer insulating layer ILD2 and the protective layer PSV. In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the second conductive line CL2 may transmit a predetermined alignment signal (or alignment voltage) to the second electrode EL2 to allow the second electrode EL2 to serve as a second alignment electrode (or second alignment line). Additionally, after the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, a portion of the second conductive line CL2 may be removed or disconnected, and the second conductive line CL2 may be in a floating state. A detailed description related thereto will be provided later.

[0204] The third conductive line CL3 may be disposed and / or formed on the first interlayer insulating layer ILD1, and may be spaced apart from the first conductive line CL1 and the second conductive line CL2 to be electrically and / or physically separated from the first conductive line CL1 and the second conductive line CL2. The third conductive line CL3 may be electrically connected to a partial structure (e.g., the third electrode EL3) of the display element unit DPL through a third contact hole CH3 that sequentially penetrates the second interlayer insulating layer ILD2 and the protective layer PSV. In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the third conductive line CL3 may transmit a predetermined alignment signal (or alignment voltage) to the third electrode EL3 to allow the third electrode EL3 to serve as a third alignment electrode (or third alignment line). Additionally, after the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, a portion of the third conductive line CL3 may be removed or disconnected, and the third conductive line CL3 may be in a floating state. A detailed description related thereto will be provided later.

[0205] The fourth conductive line CL4 may be disposed and / or formed on the first interlayer insulating layer ILD1, and may be spaced apart from the first conductive line CL1, the second conductive line CL2, and the third conductive line CL3 to be electrically and / or physically separated from the first conductive line CL1, the second conductive line CL2, and the third conductive line CL3. The fourth conductive line CL4 may be electrically connected to a partial structure (e.g., the fourth electrode EL4) of the display element unit DPL through a fourth contact hole CH4 that sequentially penetrates the second interlayer insulating layer ILD2 and the protective layer PSV. In an embodiment of the present disclosure, the fourth conductive line CL4 may be in Figure 7b and Figure 7cThe second power line PL2 to which the second driving power supply VSS is applied in the pixel PXL shown. When the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the fourth conductive line CL4(PL2) can transmit a predetermined alignment signal (or alignment voltage) to the fourth electrode EL4 to allow the fourth electrode EL4 to be used as a fourth alignment electrode (or fourth alignment line). Additionally, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the fourth conductive line CL4(PL2) can transmit the second driving power supply VSS to the fourth electrode EL4 to allow the fourth electrode EL4 to be used as a driving electrode of the light-emitting element LD.

[0206] In the above embodiment, the first conductive line CL1 to the fourth conductive line CL4 are provided and / or formed on the first interlayer insulating layer ILD1, so the first conductive line CL1 to the fourth conductive line CL4 are provided in the same layer, but the present disclosure is not limited thereto. According to an embodiment, the first conductive line CL1 to the fourth conductive line CL4 may be provided in different layers. For example, as Fig.14 and Fig.15 shown, the first conductive line CL1 and the third conductive line CL3 may be provided and / or formed on the first interlayer insulating layer ILD1, and the second conductive line CL2 and the fourth conductive line CL4 may be provided and / or formed on the second interlayer insulating layer ILD2. Additionally, in the opposite case, the second conductive line CL2 and the fourth conductive line CL4 may be provided and / or formed on the first interlayer insulating layer ILD1, and the first conductive line CL1 and the third conductive line CL3 may be provided and / or formed on the second interlayer insulating layer ILD2. The position of each of the first conductive line CL1 to the fourth conductive line CL4 is not limited to the above embodiment. When the second conductive line CL2 and the fourth conductive line CL4 are provided and / or formed on the second interlayer insulating layer ILD2, the second conductive line CL2 may be electrically connected to the second electrode EL2 through the second contact hole CH2 passing through the protective layer PSV, and the fourth conductive line CL4 may be electrically connected to the fourth electrode EL4 through the fourth contact hole CH4 passing through the protective layer PSV.

[0207] Next, the display element unit DPL is described.

[0208] The first bank pattern BNK1 may be a support member or an insulating pattern that supports each of the first electrode EL1 to the fourth electrode EL4 to change the surface profile of each of the first electrode EL1 to the fourth electrode EL4 so that the light emitted from the light-emitting element LD travels further in the image display direction of the display device.

[0209] The first bank pattern BNK1 can be disposed and / or formed in the emission area EMA of each pixel PXL and / or between the protective layer PSV and the first to fourth electrodes EL1 to EL4. For example, the first bank pattern BNK1 can be disposed and / or formed between the protective layer PSV and the first electrode EL1, between the protective layer PSV and the second electrode EL2, between the protective layer PSV and the third electrode EL3, and between the protective layer PSV and the fourth electrode EL4.

[0210] The first bank pattern BNK1 can include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. According to an embodiment, the first bank pattern BNK1 can include a single-layer organic insulating layer and / or a single-layer inorganic insulating layer, but the present disclosure is not limited thereto. According to an embodiment, the first bank pattern BNK1 can be provided in the form of a multi-layer in which at least one organic insulating layer and at least one inorganic insulating layer are stacked.

[0211] The first bank pattern BNK1 can have a trapezoidal cross-sectional shape that narrows upward from one surface of the protective layer PSV, but the present disclosure is not limited thereto. According to an embodiment, as Fig.11 shown, the first bank pattern BNK1 can include a curved surface having a semi-elliptical shape, a semi-circular shape, etc. in which the width narrows upward from one surface of the protective layer PSV. When viewed in cross-section, the shape of the first bank pattern BNK1 is not limited to the above embodiments and can be variably changed within a range that can improve the efficiency of light emitted from each of the light-emitting elements LD. Adjacent first bank patterns BNK1 can be disposed on the same plane on the protective layer PSV and can have the same height (or thickness).

[0212] The second bank pattern BNK2 can surround at least one side of the peripheral area of each pixel PXL. The second bank pattern BNK2 is a structure that defines (or divides) the emission area EMA between each pixel PXL and each of the adjacent pixels PXL, and can be, for example, a pixel defining layer. The second bank pattern BNK2 can be configured to include at least one light-blocking material and / or a reflective material to prevent light leakage defects in which light (or light rays) leak between each pixel PXL and the adjacent pixels PXL. According to an embodiment, a reflective material layer can be formed on the second bank pattern BNK2 to further improve the efficiency of light emitted from each pixel PXL. The second bank pattern BNK2 can be formed and / or disposed in a layer different from the layer of the first bank pattern BNK1, but the present disclosure is not limited thereto. According to an embodiment, the second bank pattern BNK2 can be formed and / or disposed in the same layer as the first bank pattern BNK1. In an embodiment of the present disclosure, the second bank pattern BNK2 can be formed in a layer different from the layer of the first bank pattern BNK1 and can be located on the first insulating layer INS1.

[0213] The first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 included in each pixel PXL may be spaced apart from each other. The second electrode EL2 and the third electrode EL3 may be disposed between the first electrode EL1 and the fourth electrode EL4. For example, the second electrode EL2 may be disposed between the first electrode EL1 and the third electrode EL3, and the third electrode EL3 may be disposed between the second electrode EL2 and the fourth electrode EL4. When viewed in a plan view, the first electrode EL1, the second electrode EL2, the third electrode EL3, and the fourth electrode EL4 may be spaced apart from each other.

[0214] In an embodiment of the present disclosure, the first electrode EL1 and the second electrode EL2 may be spaced apart from each other by a predetermined distance, the second electrode EL2 and the third electrode EL3 may be spaced apart from each other by a predetermined distance, and the third electrode EL3 and the fourth electrode EL4 may be spaced apart from each other by a predetermined distance. In the emission region EMA of each pixel PXL, the distance between the first electrode EL1 and the second electrode EL2, the distance between the second electrode EL2 and the third electrode EL3, and the distance between the third electrode EL3 and the fourth electrode EL4 may be the same. Accordingly, the light-emitting elements LD may be more uniformly aligned in the emission region EMA of each pixel PXL. However, the present disclosure is not limited thereto, and according to an embodiment, the distance between the first electrode EL1 and the second electrode EL2, the distance between the second electrode EL2 and the third electrode EL3, and the distance between the third electrode EL3 and the fourth electrode EL4 may be different from each other.

[0215] Each of the first electrode EL1 to the fourth electrode EL4 may be disposed and / or formed on the first bank pattern BNK1 to have a surface profile corresponding to the shape of the first bank pattern BNK1. For example, each of the first electrode EL1 to the fourth electrode EL4 may include a protruding portion corresponding to the first bank pattern BNK1 and a flat portion corresponding to the protective layer PSV. Each of the first electrode EL1 to the fourth electrode EL4 may be formed of a material having a constant reflectivity to allow the light emitted from each of the light-emitting elements LD to travel in the image display direction of the display device.

[0216] Each of the first electrode EL1 to the fourth electrode EL4 may be formed of a conductive material having a constant reflectivity. The conductive material may include an opaque metal that is conducive to reflecting the light emitted from the light-emitting element LD in the image display direction of the display device. The opaque metal may include metals such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, and their alloys as examples. According to an embodiment, each of the first electrode EL1 to the fourth electrode EL4 may include a transparent conductive material. The transparent conductive material may include conductive oxides such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), conductive polymers such as PEDOT, and the like. When each of the first electrode EL1 to the fourth electrode EL4 includes a transparent conductive material, it may further include a separate conductive layer formed of an opaque metal for reflecting the light emitted from the light-emitting element LD in the image display direction of the display device. However, the material of each of the first electrode EL1 to the fourth electrode EL4 is not limited to the above materials.

[0217] In addition, each of the first electrode EL1 to the fourth electrode EL4 may be provided and / or formed as a single layer, but the disclosure is not limited thereto. According to an embodiment, each of the first electrode EL1 to the fourth electrode EL4 may be provided and / or formed as a multilayer in which at least two materials among metals, alloys, conductive oxides, and conductive polymers are stacked. Each of the first electrode EL1 to the fourth electrode EL4 may be formed as a multilayer of at least two layers to minimize distortion caused by signal delay when a signal (or voltage) is transmitted to both ends of each of the light-emitting elements LD. For example, each of the first electrode EL1 to the fourth electrode EL4 may be formed of a multilayer in which ITO / Ag / ITO are sequentially stacked.

[0218] As described above, since each of the first electrode EL1 to the fourth electrode EL4 has a surface profile corresponding to the shape of the first bank pattern BNK1 provided thereunder, the light emitted from each of the light-emitting elements LD can be reflected by each of the first electrode EL1 to the fourth electrode EL4 to travel further in the image display direction of the display device. Finally, the efficiency of the light emitted from each of the light-emitting elements LD can be further improved.

[0219] The first bank pattern BNK1 and each of the first electrode EL1 to the fourth electrode EL4 may be used as a reflection member for improving the light efficiency of the display device by guiding the light emitted from the light-emitting element LD in a desired direction. That is, the first bank pattern BNK1 and each of the first electrode EL1 to the fourth electrode EL4 may be used as a reflection member for causing the light emitted from the light-emitting element LD to travel in the image display direction of the display device to improve the light output efficiency of the light-emitting element LD.

[0220] In an embodiment of the present disclosure, the fourth electrode EL4 among the first electrode EL1 to the fourth electrode EL4 may be located at the center (e.g., the core) of the emission region EMA of each pixel PXL, and may have a circular shape, but the present disclosure is not limited thereto. According to an embodiment, the fourth electrode EL4 may have an elliptical shape including a curve with a predetermined curvature, an annular shape, or the like. Additionally, according to an embodiment, the fourth electrode EL4 may have a polygonal shape such as a quadrilateral shape, a triangular shape, or an octagonal shape. The fourth electrode EL4 may be electrically connected to the fourth conductive line CL4 (PL2) of the pixel circuit portion PCL through the fourth contact hole CH4.

[0221] The third electrode EL3 may have a shape surrounding the periphery of the fourth electrode EL4 in the circumferential direction of the fourth electrode EL4. For example, the third electrode EL3 may have an annular shape (or a closed-loop shape) surrounding at least one side of the fourth electrode EL4. The third electrode EL3 may have an annular shape, but the present disclosure is not limited thereto. According to an embodiment, the third electrode EL3 is not limited to an annular shape, and may have a polygonal ring shape forming a closed circuit (including a rectangular ring shape of a quadrilateral shape and an octagonal ring shape of an octagonal shape, etc.). In the above embodiment, the third electrode EL3 has a shape completely surrounding the periphery of the fourth electrode EL4, but the present disclosure is not limited thereto. According to an embodiment, the third electrode EL3 may have a shape surrounding only the remaining region except for at least one region of the fourth electrode EL4. For example, it may have a "C" shape in which any part is open and does not form a perfect circle. The fourth electrode EL4 may be provided in an isolated circular island shape surrounded by the third electrode EL3, but the present disclosure is not limited thereto. The third electrode EL3 and the fourth electrode EL4 may be provided on the corresponding first bank pattern BNK1 with a predetermined distance therebetween.

[0222] The second electrode EL2 may have a shape surrounding the periphery of the third electrode EL3 along the circumferential direction of the third electrode EL3. For example, the second electrode EL2 may have an annular shape (or a closed-loop shape) surrounding at least one side of the third electrode EL3. The second electrode EL2 may have a circular ring shape, but the present disclosure is not limited thereto. According to an embodiment, the second electrode EL2 is not limited to a circular ring shape and may have a polygonal ring shape such as a quadrilateral shape or an octagonal shape forming a closed circuit. In the above embodiment, the second electrode EL2 has a shape completely surrounding the periphery of the third electrode EL3, but the present disclosure is not limited thereto. According to an embodiment, the second electrode EL2 may have a shape surrounding only the remaining area except for at least one area of the third electrode EL3. For example, it may have a "C" shape in which any part is open and does not form a perfect circle. The third electrode EL3 may be arranged in an isolated annular shape surrounded by the second electrode EL2, but the present disclosure is not limited thereto. The second electrode EL2 and the third electrode EL3 may be arranged on the corresponding first bank pattern BNK1 with a predetermined distance therebetween.

[0223] The first electrode EL1 may have a shape surrounding the periphery of the second electrode EL2 along the circumferential direction of the second electrode EL2. For example, the first electrode EL1 may have an annular shape (or a closed-loop shape) surrounding at least one side of the second electrode EL2. The first electrode EL1 may have a closed-loop shape surrounding the second electrode EL2 and including an inner surface formed by a curve with a predetermined curvature and an outer surface formed by a straight line, but the present disclosure is not limited thereto. According to an embodiment, the first electrode EL1 may have a circular ring shape in which both the inner surface and the outer surface are formed by curves, or may have a polygonal ring shape such as a quadrilateral shape or an octagonal shape forming a closed circuit. In the above embodiment, the first electrode EL1 has a shape completely surrounding the periphery of the second electrode EL2, but the present disclosure is not limited thereto. According to an embodiment, the first electrode EL1 may have a shape surrounding only the remaining area except for at least one area of the second electrode EL2. For example, it may have a "C" shape in which any part is open and does not form a perfect circle. The second electrode EL2 may be arranged in an isolated annular shape surrounded by the first electrode EL1, but the present disclosure is not limited thereto. The first electrode EL1 and the second electrode EL2 may be arranged on the corresponding first bank pattern BNK1 with a predetermined distance therebetween.

[0224] As described above, when the fourth electrode EL4 is located at the center of the emission region EMA of each pixel PXL, the third electrode EL3 surrounds the periphery of the fourth electrode EL4, the second electrode EL2 surrounds the periphery of the third electrode EL3, and the first electrode EL1 surrounds the periphery of the second electrode EL2, the first electrode EL1 to the fourth electrode EL4 may form a concentric circle structure.

[0225] In the emission area EMA of each pixel PXL, a plurality of light-emitting elements LD may be aligned and / or disposed between a first electrode EL1 and a second electrode EL2, between the second electrode EL2 and a third electrode EL3, and between the third electrode EL3 and a fourth electrode EL4. In the emission area EMA, the first electrode EL1 to the fourth electrode EL4 and the light-emitting elements LD may constitute a light-emitting unit EMU of each pixel PXL. The first electrode EL1 may be an anode electrode of the light-emitting unit EMU of each pixel PXL, and the fourth electrode EL4 may be a cathode electrode of the light-emitting unit EMU of each pixel PXL.

[0226] In an embodiment of the present disclosure, the first electrode EL1 may be electrically connected to the pixel circuit unit PCL through a first contact hole CH1. For example, the first electrode EL1 may be electrically connected to a first conductive line CL1 and a first transistor T1 of the pixel circuit unit PCL through the first contact hole CH1. Accordingly, a signal (or voltage) applied to the first transistor T1 may be transmitted to the first electrode EL1.

[0227] The second electrode EL2 may be connected to the pixel circuit unit PCL through a second contact hole CH2. For example, the second electrode EL2 may be electrically connected to a second conductive line CL2 of the pixel circuit unit PCL through the second contact hole CH2. In an embodiment of the present disclosure, since the second conductive line CL2 is in a floating state after the alignment of the light-emitting elements LD, any signal (or voltage) from the second conductive line CL2 may not be applied to the second electrode EL2.

[0228] The third electrode EL3 may be connected to the pixel circuit unit PCL through a third contact hole CH3. For example, the third electrode EL3 may be electrically connected to a third conductive line CL3 of the pixel circuit unit PCL through the third contact hole CH3. In an embodiment of the present disclosure, since the third conductive line CL3 is in a floating state after the alignment of the light-emitting elements LD, any signal (or voltage) from the third conductive line CL3 may not be applied to the third electrode EL3.

[0229] The fourth electrode EL4 may be electrically connected to the pixel circuit unit PCL through a fourth contact hole CH4. For example, the fourth electrode EL4 may be electrically connected to a fourth conductive line CL4 (PL2) through the fourth contact hole CH4. Accordingly, a second driving power source VSS applied to the fourth conductive line CL4 (PL2) may be transmitted to the fourth electrode EL4.

[0230] In the above embodiments, each of the light-emitting elements LD may be an ultra-small light-emitting element using an inorganic crystal structure material, such as having a size ranging from nanoscale to micrometer scale. For example, each of the light-emitting elements LD may be an ultra-small light-emitting element manufactured by an etching method or an ultra-small light-emitting element manufactured by a growth method. However, the type, size, shape, etc. of the light-emitting element LD may be variably changed. At least two to dozens of light-emitting elements LD may be aligned and / or disposed in the emission area EMA of each pixel PXL, but the number of the light-emitting elements LD is not limited thereto. According to an embodiment, the number of the light-emitting elements LD aligned and / or disposed in the emission area EMA of each pixel PXL may be variably changed.

[0231] In the emission area EMA, the light-emitting elements LD may be radially aligned and / or disposed with respect to the fourth electrode EL4. For example, a part of the light-emitting elements LD may be aligned and / or disposed along the circumferential direction of the fourth electrode EL4 between the fourth electrode EL4 and the third electrode EL3, another part of the light-emitting elements LD may be aligned and / or disposed along the circumferential direction of the third electrode EL3 between the third electrode EL3 and the second electrode EL2, and still another part of the light-emitting elements LD may be aligned and / or disposed along the circumferential direction of the second electrode EL2 between the second electrode EL2 and the first electrode EL1.

[0232] The light-emitting elements LD may be disposed in a dispersed form in a solution and may be injected into the emission area EMA of the pixel PXL.

[0233] In the disclosed embodiments, the light-emitting elements LD may be injected into the emission area EMA of each pixel PXL by an inkjet printing method, a slot coating method, or various other methods. For example, the light-emitting elements LD may be mixed with a volatile solvent and supplied to the emission area EMA of each pixel PXL by an inkjet printing method or a slot coating method. At this time, when an alignment signal (or alignment voltage) corresponding to each of the first electrode EL1 to the fourth electrode EL4 located in the emission area EMA of each pixel PXL is applied, an electric field may be formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. Accordingly, the light-emitting elements LD may be aligned between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. At this time, due to the shape of the first electrode EL1 to the fourth electrode EL4, the light-emitting elements LD may be aligned and / or disposed in a radial shape (or radially) along the circumferential direction of the fourth electrode EL4 located at the center (or middle) (e.g., core) of the emission area EMA of each pixel PXL.

[0234] After the light-emitting element LD is aligned, the solvent can be evaporated or removed by other methods, so that the light-emitting element LD can be finally aligned and / or disposed in the emission area EMA of each pixel PXL.

[0235] The light-emitting element LD may include a first light-emitting element LD1, a second light-emitting element LD2, and a third light-emitting element LD3. For example, the light-emitting element LD includes a plurality of first light-emitting elements LD1 disposed between the first electrode EL1 and the second electrode EL2, a plurality of second light-emitting elements LD2 disposed between the second electrode EL2 and the third electrode EL3, and a plurality of third light-emitting elements LD3 disposed between the third electrode EL3 and the fourth electrode EL4.

[0236] When the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, each of the first electrode EL1 to the fourth electrode EL4 can receive a predetermined alignment signal (or alignment voltage) from a corresponding conductive wire to serve as an alignment electrode (or alignment line) for aligning the light-emitting element LD. For example, the first electrode EL1 may be a first alignment electrode (or first alignment line) that receives a first alignment signal (or first alignment voltage) from the first conductive wire CL1, and the second electrode EL2 may be a second alignment electrode (or second alignment line) that receives a second alignment signal (or second alignment voltage) from the second conductive wire CL2. Additionally, the third electrode EL3 may be a third alignment electrode (or third alignment line) that receives a third alignment signal (or third alignment voltage) from the third conductive wire CL3, and the fourth electrode EL4 may be a fourth alignment electrode (or fourth alignment line) that receives a fourth alignment signal (or fourth alignment voltage) from the fourth conductive wire CL4. In an embodiment of the present disclosure, the first alignment signal to the fourth alignment signal may have different voltage levels. The first alignment signal to the fourth alignment signal may be a signal having a voltage difference and / or a phase difference to the extent that the light-emitting element LD can be aligned between the first electrode EL1 to the fourth electrode EL4. At least some of the above first alignment signal to the fourth alignment signal may be AC signals, but the present disclosure is not limited thereto.

[0237] When a corresponding alignment signal is applied to each of the first electrode EL1 to the fourth electrode EL4, an electric field can be formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. The light-emitting element LD can be aligned and / or disposed in the emission area EMA of each pixel PXL by the electric field formed between two adjacent electrodes.

[0238] After the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, a part of each of the second conductive line CL2 and the third conductive line CL3 can be removed or disconnected, and each of the second conductive line CL2 and the third conductive line CL3 can be in a floating state. For example, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the second conductive line CL2 can be in a floating state by removing one side thereof (e.g., a part not in contact with the second electrode EL2 or a part connected to an alignment pad (or "pad", also known as a "bonding pad") (not shown) to which a second alignment signal (or second alignment voltage) is applied). Additionally, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the third conductive line CL3 can be in a floating state by removing one side thereof (e.g., a part not in contact with the third electrode EL3 or a part connected to an alignment pad (not shown) to which a third alignment signal (or third alignment voltage) is applied).

[0239] After the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the first electrode EL1 to the fourth electrode EL4 can serve as driving electrodes for driving the light-emitting element LD.

[0240] In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the alignment of the light-emitting element LD supplied to the emission area EMA can be controlled to be relatively deflected by controlling the alignment signal (or alignment voltage) applied to each of the first electrode EL1 to the fourth electrode EL4 or by forming a magnetic field.

[0241] Each of the light-emitting elements LD can include a light-emitting element manufactured by an etching method or a core-shell structured light-emitting element manufactured by a growth method. When each of the light-emitting elements LD is a light-emitting element manufactured by an etching method, each light-emitting element LD can include a light-emitting stack (or stack pattern) in which a first semiconductor layer 11, an active layer 12, a second semiconductor layer 13, and an additional electrode 15 are sequentially stacked. Additionally, when each of the light-emitting elements LD is a core-shell structured light-emitting element manufactured by a growth method, each light-emitting element LD can include a light-emitting pattern 10, and the light-emitting pattern 10 includes a first semiconductor layer 11 located at the center (e.g., the core), an active layer 12 surrounding at least one side of the first semiconductor layer 11, a second semiconductor layer 13 surrounding at least one side of the active layer 12, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0242] Each of the light-emitting elements LD may include a first end EP1 and a second end EP2. The first end EP1 is electrically connected to one of two electrodes adjacent to each other in the emission region EMA, and the second end EP2 is electrically connected to the remaining one of the two adjacent electrodes. In the disclosed embodiments, the first end EP1 of each light-emitting element LD may be a first semiconductor layer 11 including an n-type semiconductor layer, and the second end EP2 may be a second semiconductor layer 13 including a p-type semiconductor layer. That is, in the emission region EMA of the pixel PXL, each light-emitting element LD may be connected between two adjacent electrodes in the forward direction at a predetermined distance. As described above, the light-emitting elements LD connected between two adjacent electrodes in the forward direction may constitute the light-emitting unit EMU of each pixel PXL.

[0243] The light-emitting element LD may include a first light-emitting element LD1 aligned and / or disposed between the first electrode EL1 and the second electrode EL2, a second light-emitting element LD2 aligned and / or disposed between the second electrode EL2 and the third electrode EL3, and a third light-emitting element LD3 aligned and / or disposed between the third electrode EL3 and the fourth electrode EL4.

[0244] In the embodiments of the present disclosure, one of the two ends EP1 and EP2 of each of the first light-emitting elements LD1 may be electrically connected to the second electrode EL2, and the other end EP2 may be electrically connected to the first electrode EL1. One of the two ends EP1 and EP2 of each of the second light-emitting elements LD2 may be electrically connected to the third electrode EL3, and the other end EP2 may be electrically connected to the second electrode EL2. One of the two ends EP1 and EP2 of each of the third light-emitting elements LD3 may be electrically connected to the fourth electrode EL4, and the other end EP2 may be electrically connected to the third electrode EL3.

[0245] In the emission area EMA of each pixel PXL, the first electrode EL1 and the second electrode EL2 may together with a first light-emitting element LD1 connected in parallel between the first electrode EL1 and the second electrode EL2 form a series stage (hereinafter referred to as the "first series stage"). In the emission area EMA of each pixel PXL, the second electrode EL2 and the third electrode EL3 may together with a second light-emitting element LD2 connected in parallel between the second electrode EL2 and the third electrode EL3 form another series stage (hereinafter referred to as the "second series stage"). In the emission area EMA of each pixel PXL, the third electrode EL3 and the fourth electrode EL4 may together with a third light-emitting element LD3 connected in parallel between the third electrode EL3 and the fourth electrode EL4 form yet another series stage (hereinafter referred to as the "third series stage"). In an embodiment of the present disclosure, the first series stage to the third series stage may be provided in the emission area EMA of each pixel PXL, and the first series stage to the third series stage may form a light-emitting unit EMU of the corresponding pixel PXL. The first electrode EL1 included in the first series stage of each pixel PXL may be the anode of the light-emitting unit EMU of the corresponding pixel PXL, and the fourth electrode EL4 included in the third series stage may be the cathode of the light-emitting unit EMU.

[0246] According to an embodiment, at least one reverse light-emitting element LDr connected in the reverse direction may be provided between two adjacent electrodes at each series stage, or at least one defective light-emitting element not connected to the two electrodes (e.g., an invalid light source (not shown)) may be provided between two adjacent electrodes at each series stage. For example, in the first series stage, at least one reverse light-emitting element LDr aligned and / or arranged in a direction opposite to the first light-emitting element LD1 may be provided between the first electrode EL1 and the second electrode EL2. In the second series stage, at least one reverse light-emitting element LDr aligned and / or arranged in a direction opposite to the second light-emitting element LD2 may be provided between the second electrode EL2 and the third electrode EL3. In the third series stage, at least one reverse light-emitting element LDr aligned and / or arranged in a direction opposite to the third light-emitting element LD3 may be provided between the third electrode EL3 and the fourth electrode EL4.

[0247] The above light-emitting element LD may be provided and / or formed on a first insulating layer INS1 in the emission area EMA of each pixel PXL.

[0248] The first insulating layer INS1 may be formed and / or disposed under each of the light-emitting elements LD, and each of the light-emitting elements LD is aligned and / or disposed between two electrodes constituting each series stage in the emission area EMA of each pixel PXL. The first insulating layer INS1 may fill the space between each of the light-emitting elements LD and the protective layer PSV to stably support the light-emitting elements LD and prevent the light-emitting elements LD from separating from the protective layer PSV.

[0249] In addition, in the emission area EMA of each pixel PXL, the first insulating layer INS1 may expose one area of each of the two electrodes constituting each series stage, and may cover the remaining area except for the one area. Here, the contact electrode CNE may be disposed and / or formed on one area of each of the exposed electrodes, so that each of the electrodes and the contact electrode CNE can be electrically connected and / or physically connected to each other.

[0250] The first insulating layer INS1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In the disclosed embodiment, the first insulating layer INS1 may be formed of an inorganic insulating layer that is conducive to protecting the light-emitting element LD from the influence of the pixel circuit portion PCL of each pixel PXL, but the disclosure is not limited thereto. According to an embodiment, the first insulating layer INS1 may be formed of an organic insulating layer that is conducive to flattening the support surface of the light-emitting element LD.

[0251] The second insulating layer INS2 may be disposed and / or formed on each of the light-emitting elements LD. The second insulating layer INS2 may be disposed and / or formed on each of the light-emitting elements LD to cover a part of the upper surface of each of the light-emitting elements LD and expose both ends EP1 and EP2 of each of the light-emitting elements LD to the outside. The second insulating layer INS2 may be formed in an independent pattern in the emission area EMA of each pixel PXL, but the disclosure is not limited thereto.

[0252] The second insulating layer INS2 may be composed of a single layer or multiple layers, and may include an inorganic insulating layer containing at least one inorganic material or an organic insulating layer containing at least one organic material. The second insulating layer INS2 may also fix each of the light-emitting elements LD aligned in the emission area EMA of each pixel PXL. In the disclosed embodiment, the second insulating layer INS2 may include an inorganic insulating layer that is conducive to protecting the active layer 12 of each of the light-emitting elements LD from the influence of external oxygen, moisture, etc. However, the disclosure is not limited thereto. The second insulating layer INS2 may include an organic insulating layer containing an organic material according to the design conditions of the display device to which the light-emitting element LD is applied.

[0253] In the disclosed embodiments, after the alignment of the light-emitting element LD is completed in the emission area EMA of each pixel PXL, the separation of the light-emitting element LD from the alignment position can be prevented by forming a second insulating layer INS2 on the light-emitting element LD. At the same time, as Fig.12 shown, when there is a gap (or space) between the first insulating layer INS1 and the light-emitting element LD before the formation of the second insulating layer INS2, the gap can be filled with the second insulating layer INS2 in the process of forming the second insulating layer INS2. Therefore, the light-emitting element LD can be constructed of an organic insulating layer that is favorable for filling the gap between the first insulating layer INS1 and the light-emitting element LD.

[0254] In the disclosed embodiments, the second insulating layer INS2 can be formed on the light-emitting element LD to prevent the active layer 12 of each of the light-emitting elements LD from contacting an external conductive material. The second insulating layer INS2 can cover only a part of the surface of each of the light-emitting elements LD so that both ends EP1 and EP2 of each of the light-emitting elements LD are exposed to the outside.

[0255] The contact electrode CNE can be provided on each of the first electrode EL1 to the fourth electrode EL4. The contact electrode CNE can be configured to more stably electrically connect each of the first electrode EL1 to the fourth electrode EL4 to the corresponding light-emitting element LD.

[0256] The contact electrode CNE can be formed of various transparent conductive materials. For example, the contact electrode CNE can include at least one of various transparent conductive materials including ITO, IZO, and ITZO, and can be substantially transparent or translucent to meet a predetermined light transmittance. However, the material of the contact electrode CNE is not limited to the above embodiments, and according to the embodiments, the contact electrode CNE can be formed of various opaque conductive materials. In the embodiments of the present disclosure, the contact electrode CNE can include a first contact electrode CNE1 provided on the first electrode EL1, a second contact electrode CNE2 provided on the second electrode EL2, a third contact electrode CNE3 provided on the third electrode EL3, and a fourth contact electrode CNE4 provided on the fourth electrode EL4.

[0257] The first contact electrode CNE1 can connect one end of the first electrode EL1 to one of the two ends EP1 and EP2 of each of the first light-emitting elements LD1 in the emission region EMA of each pixel PXL. When viewed in a plan view, the first contact electrode CNE1 can overlap with one end of each of the first light-emitting elements LD1 and each of the first electrodes EL1, and can be arranged in an annular shape. The shape of the first contact electrode CNE1 is not limited to the above embodiment. The first contact electrode CNE1 can be arranged in various shapes including an elliptical annular shape, a polygonal annular shape, etc. within a range capable of covering one end of each of the first light-emitting elements LD1 and the first electrode EL1.

[0258] The second contact electrode CNE2 can connect one side of the second electrode EL2 to the remaining end of one of the two ends EP1 and EP2 of each of the first light-emitting elements LD1 in the emission region EMA of each pixel PXL. Additionally, the second contact electrode CNE2 can connect the other side of the second electrode EL2 to one of the two ends EP1 and EP2 of each of the second light-emitting elements LD2 in the emission region EMA of each pixel PXL. When viewed in a plan view, the second contact electrode CNE2 can overlap with the remaining end of each of the first light-emitting elements LD1, the said one end of each of the second light-emitting elements LD2, and each of the second electrodes EL2, and can sufficiently cover the second electrode EL2, the remaining end of each of the first light-emitting elements LD1, and the said one end of each of the second light-emitting elements LD2. The second contact electrode CNE2 can be arranged in an annular shape surrounding the periphery of the third contact electrode CNE3. The shape of the second contact electrode CNE2 is not limited to the above embodiment. The second contact electrode CNE2 can be arranged in various shapes including an elliptical annular shape, a polygonal annular shape, etc. within a range capable of covering the remaining end of each of the first light-emitting elements LD1, the said one end of each of the second light-emitting elements LD2, and the second electrode EL2.

[0259] The third contact electrode CNE3 can connect one side of the third electrode EL3 to the remaining ends of the two ends EP1 and EP2 of each of the second light-emitting elements LD2 in the emission area EMA of each pixel PXL. Additionally, the third contact electrode CNE3 can connect the other side of the third electrode EL3 to one of the two ends EP1 and EP2 of each of the third light-emitting elements LD3 in the emission area EMA of each pixel PXL. When viewed in a plan view, the third contact electrode CNE3 can overlap with the remaining ends of each of the second light-emitting elements LD2, the said one end of each of the third light-emitting elements LD3, and each of the third electrodes EL3, and can sufficiently cover the third electrode EL3, the remaining ends of each of the second light-emitting elements LD2, and the said one end of each of the third light-emitting elements LD3. The third contact electrode CNE3 can be arranged in an annular shape surrounding the periphery of the fourth contact electrode CNE4. The shape of the third contact electrode CNE3 is not limited to the above embodiments. The third contact electrode CNE3 can be arranged in various shapes including an elliptical annular shape, a polygonal annular shape, etc. within the range capable of covering the third electrode EL3, the remaining ends of each of the second light-emitting elements LD2, and the said one end of each of the third light-emitting elements LD3.

[0260] The fourth contact electrode CNE4 can connect the fourth electrode EL4 to the remaining ends of each of the third light-emitting elements LD3 in the emission area EMA of each pixel PXL. When viewed in a plan view, the fourth contact electrode CNE4 can overlap with each of the fourth electrode EL4 and the remaining ends of each of the third light-emitting elements LD3, and can sufficiently cover the fourth electrode EL4 and the remaining ends of each of the third light-emitting elements LD3. The fourth contact electrode CNE4 can be arranged in an isolated circular island shape surrounded by the third electrode EL3. The shape of the fourth contact electrode CNE4 is not limited to the above embodiments. The fourth contact electrode CNE4 can be arranged in various shapes including an elliptical shape, a polygonal shape, etc. within the range capable of covering the fourth electrode EL4, the remaining ends of each of the third light-emitting elements LD3.

[0261] As described above, when the first contact electrode CNE1 having an annular shape surrounds the periphery of the second contact electrode CNE2 having an annular shape, the second contact electrode CNE2 having an annular shape surrounds the periphery of the third contact electrode CNE3 having an annular shape, and the third contact electrode CNE3 surrounds the periphery of the fourth contact electrode CNE4 having a circular shape, the first contact electrode CNE1 to the fourth contact electrode CNE4 can construct a concentric circle structure in the emission area EMA of each pixel PXL.

[0262] In an embodiment of the present disclosure, the encapsulation layer ENC may be provided and / or formed on the first contact electrode CNE1 to the fourth contact electrode CNE4. The encapsulation layer ENC may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the encapsulation layer ENC may have a structure in which at least one inorganic insulating layer or at least one organic insulating layer is alternately stacked. The encapsulation layer ENC may completely cover the display element portion DPL to prevent water or moisture from flowing into the display element portion DPL including the light-emitting element LD from the outside.

[0263] A cover layer (not shown) may be provided and / or formed in the emission area EMA of each pixel PXL. The cover layer may be provided and / or formed between each of the first electrode EL1 to the fourth electrode EL4 and the contact electrode CNE formed on each of the first electrode EL1 to the fourth electrode EL4. For example, the cover layer may be provided and / or formed between the first electrode EL1 and the first contact electrode CNE1, between the second electrode EL2 and the second contact electrode CNE2, between the third electrode EL3 and the third contact electrode CNE3, and between the fourth electrode EL4 and the fourth contact electrode CNE4. The above cover layer may prevent damage to each of the first electrode EL1 to the fourth electrode EL4 due to defects or the like occurring during the manufacturing process of the display device, and may also enhance the adhesion between each of the first electrode EL1 to the fourth electrode EL4 and the protective layer PSV. The cover layer may be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize the loss of light emitted from each of the light-emitting elements LD and reflected by each of the first electrode EL1 to the fourth electrode EL4 in the image display direction of the display device.

[0264] According to the above embodiment, the circular fourth electrode EL4 is provided at the center (or middle) (e.g., the core) of the emission area EMA of each pixel PXL, the third electrode EL3 is provided around the fourth electrode EL4, the second electrode EL2 is provided around the third electrode EL3, and the first electrode EL1 is provided around the second electrode EL2. In addition, by applying a predetermined alignment signal to each of the first electrode EL1 to the fourth electrode EL4 via a separate (or corresponding) conductive wire, an electric field is formed between two adjacent electrodes among the first electrode EL1 to the fourth electrode EL4. Due to the electric field formed between two adjacent electrodes, the light-emitting element LD can be aligned between the first electrode EL1 to the fourth electrode EL4.

[0265] At this time, the light-emitting element LD may be aligned and / or disposed in a radial shape (or radially) with respect to the fourth electrode EL4 formed in a circular island shape, and the fourth electrode EL4 is located at the center (or middle) (e.g., the core) of the emission region EMA of each pixel PXL. Accordingly, the light-emitting element LD may not be aligned and / or disposed in the emission region EMA of each pixel PXL to be biased in a specific direction. Accordingly, the light emitted from each of the light-emitting elements LD may not be concentrated in a specific direction. Accordingly, the amount (or intensity) of light emitted from the emission region EMA of each pixel PXL may be similar or substantially the same as the amount (or intensity) of light emitted from the emission region EMA of an adjacent pixel PXL. Finally, the display device according to an embodiment of the present disclosure may have a uniform light output distribution throughout the entire display area DA in which an image is displayed therein.

[0266] According to the above embodiment, the first electrode EL1 and the second electrode EL2 spaced apart from each other and the first light-emitting element LD1 connected in parallel between the first electrode EL1 and the second electrode EL2 constitute a first series stage, the second electrode EL2 and the third electrode EL3 spaced apart from each other and the second light-emitting element LD2 connected in parallel between the second electrode EL2 and the third electrode EL3 constitute a second series stage, and the third electrode EL3 and the fourth electrode EL4 spaced apart from each other and the third light-emitting element LD3 connected in parallel between the third electrode EL3 and the fourth electrode EL4 constitute a third series stage. The light-emitting elements LD included in each of two consecutive series stages may share one electrode to be electrically connected to each other. That is, the first light-emitting element LD1 included in the first series stage and the second light-emitting element LD2 included in the second series stage may share the second electrode EL2 to be electrically connected to each other. In addition, the second light-emitting element LD2 included in the second series stage and the third light-emitting element LD3 included in the third series stage may share the third electrode EL3 to be electrically connected to each other. In this way, the light-emitting unit EMU of each pixel PXL may be constructed by connecting the light-emitting elements LD aligned in the emission region EMA of each pixel PXL in a series / parallel hybrid structure.

[0267] According to the above embodiment, each pixel PXL may be stably driven by constructing the light-emitting unit EMU having a series / parallel hybrid structure, and thus the driving current flowing through the display panel of the display device may be reduced, thereby improving power consumption efficiency.

[0268] According to the above embodiments, the fourth electrode EL4 can be disposed at the center of the emission area EMA of each pixel PXL. The third electrode EL3 can be disposed around the fourth electrode EL4. The second electrode EL2 can be disposed around the third electrode EL3. The first electrode EL1 can be disposed around the second electrode EL2. Thus, the first electrode EL1 to the fourth electrode EL4 can have a concentric circle structure. In this case, the alignment and / or the integration degree of the light-emitting element LD disposed in the emission area EMA of each pixel PXL can be improved. Thus, the alignment area of the light-emitting element LD can be further ensured. Therefore, the display device according to the embodiments of the present disclosure can more easily achieve high resolution.

[0269] Fig.16 is a plan view showing a driving current flowing through a pixel according to an embodiment of the present disclosure, and as an example, shows the flow of the driving current flowing through Figure 8 the pixel. In Fig.16 when Figure 8 the pixel PXL is driven to emit light in response to a data signal of a predetermined gray scale, the flow of the driving current flowing through the pixel PXL is shown by a dotted arrow.

[0270] Referring to Figures 1a to 5 and Figure 7b and Figure 7c and Figures 8 to 16 when it is assumed that the driving current flows from the first power line PL1 to the fourth conductive line CL4 (PL2) through the first transistor T1 (e.g., a driving transistor) included in the pixel circuit portion PCL included in each pixel PXL, the driving current can flow into the light-emitting unit EMU of each pixel PXL through the first conductive line CL1 and the first contact hole CH1. For example, the driving current is supplied to the first electrode EL1 through the first conductive line CL1 and the first contact hole CH1, and the driving current flows to the second electrode EL2 via the first light-emitting element LD1. Thus, the first light-emitting element LD1 disposed between the first electrode EL1 and the second electrode EL2 can emit light having a brightness corresponding to the current assigned to each of the first light-emitting elements LD1. The driving current flowing through the second electrode EL2 flows to the third electrode EL3 via the second light-emitting element LD2 disposed between the second electrode EL2 and the third electrode EL3. Thus, the second light-emitting element LD2 can emit light having a brightness corresponding to the current assigned to each of the second light-emitting elements LD2. The driving current flowing through the third electrode EL3 flows to the fourth electrode EL4 via the third light-emitting element LD3 disposed between the third electrode EL3 and the fourth electrode EL4. Thus, the third light-emitting element LD3 can emit light having a brightness corresponding to the current assigned to each of the third light-emitting elements LD3.

[0271] In the above method, the driving current of each pixel PXL can flow while sequentially passing through a first light-emitting element LD1 disposed between a first electrode EL1 and a second electrode EL2, a second light-emitting element LD2 disposed between the second electrode EL2 and a third electrode EL3, and a third light-emitting element LD3 disposed between the third electrode EL3 and a fourth electrode EL4. Accordingly, each pixel PXL can emit light having a luminance corresponding to a data signal supplied during each frame period.

[0272] Figures 17a to 17f sequentially shows the manufacturing Figure 8 a schematic plan view of the method for manufacturing the pixel shown in Figures 18a to 18h sequentially shows the manufacturing Fig. 9 a cross-sectional view of the method for manufacturing the pixel shown in

[0273] Hereinafter, according to the manufacturing method in combination with Figures 17a to 17f and Figures 18a to 18h the pixels according to embodiments of the present disclosure shown in Figure 8 and Fig. 9 will be sequentially described.

[0274] Referring to Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 17a and Fig.18a a pixel circuit portion PCL included in each pixel PXL is formed on a substrate SUB. A pixel region PXA in which the pixel PXL is provided (or prepared) may include an emission region EMA that emits light and a peripheral region surrounding the periphery of the emission region EMA.

[0275] The pixel circuit portion PCL may include a pixel circuit 144, and the pixel circuit 144 includes at least one transistor T, first to fourth conductive lines CL1 to CL4, and at least one insulating layer. Here, the at least one insulating layer may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, and a protective layer PSV that are sequentially formed on the substrate SUB.

[0276] Each of the second interlayer insulating layer ILD2 and the protective layer PSV may include a first contact hole CH1 that exposes a part of the first conductive line CL1 integrally provided with a second terminal DE of the first transistor T1 included in the pixel circuit 144, a second contact hole CH2 that exposes a part of the second conductive line CL2, a third contact hole CH3 that exposes a part of the third conductive line CL3, and a fourth contact hole CH4 that exposes a part of the fourth conductive line CL4.

[0277] Each of the first conductive line CL1 to the fourth conductive line CL4 may be formed on the first interlayer insulating layer ILD1. When viewed in a plan view, each of the first conductive line CL1 to the fourth conductive line CL4 may extend in one direction and may be spaced apart from each other to be electrically separated and / or physically separated. For example, the first conductive line CL1 and the fourth conductive line CL4 may extend along a second direction DR2 (e.g., a vertical direction), and the second conductive line CL2 and the third conductive line CL3 may extend along a first direction DR1 that intersects (e.g., is orthogonal to) the second direction DR2.

[0278] In an embodiment of the present disclosure, each of the first conductive line CL1 to the fourth conductive line CL4 may be electrically connected to a different alignment pad (not shown) provided in the non-display area NDA of the display device DD. For example, the first conductive line CL1 may be electrically connected to the first alignment pad, the second conductive line CL2 may be electrically connected to the second alignment pad, the third conductive line CL3 may be electrically connected to the third alignment pad, and the fourth conductive line CL4 may be electrically connected to the fourth alignment pad. Different alignment signals (or alignment voltages) may be applied to the corresponding first alignment pad to the fourth alignment pad.

[0279] Refer to Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 、 Fig.17b 、 Fig.18a and Fig.18b On the protective layer PSV, a first bank pattern BNK1 is formed. On the protective layer PSV, the first bank pattern BNK1 may be spaced apart from an adjacent first bank pattern BNK1 by a predetermined distance. The first bank pattern BNK1 may include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0280] When viewed in a plan view, the first bank pattern BNK1 may be formed in an annular shape (or a closed-loop shape), and may form a concentric circle structure with an adjacent first bank pattern BNK1 in each emission area EMA. The shape of the first bank pattern BNK1 is not limited to the above embodiment, and may be provided in various shapes within a range capable of further ensuring the amount of light traveling in the image display direction of the display device through the first electrode EL1 to the fourth electrode EL4.

[0281] Refer to Figures 1a to 4b 、 Figure 5 、 Figure 7b 、 Figure 7c 、 Figures 8 to 16 、 Fig.17c and Figures 18a to 18c, on a protective layer PSV including a first bank pattern BNK1, first to fourth electrodes EL1 to EL4 including a conductive material (or substance) having a high reflectivity are formed.

[0282] Each of the first to fourth electrodes EL1 to EL4 can be formed on the first bank pattern BNK1.

[0283] The fourth electrode EL4 can be located at the center (or middle) (e.g., the core) of the emission region EMA of each pixel PXL, and the fourth electrode EL4 can be formed in an isolated circular island shape. The third electrode EL3 can be formed in an annular shape surrounding the periphery of the fourth electrode EL4 along the circumferential direction of the fourth electrode EL4. The second electrode EL2 can be formed in an annular shape surrounding the periphery of the third electrode EL3 along the circumferential direction of the third electrode EL3. The first electrode EL1 can be located at the outermost part of the emission region EMA of each pixel PXL, and the first electrode EL1 can be formed in a polygonal ring shape surrounding the periphery of the second electrode EL2 along the circumferential direction of the second electrode EL2.

[0284] In an embodiment of the present disclosure, the first electrode EL1 can be electrically connected to a first conductive line CL1 through a first contact hole CH1, the second electrode EL2 can be electrically connected to a second conductive line CL2 through a second contact hole CH2, the third electrode EL3 can be electrically connected to a third conductive line CL3 through a third contact hole CH3, and the fourth electrode EL4 can be electrically connected to a fourth conductive line CL4 through a fourth contact hole CH4.

[0285] Refer to Figures 1a to 4b , Figure 5 , Figure 7b , Figure 7c , Figures 8 to 16 and Figures 18a to 18d , an insulating material layer INSM is formed on the protective layer PSV including the first to fourth electrodes EL1 to EL4. The insulating material layer INSM can include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material.

[0286] Subsequently, a second bank pattern BNK2 is formed in the peripheral region of each pixel PXL. At this time, the second bank pattern BNK2 can be formed on the insulating material layer INSM. The second bank pattern BNK2 can be a structure (e.g., a pixel defining layer) that defines (or divides) the emission region EMA between each pixel PXL and adjacent pixels PXL.

[0287] Refer to Figures 1a to 4b , Figure 5 , Figure 7b , Figure 7c , Figures 8 to 16 , Fig.17d and Figures 18a to 18e By applying corresponding alignment signals (or alignment voltages) to each of the first electrode EL1 to the fourth electrode EL4 via the first conductive wire CL1 to the fourth conductive wire CL4, an electric field is formed between the first electrode EL1 to the fourth electrode EL4. For example, when an AC power source or a DC power source having a predetermined voltage and period is repeatedly applied to each of the first electrode EL1 to the fourth electrode EL4 a plurality of times, an electric field based on the potential difference between two adjacent electrodes among the first electrode EL1 to the fourth electrode EL4 can be formed.

[0288] In an embodiment of the present disclosure, the first electrode EL1 can receive a first alignment signal from a first alignment pad through the first conductive wire CL1, the second electrode EL2 can receive a second alignment signal from a second alignment pad through the second conductive wire CL2, the third electrode EL3 can receive a third alignment signal from a third alignment pad through the third conductive wire CL3, and the fourth electrode EL4 can receive a fourth alignment signal from a fourth alignment pad through the fourth conductive wire CL4. The first alignment signal to the fourth alignment signal can have different voltage levels.

[0289] As described above, in a state where an electric field is formed between the first electrode EL1 to the fourth electrode EL4, a mixed solution including a light-emitting element LD is injected (or supplied) into the emission region EMA of each pixel PXL using an inkjet printing method or the like. For example, an inkjet nozzle can be provided on an insulating material layer INSM, and a solvent in which a plurality of light-emitting elements LD are mixed can be injected (or supplied) into the emission region EMA of each pixel PXL through the inkjet nozzle. Here, the solvent can be any one or more of acetone, water, ethanol, and toluene, but the present disclosure is not limited thereto. For example, the solvent can be in the form of ink or paste. The method of injecting (or supplying) the light-emitting element LD into the emission region EMA of each pixel PXL is not limited to the above embodiment, and the method of injecting (or supplying) the light-emitting element LD can be changed differently.

[0290] After injecting (or supplying) the light-emitting element LD into the emission region EMA of each pixel PXL, the solvent can be removed.

[0291] When the light-emitting element LD is injected into the emission region EMA, self-alignment of the light-emitting element LD can be caused by an electric field formed between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. Therefore, the light-emitting element LD can be aligned between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and between the third electrode EL3 and the fourth electrode EL4. At this time, the light-emitting element LD can be aligned and / or disposed on the insulating material layer INSM between two corresponding adjacent electrodes in the emission region EMA of each pixel PXL. For example, the first light-emitting element LD1 can be aligned on the insulating material layer INSM between the first electrode EL1 and the second electrode EL2, the second light-emitting element LD2 can be aligned on the insulating material layer INSM between the second electrode EL2 and the third electrode EL3, and the third light-emitting element LD3 can be aligned on the insulating material layer INSM between the third electrode EL3 and the fourth electrode EL4.

[0292] According to an embodiment, the light-emitting element LD may include at least one reverse light-emitting element LDr, and the at least one reverse light-emitting element LDr is connected in a direction opposite to the forward direction in the emission region EMA of each pixel PXL according to the waveform, intensity, etc. of the alignment signal applied to each of the first electrode EL1 to the fourth electrode EL4.

[0293] As described above, by adjusting the direction or intensity of the electric field formed between the first electrode EL1 to the fourth electrode EL4 by adjusting the alignment signal applied in the step of aligning the light-emitting element LD, the ratio of the light-emitting element (e.g., the reverse light-emitting element LDr) connected in a direction opposite to the light-emitting element LD in the forward direction in the emission region EMA of each pixel PXL can be adjusted, or the light-emitting element LD in the forward direction can be densely arranged at a specific position.

[0294] In an embodiment of the present disclosure, the light-emitting element LD can be aligned and / or disposed in a radial shape (or radially) with respect to the fourth electrode EL4 in the emission region EMA of each pixel PXL. After the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, each of the first alignment pad to the fourth alignment pad can stop supplying the corresponding alignment signal to the corresponding conductive wire. According to an embodiment, after the light-emitting element LD is aligned, each of the first alignment pad to the fourth alignment pad can be electrically disconnected from the corresponding conductive wire, so that each of the first alignment pad to the fourth alignment pad can not supply the corresponding alignment signal to the corresponding conductive wire.

[0295] Refer to Figures 1a to 4b 、 Figure 5 、 Figure 7b 、Figure 7c , Figures 8 to 16 and Figures 18a to 18f , after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, a second insulating layer INS2 is formed on each of the light-emitting elements LD. The second insulating layer INS2 may cover at least a part of the upper surface of each of the light-emitting elements LD, so that both ends EP1 and EP2 except for the active layer 12 of each of the light-emitting elements LD are exposed to the outside.

[0296] The insulating material layer INSM can be etched by the process of forming the second insulating layer INS2 or the etching process performed before and after the process of forming the second insulating layer INS2, so that a part of each of the first electrode EL1 to the fourth electrode EL4 is exposed, and thus the first insulating layer INS1 can be formed.

[0297] Referring to Figures 1a to 4b , Figure 5 , Figure 7b , Figure 7c , Figures 8 to 16 , Figure 17e and Figures 18a to 18g , the first contact electrode CNE1 to the fourth contact electrode CNE4 are formed on the protective layer PSV including the second insulating layer INS2.

[0298] The first contact electrode CNE1 can be directly formed on one of both ends EP1 and EP2 of each of the first electrode EL1 and the first light-emitting element LD1. The second contact electrode CNE2 can be directly formed on the remaining end of both ends EP1 and EP2 of each of the second electrode EL2 and the first light-emitting element LD1 and on one of both ends EP1 and EP2 of each of the second light-emitting elements LD2. The third contact electrode CNE3 can be directly formed on the remaining end of both ends EP1 and EP2 of each of the third electrode EL3 and each of the second light-emitting elements LD2 and on one of both ends EP1 and EP2 of each of the third light-emitting elements LD3. The fourth contact electrode CNE4 can be directly formed on the remaining end of both ends EP1 and EP2 of each of the fourth electrode EL4 and the third light-emitting element LD3.

[0299] Referring to Figures 1a to 4b , Figure 5 , Figure 7b , Figure 7c , Figures 8 to 16 , Figure 17f and Figures 18a to 18h, a part of each of the second conductive line CL2 and the third conductive line CL3 is removed so that each of the second conductive line CL2 and the third conductive line CL3 is in a floating state. Accordingly, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 aligned in the emission area EMA of each pixel PXL can be connected in series, and thus a driving current can flow from the first power line PL1 to the fourth conductive line CL4 (PL2) through the first transistor T1 (e.g., a driving transistor) of the pixel circuit 144 included in each pixel PXL.

[0300] When performing the process of removing a part of each of the second conductive line CL2 and the third conductive line CL3, a part of the first electrode EL1 located between each pixel PXL and an adjacent pixel PXL thereto can be removed. Accordingly, each pixel PXL can be driven independently (or individually) from an adjacent pixel PXL thereto.

[0301] Subsequently, an encapsulation layer ENC covering the first contact electrode CNE1 to the fourth contact electrode CNE4 is formed. The encapsulation layer ENC may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked.

[0302] Figure 19 is a diagram showing a pixel according to another embodiment, and is a schematic plan view of a pixel including only a partial configuration of a display element unit. Figure 8 In

[0303] In Figure 19 , the structure of the pixel PXL is simplified, such as only showing the first conductive line to the fourth conductive line, the first electrode to the fourth electrode, and a plurality of light-emitting elements included in the pixel PXL, but the present disclosure is not limited thereto.

[0304] Regarding Figure 19 the pixel of Figure 8 , a detailed description of a configuration identical or similar to the configuration of the above

[0305] embodiment is omitted. Figures 1a to 5 、 Figure 7b 、 Figure 7c and Figure 19 , in which a pixel area PXA provided with each pixel PXL may include an emission area EMA that emits light and a peripheral area surrounding the periphery of the emission area EMA. Each pixel PXL may include a first conductive line CL1 to a fourth conductive line CL4, a first electrode EL1 to a fourth electrode EL4, and a plurality of light-emitting elements LD.

[0306] The fourth electrode EL4 may be located at the center (or middle) (e.g., the core) of the emission area EMA of each pixel PXL and may have a circular island shape. The third electrode EL3 may have an annular shape surrounding the periphery of the fourth electrode EL4 along the circumferential direction of the fourth electrode EL4. At this time, the third electrode EL3 and the fourth electrode EL4 may be spaced apart from each other by a predetermined distance and may be electrically separated from each other. That is, the third electrode EL3 and the fourth electrode EL4 may be insulated from each other. The fourth electrode EL4 may be surrounded by the third electrode EL3 and may be isolated.

[0307] The second electrode EL2 may have an annular shape surrounding the periphery of the third electrode EL3 along the circumferential direction of the third electrode EL3. At this time, the second electrode EL2 and the third electrode EL3 may be spaced apart from each other by a predetermined distance and may be electrically separated from each other. That is, the second electrode EL2 and the third electrode EL3 may be insulated from each other. The third electrode EL3 may be surrounded by the second electrode EL2 and may be isolated.

[0308] The first electrode EL1 may have a polygonal ring shape surrounding the periphery of the second electrode EL2 along the circumferential direction of the second electrode EL2. Specifically, the first electrode EL1 may have a polygonal shape (e.g., an octagonal shape) in which the inner surface adjacent to the second electrode EL2 has an annular shape formed by a curve having a predetermined curvature, and the outer surface located at the outermost part of the emission area EMA is formed by a straight line. The first electrode EL1 and the second electrode EL2 having the above shape may be spaced apart from each other by a predetermined distance and may be electrically separated from each other. That is, the first electrode EL1 and the second electrode EL2 may be insulated from each other. The second electrode EL2 may be surrounded by the first electrode EL1 and may be isolated. In the above embodiment, the first electrode EL1 has a polygonal ring shape, but the present disclosure is not limited thereto. According to an embodiment, the first electrode EL1 may have the same annular shape as the second electrode EL2 and the third electrode EL3.

[0309] In the emission area EMA of each pixel PXL, the first electrode EL1 to the fourth electrode EL4 may have a concentric circle structure. The light-emitting element LD may be aligned and / or disposed between the first electrode EL1 to the fourth electrode EL4. The light-emitting element LD may be aligned and / or disposed in a radial shape (or radially) with respect to the fourth electrode EL4 in the emission area EMA. Therefore, the light-emitting element LD may not be aligned and / or disposed in a specific direction and may be biased in the emission area EMA of each pixel PXL. Therefore, the light emitted from each of the light-emitting elements LD may travel in various directions without being concentrated in a specific direction.

[0310] Figure 20 is a schematic plan view showing a pixel according to still another embodiment,Figure 21 is a cross-sectional view taken along line V-V' Figure 20 and is a plan view showing the driving current flowing through the pixel according to an embodiment of the present disclosure, and shows, for example, the flow of the driving current flowing through the pixel Figure 22 and is a view showing the shape when the light-emitting element is aligned in the pixel Figure 20 and is a schematic plan view of a pixel including only a partial structure of the display element portion. Figure 23 Regarding the pixel Figure 20 , the differences from the above-described embodiment are mainly described to avoid redundant description. Parts not specifically described in the present disclosure are based on the above-described embodiment, and the same reference numerals denote the same components, and similar reference numerals denote similar components.

[0311] Referring to Figures 20 to 23 , each pixel PXL may include a pixel circuit portion PCL and a display element portion DPL. The pixel circuit portion PCL includes a pixel circuit 144, and the display element portion DPL includes a plurality of light-emitting elements LD. The light-emitting element LD may be located in an emission region EMA of a pixel region PXA in which each pixel PXL is provided.

[0312] The pixel circuit portion PCL may include at least one transistor T, a first conductive line CL1 and a second conductive line CL2, and at least one insulating layer. The display element portion DPL may include a first electrode EL1 to a fourth electrode EL4, a plurality of light-emitting elements LD, a first bank pattern BNK1 and a second bank pattern BNK2, and a contact electrode CNE. Figures 1a to 5 、 Figure 7b 、 Figure 7c and Figures 20 to 23 , the first conductive line CL1 and the second conductive line CL2 may have a strip shape extending in a second direction DR2 (for example, a vertical direction) on the substrate SUB. The first conductive line CL1 and the second conductive line CL2 may be provided and / or formed on a first interlayer insulating layer ILD1. The first conductive line CL1 may be integrally provided with a second terminal DE of a driving transistor (for example, a first transistor T1) included in the pixel circuit portion PCL to be electrically connected to the second terminal DE of the first transistor T1. According to an embodiment, the first conductive line CL1 may be provided non-integrally with the second terminal DE of the first transistor T1 and may be electrically connected to the second terminal DE of the first transistor T1 by a separate connection method such as a contact hole and a bridge electrode.

[0313]

[0314]

[0315] ​​The first conductive line CL1 can be electrically connected to the first electrode EL1 of the display element portion DPL through the first contact hole CH1 penetrating the second interlayer insulating layer ILD2 and the protective layer PSV. Additionally, the first conductive line CL1 can be electrically connected to a partial structure (e.g., the 3-2 electrode EL3_2) of the third electrode EL3 of the display element portion DPL through the third contact hole CH3 penetrating the second interlayer insulating layer ILD2 and the protective layer PSV. Here, the 3-2 electrode EL3_2 can be in an electrically isolated state, e.g., in a floating state. That is, the first conductive line CL1 can be connected to the 3-2 electrode EL3_2 serving as a floating electrode through the third contact hole CH3.

[0316] In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the first conductive line CL1 can allow each of the first electrode EL1 and the third electrode EL3 to serve as a first alignment electrode (or first alignment line) by transmitting a predetermined alignment signal (or alignment voltage) to the first electrode EL1 and the third electrode EL3. Additionally, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the first conductive line CL1 can be electrically connected to a driving transistor (e.g., the first transistor T1) of the pixel circuit portion PCL to allow the first electrode EL1 to serve as a driving electrode of the light-emitting element LD. Additionally, after the light-emitting element LD is aligned, by removing a part of the third electrode EL3, the first conductive line CL1 can be connected to the 3-2 electrode EL3_2 in a floating state.

[0317] The second conductive line CL2 can be electrically connected to the fourth electrode EL4 of the display element portion DPL through the fourth contact hole CH4 penetrating the second interlayer insulating layer ILD2 and the protective layer PSV. Additionally, the second conductive line CL2 can be electrically connected to a partial structure (e.g., the 2-2 electrode EL2_2) of the second electrode EL2 of the display element portion DPL through the second contact hole CH2 penetrating the second interlayer insulating layer ILD2 and the protective layer PSV. Here, the 2-2 electrode EL2_2 can be in an electrically isolated state, e.g., in a floating state. That is, the second conductive line CL2 can be connected to the 2-2 electrode EL2_2 serving as a floating electrode through the second contact hole CH2. The second conductive line CL2 can be the second power supply line PL2 to which the second driving power supply VSS is applied in the pixel PXL shown in Figure 7b and Figure 7c the pixel PXL shown in

[0318] In an embodiment of the present disclosure, when the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the second conductive line CL2 can allow each of the second electrode EL2 and the fourth electrode EL4 to serve as a second alignment electrode (or second alignment line) by transmitting a predetermined alignment signal (or alignment voltage) to the second electrode EL2 and the fourth electrode EL4. Additionally, after the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the second conductive line CL2 can allow the fourth electrode EL4 to serve as a driving electrode of the light-emitting element by transmitting the second driving power supply VSS to the fourth electrode EL4. Additionally, after aligning the light-emitting element LD, by removing a part of the second electrode EL2, the second conductive line CL2 can be connected to the 2-2 electrode EL2_2 in a floating state.

[0319] In an embodiment of the present disclosure, the fourth electrode EL4 may have a circular shape disposed at the center (or middle) (e.g., the core) of the emission area EMA of each pixel PXL.

[0320] The third electrode EL3 may be spaced apart from the fourth electrode EL4 and may have a shape surrounding the periphery of the fourth electrode EL4 along the circumferential direction of the fourth electrode EL4. In an embodiment of the present disclosure, the third electrode EL3 may include a 3-1 electrode EL3_1 having a shape in which at least one area is open (or unclosed) and a 3-2 electrode EL3_2 spaced apart from the 3-1 electrode EL3_1. For example, the 3-1 electrode EL3_1 may have a "C" shape.

[0321] Before the light-emitting element LD is aligned in the emission area EMA of each pixel PXL, the third electrode EL3 may be disposed in an elliptical ring shape surrounding the fourth electrode EL4, as Figure 23 shown. When the light-emitting element LD is aligned in the emission area EMA, the third electrode EL3 can serve as a first alignment electrode for aligning the light-emitting element by receiving a first alignment signal (or first alignment voltage) from the first conductive line CL1 together with the first electrode EL1. That is, when the light-emitting element LD is aligned in the emission area EMA, the same alignment signal (e.g., the first alignment signal) can be transmitted to the first electrode EL1 and the third electrode EL3 through the first conductive line CL1.

[0322] When the alignment of the light-emitting element LD is completed, a part of the third electrode EL3 can be removed or disconnected. Accordingly, after the alignment of the light-emitting element LD is completed, the third electrode EL3 can be provided in a shape including a 3-1 electrode EL3_1 in which at least one region is open and a 3-2 electrode EL3_2 spaced apart from and electrically separated from the 3-1 electrode EL3_1. When the alignment of the light-emitting element LD is completed, the 3-1 electrode EL3_1 can become a connection path for applying a driving current to the light-emitting element LD aligned between the third electrode EL3 and an electrode adjacent to the third electrode EL3, and the 3-2 electrode EL3_2 can be in a floating state. In an embodiment of the present disclosure, the 3-1 electrode EL3_1 can be provided in a shape surrounding one region of the fourth electrode EL4, and the 3-2 electrode EL3_2 can be provided in a shape surrounding another region of the fourth electrode EL4. When viewed in a plan view, the 3-2 electrode EL3_2 can be provided and / or formed in an opening region of the third electrode EL3.

[0323] The second electrode EL2 can be spaced apart from the third electrode EL3 and can have a shape surrounding the periphery of the third electrode EL3. In an embodiment of the present disclosure, the second electrode EL2 can include a 2-1 electrode EL2_1 in which at least one region is open (or unclosed) and a 2-2 electrode EL2_2 spaced apart from the 2-1 electrode EL2_1. For example, the 2-1 electrode EL2_1 can have a "C" shape.

[0324] Before the light-emitting element LD is aligned in the emission region EMA of each pixel PXL, the second electrode EL2 can have an elliptical ring shape surrounding the third electrode EL3, as Figure 23 shown. When the light-emitting element LD is aligned in the emission region EMA, the second electrode EL2 can be used as a second alignment electrode for aligning the light-emitting element by receiving a second alignment signal (or a second alignment voltage) from the second conductive line CL2 together with the fourth electrode EL4. That is, when the light-emitting element LD is aligned in the emission region EMA, the same alignment signal (e.g., the second alignment signal) can be transmitted to the second electrode EL2 and the fourth electrode EL4 through the second conductive line CL2.

[0325] When the alignment of the light-emitting element LD is completed, a part of the second electrode EL2 can be removed or disconnected. Therefore, after the alignment of the light-emitting element LD is completed, the second electrode EL2 can be arranged in a shape including a 2-1 electrode EL2_1 in which at least one region is open and a 2-2 electrode EL2_2 spaced apart from and electrically separated from the 2-1 electrode EL2_1. When the alignment of the light-emitting element LD is completed, the 2-1 electrode EL2_1 can become a connection path for applying a driving current to the light-emitting element LD aligned between the second electrode EL2 and the electrode adjacent to the second electrode EL2, and the 2-2 electrode EL2_2 can be in a floating state. In an embodiment of the present disclosure, the 2-1 electrode EL2_1 can be arranged in a shape surrounding one region of the third electrode EL3, and the 2-2 electrode EL2_2 can be arranged in a shape surrounding another region of the third electrode EL3. When viewed in a plan view, the 2-2 electrode EL2_2 can be arranged and / or formed in an opening region of the second electrode EL2.

[0326] The first electrode EL1 can be spaced apart from the second electrode EL2 and can have a shape surrounding the periphery of the second electrode EL2. For example, the first electrode EL1 can have a diamond-shaped ring shape surrounding the periphery of the second electrode EL2.

[0327] The above-described first electrode EL1 to fourth electrode EL4 can have a concentric circle structure in the emission region EMA of each pixel PXL. Therefore, the light-emitting element LD can be aligned in a radial shape (or radially) with respect to the fourth electrode EL4 located at the core of the emission region EMA.

[0328] The light-emitting element LD can include at least one first light-emitting element LD1 aligned between the first electrode EL1 and the second electrode EL2, at least one second light-emitting element LD2 aligned between the second electrode EL2 and the third electrode EL3, and at least one third light-emitting element LD3 aligned between the third electrode EL3 and the fourth electrode EL4.

[0329] In the emission region EMA of each pixel PXL, the first electrode EL1 and the second electrode EL2 and the first light-emitting element LD1 connected in parallel between the first electrode EL1 and the second electrode EL2 can constitute a first series stage, the second electrode EL2 and the third electrode EL3 and the second light-emitting element LD2 connected in parallel between the second electrode EL2 and the third electrode EL3 can constitute a second series stage, and the third electrode EL3 and the fourth electrode EL4 and the third light-emitting element LD3 connected in parallel between the third electrode EL3 and the fourth electrode EL4 can constitute a third series stage. At least one reverse light-emitting element LDr connected in the reverse direction can also be provided between two adjacent electrodes in each series stage.

[0330] When a driving current is assumed to flow from a first power line PL1 to a second conductive line CL2 through a first transistor T1 included in a pixel circuit portion PCL included in each pixel PXL, the driving current can flow into a first electrode EL1 through a first conductive line CL1 and a first contact hole CH1. The driving current flowing into the first electrode EL1 flows into a second - 1 electrode EL2_1 via a first light - emitting element LD1. Accordingly, the first light - emitting element LD1 disposed between the first electrode EL1 and the second - 1 electrode EL2_1 can emit light having a luminance corresponding to the current assigned to each of the first light - emitting elements LD1. The driving current flowing through the second - 1 electrode EL2_1 flows into a third - 1 electrode EL3_1 via a second light - emitting element LD2. Accordingly, the second light - emitting element LD2 can emit light having a luminance corresponding to the current assigned to each of the second light - emitting elements LD2. The driving current flowing through the third - 1 electrode EL3_1 flows into a fourth electrode EL4 via a third light - emitting element LD3. Accordingly, the third light - emitting element LD3 can emit light having a luminance corresponding to the current assigned to each of the third light - emitting elements LD3.

[0331] In the above method, the driving current of each pixel PXL can flow while sequentially passing through a first light - emitting element LD1 disposed between a first electrode EL1 and a second - 1 electrode EL2_1, a second light - emitting element LD2 disposed between the second - 1 electrode EL2_1 and a third - 1 electrode EL3_1, and a third light - emitting element LD3 disposed between the third - 1 electrode EL3_1 and a fourth electrode EL4. Accordingly, each pixel PXL can emit light having a luminance corresponding to a data signal supplied during each frame period.

[0332] Although the above has been described with reference to the preferred embodiments of the present disclosure, those skilled in the art or those having ordinary knowledge in the corresponding technical field will understand that the present disclosure can be differently changed and modified without departing from the technical scope of the present disclosure described in the claims.

[0333] Therefore, the technical scope of the present disclosure should not be limited to the content described in the detailed description of the specification, but should be defined by the claims.

Claims

1. A display device, the display device comprising: a substrate including a display area and a non-display area, the display area including a plurality of pixel areas each including an emission area; and pixels disposed in each of the plurality of pixel areas, wherein the pixels include: a first electrode; a second electrode spaced apart from the first electrode and surrounding the periphery of the first electrode; a third electrode spaced apart from the second electrode and surrounding the periphery of the second electrode; a fourth electrode spaced apart from the third electrode and surrounding the periphery of the third electrode; a plurality of light-emitting elements disposed between the first electrode and the fourth electrode; and a first conductive wire and a second conductive wire disposed below the first electrode to the fourth electrode, and an insulating layer is disposed between the first conductive wire and the second conductive wire and the first electrode to the fourth electrode, the first conductive wire is electrically connected to the first electrode, and the second conductive wire is electrically connected to the fourth electrode, wherein the plurality of light-emitting elements include: a first light-emitting element disposed between the first electrode and the second electrode; a second light-emitting element disposed between the second electrode and the third electrode; and a third light-emitting element disposed between the third electrode and the fourth electrode.

2. The display device according to claim 1, wherein, when viewed in a plan view, each of the second electrode to the fourth electrode has an annular shape, and the first electrode has an isolated circular island shape surrounded by the second electrode to the fourth electrode.

3. The display device according to claim 1, wherein, the first light-emitting element is disposed between the first electrode and the second electrode along a circumferential direction centered on the first electrode, the second light-emitting element is disposed between the second electrode and the third electrode along a circumferential direction centered on the second electrode, and the third light-emitting element is disposed between the third electrode and the fourth electrode along a circumferential direction centered on the third electrode.

4. The display device according to claim 3, wherein, the first conductive wire and the second conductive wire are disposed on the same layer.

5. The display device according to claim 3, wherein, the first conductive wire and the second conductive wire are disposed on different layers.

6. The display device according to claim 5, wherein, the insulating layer includes a first insulating layer and a second insulating layer sequentially stacked on the substrate, the first conductive wire is disposed on one of the first insulating layer and the second insulating layer, and the second conductive wire is disposed on the other of the first insulating layer and the second insulating layer.

7. The display device according to claim 5, wherein, the pixel further includes: a third conductive wire connected to the second electrode, and the insulating layer is disposed between the third conductive wire and the second electrode; and a fourth conductive wire connected to the third electrode, and the insulating layer is disposed between the fourth conductive wire and the third electrode, and the third conductive wire and the fourth conductive wire are in a floating state.

8. The display device according to claim 7, wherein, the third conductive wire and the fourth conductive wire are disposed on the same layer as the first conductive wire and the second conductive wire.

9. The display device according to claim 7, wherein, the third conductive wire and the fourth conductive wire are disposed on different layers.

10. The display device according to claim 7, wherein, the first light-emitting element forms a first stage connected in parallel between the first electrode and the second electrode, the second light-emitting element forms a second stage connected in parallel between the second electrode and the third electrode, and the third light-emitting element forms a third stage connected in parallel between the third electrode and the fourth electrode.

11. The display device according to claim 1, wherein, the pixel further includes: a bank pattern disposed under each of the first electrode to the fourth electrode; and contact electrodes respectively disposed on the first electrode to the fourth electrode.

12. The display device according to claim 11, wherein, the second electrode includes a 2-1 electrode surrounding one region of the first electrode and a 2-2 electrode spaced apart from the 2-1 electrode and surrounding another region of the first electrode, and the third electrode includes a 3-1 electrode surrounding one region of the second electrode and a 3-2 electrode spaced apart from the 3-1 electrode and surrounding another region of the second electrode.

13. The display device according to claim 12, wherein, the 2-2 electrode and the 3-2 electrode are in a floating state.

14. The display device according to claim 12, wherein, the 2-2 electrode is connected to the second conductive wire, and the 3-2 electrode is connected to the first conductive wire.

15. The display device according to claim 14, wherein, the first conductive wire and the second conductive wire are disposed on the same layer.

16. The display device according to claim 1, wherein, the pixel further includes a pixel circuit portion, the pixel circuit portion includes at least one transistor electrically connected to the fourth electrode, and the first electrode is the cathode of the pixel, and the fourth electrode is the anode of the pixel.

17. A method of manufacturing a display device, the method comprising: providing pixels including a pixel region, wherein the step of providing the pixels includes forming a pixel circuit portion and forming a display element portion, the step of forming the pixel circuit portion includes: forming at least one transistor and first, second, third, and fourth conductive wires spaced apart from each other on a substrate; and forming a protective layer on the transistor and the first to fourth conductive wires, and The steps of forming the display element portion include: forming a first electrode connected to the first conductive wire, a second electrode spaced apart from the first electrode and connected to the second conductive wire, a third electrode spaced apart from the second electrode and connected to the third conductive wire, and a fourth electrode spaced apart from the third electrode and connected to the fourth conductive wire on the protective layer; forming an electric field between the first electrode and the second electrode, between the second electrode and the third electrode, and between the third electrode and the fourth electrode by applying alignment signals corresponding to each of the first conductive wire to the fourth conductive wire, and aligning a plurality of light-emitting elements between the first electrode and the fourth electrode; and forming a contact electrode on each of the first electrode to the fourth electrode.

18. The method according to claim 17, the method further comprises: removing a part of each of the second conductive wire and the third conductive wire after forming the contact electrode.

19. The method according to claim 17, wherein, the first electrode is located at the center of the pixel region, the second electrode surrounds the periphery of the first electrode, the third electrode surrounds the periphery of the second electrode, and the fourth electrode surrounds the periphery of the third electrode.

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