A MEMS device, a preparation method thereof, and an electronic device

Abstract

The present application discloses a MEMS device, a preparation method thereof, and an electronic device. The preparation method includes: providing a semiconductor substrate, forming a vibrating membrane on the semiconductor substrate; performing a first annealing step; forming a sacrificial material layer on the vibrating membrane to cover the vibrating membrane; forming a backplane on the sacrificial material layer; performing a second annealing step; removing the sacrificial material layer between the vibrating membrane and the backplane to form a cavity. By combining multiple annealing steps and separately adjusting the stress of each layer, the method can meet the stress requirements of each layer that cannot be achieved by the current deposition condition adjustment method, improve the process stability and window at the same time, and the method can also unify the formation conditions of the film layers and improve the production capacity utilization rate of the furnace tube.

Description

Technical Field

[0001] This application relates to the field of MEMS, and more particularly to a MEMS device, a method for manufacturing the same, and an electronic device. Background Art

[0002] The MEMS (Micro-Electro-Mechanical System) process has specific requirements for the stress of each film layer due to the mechanical properties of the micro-mechanical structure. For MEMS structures that require multiple film layers with different stresses for each layer, in order to meet the stress requirements of each film layer, different stress film layers are generally deposited to meet the requirements. However, due to the growth characteristics of the stress film layer, the process window for producing film layers that simultaneously meet stress, surface roughness, and stability is relatively small, and it may not be possible to balance the stress requirements and process stability of the process in some demanding conditions.

[0003] Therefore, it is necessary to improve the current manufacturing method to solve the above problems. Summary of the Invention

[0004] In view of the problems existing in the prior art, this application provides a method for manufacturing a MEMS device, the manufacturing method including:

[0005] Providing a semiconductor substrate, and forming a vibrating membrane on the semiconductor substrate;

[0006] Performing a first annealing step;

[0007] Forming a sacrificial material layer on the vibrating membrane to cover the vibrating membrane;

[0008] Forming a backplane on the sacrificial material layer;

[0009] Performing a second annealing step;

[0010] Removing the sacrificial material layer between the vibrating membrane and the backplane to form a cavity.

[0011] Optionally, the vibrating membrane and the backplane are made of the same material; and / or

[0012] The vibrating membrane and the backplane are formed by the same process.

[0013] Optionally, the temperature of the second annealing step is lower than the temperature of the first annealing step.

[0014] Optionally, the growth temperature of the vibrating membrane and the backplane is 540°C to 560°C, and the pressure is 200 mtor to 300 mtor.

[0015] Optionally, the temperature of the first annealing step is 1015°C - 1030°C, and the time is 95 min - 115 min;

[0016] The temperature of the second annealing step is 970°C - 980°C, and the time is 95 min - 115 min.

[0017] Optionally, the growth temperature of the diaphragm is 540°C - 560°C, and the pressure is 200 mtor - 300 mtor; and / or

[0018] The growth temperature of the backplane is 540°C - 560°C, and the pressure is 200 mtor - 300 mtor.

[0019] Optionally, the preparation method further includes:

[0020] Patterning the semiconductor substrate to form a back cavity exposing the diaphragm.

[0021] Optionally, before forming the diaphragm on the semiconductor substrate, the preparation method further includes a step of forming an insulating layer on the semiconductor substrate.

[0022] This application also provides a MEMS device prepared by the preparation method described above.

[0023] This application also provides an electronic device including the MEMS device described above.

[0024] To solve the existing technical problems, this application provides a MEMS device and its preparation method. The method combines multiple annealing steps with separately adjusting the stress of each layer to meet the stress requirements of each layer that cannot be achieved by the current deposition condition adjustment method, while improving the process stability and window. The method can also unify the formation conditions of the film layers and improve the productivity utilization rate of the furnace tube. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The following drawings of this application are used as part of this application to understand this application. The drawings show the embodiments of this application and their descriptions, and are used to explain the device and principle of this application. In the drawings,

[0026] Figures 1A - 1D is a schematic cross-sectional structure diagram of each device structure during the preparation of the MEMS device described in an embodiment of this application;

[0027] Figure 2 is a schematic flow diagram of the preparation method of the MEMS device described in an embodiment of this application. DETAILED DESCRIPTION

[0028] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present application. However, it will be apparent to one of ordinary skill in the art that the present application may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present application.

[0029] It should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity. Like reference numerals throughout the figures indicate like elements.

[0030] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or section from another element, component, region, layer, or section. Thus, a first element, component, region, layer, or section discussed below could be termed a second element, component, region, layer, or section without departing from the teachings of the present application.

[0031] Spatial relationship terms such as "below," "beneath," "lower," "under," "above," "upper," etc. are used herein for convenience in describing the relationship of one element or feature to another element or feature shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, then an element or feature described as "below" or "beneath" or "under" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0032] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present application. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0033] To thoroughly understand the present application, detailed structures will be presented in the following description to illustrate the technical solutions proposed by the present application. The preferred embodiments of the present application are described in detail below. However, in addition to these detailed descriptions, the present application may have other embodiments.

[0034] In the current MEMS (Micro-Electro-Mechanical System) process, the MEMS microphone process requires two layers of polysilicon (poly) to be used as the diaphragm and the backplane respectively. Since the two layers of polysilicon (poly) serve as different functional regions of the device, they have different stress requirements. As the diaphragm needs to collect air vibrations, it requires less stress, while the backplane, as the other end of the two poles of the microphone, requires higher stress and certain support.

[0035] The current process sequence for manufacturing the MEMS microphone is as follows: (1) grow the first layer of polysilicon (poly) on a substrate with oxide as the diaphragm; (2) grow plasma-enhanced oxide (PEOXIDE) on the first layer of polysilicon (poly) as the sacrificial layer; (3) grow the second layer of polysilicon (poly) on the sacrificial layer as the backplane; (4) adjust the stress of the backplane and the diaphragm through annealing; (5) remove the sacrificial layer and the back to form a cavity.

[0036] The current different stress requirements are achieved by changing the polysilicon (poly) deposition conditions. The stress of the two layers of polysilicon (poly) is adjusted to the target value through a single annealing step. Adjusting the stress of any one layer of polysilicon will affect the stress of the other layer of polysilicon (poly), thus requiring adjustment of the polysilicon (poly) deposition conditions.

[0037] Another drawback of the above adjustment method is that the adjustment of the polysilicon (poly) deposition conditions is limited by the polysilicon (poly) process itself. The stress of high-temperature polysilicon is compressive stress, which generally does not meet the stress parameter requirements in the microphone process. Reducing the temperature will have a transition zone where polysilicon transforms into amorphous silicon. There are two adverse effects on the process in this process interval. On the one hand, the surface of the polysilicon (poly) deposited in the transition zone will be very rough, with pits on the surface topography, which may affect the subsequent manufacturing process and the device itself. On the other hand, the stress stability of the polysilicon (poly) in the transition zone is poor, which is unacceptable for both the process and product parameters. Therefore, the generally selectable polysilicon (poly) deposition interval is only from the point of entering the amorphous state to the state where the degree of amorphization is relatively saturated. However, as the degree of amorphization approaches saturation, the stress change brought about by the polysilicon (poly) deposition conditions becomes tiny, and thus the purpose of changing the stress magnitude cannot be achieved.

[0038] To solve the existing problems, the present application provides a method for manufacturing a MEMS device, as Figure 2 shown, the manufacturing method includes:

[0039] Step S1: Provide a semiconductor substrate and form a diaphragm on the semiconductor substrate;

[0040] Step S2: Perform a first annealing step;

[0041] Step S3: Form a sacrificial material layer on the diaphragm to cover the diaphragm;

[0042] Step S4: Form a backplane on the sacrificial material layer;

[0043] Step S5: Perform a second annealing step;

[0044] Step S6: Remove the sacrificial material layer between the diaphragm and the backplane to form a cavity.

[0045] By combining multiple annealing steps and separately adjusting the stress of each layer, the method can meet the stress requirements of each layer that cannot be achieved by the current deposition condition adjustment method, while improving the stability and window of the process. The method can also unify the formation conditions of the film layers and improve the production capacity utilization rate of the furnace tube.

[0046] Embodiment 1

[0047] The following will describe in detail the method for manufacturing the MEMS device of the present application with reference to the accompanying drawings. Among them, Figures 1A - 1D is a schematic cross-sectional structure diagram of each device structure in the manufacturing process of the MEMS device according to an embodiment of the present application.

[0048] In the step S1, a semiconductor substrate 101 is provided, and an insulating layer 102 and a diaphragm 103 are formed on the semiconductor substrate 101.

[0049] Specifically, as Figure 1A shown, in this step, the semiconductor substrate 101 may be at least one of the materials mentioned below: silicon, silicon on insulator (SOI), stacked silicon on insulator (SSOI), stacked silicon germanide on insulator (S-SiGeOI), silicon germanide on insulator (SiGeOI), and germanium on insulator (GeOI), etc.

[0050] The insulating layer 102 may be selected as SiN, but is not limited to this material.

[0051] The diaphragm 103 may be selected as polysilicon or SiGe.

[0052] In an embodiment of the present application, the diaphragm 103 is selected as polysilicon.

[0053] The growth temperature is 540°C to 560°C, and the pressure is 200 mtor to 300 mtor.

[0054] In another embodiment of the present application, the growth temperature of the diaphragm 103 is 560°C, and the pressure is 85 mtor.

[0055] Among them, the thickness of the diaphragm can be set according to actual needs and is not limited to a certain one.

[0056] Optionally, in an embodiment of the present application, a groove is further formed on the semiconductor substrate 101 to increase the elasticity of the diaphragm.

[0057] In the step S2, a first annealing step is performed, where the first annealing step is used to adjust the stress of the diaphragm.

[0058] Among them, the temperature of the first annealing step is 1015°C - 1030°C, and the time range is 95 min to 115 min.

[0059] Among them, the annealing step may be a conventional annealing process, is not limited to a certain one, and can be selected according to actual needs.

[0060] In the step S3, a sacrificial material layer 104 is formed on the diaphragm 103 to cover the diaphragm 103, as Figure 1B shown.

[0061] Among them, the sacrificial material layer 104 may be selected as plasma enhanced oxide (PEOX), and its thickness is not limited to a certain numerical range.

[0062] In an embodiment of the present application, a sacrificial material layer 104 is deposited to fill the first opening and cover the diaphragm 103.

[0063] Among them, the sacrificial material layer 104 can be formed by using common deposition methods in the prior art, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD), etc. In the present invention, chemical vapor deposition (CVD) is preferably used.

[0064] In an embodiment of the present application, the method further includes patterning the sacrificial material layer 104 to form an opening in the sacrificial material layer 104 to expose the diaphragm 103, which is then used to form an electrical connection between the diaphragm and the backplane subsequently.

[0065] Among them, the opening is formed in the edge region of the sacrificial material layer 104.

[0066] In step S4, a backplane 105 is formed on the sacrificial material layer 104 to cover the sacrificial material layer 104, as Figure 1C shown.

[0067] In this step, the backplane 105 also fills the opening in the sacrificial material layer 104 and contacts the exposed diaphragm 103 to form an electrical connection.

[0068] Among them, in an embodiment of the present application, the backplane 105 is made of polysilicon.

[0069] In an embodiment of the present application, the growth temperature of the backplane 105 is 540°C to 560°C, and the pressure is 200 mtor to 300 mtor., which is the same as the growth process of the diaphragm 103.

[0070] In the present application, multi-channel annealing is used to adjust the stress of different layers respectively. The growth process conditions of the diaphragm and the backplane can be selected with a temperature of 540°C to 560°C and a pressure of 200 mtor to 300 mtor. By this setting, a flat polysilicon surface, high process stability, and production speed are taken into account. On the other hand, the consistency of the growth process conditions can greatly improve the productivity of the polysilicon furnace tube. At the same time, the process flexibility brought by the multi-channel annealing process will also be greatly improved and can be applied to processes with more layers of polysilicon requirements other than microphones.

[0071] In another embodiment of the present application, the growth temperature of the backplane 105 is 540°C, and the pressure is 500 mtor.

[0072] Among them, the thickness of the backplane 105 can be set according to actual needs and is not limited to a certain type.

[0073] In the step S5, a second annealing step is performed, where the second annealing step is used to adjust the stress of the backplane 105.

[0074] Wherein, the temperature of the second annealing step is 970 °C to 980 °C, and the time range is 95 min to 115 min.

[0075] Wherein, the annealing step can be a conventional annealing process, not limited to a certain one, and can be selected according to actual needs.

[0076] In the step S6, acoustic holes are formed in the backplane 105 to expose the sacrificial layer, and the sacrificial layer is removed by a buffered etching method to form a cavity between the backplane and the diaphragm.

[0077] Wherein, when the sacrificial material layer 104 is selected as an oxide layer, TMAH wet etching can be used to remove the sacrificial material layer.

[0078] The mass fraction of the TMAH solution is 0.1% - 10%, the wet etching temperature is 25 - 90 °C, and the wet etching time is 10 s - 1000 s. However, it is not limited to this example, and other methods commonly used in the art can also be selected.

[0079] The method further includes etching the semiconductor substrate to form a back cavity under the diaphragm and expose the diaphragm.

[0080] The method can further include forming pads on the backplane and / or the diaphragm for electrical connection.

[0081] So far, the introduction of the relevant steps for preparing the MEMS device in the embodiment of the present invention has been completed. After the above steps, other relevant steps may be included, which will not be elaborated here. And, in addition to the above steps, the preparation method of this embodiment may also include other steps among or between the above various steps, and these steps can all be realized by various processes in the prior art, which will not be elaborated here.

[0082] The present application provides a MEMS device and its preparation method. The method combines multiple annealing steps to separately adjust the stress of each layer, achieving the stress requirements of each layer that cannot be achieved by the current deposition condition adjustment method, while improving the process stability and window. The method can also unify the formation conditions of the film layers and improve the productivity utilization rate of the furnace tube.

[0083] Embodiment 2

[0084] The present application also provides a MEMS device prepared by the method as described in Example 1. The method includes: providing a semiconductor substrate and forming a vibrating membrane on the semiconductor substrate;

[0085] Performing a first annealing step to adjust the stress of the vibrating membrane;

[0086] Forming a sacrificial material layer on the vibrating membrane to cover the vibrating membrane;

[0087] Forming a backplane on the sacrificial material layer;

[0088] Performing a second annealing step to adjust the stress of the backplane, wherein the temperature of the second annealing step is lower than that of the first annealing step;

[0089] Removing the sacrificial material layer between the vibrating membrane and the backplane to form a cavity.

[0090] Since the MEMS device is prepared by the above method, the MEMS device has all the advantages of the method.

[0091] Example 3

[0092] The present invention also provides an electronic device including the MEMS device as described in Example 2 or the MEMS device obtained by the preparation method as described in Example 1.

[0093] The electronic device of this embodiment can be any electronic product or device such as a mobile phone, a tablet computer, a laptop computer, a netbook, a game console, a television, a VCD, a DVD, a navigator, a camera, a video camera, a recording pen, an MP3, an MP4, a PSP, etc., or can also be any intermediate product including the MEMS device. The electronic device of the embodiment of the present invention has better performance due to the use of the above MEMS device.

[0094] Although example embodiments have been described herein with reference to the drawings, it should be understood that the above example embodiments are merely exemplary and are not intended to limit the scope of the present application thereto. Those of ordinary skill in the art can make various changes and modifications therein without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed in the appended claims.

[0095] Those of ordinary skill in the art will realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods for each specific application to implement the described functions, but such implementation should not be considered to exceed the scope of this application.

[0096] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division. In actual implementation, there may be other division methods. For example, multiple units or components can be combined or integrated into another device, or some features can be ignored or not executed.

[0097] In the specification provided here, a large number of specific details are described. However, it can be understood that the embodiments of this application can be practiced without these specific details. In some instances, well-known methods, structures, and technologies are not shown in detail so as not to obscure the understanding of this specification.

[0098] Similarly, it should be understood that, in order to streamline this application and help understand one or more of the various inventive aspects, in the description of the exemplary embodiments of this application, the various features of this application are sometimes grouped together into a single embodiment, figure, or description thereof. However, the method of this application should not be construed as reflecting the intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected by the corresponding claims, the inventive point lies in being able to solve the corresponding technical problems with fewer features than all the features of a single disclosed embodiment. Therefore, the claims following the specific implementation manner are hereby expressly incorporated into the specific implementation manner, where each claim itself serves as a separate embodiment of this application.

[0099] Those skilled in the art can understand that, except for features that are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0100] In addition, those skilled in the art will appreciate that although some of the embodiments described herein include certain features included in other embodiments rather than other features, the combination of features of different embodiments is meant to be within the scope of this application and forms different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0101] It should be noted that the above embodiments are illustrative of the application and not restrictive of the application, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The application can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In the unit claims enumerating several devices, several of these devices can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names.

Claims

1. A method for preparing a MEMS device, characterized in that, The preparation method includes: providing a semiconductor substrate and forming a diaphragm on the semiconductor substrate; performing a first annealing step; forming a sacrificial material layer on the diaphragm to cover the diaphragm; forming a backplane on the sacrificial material layer; performing a second annealing step; removing the sacrificial material layer between the diaphragm and the backplane to form a cavity; wherein, the temperature of the second annealing step is lower than that of the first annealing step; the forming processes of the diaphragm and the backplane are the same; the growth temperature of the diaphragm is 540°C to 560°C, and the pressure is 200 mtor to 300 mtor; and the growth temperature of the backplane is 540°C to 560°C, and the pressure is 200 mtor to 300 mtor.

2. The preparation method according to claim 1, wherein, The diaphragm and the backplane are made of the same material.

3. The preparation method according to claim 1, wherein The temperature of the first annealing step is 1015°C - 1030°C, and the time is 95 min to 115 min; The temperature of the second annealing step is 970°C - 980°C, and the time is 95 min to 115 min.

4. The preparation method according to claim 1, characterized in that, The preparation method further includes: patterning the semiconductor substrate to form a back cavity exposing the diaphragm.

5. The preparation method according to claim 1, characterized in that, Before forming the diaphragm on the semiconductor substrate, the preparation method further includes a step of forming an insulating layer on the semiconductor substrate.

6. A MEMS device, characterized in that, The MEMS device is prepared by the preparation method according to any one of claims 1 to 5.

7. An electronic device, characterized in that, including the MEMS device according to claim 6.

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