Zero-crossing detection circuit

Abstract

A zero-crossing detection circuit comprises a zero-crossing detection unit for comparing first and second monitoring target signals input from first and second nodes, between which an AC signal is applied, through diodes, respectively, thereby generating a first comparison signal, and a logic unit for estimating a zero-crossing of the AC signal from the first comparison signal, thereby generating a zero-crossing detection signal. The zero-crossing detection circuit preferably comprises a monitoring unit for adjusting the first and second monitoring target signals to be suitable for input to the zero-crossing detection unit. The logic unit preferably counts cycles of the first comparison signal and uses the count value thereof to estimate the zero-crossing of the AC signal.

Description

[0001] This application is a divisional application of the invention application filed on July 25, 2018, with application number 2018800496802 and entitled "Zero-crossing detection circuit". Technical Field

[0002] The invention disclosed in this specification relates to zero-crossing detection circuits. Background Technology

[0003] Figure 57 This is a diagram illustrating a conventional example of a zero-crossing detection circuit. The zero-crossing detection circuit DET in this conventional example is used to detect the zero-crossing (i.e., the point where the AC voltage Vac crosses the ground potential) of the AC voltage Vac applied between the live (L) terminal and the neutral (N) terminal, and is installed in a household appliance as a substantially discrete component (in the example shown in the diagram, a total of eleven components, including an optocoupler PC, a PNP bipolar transistor Qa, resistors Ra to Rd, diodes Da and Db, a Zener diode ZD, and a capacitor Ca).

[0004] Note that there is a patent document 1 that serves as an example of conventional technology related to the above description.

[0005] Existing technical documents

[0006] Patent documents

[0007] Patent Document 1: JP 2017-99178 Summary of the Invention

[0008] The problem that the invention aims to solve

[0009] Currently, the conventional zero-crossing detection circuit DET has the following problems: (1) the optocoupler PC has high power consumption; (2) there are many discrete components; (3) the detection accuracy is low due to the temperature characteristics of the optocoupler PC or other factors; and (4) the high-voltage components have low reliability (in applications such as washing machines, electro-corrosion of the resistor Ra is prone to occur). However, the conventional zero-crossing detection circuit DET has many years of operating experience and is difficult to redesign. Therefore, it continues to be used as before.

[0010] In view of the above-mentioned problems discovered by the inventors, the object of the present invention disclosed in this specification is to provide a zero-crossing detection circuit that can detect the zero crossing of an AC signal without using an optocoupler.

[0011] The means adopted to solve the problem

[0012] The zero-crossing detection circuit disclosed in this specification includes: a peak detection unit for detecting the peak value of a monitoring target signal input from an AC signal input terminal via a diode, thereby generating a peak detection signal; and a zero-crossing detection unit for estimating the zero-crossing of the AC signal based on the peak detection signal, thereby generating a zero-crossing detection signal.

[0013] Furthermore, the zero-crossing detection circuit disclosed in this specification includes: a zero-crossing detection unit for comparing a first monitoring target signal and a second monitoring target signal input from a first node and a second node through which an AC signal is applied respectively via a diode, thereby generating a first comparison signal; and a logic unit for estimating the zero-crossing of the AC signal based on the first comparison signal, thereby generating a zero-crossing detection signal.

[0014] Furthermore, the zero-crossing detection circuit disclosed in this specification includes: a logic unit configured to estimate the zero-crossing of the AC signal based on at least one of a first monitoring target signal and a second monitoring target signal input from a first node and a second node through a diode, respectively, thereby generating a zero-crossing detection signal; and an input stop detection unit configured to compare the first monitoring target signal and the second monitoring target signal after giving an offset to one of them to generate an input stop detection signal, wherein the logic unit fixes the logic level of the zero-crossing detection signal based on the input stop detection signal.

[0015] Note that other features, elements, steps, advantages, and characteristics will become clear from the following detailed description of the embodiments and the accompanying drawings.

[0016] The effects of the invention

[0017] According to the invention disclosed in this specification, a zero-crossing detection circuit can be provided that can detect the zero crossing of an AC signal without using an optocoupler. Attached Figure Description

[0018] Figure 1 This is a diagram illustrating a first structural example of an electronic device (normal rectification).

[0019] Figure 2 This is a diagram illustrating a second structural example of an electronic device (voltage doubler rectifier).

[0020] Figure 3 It is a graph showing the relationship between the rectification method and the voltage at each part.

[0021] Figure 4 This is a diagram illustrating a first embodiment of a semiconductor integrated circuit device.

[0022] Figure 5 This is a diagram showing a structural example of an AC monitoring unit.

[0023] Figure 6 This is a diagram showing a structural example of a peak detection unit.

[0024] Figure 7 This is a diagram showing a structural example of the first output unit.

[0025] Figure 8 This is a timing diagram illustrating an example of a zero-crossing detection process.

[0026] Figure 9 This is a timing diagram illustrating an example of the noise removal process.

[0027] Figure 10 This is a diagram illustrating a second embodiment of a semiconductor integrated circuit device.

[0028] Figure 11 This is a timing diagram illustrating an example of the AC waveform determination process.

[0029] Figure 12 This is a diagram illustrating a normal, well-defined example of an AC monitoring signal.

[0030] Figure 13 This is a diagram illustrating a third embodiment of a semiconductor integrated circuit device.

[0031] Figure 14 This is a diagram illustrating a fourth embodiment of a semiconductor integrated circuit device.

[0032] Figure 15 This is an external view showing the package of a semiconductor integrated circuit device.

[0033] Figure 16 This is a diagram showing the first example of a package layout.

[0034] Figure 17 This is a diagram showing the internal structure of the first chip and the second chip.

[0035] Figure 18 This is a schematic diagram showing the α-α' cross-section.

[0036] Figure 19 This is a diagram showing a second example of the encapsulation layout.

[0037] Figure 20 This is a diagram illustrating an example of the third structure of an electronic device (normal rectification).

[0038] Figure 21 This is a diagram illustrating an example of the fourth structure of an electronic device (voltage doubler rectifier).

[0039] Figure 22 This is a diagram illustrating a fifth embodiment of a semiconductor integrated circuit device.

[0040] Figure 23 This is a diagram showing a first example of a zero-crossing detection unit.

[0041] Figure 24 This is a timing diagram illustrating a first example of the zero-crossing detection process.

[0042] Figure 25 This is a timing diagram illustrating a second example of the zero-crossing detection process.

[0043] Figure 26 This is a timing diagram illustrating a third example of the zero-crossing detection process.

[0044] Figure 27 This is a diagram showing a second example of a zero-crossing detection unit.

[0045] Figure 28 This is a timing diagram illustrating the fourth example of the zero-crossing detection process.

[0046] Figure 29 This is a timing diagram illustrating the fifth example of the zero-crossing detection process.

[0047] Figure 30 This is a timing diagram illustrating the sixth example of the zero-crossing detection process.

[0048] Figure 31 This is a diagram illustrating a fifth structural example of an electronic device (normal rectification, single-sided relay).

[0049] Figure 32 This is a diagram illustrating a sixth embodiment of a semiconductor integrated circuit device.

[0050] Figure 33 This is a timing diagram illustrating an example of the output pulse stopping process.

[0051] Figure 34 This is a diagram showing a third example of the encapsulation layout.

[0052] Figure 35 This is a diagram showing the internal structure of the first chip and the second chip.

[0053] Figure 36 This is a diagram showing the fourth example of the encapsulation layout.

[0054] Figure 37 This is a diagram showing the internal structure of the first chip and the second chip.

[0055] Figure 38 This is a diagram showing a structural example of an AC monitoring unit and a DC monitoring unit.

[0056] Figure 39 This is a diagram showing the layout of the first chip.

[0057] Figure 40 This is a longitudinal cross-sectional view showing a structural example of a high-voltage region.

[0058] Figure 41 This is an enlarged top view showing a structural example of a high-voltage region.

[0059] Figure 42 This is a diagram showing the layout of the second chip.

[0060] Figure 43 This is a diagram showing the fifth example of a package layout.

[0061] Figure 44 This is a diagram showing the sixth example of a package layout.

[0062] Figure 45 This is a plan view showing the pin assignment (seven pins) of a semiconductor integrated circuit device.

[0063] Figure 46 This is a plan view showing the pin assignment (eleven pins) of a semiconductor integrated circuit device.

[0064] Figure 47 This is a diagram illustrating the operation of generating a comparison signal (without input offset and without signal distortion).

[0065] Figure 48 This is a diagram illustrating the operation of generating a comparison signal (without input offset and with signal distortion).

[0066] Figure 49 This is a diagram illustrating the operation of generating a comparison signal (with input offset and signal distortion).

[0067] Figure 50 This is a diagram illustrating a seventh embodiment of a semiconductor integrated circuit device.

[0068] Figure 51 This is a diagram illustrating the process of suppressing changes with zero delay time.

[0069] Figure 52 This is a diagram illustrating the eighth embodiment of a semiconductor integrated circuit device.

[0070] Figure 53 This is a diagram illustrating an example of an arbitrarily set target zero-crossing delay time.

[0071] Figure 54 This is a diagram showing the first output waveform of the ACOUT signal.

[0072] Figure 55 This is a diagram showing the second output waveform of the ACOUT signal.

[0073] Figure 56 This is a diagram illustrating a ninth embodiment of a semiconductor integrated circuit device.

[0074] Figure 57 This is a diagram illustrating a conventional example of a zero-crossing detection circuit. Detailed Implementation

[0075] <Electronic Devices (First Structure Example and Second Structure Example)>

[0076] Figure 1 and Figure 2 These are diagrams illustrating a first structural example (normal rectification method) and a second structural example (voltage doubler rectification method) of an electronic device operating when an AC voltage V0 is provided. Each structural example of the electronic device 10 includes a filter 11, a rectifier unit 12, an AC / DC converter 13, a DC / DC converter 14, a microcomputer 15, a driver 16, a motor 17, and a zero-crossing detection circuit 18.

[0077] Filter 11 removes noise and surges from the AC voltage V0 (e.g., AC 80V to 264V) input between the live (L) terminal and the neutral (N) terminal to output a result between the L1 terminal and the N1 terminal. Note that a protective element such as a fuse can be provided in the stage preceding filter 11.

[0078] The rectifier unit 12 performs normal rectification or voltage doubler rectification on the AC voltage V0 filtered by the filter 11 to generate a rectified voltage V1 (e.g., DC 100V to 450V), and provides the rectified voltage V1 to the circuit blocks of the AC / DC converter 13, the motor 17, and the zero-crossing detection circuit 18. The rectifier unit 12 includes diodes 12a to 12d, capacitor 12e (normal rectification method) or capacitors 12f and 12g (voltage doubler rectification method).

[0079] Note the normal rectification method ( Figure 1 This is the mainstream rectification method used in international commercial AC power supplies, typically for 200V systems. In comparison, the voltage doubler rectification method (…) Figure 2 This is the rectification method used in mainstream commercial AC power supplies in Japan for 100V systems.

[0080] The cathode of diode 12a and the anode of diode 12c are both connected to terminal L1. The cathode of diode 12b and the anode of diode 12d are both connected to terminal N1. The cathodes of diodes 12c and 12d are connected to each other, and their connection node corresponds to the output terminal of the rectified voltage V1. The anodes of diodes 12a and 12b are connected to each other, and their connection node is connected to the ground terminal GND shared by the microcomputer 15 and the zero-crossing detection circuit 18. Thus, diodes 12a to 12d are connected to each other to form a diode bridge, which performs full-wave rectification of the AC voltage V0 after the filtering process to generate the rectified voltage V1.

[0081] Furthermore, if the rectifier unit 12 uses the normal rectification method, then a single capacitor 12e is connected between the output terminal of the rectified voltage V1 and the ground terminal GND, such as... Figure 1 As shown. In contrast, if the rectifier unit 12 adopts a voltage doubler rectification method, then capacitors 12f and 12g are connected in series between the output terminal of the rectified voltage V1 and the ground terminal GND, as shown. Figure 2 As shown. Note that the connection point of capacitors 12f and 12g is connected to terminal L1.

[0082] AC / DC converter 13 generates a desired first DC voltage V3 (e.g., DC 13.0V to 18.0V) based on the rectified voltage V1 obtained by rectifying the AC voltage V0, and outputs the first DC voltage V3 to DC / DC converter 14, driver 16 and zero-crossing detection circuit 18.

[0083] DC / DC converter 14 generates a desired second DC voltage V4 (e.g., DC 5.0V) based on the first DC voltage V3, and outputs the second DC voltage V4 to microcomputer 15, etc.

[0084] The microcomputer 15 operates when the second DC voltage V4 is provided, and generates a motor control signal S3 based on the detection results of the zero-crossing detection circuit 18 (i.e., ACOUT signal S1 and DCOUT signal S2) to control the drive of the motor 17.

[0085] The driver 16 operates when the first DC voltage V3 is provided and generates the motor drive signal S4 according to the motor control signal S3.

[0086] The motor 17 operates when a rectified voltage V1 is provided, and it is a type of load that is driven to rotate according to the motor drive signal S4.

[0087] The zero-crossing detection circuit 18 is a circuit block that detects the zero-crossing of AC voltage V0 (i.e., the intersection of AC voltage V0 and ground potential), and includes a semiconductor integrated circuit device 100, as well as a diode D1 and a capacitor C1 externally attached to the semiconductor integrated circuit device 100.

[0088] The semiconductor integrated circuit device 100 is an IC or LSI that integrates at least a portion of the circuit elements constituting the zero-crossing detection circuit 18 (details of which will be described later), and has seven external terminals (pins 1 to 7) as means for establishing connections to the outside of the device.

[0089] Pin 1 (ACOUT pin) is the output terminal of the ACOUT signal S1 and is connected to the microcomputer 15. Pin 2 (DCOUT pin) is the output terminal of the DCOUT signal S2 and is connected to the microcomputer 15. Pin 3 (GND pin) is the ground terminal and is connected to the ground terminal GND shared with the microcomputer 15. In other words, the semiconductor integrated circuit device 100 (and therefore the zero-crossing detection circuit 18 of the semiconductor integrated circuit device 100) operates relative to the ground voltage shared with the microcomputer 15. Pin 4 (VCC pin) is the power supply terminal and is connected to the output terminal of the AC / DC converter 13 (i.e., the output terminal of the first DC voltage V3). Note that capacitor C1 is connected between pin 4 and pin 3.

[0090] Pin 5 (VHDC pin) is the DC input terminal and is connected to the output terminal of rectifier unit 12 (i.e., the input terminal of rectified voltage V1). Pin 6 (NC pin) is an unused terminal and is not connected anywhere outside the semiconductor integrated circuit device 100. Pin 7 (VHAC pin) is the AC input terminal and is connected to the cathode of diode D1 (corresponding to the input terminal for monitoring target voltage V2). Note that the anode of diode D1 is connected to terminal N1 (or terminal L1).

[0091] In this way, compared with the traditional example mentioned above ( Figure 38 Unlike other circuits, the zero-crossing detection circuit 18 in this example structure utilizes only three mounted components (semiconductor integrated circuit device 100, diode D1, and capacitor C1) to detect the zero crossing of the AC voltage V0. Therefore, effects such as reduced standby power consumption (1W to tens of mW), reduced printed circuit board area (hundreds of square millimeters to tens of square millimeters), or improved accuracy of load drive control can be achieved, thus providing electronic devices 10 that adapt to market trends or customer needs.

[0092] However, in order to realize the zero-crossing detection circuit 18 of this structural example, the following technical problems need to be solved: (1) an optocoupler cannot be used; (2) the zero crossing changes when monitoring is performed outside of the L terminal and the N terminal; and (3) the zero-crossing detection point is different between the normal rectification method and the voltage doubler rectification method.

[0093] In particular, the above-mentioned technical issues (2) and (3) are described in detail with reference to the accompanying drawings. Figure 3 It is a graph showing the relationship between the rectification method and the voltage at each part, where the waveforms of AC voltage V0, rectified voltage V1 and monitoring target voltage V2 are shown from top to bottom.

[0094] For example, if the AC voltage V0 has a sinusoidal waveform varying between +1.41AC and -1.41AC, and if the rectifier unit 12 uses a normal rectification method ( Figure 1 As shown on the left side of the figure, the rectified voltage V1 has a DC waveform with ripple around +1.41 AC, while the monitored target voltage V2 has a half-wave rectified waveform varying between +1.41 AC and 0 V. In contrast, if the rectifier unit 12 uses a voltage doubler rectification method (…), Figure 2 As shown on the right side of the figure, the rectified voltage V1 has a DC waveform with ripple close to +1.41AC×2, and the monitored target voltage V2 has a sinusoidal waveform that varies between +1.41AC×2 and 0V.

[0095] In this way, the target voltage V2 has a waveform different from that of the AC voltage V0, and distortion may occur in the waveform depending on the load condition. In other words, it can be assumed that the zero-crossing of the target voltage V2 changes from the zero-crossing of the AC voltage V0. Therefore, in a structure used to detect the zero-crossing of the target voltage V2, the zero-crossing of the AC voltage V0 may not be detected correctly.

[0096] Furthermore, when attempting to detect the zero-crossing of the target voltage V2, the detection point is the 0V crossing point in the normal rectification method and the +1.41AC crossing point in the voltage doubler rectification method. Therefore, in the structure used to detect the zero-crossing of the target voltage V2, the detection point needs to be changed according to the rectification method, and it is difficult to support both rectification methods.

[0097] In the following description, embodiments of the semiconductor integrated circuit device 100 are illustrated, and it is described that all technical problems (1) to (3) have been solved.

[0098] <Semiconductor Integrated Circuit Device (First Embodiment)>

[0099] Figure 4This is a diagram showing a first embodiment of the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 of this embodiment includes an integrated AC monitoring unit 110, a peak detection unit 120, a zero-crossing detection unit 130, a first output unit 140, a DC monitoring unit 150, a second output unit 160, and an undervoltage protection unit 170.

[0100] The AC monitoring unit 110 is a high-voltage circuit unit (for example, having a withstand voltage of 650V), which generates an AC monitoring signal Sa adapted to be input to the peak detection unit 120 based on the monitoring target voltage V2 input to pin 7 (VHAC pin) (corresponding to the monitoring target signal input from the N1 terminal to which the AC voltage V0 is applied through the diode D1).

[0101] The peak detection unit 120 detects the peak value of the AC monitoring signal Sa (and thus the monitoring target voltage V2) to generate a peak detection signal Sb.

[0102] The zero-crossing detection unit 130 is a logic circuit, which estimates the zero-crossing of the AC voltage V0 based on the peak detection signal Sb to generate a zero-crossing detection signal Sc.

[0103] The first output unit 140 receives the input of the zero-crossing detection signal Sc to generate an ACOUT signal S1, and outputs the ACOUT signal S1 to pin 1 (ACOUT pin).

[0104] The DC monitoring unit 150 is a high-voltage circuit block (for example, having a withstand voltage of 650V), which generates a DC monitoring signal Sx based on the rectified voltage V1 input to pin 5 (VHDC pin).

[0105] The second output unit 160 receives the input of the DC monitoring signal Sx to generate a DCOUT signal S2, and outputs the DCOUT signal S2 to pin 2 (DCOUT pin).

[0106] Note that in the case of directly outputting the DC monitoring signal Sx as the DCOUT signal S2, the second output unit 16 can be eliminated. In addition, if the DC monitoring function itself is not necessary, all of the DC monitoring unit 150, the second output unit 160, pin 2 (DCOUT pin), and pin 5 (VHDC pin) can be eliminated. [[ID=ID=22]]

[0107] The undervoltage protection unit 170 is a protection function unit (a so-called undervoltage lockout (UVLO) protection unit), which disables the operation of the semiconductor integrated circuit device 100 when the first DC voltage V3 input to pin 4 (VCC) is lower than the lower limit value.

[0108] <AC monitoring unit>

[0109] Figure 5 This is a diagram illustrating a structural example of an AC monitoring unit 110. The AC monitoring unit 110 of this structural example includes resistors 111 to 115, an N-channel metal-oxide-semiconductor field-effect transistor (NMOSFET) 116, a P-channel MOSFET (PMOSFET) 117, and a diode 118.

[0110] Resistors 111 to 115 are connected in series between pin 7 (VHAC pin) and pin 3 (GND pin) in the order shown in the diagram. Note that the connection point of resistors 113 and 114 corresponds to the output terminal of the AC monitoring signal Sa. That is, resistors 111 to 115 function as a voltage divider circuit to generate the AC monitoring signal Sa by dividing the target monitoring voltage V2 input to pin 7. For example, assuming the combined resistance of resistors 111 to 113 is Rx (e.g., 10MΩ) and the combined resistance of resistors 114 and 115 is Ry (e.g., 0.1MΩ), then Sa = (Ry / (Rx+Ry)) × V2 (≈0.01 × V2) holds true.

[0111] Furthermore, in the example shown in the figure, each of resistors 112 and 115 out of resistors 111 to 115 can be adjusted by fine-tuning, etc. Therefore, the aforementioned voltage division ratio Ry / (Rx+Ry) can be arbitrarily set.

[0112] Note that polysilicon resistors with a withstand voltage of 100V or higher (e.g., 650V) are preferably used as resistors 111 to 115. Specifically, when integrating resistors 111 to 115, a high-voltage structure is required not only along the path through resistors 111 to 115 (in the lateral direction) but also between the semiconductor substrate and resistors 111 to 115 (in the vertical direction). Therefore, in the semiconductor substrate where the AC monitoring unit 110 is integrated, it is preferable to form a high-voltage region having a higher withstand voltage than other regions in the substrate thickness direction (in the vertical direction), and to form resistors 111 to 115 in this high-voltage region. As this high-voltage region, a laterally double-diffused MOSFET (LDMOSFET) region with abundant high withstand voltage can be used.

[0113] The drain of NMOSFET 116 is connected to pin 7. The source, gate, and back gate of NMOSFET 116 are all connected to pin 3. The drain of PMOSFET 117 is connected to pin 3. The source, gate, and back gate of PMOSFET 117 are all connected to the output terminal of the AC monitoring signal Sa. The cathode of diode 118 is connected to the back gate of PMOSFET 117. The drain of PMOSFET 117 and the anode of diode 118 are both connected to pin 3. Each of the NMOSFET 116, PMOSFET 117, and diode 118 connected in this manner serves as an electrostatic discharge (ESD) protection element.

[0114] Note that the AC monitoring unit 110 is not limited to this example structure using a voltage divider circuit, but can have, for example, a structure in which the target voltage V2 is sampled at a predetermined sampling rate and the sampled value is output as an AC monitoring signal Sa to the peak detection unit 120.

[0115] Furthermore, the DC monitoring unit 150 should have a structure substantially the same as that of the AC monitoring unit 110. In other words, in the above description, "pin 7 (VHAC pin)" can be replaced by "pin 5 (VHDC pin)" and "AC monitoring signal Sa" can be replaced by "DC monitoring signal Sx", thereby understanding the structure and operation of the DC monitoring unit 150.

[0116] Peak Detection Unit

[0117] Figure 6 This is a diagram illustrating a structural example of a peak detection unit 120. As shown in the diagram, the peak detection unit 120 of this structural example includes resistors 121 and 122, capacitors 123 and 124, and a comparator 125.

[0118] The first terminal of resistor 121 is connected to the input terminal of the AC monitoring signal Sa. The second terminal of resistor 121 is connected to the first terminal of resistor 122, the first terminal of capacitor 123, and the non-inverting input terminal (+) of comparator 125. The second terminal of resistor 122 is connected to the first terminal of capacitor 124 and the inverting input terminal (-) of comparator 125. The second terminals of capacitors 123 and 124 are both connected to pin 3 (GND pin). The output terminal of comparator 125 corresponds to the output terminal of the peak detection signal Sb.

[0119] Note that resistor 121 (e.g., 2MΩ) and capacitor 123 (e.g., 10pF) are used as RC filters to remove noise components superimposed on the AC monitoring signal Sa in order to generate the first AC monitoring signal Sa1.

[0120] In contrast, resistor 122 (e.g., 4.7 MΩ) and capacitor 124 (e.g., 20 pF) are used as delay units to give a predetermined delay to the first AC monitoring signal Sa1 in order to generate the second AC monitoring signal Sa2.

[0121] Comparator 125 compares the first AC monitoring signal Sa1 (without delay) with the second AC monitoring signal Sa2 (with delay) to generate a peak detection signal Sb. The peak detection signal Sb is high when the first AC monitoring signal Sa1 is higher than the second AC monitoring signal Sa2, and low when the first AC monitoring signal Sa1 is lower than the second AC monitoring signal Sa2. The peak detection signal Sb generated in this way drops to a low level with a slight delay after a peak occurs in the monitored target voltage V2. This will be described in detail later with a specific example.

[0122] Note that the circuit structure shown in this figure is only an example, and any circuit structure can be used as long as it can properly detect the peak value of the target voltage V2 (or AC monitoring signal Sa).

[0123] <First Output Unit>

[0124] Figure 7 This diagram illustrates a structural example of a first output unit 140. This structural example of the first output unit 140 includes inverters 141 and 142, an NMOSFET 143, and a resistor 144. The input terminal of inverter 141 is connected to the input terminal of a zero-crossing detection signal Sc. The output terminal of inverter 141 is connected to the input terminal of inverter 142. The output terminal of inverter 142 is connected to the gate of NMOSFET 143. The first terminal of resistor 144 is connected to a power supply terminal (e.g., DC 5V). The second terminal of resistor 144 and the drain of NMOSFET 143 are both connected to pin 1 (ACOUT pin). The source and back gate of NMOSFET 143 are both connected to pin 3 (GND pin).

[0125] In the first output unit 140 of this structural example, when the zero-crossing detection signal Sc is high, NMOSFET 143 is turned on, so the ACOUT signal S1 output from pin 1 goes low. Conversely, when the zero-crossing detection signal Sc is low, NMOSFET 143 is turned off, so the ACOUT signal S1 goes high.

[0126] In this way, the ACOUT number S1 generated in the first output unit 140 with an open drain is essentially the inverted logic signal of the zero-crossing detection signal Sc.

[0127] <Zero-crossing detection process>

[0128] Figure 8 This is a timing diagram illustrating an example of the zero-crossing detection process of the zero-crossing detection unit 130, where the AC voltage V0, rectified voltage V1, monitored target voltage V2 (or AC monitoring signal Sa), first AC monitoring signal Sa1, second AC monitoring signal Sa2, peak detection signal Sb, and zero-crossing detection signal Sc are shown in descending order. In the following description, the normal rectification method is used in the rectifier unit 12 ( Figure 1 The behavior in the case of ) is illustrated and described in detail.

[0129] The waveform of AC voltage V0 is a sinusoidal waveform that switches between positive and negative polarities at predetermined periods. Note that in the example in this figure, zero crossings from negative to positive occur at time points t1, t5, and t9 of AC voltage V0, while zero crossings from positive to negative occur at time points t3, t7, and t11. Furthermore, in this example, AC voltage V0 has positive peak values ​​at time points t2, t6, and t10, and negative peak values ​​at time points t4, t8, and t12.

[0130] The waveform of the rectified voltage V1 is a DC waveform with ripples near the peak of the full-wave rectified waveform of the AC voltage V0 (refer to the thin dashed line).

[0131] If rectifier unit 12 uses the normal rectification method ( Figure 1 If the AC voltage V0 is positive, then the waveform of the target voltage V2 (or the AC monitoring signal Sa) is basically the half-wave rectified waveform of the AC voltage V0. In other words, if the AC voltage V0 has a positive value, then the target voltage V2 also has a positive value, and even if the AC voltage V0 has a negative value, the target voltage V2 will not be lower than 0V.

[0132] Note that, as shown by the overlapping thin dashed line (ideal) and thick solid line (reality), the waveform of the monitored target voltage V2 may have distortions depending on load conditions, etc. Therefore, even if the zero-crossing of the monitored target voltage V2 is detected, it is difficult to accurately detect the zero-crossing of the AC voltage V0.

[0133] In contrast, after careful study, the inventors discovered that the peak timing of the monitored target voltage V2 is essentially the same as the peak timing of the AC voltage V0, regardless of load conditions, etc. In other words, the AC voltage V0 and the monitored target voltage V2 only have the same phase at each peak timing. Based on this understanding, the inventors created a novel arithmetic algorithm that can estimate the zero-crossing of the AC voltage V0 based on the peak timing of the monitored target voltage V2. In the following description, while continuing... Figure 8 Along with the description, the above arithmetic algorithm is described in detail.

[0134] The first AC monitoring signal Sa1 (thick solid line) and its delayed signal, i.e., the second AC monitoring signal Sa2 (thick dashed line), cross each other at a time point (e.g., time point tx) that is after a predetermined delay time Δ from the peak timing (e.g., time point t2) of the monitored target voltage V2. Specific descriptions are given below with reference to this figure. Before and after the time point tx, the high / low relationship between the first AC monitoring signal Sa1 and the second AC monitoring signal Sa2 switches from Sa1>Sa2 to Sa1<Sa2. As a result, the peak detection signal Sb drops from a high level to a low level at the time point tx.

[0135] In other words, it can be said that the falling edge of the peak detection signal Sb indicates the peak timing of the monitored target voltage V2 (and thus indicates the positive peak timing of the AC voltage V0). Therefore, the zero-crossing detection unit 130 sequentially detects the falling edges of the peak detection signal Sb to count the period T of the peak detection signal Sb (e.g., from the time point tx to the time point ty in this figure), and uses the count value to estimate the zero-crossing of the AC voltage V0.

[0136] More specifically, on the premise that the AC voltage V0 has a constant period and a constant phase, the zero-crossing detection unit 130 refers to the period T of the peak detection signal Sb to determine the rising timing and the falling timing of the zero-crossing detection signal Sc.

[0137] For example, the zero-crossing detection unit 130 starts counting a standby time T1 (e.g., T1=(1 / 4)×T - Δ) corresponding to the pre-obtained period T from the time point (e.g., time point ty) when the peak detection signal Sb drops to a low level, and raises the zero-crossing detection signal Sc from a low level to a high level at the time point when the standby time T1 has passed. The rising timing of the zero-crossing detection signal Sc is substantially the same as the timing when the AC voltage V0 switches from positive to negative (i.e., the zero-crossing switches from positive to negative).

[0138] In addition, the zero-crossing detection unit 130 reduces the zero-crossing detection signal Sc from a high level to a low level at a time point that is after a standby time T2 (e.g., T2=(3 / 4)×T - Δ) longer than the standby time T1 from the time point (e.g., time point ty) when the peak detection signal Sb drops to a low level. The falling timing of the zero-crossing detection signal Sc is substantially the same as the timing when the AC voltage V0 switches from negative to positive (i.e., the zero-crossing switches from negative to positive).

[0139] Note that the count value used to determine the time intervals T1 and T2 can be the count value from one period ago, or the average count value from several periods. Furthermore, the delay time Δ (i.e., the offset between the true peak timing and pulse edge timing of the peak detection signal Sb) used to determine T1 and T2 is known based on the circuit characteristics of the delay units (resistor 122 and capacitor 124). However, the delay time Δ can be ignored, and the rise and fall timings of the zero-crossing detection signal Sc can be determined without correction.

[0140] Furthermore, in this figure, as described above, the normal rectification method ( Figure 1 The zero-crossing detection process was illustrated in the voltage doubler rectification method () Figure 2 The same applies to the zero-crossing detection process in [the context of ], except for the different waveform of the monitored target voltage V2 (or AC monitoring signal Sa), the same zero-crossing detection process can be performed as described above. In other words, the novel arithmetic algorithm described above can support normal rectification methods ( Figure 1 ) and voltage multiplier rectification method ( Figure 2 )both sides.

[0141] However, the zero-crossing detection process in this figure is merely an example, and any arithmetic algorithm can be used as long as the pulse edges of the zero-crossing detection signal Sc can be appropriately generated based on the peak detection signal Sb.

[0142] <Noise Removal Process>

[0143] Next, in practical applications, a method for removing noise that is assumed to be superimposed on the peak detection signal Sb will be described in detail with reference to the accompanying drawings. Figure 9 This is a timing diagram illustrating an example of the noise removal process of the zero-crossing detection unit 130, where the AC monitoring signal Sa, the peak detection signal Sb, and the zero-crossing detection signal Sc are shown in order from top to bottom. Note that the delay time Δ is omitted in the following description for ease of explanation.

[0144] In the example shown in the figure, the AC monitoring signal Sa has peaks at times t22 and t25, and subsequently, the peak detection signal Sb drops from a high level to a low level. Therefore, the rise and fall timings of the zero-crossing detection signal Sc are determined for the falling edge of the peak detection signal Sb, thus allowing for a correct estimation of the zero-crossing of the AC voltage V0. This has already been described above.

[0145] However, in electronic device 10, undesirable noise (noise N1 to N3 in this figure) is superimposed on the AC monitoring signal Sa due to the back electromotive force of motor 17, etc. Note that noise N1 is superimposed during the period when the AC monitoring signal Sa increases from zero to its peak value (i.e., from time point t21 to time point t22). In contrast, noise N2 is superimposed during the period when the AC monitoring signal Sa remains at zero (i.e., from time point t23 to time point t24). Furthermore, noise N3 is superimposed during the period when the AC monitoring signal Sa decreases from its peak value to zero (i.e., from time point t25 to time point t26).

[0146] When these noises N1 to N3 are superimposed, the peak detection signal Sb may be switched to an unwanted logic level, thus failing to correctly detect the peak value of the AC monitoring signal Sa. Therefore, after switching the logic level of the peak detection signal Sb, if the logic level after the switch does not maintain a predetermined shielding period (e.g., 1600 μs), the zero-crossing detection unit 130 ignores the logic level switch.

[0147] For example, from time point t21 to time point t22, the peak detection signal Sb drops to a low level due to noise N1, but quickly rises to a high level, so this falling edge is ignored. In other words, the zero-crossing detection unit 130 considers the peak detection signal Sb to remain at a high level from time point t21 to time point t22.

[0148] Similarly, from time point t23 to time point t24, the peak detection signal Sb drops to a low level due to noise N2, but quickly rises to a high level, so this falling edge is ignored. In other words, the zero-crossing detection unit 130 considers the peak detection signal Sb to remain at a high level from time point t23 to time point t24.

[0149] In contrast, from time point t25 to time point t26, the peak detection signal Sb rises to a high level due to noise N3, but quickly falls to a low level, so this rising edge is ignored. In other words, the zero-crossing detection unit 130 considers the peak detection signal Sb to remain at a low level from time point t25 to time point t26.

[0150] Note that the unit performing the above noise removal process is not necessarily limited to the zero-crossing detection unit 130. It is useful to complete the noise removal process after receiving the peak detection signal Sb input and before performing specific signal processing.

[0151] In addition, an analog noise filter or a digital noise filter (e.g., a finite impulse response (FIR) filter) can be provided between the peak detection unit 120 and the zero-crossing detection unit 130.

[0152] <Semiconductor Integrated Circuit Device (Second Embodiment)>

[0153] Figure 10 This is a diagram showing a second embodiment of the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 of this embodiment is based on the first embodiment ( Figure 1 ), and further includes a comparison unit 180 and an AC waveform determination unit 190 (in this diagram, the AC monitoring unit 110, the first output unit 140, the DC monitoring unit 150, the second output unit 160, and the undervoltage protection unit 170 are not shown). Therefore, elements having the same structure as those in the first embodiment are represented by the same numbers or symbols as Figure 4 to omit repetitive descriptions. In the following description, the characteristic parts of this embodiment will be mainly described.

[0154] The comparison unit 180 includes four comparators 181 to 184, and compares the AC monitoring signal Sa with each of a plurality of threshold values Vth1 to Vth4 (Vth1 < Vth2 < Vth3 < Vth4) to generate a plurality of comparison signals Sd1 to Sd4.

[0155] More specifically, the comparator 181 compares the AC monitoring signal Sa input to the non-inverting input terminal (+) with the threshold value Vth1 input to the inverting input terminal (-) to generate a comparison signal Sd1. Therefore, when the AC monitoring signal Sa is higher than the threshold value Vth1, the comparison signal Sd1 is at a high level, and when the AC monitoring signal Sa is lower than the threshold value Vth1, the comparison signal Sd1 is at a low level.

[0156] The comparator 182 compares the AC monitoring signal Sa input to the non-inverting input terminal (+) with the threshold value Vth2 input to the inverting input terminal (-) to generate a comparison signal Sd2. Therefore, when the AC monitoring signal Sa is higher than the threshold value Vth2, the comparison signal Sd2 is at a high level, and when the AC monitoring signal Sa is lower than the threshold value Vth2, the comparison signal Sd2 is at a low level.

[0157] The comparator 183 compares the AC monitoring signal Sa input to the non-inverting input terminal (+) with the threshold value Vth3 input to the inverting input terminal (-) to generate a comparison signal Sd3. Therefore, when the AC monitoring signal Sa is higher than the threshold value Vth3, the comparison signal Sd3 is at a high level, and when the AC monitoring signal Sa is lower than the threshold value Vth3, the comparison signal Sd3 is at a low level.

[0158] Comparator 184 compares the AC monitoring signal Sa input to the non-inverting input terminal (+) with the threshold value Vth4 input to the inverting input terminal (-) to generate a comparison signal Sd4. Therefore, when the AC monitoring signal Sa is higher than the threshold value Vth4, the comparison signal Sd4 is at a high level, and when the AC monitoring signal Sa is lower than the threshold value Vth4, the comparison signal Sd4 is at a low level.

[0159] Note that the comparison unit 180 is not limited to four channels. The number of channels can be arbitrary (two or more channels).

[0160] The AC waveform determination unit 190 stores whether each of the rising edge and the falling edge has occurred in each of the comparison signals Sd1 to Sd4, and detects whether both the rising edge and the falling edge have occurred in at least one of the comparison signals Sd1 to Sd4 during one cycle of the zero-crossing detection signal Sc, thereby generating a waveform determination signal Se. When the AC monitoring signal Sa has a normal waveform, the waveform determination signal Se is at a normal determination logic level (for example, a low level), and when the AC monitoring signal Sa has an abnormal waveform, the waveform determination signal Se is at an abnormal determination logic level (for example, a high level).

[0161] Note that when the logic level of each of the comparison signals Sd1 to Sd4 remains for a predetermined period (for example, 40 μs), the AC waveform determination unit 190 first recognizes that the logic level is valid. With this structure, noise or jitter in the comparison signals Sd1 to Sd4 can be ignored, and thus the AC waveform determination process can be correctly performed.

[0162] When the waveform determination signal Se is at an abnormal determination logic level (for example, a high level), the zero-crossing detection unit 130 stops generating or outputting the zero-crossing detection signal Sc. For example, when an instantaneous power failure occurs in the AC power supply, if the waveform of the AC monitoring signal Sa becomes abnormal, the generation or output of the zero-crossing detection signal Sc is stopped. Therefore, the microcomputer 15 quickly recognizes the occurrence of an abnormality in the AC voltage V0, and thus stops driving the motor 17 without delay, and therefore the safety and reliability of the electronic device 10 can be enhanced.

[0163] <AC Waveform Determination Process>

[0164] Figure 11 is a timing chart showing an example of the AC waveform determination process performed by the AC waveform determination unit 190, in which the AC monitoring signal Sa, the peak detection signal Sb, the zero-crossing detection signal Sc, the comparison signals Sd1 to Sd4, and the waveform determination signal Se are shown in order from top to bottom.

[0165] The AC monitoring signal Sa is normally input during the period from time point t31 to time point t32, and within the predetermined detection period Tdet (corresponding to one cycle of the zero-crossing detection signal Sc), the AC monitoring signal Sa rises from zero (<Vth1) to a peak (>Vth4), and then falls back to zero again. As a result, both rising edges and falling edges appear in each of the comparison signals Sd1 to Sd4. Therefore, it is determined that the AC monitoring signal Sa has a normal waveform, and the waveform determination signal Se is at a low level (i.e., the logic level in normal determination).

[0166] In contrast, during the period from time point t32 to time point t33, the AC monitoring signal Sa rises from zero to a peak and then falls again. Immediately thereafter, an instantaneous power failure occurs in the AC power supply, and as a result, the AC monitoring signal Sa remains at a voltage value higher than the threshold Vth4. Note that in a conventional structure ( Figure 20 ) using an optocoupler with high power consumption, if an instantaneous power failure occurs in the AC power supply, the power supply to the load is also stopped without delay, so there is no particular problem. However, in this structure without using an optocoupler, the monitored target voltage V2 is not discharged, so the state as shown in the figure may occur.

[0167] In this case, if the monitored target voltage V2 (and thus the AC monitoring signal Sa) changes periodically due to specific factors, although the power supply from the AC power supply is stopped, the peak value of the AC monitoring signal Sa is misdetected, and thus the zero-crossing detection signal Sc is still output. As a result, the microcomputer 15 erroneously determines that power is continuously supplied from the AC power supply, and there may be a failure in which the motor 17 continuously rotates by the remaining power.

[0168] In contrast, in a structure including the comparison unit 180 and the AC waveform determination unit 190, if the AC monitoring signal Sa remains at a voltage value higher than the threshold Vth4, all the comparison signals Sd1 to Sd4 are fixed at a high level, so it is determined that the waveform of the AC monitoring signal Sa is abnormal. Therefore, the waveform determination signal Se is raised to a high level (i.e., the abnormal determination logic level). As a result, after time point t33, the generation and output of the zero-crossing detection signal Sc are stopped, so the microcomputer 15 can quickly recognize the instantaneous power failure in the AC power supply and can stop the drive of the motor 17 without delay.

[0169] Note that due to the slow discharge of the monitored target voltage V2, rising edges and falling edges may appear in the AC monitoring signal Sa during a period longer than the above detection period Tdet. However, by setting the detection period Tdet to one cycle of the zero-crossing detection signal Sc, it is possible to prevent the erroneous determination that the AC monitoring signal Sa has a normal waveform based on this pulse edge.

[0170] Figure 12 This is a diagram illustrating a normal determination example of the AC monitoring signal Sa, where the AC monitoring signal Sa and comparison signals Sd1 to Sd4 are shown in order from top to bottom.

[0171] On the left side of the diagram, similar to Figure 11 The time points t31 to t32 in the figure show the variation of the AC monitoring signal Sa across all thresholds Vth1 to Vth4. In this case, periodic pulse edges appear in all comparison signals Sd1 to Sd4, and it is determined that the AC monitoring signal Sa is normal.

[0172] In contrast, the middle of the figure shows a case where the AC monitoring signal Sa varies only across thresholds Vth1 and Vth2 (here, the peak value of the half-wave rectified waveform is shown to be below threshold Vth3). In this case, although the comparison signals Sd3 and Sd4 are fixed at low levels, periodic pulse edges appear in both comparison signals Sd1 and Sd2, thus confirming that the AC monitoring signal Sa is normal.

[0173] Furthermore, on the right side of the figure, it is shown that the AC monitoring signal Sa varies in a manner that crosses thresholds Vth2 to Vth4 (here, the lower peak of the AC waveform is higher than the threshold Vth1). In this case, although the comparison signal Sd1 is fixed at a high level, periodic pulse edges appear in each of the comparison signals Sd2 to Sd4, thus confirming that the AC monitoring signal Sa is normal.

[0174] In this way, by using the comparison unit 180 with multiple channels, the AC waveform determination process can be appropriately performed on the AC monitoring signal Sa with various normal waveforms.

[0175] Furthermore, it is not necessary to combine the peak detection process or the zero-crossing detection process to perform the above AC waveform determination process; the above AC waveform determination process can be performed independently.

[0176] <Semiconductor Integrated Circuit Device (Third Embodiment)>

[0177] Figure 13 This is a diagram illustrating a third embodiment of the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 of this embodiment is based on the first embodiment (…). Figure 4 Furthermore, it includes an integrated AC / DC converter 13 as a feature. Therefore, elements having the same structure as in the first embodiment are combined with... Figure 4 The same numbers or symbols are used to represent features, so as to omit redundant descriptions. The following description mainly focuses on the characteristic features of this embodiment.

[0178] Among the circuit elements constituting the AC / DC converter 13, the semiconductor integrated circuit device 100 includes integrated resistors 13a and 13b, an error amplifier 13c, a comparator 13d, an RS flip-flop 13e, a level shifter 13f, and an NMOSFET 13g.

[0179] Furthermore, an external terminal (pin X) is added to the semiconductor integrated circuit device 100 along with the integration of the AC / DC converter 13. Note that the coil 13h and diode 13i in the circuit elements constituting the AC / DC converter 13 are externally connected to pin X. Specifically, the first terminal of the coil 13h and the cathode of the diode 13i are connected to pin X. The second terminal of the coil 13h is connected to the output terminal of the first DC voltage V3. The anode of the diode 13i is connected to pin 3 (GND pin).

[0180] Inside the semiconductor integrated circuit device 100, resistors 13a and 13b are connected in series between pin 4 (VCC pin) and pin 3 (GND pin) and serve as a voltage divider circuit that outputs a feedback signal FB (i.e., a voltage divider of the first DC voltage V3) from the connection node of resistors 13a and 13b.

[0181] Error amplifier 13c generates an error signal ERR based on the difference between the feedback signal FB input to the non-inverting input (+) and the predetermined reference signal REF input to the inverting input (-). The larger the difference between the feedback signal FB and the reference signal REF, the higher the error signal ERR; conversely, the smaller the difference between the feedback signal FB and the reference signal REF, the lower the error signal ERR.

[0182] Comparator 13d compares a ramp signal SLP, which has a sawtooth (or triangular) waveform input to the non-inverting input terminal (+), with an error signal ERR input to the inverting input terminal (-), to generate a reset signal RST. The reset signal RST is high when the ramp signal SLP is higher than the error signal ERR, and low when the ramp signal SLP is lower than the error signal ERR.

[0183] The RS flip-flop 13e determines the logic level of the pulse width modulation (PWM) signal based on both the set signal SET (i.e., a clock signal with a rectangular waveform oscillating at a predetermined switching frequency) input to the set terminal (S) and the reset signal RST input to the reset terminal (R), and outputs the PWM signal from the output terminal (Q). For example, when the set signal SET rises to a high level, the PWM signal is set to a high level, and when the reset signal RST rises to a high level, the PWM signal is reset to a low level.

[0184] The level shifter 13f levels the pulse width modulation signal PWM (H = V3 and L = GND) to generate the drive signal DRV (H = Vs + α and L = Vs, where Vs represents the source voltage of NMOSFET 13g at pin X).

[0185] The NMOSFET 13g is connected between pin 5 (VHDC pin) and pin X, and is an output switching element that is turned on and off by the drive signal DRV.

[0186] In this way, the AC / DC converter 13 is packaged into a single package of the semiconductor integrated circuit device 100, thus reducing the number of components.

[0187] Note that this embodiment describes a method based on the first embodiment ( Figure 4 This example is based on the second implementation ( ), but the example can also be based on the second implementation ( ). Figure 10 ).

[0188] <Semiconductor Integrated Circuit Device (Fourth Embodiment)>

[0189] Figure 14 This is a diagram illustrating a fourth embodiment of the semiconductor integrated circuit device 100. The semiconductor integrated circuit device 100 of this embodiment is based on the third embodiment (…). Figure 13 Furthermore, it includes an integrated DC / AC converter 14 as a feature. Note that an external terminal (pin Y) for outputting a second DC voltage V4 is added to the semiconductor integrated circuit device 100 of this embodiment along with the integration of the DC / DC converter 14. In this way, not only the AC / DC converter 13 but also the DC / DC converter 14 are packaged in a single package, thus further reducing the number of components.

[0190] <Packaging>

[0191] Figure 15 This is an external view showing the package of a semiconductor integrated circuit device 100. The figure shows an example of a small outline package (SOP) with external terminals extending in both directions from the long side of the package.

[0192] Pin 1 (ACOUT pin), pin 2 (DCOUT pin), pin 3 (GND pin), and pin 4 (VCC pin) are low withstand voltage terminals (pins 1 and 2 have a withstand voltage of 5V, and pins 3 and 4 have a withstand voltage of 30V) when no rectified voltage V1 is applied or the target voltage V2 is monitored, and are arranged on the first side of the package.

[0193] In contrast, pins 5 (VHDC pin) and 7 (VHAC pin) are high-voltage withstand terminals (with a withstand voltage of 700V) for which a rectified voltage V1 is applied and a target voltage V2 is monitored, and are located on the second side of the package. This pin assignment ensures the insulation creepage distance between pins 1 to 4 and pins 5 or 7, thus easily ensuring pin-to-pin insulation.

[0194] Note: The external terminal originally positioned between pin 7 (VHAC pin) and pin 6 (NC pin) has been removed. Therefore, the terminal distance between pin 7 and the adjacent pin 6 is greater than the terminal distance between adjacent pins from pin 1 to pin 4. Furthermore, ignoring the unused pin 6, the terminal distance between pin 5 and pin 7 is naturally greater than the terminal distance between adjacent pins from pin 1 to pin 4. This pin assignment also ensures adequate insulation between pins on the second side.

[0195] <Encapsulation Layout (First Example)>

[0196] Figure 16 This is a diagram (XZ plan view) showing a first example of the package layout. In the semiconductor integrated circuit device 100 of this diagram, a first chip 100a and a second chip 100b are mounted on an island 100c.

[0197] First, the internal structures of the first chip 100a and the second chip 100b will be described in detail with reference to the accompanying drawings. Figure 17 This is a diagram showing the internal structure of the first chip 100a and the second chip 100b, wherein the diagram is based on the first embodiment ( Figure 4 An example of ).

[0198] The first chip 100a includes an integrated AC monitoring unit 110 and a DC monitoring unit 150. Furthermore, the first chip 100a has pads P1 to P5 as means for establishing electrical connections to the outside of the chip. Inside the first chip 100a, pad P1 is connected to the input terminal of the DC monitoring unit 150. Pad P2 is connected to the input terminal of the AC monitoring unit 110. Pad P3 is connected to the output terminal of the DC monitoring unit 150. Pad P4 is connected to the output terminal of the AC monitoring unit 110. Pad P5 is connected to ground.

[0199] In contrast, the second chip 100b includes an integrated peak detection unit 120, a zero-crossing detection unit 130, a first output unit 140, a second output unit 160, and an undervoltage protection unit 170. Furthermore, the second chip 100b has pads P6 to P12 as means for establishing electrical connections to the outside of the chip. Inside the second chip 100b, pad P6 is connected to the input terminal of the second output unit 160. Pad P7 is connected to the input terminal of the peak detection unit 120. Pad P8 is connected to ground. Pad P9 is connected to the input terminal (i.e., power line) of the undervoltage protection unit 170. Pad P10 is connected to ground. Pad P11 is connected to the output terminal of the second output unit 160. Pad P12 is connected to the output terminal of the first output unit 140.

[0200] Note that when the second implementation method ( Figure 10 When using this as a basis, the comparison unit 180 and the AC waveform determination unit 190 should also be integrated into the second chip 100b.

[0201] Refer again Figure 16 Continuing with the package layout description: Pad P1 is connected to pin 5 (VHDC pin) via wire W1. Pad P2 is connected to pin 7 (VHAC pin) via wire W2. Pad P3 is connected to pad P6 via wire W3. Pad P4 is connected to pad P7 via wire W4. Pad P5 is connected to pad P8 via wire W5. Pad P9 is connected to pin 4 (VCC pin) via wire W6. Pad P10 is connected to pin 3 (GND pin) via wire W7. Pad P11 is connected to pin 2 (DCOUT pin) via wire W8. Pad P12 is connected to pin 1 (ACOUT pin) via wire W9.

[0202] Note that, regarding the frame area inside the package, each of pins 1 (ACOUT pin), 4 (VCC pin), 5 (VHDC pin), and 7 (VHAC pin) is larger than each of pins 2 (DCOUT pin), 3 (GND pin), and 6 (NC pin).

[0203] In other words, regarding the X direction (i.e., the left-right direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) protrude more than pins 2 (DCOUT pin) and 3 (GND pin). Similarly, pins 5 (VHDC pin) and 7 (VHAC pin) protrude more than pin 6 (NC pin).

[0204] Furthermore, regarding the Z direction (i.e., the up-down direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) partially overlap with island 100c. Similarly, pins 5 (VHDC pin) and 7 (VHAC pin) partially overlap with island 100c.

[0205] In addition, support frames 100e and 100f for supporting island 100c are formed between pin 1 (ACOUT pin) and pin 7 (VHAC pin) and between pin 4 (VCC pin) and pin 5 (VHDC pin), respectively.

[0206] Note that in the package layout shown in the figure, the first chip 100a is positioned near the second side of island 100c (i.e., near pins 5 to 7), while the second chip 100b is positioned near the first side (i.e., near pins 1 to 4). By adopting this package layout, the wires W1 to W9 can be kept as short as possible.

[0207] Next, the reason why the semiconductor integrated circuit device 100 is composed of a dual-chip structure instead of a single-chip structure will be described. If both the AC monitoring unit 110 and DC monitoring unit 150, which handle high voltages, and other circuit units (120 to 140, 160, and 170) that handle low voltages are integrated into a single chip, a buffer region needs to be provided between the high-voltage processing region and the low-voltage processing region. As a result, the chip size becomes very large, leading to a significant increase in cost.

[0208] In contrast, if the semiconductor integrated circuit device 100 is composed of a dual-chip structure, it is not necessary to provide a buffer region in each of the first chip 100a and the second chip 100b. Therefore, the chip size can be reduced, resulting in lower costs. Furthermore, the separation of the first chip 100a and the second chip 100b is also highly advantageous for voltage withstand capabilities.

[0209] Next, the grounding path of the first chip 100a is described. Pin 3 (GND pin) is positioned between pin 2 (DCOUT pin) and pin 4 (VCC pin) as a shielding element to prevent noise from propagating from pin 4 (VCC pin) to pin 2 (DCOUT pin) or pin 1 (ACOUT pin). Therefore, if an attempt is made to wire bond directly from pad P5 (i.e., ground pad) of the first chip 100a to pin 3 (GND pin), it will inevitably interfere with the wiring W8 from pad P11 of the second chip 100b to pin 2 (DCOUT pin) or from pad P12 to pin 1 (ACOUT pin).

[0210] Therefore, the pad P5 (i.e., the ground pad) of the first chip 100a is not directly wire-bonded to pin 3 (GND pin), but is wire-bonded to the pad P8 of the second chip 100b via wire W5. As described above. Figure 17 As shown, pad P8 is connected to pad P10 (i.e., ground pad) of the second chip 100b via a GND line formed inside the second chip 100b, and further connected to pin 3 (GND pin) via wire W7. Therefore, the ground of the first chip 100a is connected to pin 3 (GND) via pad P5, wire W5, pad P8, the ground line formed inside the second chip 100b, pad P10, and wire W7. This grounding path avoids interference with wires W8 or W9.

[0211] Figure 18 It is shown schematically. Figure 16 The diagram shows the α-α' cross-section. If the semiconductor integrated circuit device 100 is cut along the α-α' line, it can be understood from the diagram that a signal path from pin 7 (VHAC pin) to pin 1 (ACOUT pin) is formed via wire W2, pads P2 and P4 of the first chip 100a, wire W4, pads P7 and P12 of the second chip 100b, and wire W9.

[0212] Furthermore, it can be clearly understood from the figure that the first chip 100a and the second chip 100b are disposed on the common island 100c and sealed with molding resin 100d.

[0213] Furthermore, it is clear from the figure that the external terminals of the semiconductor integrated circuit device 100 are soldered to the copper wires 210 of the printed circuit board 200 using solder 220.

[0214] <Encapsulation Layout (Second Example)>

[0215] Figure 19 This is a diagram illustrating a second example of the package layout. As shown in the diagram, the positional relationship between the first chip 100a and the second chip 100b along the Z-axis can be the same as that in the first example described above ( Figure 16 The positional relationship in () is reversed.

[0216] More specifically, in the first example ( Figure 16 In the example ), on island 100c, the first chip 100a is positioned near the upper side of the paper, while the second chip 100b is positioned near the lower side of the paper. Conversely, in the second example ( Figure 19 In the same island 100c, the first chip 100a is disposed near the lower side of the paper, while the second chip 100b is disposed near the upper side of the paper.

[0217] Note that when changing the chip layout described above, it is preferable to appropriately change the pin functions and pad arrangements as shown in the figure so that no obstruction occurs during wire bonding between the pins and pads.

[0218] Furthermore, regarding the frame area inside the package, each of pin 1 (VCC pin), pin 4 (ACOUT pin), pin 5 (VHAC pin), and pin 7 (VHDC pin) is larger than pin 2 (GND pin), pin 3 (DCOUT pin), or pin 6 (NC pin).

[0219] In other words, regarding the X direction (i.e., the left-right direction on the paper), pins 1 (VCC pin) and 4 (ACOUT pin) protrude more than pins 2 (GND pin) and 3 (DCOUT pin). Similarly, pins 5 (VHAC pin) and 7 (VHDC pin) protrude more than pin 6 (NC pin).

[0220] Furthermore, regarding the Z direction (i.e., the up-down direction on the paper), pin 1 (VCC pin) and pin 4 (COUT pin) partially overlap with island 100c. Similarly, pin 5 (VHAC pin) and pin 7 (VHDC pin) partially overlap with island 100c.

[0221] In addition, support frames 100e and 100f for supporting island 100c are formed between pin 1 (VCC pin) and pin 7 (VHDC pin) and between pin 4 (ACOUT pin) and pin 5 (VHAC pin), respectively.

[0222] <Electronic Devices (Examples of Third and Fourth Structures)>

[0223] Figure 20 and Figure 21 These are diagrams illustrating a third structural example (normal rectification method) and a fourth structural example (voltage doubler rectification method) of the electronic device 10, respectively. These structural examples of the electronic device 10 are based on the first structural example described above (…). Figure 1 ) and second structure example ( Figure 2 Furthermore, unlike the first and second structural examples described above, the structure of the zero-crossing detection circuit 18 has been modified and an input reactor 19 has been added.

[0224] Therefore, elements having the same structure as in the first and second structural examples are composed of... Figure 1 and Figure 2 The same numbers or symbols are used to represent the same elements, thus omitting redundant descriptions. The following description primarily focuses on the characteristic parts of the third and fourth structural examples.

[0225] As described above, the zero-crossing detection circuit 18 is a circuit block that detects the zero-crossing of the AC voltage V0, and includes a semiconductor integrated circuit device 300, diodes D11 and D12 externally connected to the semiconductor integrated circuit device 300, and a capacitor C11.

[0226] The semiconductor integrated circuit device 300 is an IC or LSI that integrates at least a portion of the circuit elements forming a zero-crossing detection circuit 18 (details will be described later), and has seven external terminals (pins 1 to 7) as means for establishing electrical connections to the outside of the device.

[0227] Pin 1 (ACOUT pin) is the output terminal of the ACOUT signal S1 and is connected to the microcomputer 15. Pin 2 (NC pin) is an unused terminal and is not connected anywhere outside the semiconductor integrated circuit device 300. Pin 3 (GND pin) is the ground terminal and is connected to the ground terminal GND shared with the microcomputer 15. In other words, the semiconductor integrated circuit device 300 (and therefore the zero-crossing detection circuit 18 of the semiconductor integrated circuit device 300) operates relative to the ground voltage shared with the microcomputer 15. Pin 4 (VCC pin) is the power supply terminal and is connected to the output terminal of the AC / DC converter 13 (i.e., the output terminal of the first DC voltage V3). Note that capacitor C11 is connected between pin 4 and pin 3.

[0228] Pin 5 (NC pin) is an unused terminal and is not connected anywhere outside the semiconductor integrated circuit device 300. Pin 6 (VHAC2 pin) is the second AC input terminal and is connected to the cathode of diode D12 (corresponding to the input terminal for monitoring the target voltage V12). The anode of diode D12 is connected to terminal L1 (corresponding to the second node). Pin 7 (VHAC1 pin) is the first AC input terminal and is connected to the cathode of diode D11 (corresponding to the input terminal for monitoring the target voltage V11). The anode of diode D11 is connected to terminal N1 (corresponding to the first node).

[0229] Note that if rectifier unit 12 uses the normal rectification method ( Figure 20 When the terminals of L1 and N1 are connected, the terminal voltages are equal. Therefore, there is no problem if the anode connections of diodes D11 and D12 are interchanged.

[0230] Furthermore, the anode connection destinations of diodes D11 and D12 are not necessarily limited to terminals L1 and N1. The target voltages V11 and V12 can be taken from any node where an AC voltage V0 is applied, regardless of whether it is the stage before or after the input reactor 19.

[0231] The input reactor 19 is provided for purposes such as improving the input power factor, reducing harmonics, and reducing motor noise. Note that this figure shows an example where the input reactor 19 is located on the stage before the filter 11 (L terminal side), but its location is not limited to this. The input reactor 19 can be located on the N terminal side or the stage after the filter 11.

[0232] <Semiconductor Integrated Circuit Device (Fifth Embodiment)>

[0233] Figure 22 This is a figure illustrating a fifth embodiment of the semiconductor integrated circuit device 300. As shown in the figure, the semiconductor integrated circuit device 300 of this embodiment includes an integrated AC monitoring unit 310, a zero-crossing detection unit 320, a logic unit 330, a first output unit 340, a comparison unit 350, and an undervoltage protection unit 360.

[0234] AC monitoring unit 310 is a high-voltage circuit unit (e.g., having a withstand voltage of 650V), which generates AC monitoring signals SA1 and SA2 adapted to be input to zero-crossing detection unit 320 based on the monitoring target voltage V11 input to pin 7 (VHAC1 pin) and the monitoring target voltage V12 input to pin 6 (VHAC2 pin), respectively. Note that the monitoring target voltages V11 and V12 correspond to the first monitoring target signal and the second monitoring target signal input to the N1 terminal and L1 terminal, respectively, through diodes D11 and D12 from which an AC voltage V0 is applied.

[0235] The zero-crossing detection unit 320 compares the AC monitoring signal SA1 with the AC monitoring signal SA2 to generate a comparison signal SB.

[0236] Logic unit 330 estimates the zero-crossing of AC voltage V0 based on comparison signal SB, thereby generating a zero-crossing detection signal SC. Furthermore, logic unit 330 also has the function of stopping the generation or output of the zero-crossing detection signal SC based on the detection result of comparison signal SD (i.e., AC waveform determination function). This AC waveform determination function is essentially the same as the function of the AC waveform determination unit 190 described above, and repeated descriptions are omitted.

[0237] The first output unit 340 receives the zero-crossing detection signal SC as input to generate the ACOUT signal S1, and outputs the ACOUT signal S1 to pin 1 (ACOUT pin). Note that the first output unit 340 should have the same characteristics as... Figure 7 The first output unit 140 has a basically the same structure. In other words, Figure 7 The “zero-crossing detection signal Sc” can be replaced by “zero-crossing detection signal SC”, which helps to understand the structure and operation of the first output unit 340.

[0238] The comparison unit 350 compares the AC monitoring signal SA1 with each of a plurality of threshold values to generate a plurality of comparison signals SD. Note that the comparison unit 350 should have substantially the same structure as the Figure 10 comparison unit 180. In other words, Figure 10 the “AC monitoring signal Sa” in can be replaced with “AC monitoring signal SA1”, and “comparison signals Sd1 to Sd4” can be replaced with “comparison signal SD”, so that the structure and operation of the comparison unit 350 can be understood. Regarding the plurality of threshold values to be compared with the AC monitoring signal SA1, for example, not only a threshold value for detecting an instantaneous power failure can be set, but also a threshold value for detecting UVLO can be set.

[0239] The undervoltage protection unit 360 is a protection functional unit (a so-called UVLO protection unit) that disables the operation of the semiconductor integrated circuit device 300 when the first DC voltage V3 input to the pin 4 (VCC) is lower than the lower limit value.

[0240] <Zero-crossing detection unit (first example)>

[0241] Figure 23 is a diagram showing a first example of the zero-crossing detection unit 320. The zero-crossing detection unit 320 of this example includes a comparator 321 that compares the AC monitoring signal SA1 input to the non-inverting input terminal (+) with the AC monitoring signal SA2 input to the inverting input terminal (-) to generate a comparison signal SB. When SA1 > SA2 holds, the comparison signal SB is at a high level, and when SA1 < SA2 holds, the comparison signal SB is at a low level.

[0242] The AC monitoring unit 310 provided at the previous stage of the zero-crossing detection unit 320 includes resistors 311 to 314. The resistors 311 and 312 are connected in series between the pin 7 (VHAC1) and the pin 3 (GND) so as to output the AC monitoring signal SA1 (the divided voltage corresponding to the monitored target voltage V11) from the connection node of the resistors 311 and 312. The resistors 313 and 134 are connected in series between the pin 6 (VHAC2) and the pin 3 (GND) so as to output the AC monitoring signal SA2 (the divided voltage corresponding to the monitored target voltage V12) from the connection node of the resistors 313 and 134.

[0243] Note that in this diagram, for simplicity of description, only the resistors 311 to 314 are shown as the structural elements of the AC monitoring unit 310, but in reality, similar to Figure 5 the AC monitoring unit 110, it preferably includes various electrostatic protection elements.

[0244] <Zero-crossing detection process (first example to third example)>

[0245] Next, the zero-crossing detection process of the semiconductor integrated circuit device 300 will be described. Figure 24 is a timing chart showing a first example of the zero-crossing detection process, where the AC voltage V0, the monitored target voltages V11 and V12, and the ACOUT signal S1 are shown in this order from top to bottom. In particular, this figure shows an ideal state where the monitored target voltages V11 and V12 cross each other at the zero-crossing of the AC voltage V0.

[0246] The semiconductor integrated circuit device 300 pseudo-monitors the voltages at both ends of the AC voltage V0 (i.e., the terminal voltage at the N1 terminal and the terminal voltage at the L1 terminal) as the monitored target voltages V11 and V12, and switches the logic level of the ACOUT signal S1 according to the comparison result. Referring to this figure, when V11 > V12 holds, the ACOUT signal S1 is at a high level, and when V11 < V12 holds, the ACOUT signal S1 is at a low level.

[0247] In this case, the rising timing of the ACOUT signal S1 is basically the same as the timing when the AC voltage V0 switches from negative to positive (i.e., at the zero-crossing from negative to positive) (see time points t41, t43, and t45). On the contrary, the falling timing of the ACOUT signal S1 is basically the same as the timing when the AC voltage V0 switches from positive to negative (i.e., at the zero-crossing from positive to negative) (see time points t42, t44, and t46).

[0248] Figure 25 is a timing chart showing a second example of the zero-crossing detection process, where the AC voltage V0, the AC monitoring signals SA1 (solid line) and SA2 (dashed line), and the comparison signal SB are shown in this order from top to bottom. Note that this figure shows the behavior in the case where the rectifying unit 12 employs a voltage doubler rectification method ( Figure 21 ).

[0249] As shown in this figure, in the actual electronic device 10, due to the influence of the input reactor 19, the waveforms of the AC monitoring signals SA1 and SA2 are greatly distorted. In particular, the rising speed of the AC monitoring signal SA1 is liable to vary according to the load Z, so the rising timing of the comparison signal SB may vary greatly. On the contrary, the falling speed of the AC monitoring signal SA1 is not liable to vary according to the load Z, so the falling timing of the comparison signal SB has a relatively small variation.

[0250] From the above considerations, preferably, the logic unit 330 should detect the falling timing of the comparison signal SB (i.e., the timing when SA1 > SA2 switches to SA1 < SA2 and the AC monitoring signal SA1 decreases) in order to estimate the zero-crossing of the AC voltage V0 based on the detected falling timing.

[0251] Figure 26 is a timing chart showing a third example of the zero-crossing detection process, in which the AC voltage V0, the AC monitoring signals SA1 (solid line) and SA2 (dashed line), the comparison signal SB, the edge detection signal EDGE (i.e., the internal signal of the logic unit 330), and the zero-crossing detection signal SC are shown in this order from top to bottom. Note that this figure shows the behavior in the case where the rectifying unit 12 employs a voltage-doubling rectification method ( Figure 21 ).

[0252] As shown at time points t51 to t55, inside the logic unit 330, at each falling timing of the comparison signal SB, pulses are generated on the edge detection signal EDGE. Then, the logic unit 330 counts the pulse intervals of the edge detection signal EDGE (i.e., the period T of the comparison signal SB) in order to estimate the zero-crossing of the AC voltage V0 using the count value.

[0253] More specifically, on the premise that the AC voltage V0 has a constant period and a constant phase, the logic unit 330 refers to the period T of the comparison signal SB to determine the rising timing and the falling timing of the zero-crossing detection signal SC.

[0254] For example, the logic unit 330 reduces the zero-crossing detection signal SC from a high level to a low level at the time point when the comparison signal SB drops to a low level (e.g., time point t53). This falling timing of the zero-crossing detection signal SC is substantially the same as the timing when the AC voltage V0 switches from negative to positive (i.e., the zero-crossing switches from negative to positive). <第

[0255] In addition, the logic unit 330 counts the standby time T3 (e.g., T3 = T / 2) corresponding to the previously obtained period T starting from the time point when the comparison signal SB drops to a low level, and increases the zero-crossing detection signal SC from a low level to a high level at the time point when the standby time T3 has passed. The rising timing of the zero-crossing detection signal SC is substantially the same as the timing when the AC voltage V0 switches from positive to negative (i.e., the zero-crossing switches from positive to negative).

[0256] <Zero-crossing detection unit (second example)>

[0257] Figure 27 is a diagram showing a second example of the zero-crossing detection unit 320. The zero-crossing detection unit 320 of this example is based on the first example ( Figure 23 ), and further includes a comparator 322. The comparator 322 compares the AC monitoring signal SA1 input to the non-inverting input terminal (+) with a predetermined threshold value VTH (e.g., VTH = 20 mV) input to the inverting input terminal (-), thereby generating a comparison signal SB2. When SA1 > VTH holds, the comparison signal SB2 is at a high level, and when SA1 < VTH holds, the comparison signal SB2 is at a low level.

[0258] In the following description, the significance of introducing comparator 322 is described with reference to the zero-crossing detection process of semiconductor integrated circuit device 300.

[0259] <Zero-crossing detection process (Examples 4 to 6)>

[0260] Figure 28 This is a timing diagram illustrating a fourth example of the zero-crossing detection process, where the AC voltage V0, AC monitoring signals SA1 (solid line) and SA2 (dashed line), comparison signals SB and SB2, edge detection signal EDGE, and zero-crossing detection signal SC are shown in descending order. Note that this diagram illustrates the use of a voltage doubler rectification method in rectifier unit 12. Figure 21 The behavior under the circumstances.

[0261] As shown in the figure, when both AC monitoring signals SA1 and SA2 drop to near 0V, the logic level of the comparison signal SB may become unstable, which may cause jitter.

[0262] Therefore, when the AC monitoring signal SA1 is lower than the predetermined threshold VTH, the logic unit 330 counts the period T of the comparison signal SB2 instead of the comparison signal SB, and uses the count value to estimate the zero crossing of the AC voltage V0.

[0263] Specifically, as shown at each of time points t61 to t65, within logic unit 330, a pulse is generated in the edge detection signal EDGE at each falling time of the comparison signal SB2. Then, logic unit 330 counts the pulse intervals of the edge detection signal EDGE (i.e., the period T of the comparison signal SB2) to use the count values ​​to estimate the zero crossing of the AC voltage V0.

[0264] For example, logic unit 330 lowers the zero-crossing detection signal SC from high to low at the time when the comparison signal SB2 falls to low (e.g., at time t63). This timing of the fall of the zero-crossing detection signal SC is essentially the same as the timing when the AC voltage V0 switches from negative to positive (i.e., the zero-crossing switches from negative to positive).

[0265] Furthermore, logic unit 330 starts counting the standby time T3 (e.g., T3 = T / 2) corresponding to the pre-obtained period T from the time the comparison signal SB2 falls to a low level, and increases the zero-crossing detection signal SC from a low level to a high level when the standby time T3 has elapsed. The rising timing of the zero-crossing detection signal SC is basically the same as the timing when the AC voltage V0 switches from positive to negative (i.e., the zero-crossing switches from positive to negative).

[0266] Figure 29 and Figure 30These are timing diagrams illustrating the fifth and sixth examples of the zero-crossing detection process, respectively. The AC voltage V0, AC monitoring signals SA1 (solid line) and SA2 (dashed line), comparison signals SB and SB2, edge detection signal EDGE, and zero-crossing detection signal SC are shown in descending order. Note that the timing diagrams show the use of a voltage doubler rectification method in rectifier unit 12. Figure 21 The behavior under the circumstances.

[0267] As shown in the figure, logic unit 330 has a shielding function as a measure against jitter in the comparison signal SB2. Specifically, if the comparison signal SB does not remain at a low level during a predetermined shielding period Tm after the comparison signal SB2 falls from a high level to a low level, logic unit 330 ignores the falling edge of the comparison signal SB2.

[0268] Using this shielding function, even if jitter occurs in the comparison signal SB2, no pulses that are not needed for the edge detection signal EDGE will be generated, so no obstacles will occur during the zero-crossing detection of AC voltage V0.

[0269] Note that the length of the shielding period Tm should be appropriately adjusted within logic unit 330. Furthermore, the counting start timing for standby time T3 can be the pulse generation timing of the edge detection signal EDGE, rather than the falling timing of the comparison signal SB2. In this case, by setting standby time T3 to T / 2-Tm, the rising timing of the zero-crossing detection signal SC can be adjusted to the zero-crossing of the AC voltage V0.

[0270] <Electronic Devices (Fifth Structural Example)>

[0271] Figure 31 This is a diagram illustrating a fifth structural example of electronic device 10 (normal rectification method, single-sided relay). This structural example of electronic device 10 is based on the third structural example described above (…). Figure 20 Furthermore, unlike the third structural example described above, the relay switch 20 is located on the N-terminal side. Therefore, elements having the same structure as in the third structural example are... Figure 20 The same numbers or symbols are used to represent the same elements, thus omitting redundant descriptions. The following description primarily focuses on the characteristic parts of the fifth structural example.

[0272] As shown in the figure, in the electronic device 10 of this structural example, when the power is turned off, the relay switch 20 is open and the N terminal is open. In this case, if the L1 terminal and the N1 terminal are completely insulated from each other, the N1 terminal remains in a high impedance state even if the AC voltage V0 is continuously applied to the L1 terminal, so the monitored target voltages V11 and V12 do not change to the same potential.

[0273] However, in reality, there is a leakage path (i.e., the resistance component R) between the L1 terminal and the N1 terminal. Therefore, after the relay switch 20 is turned off, the monitored target voltages V11 and V12 become the same potential (same phase). As a result, jitter may occur in the comparison signal SB, causing an unexpected pulse output in the ACOUT signal S1.

[0274] Note that this figure illustrates the case where the rectifying unit 12 employs the normal rectification method, but the same failure as described above may occur when the rectifying unit 12 employs the voltage doubler rectification method.

[0275] <Semiconductor Integrated Circuit Device (Sixth Embodiment)>

[0276] Figure 32 This shows the sixth embodiment of the semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 of this embodiment is based on the above-mentioned fifth embodiment ( Figure 22 ) and further includes an input stop detection unit 370. Therefore, elements having the same structure as in the fifth embodiment are denoted by the same numbers or symbols as in Figure 22 to omit repetitive descriptions. In the following description, the characteristic parts of this embodiment will be mainly described.

[0277] The input stop detection unit 370 includes a bias power supply 371 and a comparator 372.

[0278] The bias power supply 371 pulls up the AC monitoring signal SA1 by a predetermined bias voltage Vofs (e.g., Vofs = 20V to 40V) and outputs the result to the comparator 372.

[0279] The comparator 372 compares the AC monitoring signal after offsetting (SA1 + Vofs) input to the non-inverting input terminal (+) with the AC monitoring signal SA2 input to the inverting input terminal (-), thereby generating an input stop detection signal SE. Therefore, when SA1 + Vofs > SA2 holds, the input stop detection signal SE is at a high level, and when SA1 + Vofs < SA2 holds, the input stop detection signal SE is at a low level.

[0280] In other words, after the relay switch 20 is turned off, when the AC monitoring signals SA1 and SA2 become the same phase (or the same potential), SA1 + Vofs > SA2 always holds, so the input stop detection signal SE does not drop to the low level.

[0281] Logic unit 330 detects that the input stop detection signal SE remains high and fixes the zero-crossing detection signal SC at a high level. As a result, even if unwanted jitter occurs in the comparison signal SB, the ACOUT signal S1 can be fixed at a low level. Therefore, the pulse output in the ACOUT signal S1 can be reliably stopped after the relay switch 20 is opened.

[0282] Note that if the input stop detection signal SE does not remain high for a predetermined masking period Tmask (>T) after it rises to a high level, logic unit 330 ignores the rise.

[0283] With this arrangement, as long as the high-low relationship between the AC monitoring signals SA1 and SA2 is periodically reversed, the zero-crossing detection signal SC will not be fixed at a high level, so there will be no obstruction in the normal output operation of the ACOUT signal S1.

[0284] <Output Pulse Stopping Process>

[0285] Figure 33 This is a timing diagram illustrating an example of the output pulse stopping process when the power is turned off, where the AC monitoring signals SA1 (solid line) and SA2 (dashed line), the zero-crossing detection signal SC, and the input stop detection signal SE are shown in order from top to bottom.

[0286] Before time point t91, relay switch 20 is turned on. Therefore, the high-low relationship between AC monitoring signals SA1 and SA2 is periodically reversed, generating periodic pulses in the zero-crossing detection signal SC and the input stop detection signal SE, respectively. Note that, as mentioned above, the zero-crossing detection signal SC is not fixed at a high level unless the input stop detection signal SE remains high during the masking period Tmask (>T).

[0287] When relay switch 20 is opened at time t91, AC monitoring signals SA1 and SA2 become out of phase, so the input stop detection signal SE does not drop to a low level. However, the shielding period Tmask has not passed at this time point, so the zero-crossing detection signal SC is not fixed at a high level.

[0288] Subsequently, when the input stop detection signal SE remains high and the shielding period Tmask passes at time point t92, and given that the AC monitoring signals SA1 and SA2 are in phase, the zero-crossing detection signal SC is fixed at a high level. Therefore, the pulse output in the ACOUT signal S1 can be reliably stopped.

[0289] Note that the semiconductor integrated circuit device 300 in this embodiment is based on the fifth embodiment ( Figure 22However, the zero-crossing detection method does not concern itself with when the input stop detection unit 370 is introduced. For example, Figure 32 The zero-crossing detection unit 320 and logic unit 330 can be derived from... Figure 4 The peak detection unit 120 and the zero-crossing detection unit 130 are replaced. Note that when this replacement is performed, only one of the AC monitoring signals SA1 and SA2 (e.g., AC monitoring signal SA1) should be input to the peak detection unit 120.

[0290] <Encapsulation Layout (Third Example)>

[0291] Figure 34 This is a diagram (XZ plan view) showing a third example of the package layout of a semiconductor integrated circuit device 300. In the semiconductor integrated circuit device 300 of this diagram, a first chip 300a and a second chip 300b are mounted on an island 300c.

[0292] First, the internal structures of the first chip 300a and the second chip 300b will be described in detail with reference to the accompanying drawings. Figure 35 This is a diagram showing the internal structure of the first chip 300a and the second chip 300b, and it illustrates a fifth embodiment ( Figure 22 An example of ).

[0293] The first chip 300a includes an integrated AC monitoring unit 310. Furthermore, the first chip 300a has pads P21 to P25 as means for establishing electrical connections to the outside of the chip. Inside the first chip 300a, pad P21 is connected to a first input terminal of the AC monitoring unit 310 (corresponding to the input terminal for monitoring target voltage V11). Pad P22 is connected to a second input terminal of the AC monitoring unit 310 (corresponding to the input terminal for monitoring target voltage V12). Pad P23 is connected to a first output terminal of the AC monitoring unit 310 (corresponding to the output terminal for AC monitoring signal SA1). Pad P24 is connected to a second output terminal of the AC monitoring unit 310 (corresponding to the output terminal for AC monitoring signal SA2). Pad P25 is connected to ground.

[0294] In comparison, the second chip 300b includes an integrated zero-crossing detection unit 320, a logic unit 330, a first output unit 340, a comparison unit 350, and an undervoltage protection unit 360. Furthermore, the second chip 300b has pads P26 to P31 as means for establishing electrical connections to the outside of the chip. Inside the second chip 300b, pad P26 is connected to the first input terminal of the zero-crossing detection unit 320 (corresponding to the input terminal of the AC monitoring signal SA1). Pad P27 is connected to the second input terminal of the zero-crossing detection unit 320 (corresponding to the input terminal of the AC monitoring signal SA2). Pad P28 is connected to ground. Pad P29 is connected to the input terminal (i.e., the power line) of the undervoltage protection unit 360. Pad P30 is connected to ground. Pad P31 is connected to the output terminal of the first output unit 340.

[0295] Note that when the sixth implementation method ( Figure 32 When using this as a base, the input stop detection unit 370 should also be integrated into the second chip 300b.

[0296] Refer again Figure 34 Continuing with the package layout description: Pad P21 is connected to pin 7 (VHAC1 pin) via wire W21. Pad P22 is connected to pin 6 (VHAC2 pin) via wire W22. Pad P23 is connected to pad P26 via wire W23. Pad P24 is connected to pad P27 via wire W24. Pad P25 is connected to pad P28 via wire W25. Pad P29 is connected to pin 4 (VCC pin) via wire W26. Pad P30 is connected to pin 3 (GND pin) via wire W27. Pad P31 is connected to pin 1 (ACOUT pin) via wire W28.

[0297] Note that regarding the frame area inside the package, each of pin 1 (ACOUT pin), pin 4 (VCC pin), pin 5 (NC pin), and pin 7 (VHAC1 pin) is larger than pin 2 (NC pin), pin 3 (GND pin), or pin 6 (VHAC2 pin).

[0298] In other words, regarding the X direction (i.e., the left-right direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) protrude more than pins 2 (NC pin) and 3 (GND pin). Similarly, pins 5 (NC pin) and 7 (VHAC1 pin) protrude more than pin 6 (VHAC2 pin).

[0299] Furthermore, regarding the Z direction (i.e., the up-down direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) partially overlap with island 300c. Similarly, pins 5 (NC pin) and 7 (VHAC1 pin) partially overlap with island 300c.

[0300] In addition, the support frames 300e and 300f of the support island 300c are formed between pin 1 (ACOUT pin) and pin 7 (VHAC1 pin) and between pin 4 (VCC pin) and pin 5 (NC pin), respectively.

[0301] Note that the relative positions of the chips, the advantages of the dual-chip structure, and the grounding path of the first chip 300a are the same as in the first example described above ( Figure 16 ) and the second example ( Figure 19 The description is the same as that in the previous section, and repeated descriptions are omitted.

[0302] <Encapsulation Layout (Fourth Example)>

[0303] Figure 36 This is a fourth example (XZ plan view) illustrating the package layout of a semiconductor integrated circuit device 300. In this figure, the semiconductor integrated circuit device 300 is similar to the third example described above. Figure 34 The first chip 300a and the second chip 300b are mounted on island 300c. Furthermore, in the semiconductor integrated circuit device 300 of this figure, with the incorporation of the DC monitoring unit (details will be described later), the number of package pins increases from "7" to "11".

[0304] First, the internal structures of the first chip 300a and the second chip 300b will be described in detail with reference to the accompanying drawings. Figure 37 This is a diagram showing the internal structure of the first chip 300a and the second chip 300b, and it shows a fifth embodiment in which a DC monitoring unit 380 and a second output unit 390 are added. Figure 22 The structure of ).

[0305] Note that the internal structure of the first chip 300a and the second chip 300b is the same as described above. Figure 35 The basic structure is the same. Therefore, the following description mainly focuses on the structure from... Figure 35 The part is modified from the original text.

[0306] The first chip 300a also includes an integrated DC monitoring unit 380. The DC monitoring unit 380 is a high-voltage circuit block (e.g., having a withstand voltage of 650V) that generates a DC monitoring signal Sx based on the rectified voltage V1 input to pin 9 (VHDC pin) and corresponds to the DC monitoring unit 150 in the first to fourth embodiments.

[0307] Furthermore, pads P32 and P33 are added to the first chip 300a along with the integration of the DC monitoring unit 380. Inside the first chip 300a, pad P32 is connected to the input terminal of the DC monitoring unit 380. Pad P33 is connected to the output terminal of the DC monitoring unit 380.

[0308] In contrast, the second output unit 390 is additionally integrated into the second chip 300b. The second output unit 390 is a circuit block that receives the input of the DC monitoring signal Sx to generate the DCOUT signal S2 and outputs the DCOUT signal S2 to pin 4 (DCOUT pin), and it corresponds to the second output unit 160 in the first to fourth embodiments.

[0309] Furthermore, pads P34 and P35 are added to the second chip 300b along with the integration of the second output unit 390. Inside the second chip 300b, pad P34 is connected to the input terminal of the second output unit 390. Pad P35 is connected to the output terminal of the second output unit 390.

[0310] Refer again Figure 36 Continuing with the package layout description: Pad P21 is connected to pin 11 (VHAC1 pin) via wire W21. Pad P22 is connected to pin 10 (VHAC2 pin) via wire W22. Pad P23 is connected to pad P26 via wire W23. Pad P24 is connected to pad P27 via wire W24. Pad P25 is connected to pad P28 via wire W25. Pad P29 is connected to pin 7 (VCC pin) via wire W26. Pad P30 is connected to pin 5 (GND pin) via wire W27. Pad P31 is connected to pin 3 (ACOUT pin) via wire W28. Pad P32 is connected to pin 9 (VHDC pin) via wire W29. Pad P33 is connected to pad P34 via wire W30. Pad P35 is connected to pin 4 (DCOUT pin) via wire W31.

[0311] Note that for the frame area inside the package, each of pin 2 (NC pin) and pin 6 (NC pin) is greater than pin 3 (ACOUT pin), pin 4 (DCOUT pin), or pin 5 (GND pin).

[0312] In other words, regarding the X direction (i.e., the left and right direction on the paper), pins 2 (NC pin) and 6 (NC pin) have portions that protrude beyond pins 3 (ACOUT pin), 4 (DCOUT pin), and 5 (GND pin).

[0313] In addition, regarding the Z direction (i.e., the up-and-down direction on the paper), there is no overlapping part between pin 2 (N.C. pin) and island 100c, and there is also no overlapping part between pin 6 (N.C. pin) and island 100c. Similarly, there is no overlapping part between pin 1 (N.C. pin), pin 7 (VCC pin), pin 8 (N.C. pin), and pin 11 (VHAC1 pin) and island 100c.

[0314] In addition, support frames 300e and 300f for supporting island 300c are respectively formed between pin 1 (N.C. pin) and pin 11 (VHAC1 pin), and between pin 7 (VCC pin) and pin 8 (N.C. pin).

[0315] <AC Monitoring Unit and DC Monitoring Unit>

[0316] Figure 38 is a diagram showing a structural example of the AC monitoring unit 310 and the DC monitoring unit 380 in the above Figure 37 The AC monitoring unit 310 of this structural example includes resistors 311a to 315a and 311b to 315b, NMOSFETs 316a and 316b, PMOSFETs 317a and 317b, and fuses 318a and 318b.

[0317] Resistors 311a to 315a are connected in series in the order shown between pad P21 (VHAC1 pad) and pad P25 (GND pad). Note that the connection node of resistor 313a and resistor 314a is connected to pad P23 (ACIN1 pad). In other words, resistors 311a to 315a are used as a voltage divider circuit that divides the monitored target voltage V11 (i.e., the first monitored target signal) input to pad P21 to generate an AC monitoring signal SA1.

[0318] In contrast, resistors 311b to 315b are connected in series in the order shown between pad P22 (VHAC2 pad) and pad P25 (GND pad). The connection node of resistor 313b and resistor 314b is connected to pad P24 (ACIN2 pad). In other words, resistors 311b to 315b are used as a voltage divider circuit that divides the monitored target voltage V12 (i.e., the second monitored target signal) input to pad P22 to generate an AC monitoring signal SA2.

[0319] Note that among resistors 311a to 315a and resistors 311b to 315b, resistors 311a and 311b correspond to the first feedback resistors. Furthermore, resistors 312a to 315a and resistors 312b to 315b correspond to the second feedback resistors. Specifically, in the second feedback resistors, the resistance value of each resistor (312a and 315a) and resistors 312b and 315b) can be arbitrarily adjusted using fuses 318a and 318b.

[0320] The drain of NMOSFET 316a is connected to pad P21. The source, gate, and back gate of NMOSFET 316a are connected to pad P25. The drain of PMOSFET 317a is connected to pad P25. The source, gate, and back gate of PMOSFET 317a are connected to pad P23.

[0321] The drain of NMOSFET 316b is connected to pad P22. The source, gate, and back gate of NMOSFET 316b are connected to pad P25. The drain of PMOSFET 317b is connected to pad P25. The source, gate, and back gate of PMOSFET 317b are connected to pad P22.

[0322] Each of the NMOSFETs 316a and 316b and the PMOSFETs 317a and 317b connected in this manner serves as an electrostatic discharge protection element.

[0323] In contrast, the DC monitoring unit 380 of this structural example includes resistors 381 to 385, an NMOSFET 386, a PMOSFET 387, and a fuse 388.

[0324] Resistors 381 through 385 are connected in series between pad P32 (VHDC pad) and pad P25 (GND pad) in the order shown. Note that the connection node of resistors 383 and 384 is connected to pad P33 (DCIN pad). In other words, resistors 381 through 385 act as a voltage divider circuit, which divides the rectified voltage V1 (i.e., the third monitoring target signal) input to pad P32 to generate the DC monitoring signal Sx.

[0325] Note that among resistors 381 to 385, resistor 381 corresponds to the first feedback resistor, and resistors 382 to 385 correspond to the second feedback resistor. Specifically, in the second feedback resistor, the resistance value of each of resistors 382 and 385 can be arbitrarily adjusted by using fuse 388 for fine-tuning.

[0326] The drain of NMOSFET 386 is connected to pad P32. The source, gate, and back gate of NMOSFET 386 are connected to pad P25. The drain of PMOSFET 387 is connected to pad P25. The source, gate, and back gate of PMOSFET 387 are connected to pad P33.

[0327] The NMOSFET 386 and PMOSFET 387 (along with their accompanying body diode) connected in this manner serve as electrostatic discharge protection components.

[0328] <Chip Layout (First Chip)>

[0329] Figure 39 This is a diagram showing the layout of the first chip 300a. Note that, to avoid complexity, the wiring formed in the first chip 300a is not shown. Furthermore, in the following description, for ease of description, the up, down, left, and right directions on the paper are defined as the up, down, left, and right directions in the plan view of the first chip 300a, in order to describe the positional relationships of the pads or components.

[0330] In the plan view, the first chip 300a is cut into a rectangular shape with substantially equal ratios between the short side (right or left) and the long side (top or bottom) (more precisely, a slightly horizontal rectangular shape).

[0331] In the plan view of the first chip 300a, region A1 (i.e., the approximate left half of the first chip 300a) includes three high-voltage regions 400X to 400Z (details described later) formed and arranged in the vertical direction of the first chip 300a. A pair of resistors 311a and pad P21 (VHAC1), a pair of resistors 311b and pad P22 (VHAC2), and a pair of resistors 381 and pad P32 (VHDC) are respectively formed in the high-voltage regions 400X to 400Z.

[0332] In contrast, in the plan view of the first chip 300a, pads P23 to P25 and pad P33, resistors 312a to 315a, 312b to 315b and 382 to 385, NMOSFETs 316a, 316b and 386, PMOSFETs 317a, 317b and 387 and fuses 318a, 318b and 388 are formed in region A2 (i.e., the approximate right half of the region of the first chip 300a).

[0333] In the plan view of the first chip 300a, pads P23 to P25 and pad P33 are formed and arranged in the left-right direction of the first chip 300a, slightly upward from the middle in the vertical direction of the first chip 300a (i.e., on the line extending to the right from the boundary between the high-voltage regions 400Y and 400Z). Note that the pads should be arranged, for example, in the order of pad P33 (DCIN), pad P24 (ACIN2), pad P23 (ACIN1), and pad P25 (GND) from the left side of the paper. Furthermore, the distance between pads P23 and P25 should be greater than the distance between pads P23 and P24 or the distance between pads P24 and P33.

[0334] In the plan view of the first chip 300a, resistors 312a to 315a are formed closer to the lower side of the first chip 300a than pads P23 to P25 and pad P33, and are formed adjacent to the right side of the high voltage region 400X (more specifically, formed slightly upward from the middle in the vertical direction of the high voltage region 400X). Furthermore, in the left-right direction on the paper, in the plan view of the first chip 300a, resistors 312a to 315a are formed from a position on a line substantially the same to the left of pad P33 (DCIN) to a position on a line substantially the same to the left of pad P23 (ACIN1).

[0335] In the plan view of the first chip 300a, resistors 312b to 315b are formed at a position closer to the lower side of the first chip 300a than pads P23 to P25 and pad P33 (more specifically, formed between resistors 312b to 315a and pads P23 to P25 and P33), and are formed at a position adjacent to the right side of the high voltage region 400Y (more specifically, at a position close to the lower side of the high voltage region 400Y). Furthermore, in the left-right direction on the paper, similar to resistors 312b to 315a, in the plan view of the first chip 300a, resistors 312b to 315b are formed from a position on a line substantially the same to the left of pad P33 (DCIN) to a position on a line substantially the same to the left of pad P23 (ACIN1).

[0336] In the plan view of the first chip 300a, resistors 382 to 385 are formed at a position closer to the upper side of the first chip 300a than pads P23 to P25 and pad P33, and are formed at a position adjacent to the right side of the high voltage region 400Z (more specifically, formed at a position close to the upper side of the high voltage region 400Z). Furthermore, in the left-right direction on the paper, similar to resistors 312a to 315a and 312b to 315b, in the plan view of the first chip 300a, resistors 382 to 385 are formed from a position on a line substantially the same to the left of pad P33 (DCIN) to a position on a line substantially the same to the left of pad P23 (ACIN1).

[0337] Note that resistors 312a and 315a, resistors 312b and 315b, and resistors 382 and 385 each have multiple unit resistors, and their connection states (number of series connections and number of parallel connections) can be arbitrarily changed using fuses 318a, 318b, and 388.

[0338] In the plan view of the first chip 300a, NMOSFETs 316a, 316b, and 386 are formed and arranged in the vertical direction of the first chip 300a. Referring to the figure, NMOSFET 316a is formed below pad P25, and NMOSFET 316b is formed above pad P25. Furthermore, NMOSFET 386 is further formed above NMOSFET 316b (i.e., at the upper right corner of the first chip 300a).

[0339] In the plan view of the first chip 300a, PMOSFET 317a is formed at approximately the midpoint between pad P23 and the lower side of the first chip 300a. In contrast, in the plan view of the first chip 300a, PMOSFET 317b is formed between pad P33 and the high-voltage region 400Y. Furthermore, in the plan view of the first chip 300a, PMOSFET 387 is formed between pad P33 and the high-voltage region 400Z. Note that PMOSFETs 317b and 387 are formed and arranged in the vertical direction of the first chip 300a.

[0340] In the plan view of the first chip 300a, fuses 318a, 318b, and 388 are formed and arranged in the vertical direction of the first chip 300a. Referring to the figure, fuse 318a is formed between the PMOSFET 317a and the lower side of the first chip 300a, and fuse 318b is formed between pad P23 and PMOSFET 317a. Furthermore, fuse 388 is formed between pad P23 and the upper side of the first chip 300a. Note that each of fuses 318a, 318b, and 388 can be understood as a group of fuse elements comprising multiple fuse elements.

[0341] Note that polysilicon resistors with a withstand voltage of 100V or higher (e.g., 650V) are preferably used as resistors 311a, 311b, and 381 to which high voltages are applied. In particular, when integrating the above resistors, not only is a high withstand voltage required (in the lateral direction) through the path of the resistor, but also a high withstand voltage (in the vertical direction) between each resistor and the semiconductor substrate.

[0342] Therefore, in the first chip 300a that integrates AC monitoring unit 310 and DC monitoring unit 380, it is preferable to form three high-voltage regions 400X to 400Z with higher withstand voltage than other regions in the substrate thickness direction (in the vertical direction), and resistors 311a and 311b and resistor 381 are formed on the high-voltage regions 400X to 400Z respectively.

[0343] Note that for the three high-voltage regions 400X to 400Z mentioned above, lateral double-diffused MOSFET (LDMOSFET) regions with abundant high withstand voltage can be used. The structure of the LDMOSFET region is described in detail below.

[0344] <High Voltage Region (LDMOSFET Region)>

[0345] Figure 40 and Figure 41 These are, respectively, a longitudinal cross-sectional view and a top view showing a structural example of the first chip 300a (specifically, the area formed by the feedback resistor and its vicinity, located in the middle of the high-voltage regions 400X to 400Z). Note that... Figure 40 The longitudinal section view is shown exemplarily. Figure 41 The α1-α2 cross section.

[0346] The first chip 300a in this figure includes a p-type semiconductor substrate 410, and an LDMOSFET region serving as a high-voltage region 400 (corresponding to the aforementioned high-voltage regions 400X to 400Z) is formed on the p-type semiconductor substrate 410. More specifically, a low-concentration n-type semiconductor region 411 and a high-concentration p-type semiconductor region 412 surrounding the low-concentration n-type semiconductor region 411 are formed in the middle portion of the high-voltage region 400 on the p-type semiconductor substrate 410. Note that the withstand voltage in the thickness direction of the substrate in the high-voltage region 400 is increased by reducing the impurity concentration in the low-concentration n-type semiconductor region 411 or by increasing the thickness of the low-concentration n-type semiconductor region 411.

[0347] A high-concentration n-type semiconductor region 413 is formed within a low-concentration n-type semiconductor region 411, and a high-concentration n-type semiconductor region 414 is formed within a high-concentration p-type semiconductor region 412. These high-concentration n-type semiconductor regions 413 and 414 correspond to the drain region (D) and source region (S) of the LDMOSFET, respectively. Note that... Figure 41 As shown in the planar diagram, multiple concentric annular drain regions (D) and source regions (S) are alternately formed in the high-voltage region 400.

[0348] Additionally, a field oxide film 415 is formed on the outer surface layer of the low-concentration n-type semiconductor region 411, surrounding the high-concentration n-type semiconductor region 413. Furthermore, a gate oxide film 416 is formed on the surface layer of the p-type semiconductor substrate 410 to bridge the high-concentration n-type semiconductor region 414 and the field oxide film 415. Note that a gate region 417 made of polysilicon is formed on the gate oxide film 416.

[0349] Furthermore, a field plate 418 made of polycrystalline silicon is formed on the field oxide film 415 as a means of equalizing the electric field distribution (i.e., the spacing between equipotential lines) to prevent dielectric breakdown.

[0350] Furthermore, a low-concentration p-type semiconductor region 419 is formed directly below the field oxide film 415 as a means of forming parasitic capacitance between the field oxide film 415 and the low-concentration n-type semiconductor region 411. According to this structure, the withstand voltage in the thickness direction of the substrate can be increased corresponding to the voltage maintained by the parasitic capacitance.

[0351] Furthermore, a field oxide film 402 is formed on the surface layer of the middle portion of the low-concentration n-type semiconductor region 411, which is surrounded by a high-concentration n-type semiconductor region 413 (corresponding to the innermost drain region (D)). A feedback resistor 401 (i.e., resistors 311a, 311b, or 381) is formed on this field oxide film 402. Note that the feedback resistor 401 should be formed using the same polysilicon layer as the gate region 417 and the field plate 418.

[0352] Furthermore, in the example shown, the two ends of the feedback resistor 401 are connected to the first metal layer 1M via vias, and further, the first metal layer 1M is connected to the second metal layer 2M via vias. For example, pads 403 (i.e., pads P21, P22, or P32) should be formed on the second metal layer 2M. However, the number of metal layers is not limited to this. There may be only one layer, or there may be three or more layers.

[0353] Furthermore, such as Figure 41 As shown, the feedback resistor 401 is preferably formed by combining multiple unit resistors 401(1) to 401(m) (m≥2). For example, if the resistance value of a single unit resistor is 1MΩ, then ten unit resistors should be connected in series so that the feedback resistor 401 has a combined resistance of 10MΩ.

[0354] In this way, a high withstand voltage can be achieved between the feedback resistor 401 and the p-type semiconductor substrate 410 by using an LDMOSFET region (e.g., with a withstand voltage of 600V) as a high voltage region 400.

[0355] <Chip Layout (Second Chip)>

[0356] Figure 42 This is a diagram showing the layout of the second chip 300b. In the following description, for ease of description, the top, bottom, left, and right directions on the paper are defined as the top, bottom, left, and right directions in the plan view of the second chip 300b, in order to describe the positional relationship of the pads or circuit blocks.

[0357] Note that in this diagram, in addition to the references already mentioned above... Figure 37 In addition to the described pads P26 to P31 and pads P34 to P35, pads P41 to P49 for chip testing are newly shown. A brief description of pads P41 to P49 follows. Pads P41 (SCANIN), P42 (SCANMODE), P43 (SCANCLK), P44 (SCANRST), P45 (SCANEN), and P49 (SCANOUT) are the pad groups used for scan-through testing (test signal input pad, mode switch signal input pad, clock signal input pad, reset signal input pad, enable signal input pad, and test signal output pad). Pad P46 (TSD) is the temperature protection signal output pad. Pad P47 (VCLA) is the test voltage application pad for analog circuits. Pad P48 (VCLD) is the test voltage application pad for digital circuits.

[0358] In the plan view, the second chip 300b is cut into a vertical rectangular shape, with the right and left sides being longer than the top and bottom sides.

[0359] In the plan view of the second chip 300b, near the left side of the second chip 300b, pads P34 (DCIN), P27 (ACIN2), P26 (ACIN1), P28 (GND), P31 (ACOUT), and P49 (SCANOUT) are formed and arranged in the vertical direction on the paper in order from top to bottom.

[0360] In contrast, in the plan view of the second chip 300b, near the right side of the second chip 300b, pads P41 (SCANIN), P42 (SCANMODE), P43 (SCANCLK), P44 (SCANRST), P45 (SCANRST), P46 (TSD), P47 (VCLA), and P48 (VCLD) are formed and arranged sequentially from top to bottom on the paper.

[0361] Furthermore, in the plan view of the second chip 300b, near the lower side of the second chip 300b, pads P35 (DCOUT), P30 (GND), and P29 (VCC) are sequentially formed and arranged on the paper in the left-right direction from left to right.

[0362] Pads P26 and P27 are preferably placed close to each other. Preferably, the distance between pads P27 and P34 is greater than the distance between pads P26 and P27. Preferably, pad P28 (GND) is positioned between pads P26 (ACIN1) and P31 (ACOUT). Preferably, pad P30 (GND) is positioned between pads P29 (VCC) and P35 (DCOUT). Electrostatic discharge (ESD) protection elements (28VPD or EBZ) are formed directly below pads P26 to P28, P31, and P34 to P35. Test blocks (test circuits) are formed between pads P41 and P42, and between pads P43 and P44, respectively.

[0363] In the plan view of the second chip 300b, in the area near pads P26 to P28, pads P31 and P34 (i.e., the area occupying approximately 1 / 4 of the left side and approximately 3 / 4 of the top side of the second chip 300b, excluding the pad formation area), an ACDET block (corresponding to comparator unit 350) and an ACMON block (i.e., an RC filter set on the stage before the ZERODET block) are formed. Figure 37(not shown in the image), ZERODET block (corresponding to zero-crossing detection unit 320), ZERODET02V block (corresponding to input stop detection unit 370), and ACOUI block (corresponding to first output unit 340).

[0364] Each of the ACMON block, ZERODET block, and ZERODET02V block is formed in a longitudinal region from the position of the adjacent pad P26 to the position of the adjacent pad P31. In addition, the ACMON block, ZERODET block, and ZERODET02V block are formed and arranged in the left-right direction of the second chip 300b.

[0365] An ACDET block is formed in the region between the upper side of the second chip 300b and the upper sides of the ACMON block, the ZERODET block, and the ZERODET02V block. Note that the ACDET block has a larger area than each of the ACMON block, the ZERODET block, and the ZERODET02V block.

[0366] The ACOUT block is formed in a curved region extending from the underside of the ACMON block, the underside of the ZERODET block, and the underside of the ZERODET02V block to the left side of the second chip 300b. In other words, a portion of the ACOUT block is formed in the region between pad P31 and pad P49.

[0367] A DCOUT block is formed in the area near pad P35 (DCOUT) (i.e., in the lateral area surrounded by pads P35, P30, and P49). The DCOUT block has a larger area than the ACOUT block.

[0368] A LOGIC block (corresponding to the aforementioned logic unit 330) is formed in the upper right region of the second chip 300b (i.e., the region occupying approximately 3 / 4 of the right side and approximately 4 / 7 of the upper side of the second chip 300b, excluding the pad formation area). The LOGIC block has a larger area than any other block.

[0369] In the plan view of the second chip 300b, in the area where the aforementioned blocks (ACDET, ACMON, ZERODET, ZERODET02V, ACOUT, DCOUT, and LOGIC) are not formed (i.e., the area occupying approximately 3 / 4 of the right side and approximately 3 / 7 of the bottom side of the second chip 300b), a BGR block for generating a bandgap reference voltage, a VREFAMP block for generating an internal reference voltage based on the bandgap reference voltage, a VREFDET block for monitoring the internal reference voltage (corresponding to the undervoltage protection unit 360), an IREF block for generating an internal reference current, an OSC block for providing a clock signal to the LOGIC block, and a FUSE block for setting the operation of the LOGIC block are formed.

[0370] <Encapsulation Layout (Fifth Example)>

[0371] Figure 43 This is a fifth example diagram (XZ plan view) illustrating the package layout of a semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 in this diagram is based on... Figure 34 The encapsulation layout (third example), where Figure 39 The first chip 300 and Figure 42 The second chip 300b is installed on island 300c.

[0372] Specifically, in this figure, Figure 39 The first chip 300a is rotated 180° clockwise (or counterclockwise) and mounted in the upper right region of island 300c. Furthermore, in this figure, Figure 42 The second chip 300b is rotated 90° clockwise and installed in the lower left area of ​​island 300c.

[0373] Pad P21 (VHAC1) is connected to the distal side of pin 7 (VHAC1) via wire W21. Pad P22 (VHAC2) is connected to pin 6 (VHAC2) via wire W22. Pad P23 (ACIN1) is connected to pad P26 (ACIN1) via wire W23. Pad P24 (ACIN2) is connected to pad P27 (ACIN2) via wire W24. Pad P25 (GND) is connected to pad P28 (GND) via wire W25. Pad P33 (DCIN) is connected to pad P34 (DCIN) via wire W30. Pad P29 (VCC) is connected to the distal side of pin 4 (VCC) via wire W26. Pad P30 (GND) is connected to pin 3 (GND) via wire W27. Pad P31 (ACOUT) is connected to the distal side of pin 1 (ACOUT) via wire W28.

[0374] Note that in the semiconductor integrated circuit device 300 shown in this figure, DC voltage monitoring is not used; therefore, pads P32 (VHDC) and P35 (DCOUT) are not connected to any pins. In contrast, pads P33 (DCIN) and P34 (DCIN) are connected to each other via wire W30. Thus, similar to the above... Figure 37 The DC voltage monitoring function can be used by connecting pad P32 (VHDC) via wire W29 without using pin 5, and by connecting pad P35 (DCOUT) via wire W30 without using pin 2.

[0375] Furthermore, pads P23 to P25 and pad P33 of the first chip 300a, and pads P26 to P28 and pad P34 of the second chip 300b are arranged on the paper in a corresponding order along the left-right direction (X-axis direction). Therefore, the conductors W23 to W25 and W30 between the pads can be formed with minimal distance without crossing.

[0376] Furthermore, pads P21 to P22 and pad P32 of the first chip 300a are arranged on the paper in the vertical direction (Z-axis direction) corresponding to pin 7 (VHAC1 pin), pin 6 (VHAC2 pin), and pin 5 (i.e., VHDC pin when using the DC voltage monitoring function), respectively. Therefore, the wires W21 and W22 (and wire W29 when using the DC voltage monitoring function) between the pins and pads can be formed with minimal distance without crossing.

[0377] Similarly, pads P29 to P30 and P35 of the second chip 300b are arranged on the paper in the vertical (Z-axis direction) order of pin 4 (VCC pin), pin 3 (GND pin), and pin 2 (DCOUT pin when using the DC voltage monitoring function), respectively. Therefore, the wires W26 and W27 (and wire W29 when using the DC voltage monitoring function) between the pins and pads can be formed with minimal distance without crossing.

[0378] Note that after being packaged into the semiconductor integrated circuit device 300, pads P41 to P49 for chip testing are not used, therefore pads P41 to P49 are not connected to any pins.

[0379] Furthermore, regarding the frame area inside the package, each of pin 1 (ACOUT pin), pin 4 (VCC pin), pin 5 (NC pin), and pin 7 (VHAC1 pin) is larger than pin 2 (NC pin), pin 3 (GND pin), or pin 6 (VHAC2 pin).

[0380] In other words, regarding the X direction (i.e., the left-right direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) protrude more than pins 2 (NC pin) and 3 (GND pin). Similarly, pins 5 (NC pin) and 7 (VHAC1 pin) protrude more than pin 6 (VHAC2 pin).

[0381] Furthermore, regarding the Z direction (i.e., the up-down direction on the paper), pins 1 (ACOUT pin) and 4 (VCC pin) partially overlap with island 300c. Similarly, pins 5 (NC pin) and 7 (VHAC1 pin) partially overlap with island 300c.

[0382] In addition, the support frames 300e and 300f of the support island 300c are formed between pin 1 (ACOUT pin) and pin 7 (VHAC1 pin) and between pin 4 (VCC pin) and pin 5 (NC pin), respectively.

[0383] <Encapsulation Layout (Sixth Example)>

[0384] Figure 44 This is a sixth example (XZ plan view) illustrating the package layout of a semiconductor integrated circuit device 300. Compared to the fifth example described above (… Figure 43 Similarly, the semiconductor integrated circuit device 300 in this figure is based on Figure 36 The encapsulation layout (fourth example), where Figure 39 The first chip 300 and Figure 42 The second chip 300b is installed on island 300c.

[0385] Specifically, in this figure, Figure 39 The first chip 300a is rotated 180° clockwise (or counterclockwise) and installed in the upper left, right, or middle area of ​​island 300c (i.e., from...). Figure 43 The position in the center has been moved to the left and right center positions of island 300c. Furthermore, in this diagram, Figure 42 The second chip 300b is rotated 90° clockwise and installed in the lower left region of island 300c (i.e., from...). Figure 43 The position in the middle has been moved to the upper or lower middle position of island 300c.

[0386] Pad P21 (VHAC1) is connected to pin 11 (VHAC1) via wire W21. Pad P22 (VHAC2) is connected to pin 10 (VHAC2) via wire W22. Pad P32 (VHDC) is connected to pin 9 (VHDC pin) via wire W29. Pad P23 (ACIN1) is connected to pad P26 (ACIN1) via wire W23. Pad P24 (ACIN2) is connected to pad P27 (ACIN2) via wire W24. Pad P25 (GND) is connected to pad P28 (GND) via wire W25. Pad P33 (DCIN) is connected to pad P34 (DCIN) via wire W30. Pad P29 (VCC) is connected to the distal side of pin 7 (VCC) via wire W26. Pad P30 (GND) is connected to pin 5 (GND) via wire W27. Pad P35 (DCOUT) is connected to pin 4 (DCOUT pin) via wire W31. Pad P31 (ACOUT) is connected to the far side of pin 3 (ACOUT) via wire W28.

[0387] Note that pads P23 to P25 and pad P33 of the first chip 300a, and pads P26 to P28 and pad P34 of the second chip 300b are arranged on the paper in a corresponding order along the left-right direction (X-axis direction). Therefore, the traces W23 to W25 and W30 between the pads can be formed with minimal distance without crossing. This is consistent with the above reference. Figure 43 The description is the same.

[0388] Furthermore, the pads P21 to P22 and P32 of the first chip 300a are arranged on the paper in the vertical direction (Z-axis direction) in the order corresponding to pin 11 (VHAC1 pin), pin 10 (VHAC2 pin), and pin 9 (VHDC pin), respectively. Therefore, the wires W21, W22, and W29 between the pins and the pads can be formed with minimal distance and without crossing.

[0389] Similarly, pads P29 to P30 and P35 of the second chip 300b are arranged on the paper in the vertical direction (Z-axis direction) in the order corresponding to pin 7 (VCC pin), pin 5 (GND pin), and pin 4 (DCOUT pin), respectively. Therefore, the wires W26, W27, and W31 between the pins and pads can be formed with minimal distance without crossing.

[0390] Note that after being packaged into the semiconductor integrated circuit device 300, pads P41 to P49, which are used for chip testing, are not used; therefore, pads P41 to P49 are not connected to any pins. This is also consistent with the above reference. Figure 43 The description is the same.

[0391] Furthermore, for the frame area inside the package, each of pin 2 (NC pin) and pin 6 (NC pin) is larger than pin 3 (ACOUT pin), pin 4 (DCOUT pin), or pin 5 (GND pin).

[0392] In other words, regarding the X direction (i.e., the left and right direction on the paper), pins 2 (NC pin) and 6 (NC pin) have portions that protrude beyond pins 3 (ACOUT pin), 4 (DCOUT pin), and 5 (GND pin).

[0393] Furthermore, regarding the Z direction (i.e., the vertical direction on the paper), pins 2 (NC pin) and 6 (NC pin) do not overlap with island 100c. Similarly, pins 1 (NC pin), 7 (VCC pin), 8 (NC pin), and 11 (VHAC1 pin) also do not overlap with island 100c.

[0394] In addition, the support frames 300e and 300f of the support island 300c are formed between pin 1 (NC pin) and pin 11 (VHAC1 pin) and between pin 7 (VCC pin) and pin 8 (NC pin), respectively.

[0395] <Pin Assignment>

[0396] Figure 45 This shows the use of a seven-pin package ( Figure 43 This is a plan view of the pin assignment of the semiconductor integrated circuit device 300. On the left side of the package, pins 1 (ACOUT), 2 (NC), 3 (GND), and 4 (VCC) are led out from top to bottom on the paper. In contrast, on the right side of the package, pins 5 (NC), 6 (VHAC2), and 7 (VHAC1) are led out from bottom to top on the paper.

[0397] Note that, preferably, the terminal distance w11 between each high-voltage pin 7 (VHAC1) and pin 6 (VHAC2) is set to be greater than the terminal distance w12 between adjacent pins 1 to 4 and the terminal distance w13 between pin 5 and pin 6. For example, in the example shown, the external terminal initially positioned between pin 6 and pin 7 (i.e., the pin opposite pin 2) is removed, thus increasing the terminal distance w11 between pin 6 and pin 7.

[0398] Furthermore, the lengths of pins 1 to 4 extending from the left side of the package are not necessarily the same as the lengths of pins 5 to 7 extending from the right side of the package. For example, as shown in the figure, pins 5 to 7 can be extended to be longer than pins 1 to 4.

[0399] Figure 46 This shows the use of an eleven-pin package ( Figure 44 This is a plan view of the pin assignment of a semiconductor integrated circuit device 300. In this example, on the left side of the package, pins 1 (NC), 2 (NC), 3 (ACOUT), 4 (DCOUT), 5 (GND), 6 (NC), and 7 (VCC) are led out sequentially from top to bottom on the paper. In contrast, on the right side of the package, pins 8 (NC pin), 9 (VHDC), 10 (VHAC2), and 11 (VHAC1) are led out sequentially from bottom to top on the paper.

[0400] Note that, preferably, the terminal distance w21 between each high-voltage pin 11 (VHAC1) and pin 10 (VHAC2), the terminal distance w22 between pin 10 (VHAC2) and pin 9 (VHDC), and the terminal distance w23 between pin 9 (VHDC) and pin 8 (NC) are set to be greater than the terminal distance w24 between adjacent pins 1 to 7. For example, in the example shown, the external terminals (i.e., the pins opposite to pins 2, 4, and 6, respectively) initially located between pins 8 and 9, between pins 9 and 10, and between pins 10 and 11 are removed, thus increasing the terminal distance w23 between pins 8 and 9, the terminal distance w22 between pins 9 and 10, and the terminal distance w21 between pins 10 and 11.

[0401] Furthermore, the lengths of pins 1 to 7 extending from the left side of the package are not necessarily the same as the lengths of pins 8 to 11 extending from the right side of the package. For example, as shown in the figure, pins 8 to 11 can be extended to be shorter than pins 1 to 7.

[0402] Furthermore, preferably, each of pins 1 to 11 is formed to be thinner at the proximal end.

[0403] <Input Offset and Signal Delay>

[0404] Next, refer to Figures 47 to 49 The input offset and signal delay in the zero detection unit 320 have been discussed. Figures 47 to 49 This is a diagram illustrating the operation of generating the comparison signal SB in the zero-crossing detection unit 320, where the AC monitoring signals SA1 (solid line) and SA2 (dashed line) and the comparison signal SB are shown sequentially from top to bottom on the paper.

[0405] Notice, Figures 47 to 49 The behavior is shown under the first condition (no input offset and no signal distortion), the second condition (no input offset and signal distortion), and the third condition (input offset and signal distortion).

[0406] like Figure 47 As shown, in applications where almost no distortion occurs in the AC monitoring signals SA1 and SA2 (e.g., a dryer where the motor is driven by a small current), almost no jitter occurs in the comparison signal SB even if the zero-crossing detection unit 320 has no input offset. Therefore, the zero-crossing detection unit 320 has no signal delay, and the logic level of the comparison signal SB switches without delay whenever the AC monitoring signals SA1 and SA2 cross each other.

[0407] In comparison, such as Figure 48As shown, in applications where distortion is prone to occur in AC monitoring signals SA1 and SA2 (e.g., washing machines with motors driven by high current), jitter may occur in the comparison signal SB near the zero-crossing timing if the zero-crossing detection unit 320 has no input offset.

[0408] Note that, as Figure 49 As shown, if the zero-crossing detection unit 320 has an input offset (e.g., an input offset SA1_ofs that shifts the AC monitoring signal SA1 to the positive side), jitter in the comparison signal SB can be avoided even if distortion occurs in the AC monitoring signals SA1 and SA2. However, if the zero-crossing detection unit 320 has an input offset, the logic switching timing of the comparison signal SB (and therefore the detection result of the zero-crossing timing) is delayed by a delay time Td.

[0409] In particular, it is known that the delay time Td depends on the monitoring target voltage V11 (and therefore the AC voltage V0) applied to the VHAC1 pin, and may interfere with the operation of the application. In the following description, a novel implementation to address this issue is proposed.

[0410] <Semiconductor Integrated Circuit Device (Seventh Embodiment)>

[0411] Figure 50 This is a diagram illustrating a seventh embodiment of the semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 of this embodiment is based on the diagram described above. Figure 37 (that is, the fifth implementation method) Figure 22 (Including DC monitoring functionality and an 11-pin package), and also includes a delay adjustment unit 510 and a control unit 520. Therefore, the above-described structural components are composed of... Figure 37 The same numbers or symbols are used in the description, so repeated descriptions are omitted. The following description mainly focuses on the characteristic features of this embodiment.

[0412] The delay adjustment unit 510 is located at the stage after the logic unit 330. It adjusts the delay time Td of the zero-crossing detection signal SC (referred to as the zero-crossing delay time Td in the following description) according to the delay adjustment amount Td_adj indicated by the control unit 520.

[0413] The control unit 520 sets the delay adjustment amount Td_adj based on multiple comparison signals SD (i.e., monitoring the peak value of the target voltage V11, and therefore a logic signal reflecting the peak value of the AC voltage V0) output from the comparison unit 350. Furthermore, the control unit 520 also has the function of switching the input offset SA1_ofs of the zero-crossing detection unit 320 based on the multiple comparison signals SD.

[0414] Figure 51FIG. 0 is a diagram showing a process of suppressing a change in the zero-crossing delay time Td by the delay adjustment unit 510 and the control unit 520. Herein, the zero-crossing delay time Td, the delay adjustment amount Td_adj, and the input offset SA1_ofs are shown in order from top to bottom on the paper.

[0415] Note that the horizontal axis in this figure represents the peak value of the terminal voltage VHAC1 (i.e., the peak value of the monitored target voltage V11 applied to the VHAC1 pin, and thus corresponding to the peak value of the AC voltage V0), and for the threshold voltages VthH, VthM, and VthL to be compared therewith, VthH > VthM > VthL holds.

[0416] Furthermore, regarding the zero-crossing delay time Td, the solid line L1 shows the behavior in the case where the switching control of the delay adjustment amount Td_adj and the input offset SA1_ofs is performed. In comparison, the dashed line L2 shows the behavior in the case where the switching control of the delay adjustment amount Td_adj and the input offset SA1_ofs is not performed (in the case where Td_adj = 0 and SA1_ofs = +OFS always holds). Furthermore, the dotted-dashed line L3 shows the behavior in the case where no input offset SA1_ofs is given (in the case where Td_adj = 0 and SA1_ofs = 0 always holds).

[0417] In the case where the switching control of the delay adjustment amount Td_adj and the input offset SA1_ofs is not performed, as shown by the dashed line L2, as the terminal voltage VHAC1 decreases, the zero-crossing delay time Td increases and deviates from the predetermined target zero-crossing delay time Td_target.

[0418] In comparison, in the case where the switching control of the delay adjustment amount Td_adj and the input offset SA1_ofs is performed, as shown by the solid line L1, the zero-crossing delay time Td is maintained at the predetermined target zero-crossing delay time Td_target (or a value close to the predetermined target zero-crossing delay time Td_target).

[0419] Specifically referring to this figure, for example, in the voltage range (I) where VthH < VHAC1 holds, Td_adj = 0 (no delay adjustment) is set, and SA1_ofs = +OFS (with an input offset). In this voltage range (I), the zero-crossing delay time Td is not adjusted, so the solid line L1 exhibits the same behavior as the dashed line L2. In other words, as the terminal voltage VHAC1 decreases, the zero-crossing delay time Td increases and deviates from the target zero-crossing delay time Td_target. However, in the voltage range (I), the interval from the target zero-crossing delay time Td_target is not very large, so there is no special failure.

[0420] In contrast, in the voltage range (II) where VthM < VHAC1 < VthH holds, Td_adj = -ADJ1 (small delay adjustment) and SA1_ofs = +OFS (with input offset) are set. In other words, the zero-crossing delay time Td (solid line L1) after delay adjustment is shown as Td = Td0 - ADJ1, where Td0 represents the zero-crossing delay time (dashed line L2) without delay adjustment.

[0421] In addition, within the voltage range (III) where VthL < VHAC1 < VthM holds, Td_adj = -ADJ2 (larger delay adjustment) and SA1_ofs = +OFS (with input offset) are set. In other words, the zero-crossing delay time Td (solid line L1) after delay adjustment is shown as Td = Td0 - ADJ2, where ADJ2 > ADJ1 holds.

[0422] Of course, the zero-crossing delay time Td (solid line L1) after delay adjustment also varies according to the terminal voltage VHAC1, similar to the zero-crossing delay time Td0 (dashed line L2) without delay adjustment. However, since only the delay adjustment amount Td_adj is shifted to the negative side, the interval from the target zero-crossing delay time Td_target can be controlled to be smaller.

[0423] In addition, within the voltage range (IV) where VHAC1 < VthL holds, Td_adj = 0 (no delay adjustment) and SA1_ofs = 0 (no input offset) are set. Thus, in the voltage range (IV) where the interval from the target zero-crossing delay time Td_target cannot be controlled within the desired range even if delay adjustment is performed, the input offset SA1_ofs is stopped from being given. As a result, no signal delay occurs in the zero-crossing detection unit 320, and thus the zero-crossing delay time Td does not deviate from the target zero-crossing delay time Td_target.

[0424] Note that in applications where almost no distortion occurs in the AC monitoring signals SA1 and SA2, regardless of the peak value of the terminal voltage VHAC1, both the delay adjustment amount Td_adj and the input offset SA1_ofs should be fixed at zero, and the zero-crossing delay time Td should be maintained at the target zero-crossing delay time Td_target, as shown by the dotted line L3.

[0425] <Semiconductor Integrated Circuit Device (Eighth Embodiment)>

[0426] Figure 52 is a diagram showing the eighth embodiment of the semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 of this embodiment is based on the seventh embodiment ( Figure 50 ), where pin 6 is used as the delay setting terminal DSET. Therefore, the above structural elements are composed of those Figure 50 The same numbers or symbols in the text indicate the same components, and thus repeated descriptions are omitted. In the following description, the characteristic parts of this embodiment are mainly described.

[0427] Inside the semiconductor integrated circuit device 300, an internal resistor 531 (with a resistance value R1) is connected between the input terminal of the internal reference voltage VREF and the delay setting terminal DSET. In addition, outside the semiconductor integrated circuit device 300, an external resistor 532 (with a resistance value R2) is connected between the delay setting terminal DSET and the ground terminal. Therefore, the terminal voltage VDSET (=α×VREF) obtained by dividing the internal reference voltage VREF using a predetermined voltage division ratio α(=R2 / (R1 + R2)) appears at the delay setting terminal DSET.

[0428] The control unit 520 has a function of setting the target zero - crossing delay time Td_target to an arbitrary value according to the terminal voltage VDSET (corresponding to the delay setting signal).

[0429] Figure 53 is a diagram showing an example of arbitrarily setting the target zero - crossing delay time Td_target. Note that the horizontal axis in this diagram represents the terminal voltage VDSET, and for the threshold voltages VH, VM, and VL to be compared, VREF > VH > VM > VL holds (for example, VREF = 3.0V, VH = 2.5V, VM = 1.0V, and VL = 0.3V).

[0430] Specifically referring to this diagram, in the voltage range (i) where VH < VDSET holds, Td_target = 0 is set. Note that in order to control the terminal voltage VDSET within the voltage range (i), for example, the delay setting terminal DSET should be open - circuited (VDSET≈3.0V).

[0431] In addition, in the voltage range (ii) where VM < VDSET < VH holds, Td_target = - 2X (for example, X = 200 (μs)) is set. Note that in order to control the terminal voltage VDSET within the voltage range (ii), for example, an external resistor 532 of 330kΩ should be connected to an internal resistor 531 of 280kΩ (VDSET≈1.6V).

[0432] In addition, in the voltage range (iii) where VL < VDSET < VM holds, Td_target = - 1X is set. Note that in order to control the terminal voltage VDSET within the voltage range (iii), for example, an external resistor 532 of 68kΩ should be connected to an internal resistor 531 of 280kΩ (VDSET≈0.6V).

[0433] In addition, within the voltage range (iv) where VDSET < VL holds, set Td_target = +1X. Note that in order to control the terminal voltage VDSET within the voltage range (iv), for example, the delay terminal DSET should be shorted to GND (VDSET ≈ 0V).

[0434] Here, in the logic unit 330, as described above, the cross timing between the AC monitoring signals SA1 and SA2 in the previous cycle is detected, and the timing control of the zero-crossing detection signal SC in the next cycle is performed (see Figure 26 etc.). Therefore, as described above, the target zero-crossing delay time Td_target can also be set to a negative value (<0).

[0435] Note that the function of arbitrarily setting the target zero-crossing delay time Td_target (eighth embodiment) does not have to be combined with the function of suppressing the change in the zero-crossing delay time Td (seventh embodiment), but each of them can be independently introduced.

[0436] In addition, this embodiment shows an example where the target zero-crossing delay time Td_target is switched in four steps according to the terminal voltage VDSET, but the number of switching steps is arbitrary.

[0437] <ACOUT Output Waveform>

[0438] Next, check the output waveform of the ACOUT signal S1. The output form of the ACOUT signal S1 can be a rectangular type, where the logic level is alternately switched at each zero-crossing timing of the AC voltage V0 ( Figure 54 ), or it can be an edge type where a trigger pulse with a predetermined pulse width tw is generated at each zero-crossing timing of the AC voltage V0 ( Figure 55 ).

[0439] <Semiconductor Integrated Circuit Device (Ninth Embodiment)>

[0440] Figure 56 is a diagram showing the ninth embodiment of the semiconductor integrated circuit device 300. The semiconductor integrated circuit device 300 of this embodiment is based on the above-mentioned Figure 37 (i.e., the fifth embodiment ( Figure 22 ) plus the DC monitoring function plus the eleven-pin package), where pin 2 is used as the output mode setting terminal MODE. Therefore, the above structural elements are represented by the same numbers or symbols as in Figure 37 , so the repeated description is omitted. In the following description, the characteristic parts of this embodiment are mainly described.

[0441] Logic unit 330 has an input signal that sets the output mode of ACOUT signal S1 to a rectangular type based on the input signal of the output mode setting terminal MODE. Figure 54 ) and edge type ( Figure 55 One of its functions. Note that the input signal to the output mode setting terminal MODE can be either an analog signal or a digital signal.

[0442] Furthermore, the seventh implementation method ( Figure 50 ), Eighth implementation method ( Figure 52 ) and the ninth embodiment ( Figure 56 ) shows based on Figure 37 This is an example, but it can also be based on other implementations. For example, when using the seventh to ninth implementations, whether DC monitoring functionality is provided, the number of package pins, etc., are not important.

[0443] <Summary of the Invention>

[0444] In the following description, various embodiments disclosed in this specification are described in block form.

[0445] For example, the zero-crossing detection circuit disclosed in this specification includes: a peak detection unit for detecting the peak value of a monitoring target signal input from an AC signal input terminal via a diode, thereby generating a peak detection signal; and a zero-crossing detection unit for estimating the zero-crossing of the AC signal based on the peak detection signal, thereby generating a zero-crossing detection signal.

[0446] Note that the zero-crossing detection circuit with the above structure preferably further includes a monitoring unit, which is used to adjust the monitoring target signal to be suitable for input to the peak detection unit.

[0447] Furthermore, in the zero-crossing detection circuit having the above structure, the zero-crossing detection unit preferably counts the period of the peak detection signal and uses its count value to estimate the zero-crossing of the AC signal.

[0448] Furthermore, the zero-crossing detection circuit having the above structure preferably further includes: a comparison unit for comparing the monitored target signal with a plurality of thresholds to generate a plurality of comparison signals; and a waveform determination unit for detecting whether both a rising edge and a falling edge have occurred in at least one of the comparison signals during one period of the zero-crossing detection signal, thereby generating a waveform determination signal.

[0449] Furthermore, in the zero-crossing detection circuit having the above structure, when the waveform determination signal is an abnormal determination logic level, the zero-crossing detection unit preferably stops generating or outputting the zero-crossing detection signal.

[0450] Furthermore, in the zero-crossing detection circuit having the above structure, if the logic level of the peak detection signal is switched, and the logic level after the switch is not maintained for a predetermined period of time, the zero-crossing detection unit preferably ignores the switching of the logic level.

[0451] Furthermore, for example, the zero-crossing detection circuit disclosed in this specification includes: a zero-crossing detection unit for comparing a first monitoring target signal and a second monitoring target signal input from a first node and a second node through which an AC signal is applied from the middle via a diode, thereby generating a first comparison signal; and a logic unit for estimating the zero-crossing of the AC signal based on the first comparison signal, thereby generating the zero-crossing detection signal.

[0452] Note that the zero-crossing detection circuit having the above structure preferably further includes a monitoring unit, which is used to adjust the first monitoring target signal and the second monitoring target signal to be adapted to be input to the zero-crossing detection unit.

[0453] Furthermore, in the zero-crossing detection circuit having the above structure, the logic unit preferably counts the period of the first comparison signal and uses its count value to estimate the zero-crossing of the AC signal.

[0454] Furthermore, in the zero-crossing detection circuit having the above structure, the zero-crossing detection unit preferably compares the first monitoring target signal with a predetermined threshold to generate a second comparison signal, and the logic unit preferably counts the period of the second comparison signal instead of the first comparison signal when the first monitoring target signal is lower than the threshold, and uses its count value to estimate the zero-crossing of the AC signal.

[0455] Furthermore, in the zero-crossing detection circuit having the above structure, if the logic level of the second comparison signal is switched, and the logic level after the switch is not maintained for a predetermined period of time, the logic unit preferably ignores the switching of the logic level.

[0456] Furthermore, the zero-crossing detection circuit having the above structure preferably further includes: a control unit for setting a delay adjustment amount based on the peak value of the AC signal; and a delay adjustment unit for adjusting the delay time of the zero-crossing detection signal according to the delay adjustment amount.

[0457] Furthermore, in the zero-crossing detection circuit having the above structure, preferably, the lower the peak value of the AC signal, the more the control unit increases the delay adjustment amount.

[0458] Furthermore, in the zero-crossing detection circuit having the above structure, the control unit preferably switches the input offset of the zero-crossing detection unit based on the peak value of the AC signal.

[0459] Furthermore, in the zero-crossing detection circuit having the above structure, when the peak value of the AC signal is lower than a predetermined threshold, the control unit preferably sets both the delay adjustment amount and the input offset to zero.

[0460] Furthermore, the zero-crossing detection circuit having the above structure preferably further includes a comparison unit for comparing the first monitoring target signal or its voltage divider signal with a plurality of thresholds to generate a plurality of comparison signals, and the control unit preferably receives inputs of the plurality of comparison signals, wherein the inputs of the plurality of comparison signals have logic values ​​reflecting the peak value of the AC signal.

[0461] Furthermore, in the zero-crossing detection circuit having the above structure, the control unit preferably has the function of setting both the delay adjustment amount and the input offset to zero without depending on the peak value of the AC signal.

[0462] Furthermore, the zero-crossing detection circuit having the above structure preferably also includes a control unit, which is used to set the delay time of the zero-crossing detection signal according to the delay setting signal.

[0463] Furthermore, in the zero-crossing detection circuit having the above structure, the delay setting signal is an analog signal having a voltage value corresponding to the resistance value of an external resistor, and the control unit preferably switches the delay time gradually based on the comparison result between the analog signal and a threshold.

[0464] Furthermore, in the zero-crossing detection circuit having the above structure, the zero-crossing detection signal is preferably a rectangular type in which the logic level is alternately switched at each zero-crossing timing of the AC signal, or an edge type in which a trigger pulse with a predetermined pulse width is generated at each zero-crossing timing of the AC signal.

[0465] Furthermore, in the zero-crossing detection circuit having the above structure, the logic unit preferably switches the output form of the zero-crossing detection signal to one of the rectangular type and the edge type according to the output mode setting signal.

[0466] Furthermore, for example, the zero-crossing detection circuit disclosed in this specification includes: a logic unit configured to estimate the zero-crossing of the AC signal based on at least one of a first monitoring target signal and a second monitoring target signal input from a first node and a second node through a diode, respectively, thereby generating a zero-crossing detection signal; and an input stop detection unit configured to compare the first monitoring target signal and the second monitoring target signal after giving an offset to one of them to generate an input stop detection signal, wherein the logic unit fixes the logic level of the zero-crossing detection signal according to the input stop detection signal.

[0467] Note that in the zero-crossing detection circuit with the above structure, if the logic level of the input stop detection signal is switched, and the logic level after the switch is not maintained for a predetermined period of time, the logic unit preferably ignores the switching of the logic level.

[0468] Furthermore, the zero-crossing detection circuit having the above structure preferably further includes a zero-crossing detection unit, which is used to compare the first monitoring target signal with the second monitoring target signal to generate a comparison signal, and the logic unit preferably estimates the zero-crossing of the AC signal based on the comparison signal.

[0469] Furthermore, the zero-crossing detection circuit having the above structure preferably also includes a monitoring unit, which is used to adjust the first monitoring target signal and the second monitoring target signal to be adapted to be input to the zero-crossing detection unit.

[0470] Furthermore, in the zero-crossing detection circuit having the above structure, the logic unit preferably counts the period of the comparison signal and uses its count value to estimate the zero-crossing of the AC signal.

[0471] Furthermore, for example, the semiconductor integrated circuit device disclosed in this specification includes the integration of at least a portion of the circuit elements constituting the zero-crossing detection circuit having the above-described structure.

[0472] Note that in the semiconductor integrated circuit device having the above structure, preferably, the distance between the first external terminal receiving the input of the monitoring target signal and the second external terminal adjacent to the first external terminal should be greater than the distance between the other external terminals.

[0473] Furthermore, the semiconductor integrated circuit device having the above structure preferably also includes an integrated AC / DC converter for generating a first DC voltage based on the AC voltage as the AC signal input.

[0474] Furthermore, the semiconductor integrated circuit device having the above structure preferably further includes an integrated DC / DC converter for generating a second DC voltage based on the first DC voltage.

[0475] Furthermore, the semiconductor integrated circuit device having the above structure is preferably composed of a first chip and a second chip, wherein the first chip integrates a monitoring unit for adjusting the monitoring target signal to be suitable for input to the peak detection unit, and the second chip integrates the peak detection unit and the zero-crossing detection unit, and the first chip and the second chip are preferably sealed with molding resin.

[0476] Furthermore, the electronic device disclosed in this specification includes: a rectifier unit for performing normal rectification or voltage multiplier rectification of an AC voltage to generate a rectified voltage; a zero-crossing detection circuit for detecting zero crossings of the AC voltage; and a microcomputer for controlling a load based on the detection result of the zero-crossing detection circuit, wherein the zero-crossing detection circuit is a zero-crossing detection circuit having the above-described structure, or a zero-crossing detection circuit constructed using a semiconductor integrated circuit device having the above-described structure.

[0477] Note that in the electronic device having the above structure, the rectifier unit preferably includes a first capacitor and a second capacitor connected in series between the output terminal of the rectified voltage and the ground terminal, and the connection node of the first capacitor and the second capacitor is preferably connected to the second node from which the second monitoring target signal is drawn.

[0478] Note that in the electronic device having the above structure, the zero-crossing detection circuit preferably operates relative to the common ground voltage of the microcomputer.

[0479] Furthermore, in the electronic device having the above structure, the load is preferably a motor or a three-terminal bidirectional thyristor switch element.

[0480] <Note A>

[0481] Add the following information about the above. Figures 39 to 42 The annotation. In the plan view, the first chip, which integrates the monitoring unit for adjusting the first monitoring target signal and the second monitoring target signal to be adapted to be input to the zero-crossing detection unit, is preferably cut into a rectangular shape with substantially equal ratios between the short and long sides.

[0482] Note that in the first chip, a high-voltage region with a higher withstand voltage than other regions is preferably formed in the substrate thickness direction (in the vertical direction), and a first pad and a first feedback resistor connected to the first pad are formed above the high-voltage region, and the first monitoring target signal and the second monitoring target signal are input to the first pad.

[0483] Furthermore, preferably, a plurality of high-voltage regions are formed along a first side of the first chip in a plan view of the first chip. Furthermore, preferably, a plurality of high-voltage regions (e.g., a first high-voltage region, a second high-voltage region, and a third high-voltage region) are formed concentrated in a first region (e.g., half of the first chip) of the first chip in a plan view of the first chip.

[0484] In contrast, in the plan view of the first chip, preferably in the second region of the first chip (e.g., the remaining half region of the first chip), a second pad for outputting a signal from the monitoring unit to the zero-crossing detection unit, a second feedback resistor connected to the second pad, a third pad connected to the ground terminal, an electrostatic protection element for protecting the pad, and a fuse for adjusting the resistance value of the second feedback resistor are formed.

[0485] Note that in the plan view of the first chip, a plurality of second pads and third pads are preferably formed along a second side perpendicular to the first side of the first chip. Specifically, in the plan view of the first chip, the second pads and third pads are preferably formed and arranged along the second side, and the second pads and third pads are closer to the second side than the middle of the first side. Furthermore, it is preferable that the pad distance between the second pads and the third pads is set to be greater than the pad distance between the plurality of second pads.

[0486] Furthermore, in the plan view of the first chip, the second feedback resistor is preferably formed at a position adjacent to the high-voltage region.

[0487] Furthermore, it is preferable to use a polycrystalline silicon resistor with a withstand voltage of 100V or higher (e.g., 650V) as the first feedback resistor to which the high voltage is applied.

[0488] Furthermore, preferably, the high-voltage region is an LDMOSFET region.

[0489] Furthermore, in the LDMOSFET region of the first chip plan view, preferably, a plurality of concentric annular drain regions and source regions are alternately formed, and the first feedback resistor is formed on a field oxide film surrounded by the innermost drain region.

[0490] Furthermore, each of the first feedback resistor and the second feedback resistor is formed as a combination of multiple unit resistors.

[0491] In comparison, the second chip, in which the zero-crossing detection unit is integrated, is preferably cut into a rectangular shape in a planar view.

[0492] Note that in the plan view of the second chip, the plurality of pads connected to the first chip are preferably formed and arranged close to the first side of the second chip.

[0493] In contrast, in the plan view of the second chip, a plurality of pads not connected to the first chip are preferably formed and arranged close to a second side opposite to the first side of the second chip.

[0494] Furthermore, preferably, the first pad for inputting the voltage divider signal of the first monitoring target signal and the second pad for inputting the voltage divider signal of the second monitoring target signal are arranged adjacent to each other.

[0495] Furthermore, preferably, the distance between the third pad and the second pad of the voltage divider signal of the third monitoring target signal is greater than the distance between the first pad and the second pad.

[0496] Furthermore, preferably, a fifth pad connected to the ground potential is provided between the first pad and the fourth pad that outputs the ACOUT signal.

[0497] Furthermore, preferably, an eighth pad connected to the ground potential is provided between the sixth pad that outputs the DCOUT signal and the seventh pad that is connected to the power supply potential.

[0498] Furthermore, it is preferable to form an electrostatic protection element directly below each of the first to sixth pads.

[0499] Furthermore, it is preferable to form a test circuit between the first test pad and the second test pad.

[0500] Furthermore, in the plan view of the second chip, the comparison unit, the RC filter, the zero-crossing detection unit, the input stop detection unit, and the first output unit are preferably formed in the region close to the first to fifth pads.

[0501] Furthermore, in the plan view of the second chip, the second output unit is preferably formed in the area close to the sixth pad.

[0502] <Note B>

[0503] Next, add the following information about the above. Figure 43 and Figure 44The annotations are as follows. Each pad in the first and second chips is preferably connected to the corresponding pin via a wire.

[0504] Note that the DCIN pins of the first chip and the second chip are preferably connected to each other, regardless of whether the DC voltage monitoring function is used.

[0505] Furthermore, preferably, the plurality of output pads and ground pads of the first chip, which are respectively connected to each other, and the plurality of input pads and ground pads of the second chip, should be arranged in a corresponding order.

[0506] <Note C>

[0507] Next, add the following information about the above. Figure 45 and Figure 46 The annotation indicates that, as a package for the semiconductor integrated circuit device, a seven-pin or eleven-pin package is preferably used.

[0508] Note that it is preferable to bring out the pins that are not subjected to high voltage from the first side of the package and bring out the pins that are subjected to high voltage from the second side of the package.

[0509] Furthermore, preferably, the distance between terminals of pins to which high voltage is applied should be greater than the distance between terminals of pins to which no high voltage is applied.

[0510] Furthermore, the length of the pins extending from the first side of the package is not necessarily the same as the length of the pins extending from the second side of the package. For example, the pins extending from the second side can be longer than the pins extending from the first side. Conversely, the pins from the second side can be shorter than the pins from the first side.

[0511] In addition, each pin can be formed thinner near the end.

[0512] <Other variations>

[0513] Note that the above embodiment illustrates an example of controlling the motor drive based on the detection result of the zero-crossing detection circuit, but the application of the zero-crossing detection circuit is not limited to this. It can also be appropriately applied to power supply devices that detect the zero crossing of AC voltage to control the drive of three-terminal bidirectional thyristor switching elements, etc.

[0514] In this way, in addition to the embodiments described above, various technical features disclosed in this specification can be modified in various ways within the scope of the invention without departing from its spirit.

[0515] For example, bipolar transistors and MOS field-effect transistors can be interchanged, and the logic levels of various signals can be arbitrarily reversed. In other words, the above embodiments are merely examples of each aspect and should not be construed as limiting. The technical scope of the present invention is not limited to the embodiments and should be understood to include all variations within the meaning and scope of the claims.

[0516] Industrial applicability

[0517] The zero-crossing detection circuit disclosed in this specification can be used to control, for example, the drive of a motor or a three-terminal bidirectional thyristor switching element.

[0518] Explanation of symbols

[0519] 10 Electronic devices

[0520] 11 Filters

[0521] 12 rectifier units

[0522] 12a to 12d diodes

[0523] 12e to 12g capacitors

[0524] 13 AC / DC converters

[0525] 13a and 13b resistors

[0526] 13C error amplifier

[0527] 13D comparator

[0528] 13e RS trigger

[0529] 13F level shifter

[0530] 13g NMOSFET

[0531] 13h coil

[0532] 13i diode

[0533] 14 DC / DC converters

[0534] 15 Microcomputers

[0535] 16 drives

[0536] 17 Electric motor

[0537] 18 Zero-crossing detection circuit

[0538] 19 Input Reactor

[0539] 20 Relay Switch

[0540] 100 Semiconductor Integrated Circuit Devices (Zero-crossing ICs)

[0541] 100a First Chip

[0542] 100b Second Chip

[0543] 100c Island

[0544] 100d molding resin

[0545] 100e and 100f support frames

[0546] 110 AC monitoring unit

[0547] 111 to 115 resistors

[0548] 116 NMOSFET

[0549] 117 PMOSFET

[0550] 118 diode

[0551] 120 peak detection unit

[0552] 121, 122 resistors

[0553] Capacitors 123 and 124

[0554] 125 comparator

[0555] 130 zero-crossing detection units

[0556] 140 First Output Unit

[0557] Inverters 141 and 142

[0558] 143N MOSFET

[0559] 144 resistor

[0560] 150 DC monitoring unit

[0561] 160 Second Output Unit

[0562] 170 Undervoltage Protection Unit

[0563] 180 Comparison Units

[0564] 181 to 184 comparators

[0565] 190 AC waveform determination unit

[0566] 200 Printed Circuit Board

[0567] 210 copper wire

[0568] 220 solder

[0569] 300 Semiconductor Integrated Circuit Devices (Zero-crossing ICs)

[0570] 300a First Chip

[0571] 300b Second Chip

[0572] 300c Island

[0573] 310 AC monitoring unit

[0574] 311 to 314 resistors

[0575] 311a to 315a, 311b to 315b Resistors

[0576] 316a, 316b NMOSFET

[0577] 317a, 317b PMOSFET

[0578] 318a and 318b fuses

[0579] 320 Zero-crossing detection unit

[0580] 321 and 322 comparators

[0581] 330 logic units

[0582] 340 First Output Unit

[0583] 350 Comparison Units

[0584] 360° undervoltage protection unit

[0585] 370 Input Stop Detection Unit

[0586] 371 Bias Power Supply

[0587] 372 comparator

[0588] 380 DC monitoring unit

[0589] 381 to 385 resistors

[0590] 386 NMOSFET

[0591] 387 PMOSFET

[0592] 388 fuse

[0593] 390 Second Output Unit

[0594] 400, 400X to 400Z High Voltage Region (LDMOSFET Region)

[0595] 401 Feedback Resistor (Polysilicon Resistor)

[0596] 401 (1) to 401 (m) unit resistor

[0597] 402 Field Oxide Film

[0598] 410 p-type semiconductor substrate

[0599] 411 Low-concentration n-type semiconductor region

[0600] 412 High-concentration p-type semiconductor region

[0601] 413, 414 High-concentration n-type semiconductor regions

[0602] 415 Field Oxide Film

[0603] 416 gate oxide film

[0604] 417 Gate region

[0605] 418 Field Board

[0606] 419 Low-concentration p-type semiconductor region

[0607] 510 Delay Adjustment Unit

[0608] 520 Control Unit

[0609] 531 Internal Resistor

[0610] 532 External Resistor

[0611] Areas A1 and A2

[0612] C1 and C11 capacitors

[0613] diodes D1, D11, and D12

[0614] Pads P1 to P12, P21 to P35, P41 to P49

[0615] R resistor component

[0616] Conductors W1 to W9, W21 to W31

Claims

1. A zero-crossing detection circuit, comprising: A peak detection unit is used to detect the peak value of the monitoring target signal input from the AC signal input terminal through a diode, thereby generating a peak detection signal; as well as A zero-crossing detection unit is used to estimate the zero-crossing of the AC signal based on the peak detection signal, thereby generating a zero-crossing detection signal. The peak detection unit includes first and second resistors, first and second capacitors, and a comparator. The first resistor and the first capacitor are used as an RC filter to remove noise components superimposed on the monitoring target signal, thereby generating a first AC monitoring signal; The second resistor and the second capacitor serve as a delay unit, which applies a predetermined delay to the first AC monitoring signal to generate a second AC monitoring signal; and The comparator is used to compare the first AC monitoring signal with the second AC monitoring signal to generate the peak detection signal.

2. The zero-crossing detection circuit according to claim 1 further includes a monitoring unit, which is used to adjust the monitoring target signal to be suitable for input to the peak detection unit.

3. The zero-crossing detection circuit according to claim 1 or 2, wherein, The zero-crossing detection unit counts the period of the peak detection signal and uses the count value to estimate the zero-crossing of the AC signal.

4. The zero-crossing detection circuit according to claim 1 or 2 further includes: A comparison unit is used to compare the monitored target signal with multiple thresholds to generate multiple comparison signals; and A waveform determination unit is used to detect whether both the rising edge and the falling edge have appeared in at least one of the comparison signals during one period of the zero-crossing detection signal, thereby generating a waveform determination signal.

5. The zero-crossing detection circuit according to claim 4, wherein, When the waveform determination signal is at an abnormal determination logic level, the zero-crossing detection unit stops generating or outputting the zero-crossing detection signal.

6. The zero-crossing detection circuit according to claim 1 or 2, wherein, If the logic level of the peak detection signal is switched, and the logic level after the switch is not maintained for a predetermined period of time, the zero-crossing detection unit ignores the switch of the logic level.

7. The zero-crossing detection circuit according to claim 3, wherein, The zero-crossing detection unit is used for: Starting from the moment of logic level transition of the peak detection signal, the first standby time and the second standby time are counted respectively. The first standby time corresponds to the period obtained before the start of the transition, and the second standby time is longer than the first standby time. In the event of the expiration of either the first standby time or the second standby time, the logic level of the peak detection signal is switched.

8. A semiconductor integrated circuit device comprising an integration of at least a portion of circuit elements constituting a zero-crossing detection circuit according to any one of claims 1 to 7.

9. The semiconductor integrated circuit device according to claim 8, wherein, The distance between the first external terminal receiving the monitoring target signal and the second external terminal adjacent to the first external terminal is greater than the distance between the other external terminals.

10. The semiconductor integrated circuit device of claim 8, further comprising an integrated AC / DC converter for generating a first DC voltage based on an AC voltage input as an AC signal.

11. The semiconductor integrated circuit device of claim 10, further comprising an integrated DC / DC converter for generating a second DC voltage based on the first DC voltage.

12. The semiconductor integrated circuit device according to claim 8, further comprising: A first chip integrates a monitoring unit, which adjusts the monitored target signal to be suitable for input to the peak detection unit. A second chip integrates the peak detection unit and the zero-crossing detection unit, wherein... The first chip and the second chip are sealed with molding resin.

13. An electronic device comprising: A rectifier unit is used to perform normal rectification or voltage multiplication rectification on AC voltage to generate rectified voltage; A zero-crossing detection circuit is used to detect the zero crossing of the AC voltage; as well as A microcomputer is used to control the load drive based on the detection results of the zero-crossing detection circuit, wherein... The zero-crossing detection circuit is the zero-crossing detection circuit according to claim 1, or a zero-crossing detection circuit formed using a semiconductor integrated circuit device according to any one of claims 8 to 12.

14. The electronic device according to claim 13, wherein, The rectifier unit includes a first capacitor and a second capacitor connected in series between the output terminal of the rectified voltage and the ground terminal, and the connection node of the first capacitor and the second capacitor is connected to the node from which the monitoring target signal is drawn.

15. The electronic device according to claim 13, wherein, The zero-crossing detection circuit operates relative to the ground voltage shared with the microcomputer.

16. The electronic device according to claim 13, wherein, The load is a motor or a three-terminal bidirectional thyristor switch.

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